* [PATCH v3 0/3] Prepare for OMAP2+ movement to Common Clk
@ 2012-07-02 10:24 Rajendra Nayak
2012-07-02 10:24 ` [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare Rajendra Nayak
` (2 more replies)
0 siblings, 3 replies; 16+ messages in thread
From: Rajendra Nayak @ 2012-07-02 10:24 UTC (permalink / raw)
To: linux-arm-kernel
Changes in v3:
* Fixed various checkpatch warning/errors as reported by Paul W.
Changes in v2:
* Dropped all driver clk_prepare/clk_unprepare changes, will be
sent seperately to respective lists
This is a preparatory series for the OMAP Common Clk
conversion. They mostly add clk_prepare/clk_unprepare
in OMAP platform code. Also gets rid of omap_clk_get_by_name
and uses clk_get, and removes all direct 'struct clk'
dereferrencing and uses helpers similar to what is provided
by Common Clk.
Patches are boot tested on OMAP2430sdp, 3630 Beagle-Xm
and 4430/4460 Panda and suspend tested on 3630 Beagle-Xm
and 4430 Panda. Patches apply on 3.5-rc5.
Rajendra Nayak (3):
ARM: omap: clk: add clk_prepare and clk_unprepare
ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
ARM: omap: clk: Remove all direct dereferencing of struct clk
arch/arm/mach-omap2/board-apollon.c | 4 +-
arch/arm/mach-omap2/board-h4.c | 6 +-
arch/arm/mach-omap2/board-omap4panda.c | 2 +-
arch/arm/mach-omap2/clkt2xxx_apll.c | 2 +-
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 4 +-
arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 20 +++---
arch/arm/mach-omap2/clkt_clksel.c | 89 ++++++++++++++++---------
arch/arm/mach-omap2/clkt_dpll.c | 26 ++++---
arch/arm/mach-omap2/clock.c | 11 ++-
arch/arm/mach-omap2/clock2420_data.c | 17 +++++
arch/arm/mach-omap2/clock2430_data.c | 21 ++++++
arch/arm/mach-omap2/clock3xxx.c | 8 +-
arch/arm/mach-omap2/clock3xxx_data.c | 24 +++++++
arch/arm/mach-omap2/clock44xx_data.c | 17 +++++
arch/arm/mach-omap2/display.c | 4 +-
arch/arm/mach-omap2/dpll3xxx.c | 45 ++++++++------
arch/arm/mach-omap2/gpmc.c | 2 +-
arch/arm/mach-omap2/omap_hwmod.c | 21 ++++---
arch/arm/mach-omap2/pm.c | 2 +-
arch/arm/mach-omap2/pm24xx.c | 2 +
arch/arm/mach-omap2/usb-fs.c | 4 +-
arch/arm/plat-omap/include/plat/clock.h | 4 +
arch/arm/plat-omap/omap_device.c | 6 +-
23 files changed, 235 insertions(+), 106 deletions(-)
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare
2012-07-02 10:24 [PATCH v3 0/3] Prepare for OMAP2+ movement to Common Clk Rajendra Nayak
@ 2012-07-02 10:24 ` Rajendra Nayak
2012-07-30 22:31 ` Paul Walmsley
2012-07-02 10:24 ` [PATCH v3 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage Rajendra Nayak
2012-07-02 10:24 ` [PATCH v3 3/3] ARM: omap: clk: Remove all direct dereferencing of struct clk Rajendra Nayak
2 siblings, 1 reply; 16+ messages in thread
From: Rajendra Nayak @ 2012-07-02 10:24 UTC (permalink / raw)
To: linux-arm-kernel
As part of Common Clk Framework (CCF) the clk_enable() operation
was split into a clk_prepare() which could sleep, and a clk_enable()
which should never sleep. Similarly the clk_disable() was
split into clk_disable() and clk_unprepare(). This was
needed to handle complex cases where in a clk gate/ungate
would require a slow and a fast part to be implemented.
None of the clocks below seem to be in the 'complex' clocks
category and are just simple clocks which are enabled/disabled
through simple register writes.
Most of the instances also seem to be called in non-atomic
context which means its safe to move all of those from
using a clk_enable() to clk_prepare_enable() and clk_disable() to
clk_disable_unprepare().
For a few others where there is a possibility they get called from
an interrupt or atomic context, there is an additonal clk_prepare()
done before a clk_enable() and a clk_unprepare()
after a clk_disable().
This is in preparation of OMAP moving to CCF.
Based on initial changes from Mike turquette.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/board-apollon.c | 4 ++--
arch/arm/mach-omap2/board-h4.c | 6 +++---
arch/arm/mach-omap2/board-omap4panda.c | 2 +-
arch/arm/mach-omap2/clock3xxx.c | 8 ++++----
arch/arm/mach-omap2/display.c | 4 ++--
arch/arm/mach-omap2/gpmc.c | 2 +-
arch/arm/mach-omap2/omap_hwmod.c | 3 +++
arch/arm/mach-omap2/pm24xx.c | 2 ++
arch/arm/mach-omap2/usb-fs.c | 4 ++--
9 files changed, 20 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 502c31e..1d8c693 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -205,7 +205,7 @@ static inline void __init apollon_init_smc91x(void)
return;
}
- clk_enable(gpmc_fck);
+ clk_prepare_enable(gpmc_fck);
rate = clk_get_rate(gpmc_fck);
eth_cs = APOLLON_ETH_CS;
@@ -249,7 +249,7 @@ static inline void __init apollon_init_smc91x(void)
gpmc_cs_free(APOLLON_ETH_CS);
}
out:
- clk_disable(gpmc_fck);
+ clk_disable_unprepare(gpmc_fck);
clk_put(gpmc_fck);
}
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 876becf..a273af0 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -267,9 +267,9 @@ static inline void __init h4_init_debug(void)
return;
}
- clk_enable(gpmc_fck);
+ clk_prepare_enable(gpmc_fck);
rate = clk_get_rate(gpmc_fck);
- clk_disable(gpmc_fck);
+ clk_disable_unprepare(gpmc_fck);
clk_put(gpmc_fck);
if (is_gpmc_muxed())
@@ -313,7 +313,7 @@ static inline void __init h4_init_debug(void)
gpmc_cs_free(eth_cs);
out:
- clk_disable(gpmc_fck);
+ clk_disable_unprepare(gpmc_fck);
clk_put(gpmc_fck);
}
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 982fb26..f0ea558 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -172,7 +172,7 @@ static void __init omap4_ehci_init(void)
return;
}
clk_set_rate(phy_ref_clk, 19200000);
- clk_enable(phy_ref_clk);
+ clk_prepare_enable(phy_ref_clk);
/* disable the power to the usb hub prior to init and reset phy+hub */
ret = gpio_request_array(panda_ehci_gpios,
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 794d827..4c1591a 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -64,15 +64,15 @@ void __init omap3_clk_lock_dpll5(void)
dpll5_clk = clk_get(NULL, "dpll5_ck");
clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
- clk_enable(dpll5_clk);
+ clk_prepare_enable(dpll5_clk);
/* Program dpll5_m2_clk divider for no division */
dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
- clk_enable(dpll5_m2_clk);
+ clk_prepare_enable(dpll5_m2_clk);
clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
- clk_disable(dpll5_m2_clk);
- clk_disable(dpll5_clk);
+ clk_disable_unprepare(dpll5_m2_clk);
+ clk_disable_unprepare(dpll5_clk);
return;
}
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 5fb47a1..e5f8e48 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -471,7 +471,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk)
- clk_enable(oc->_clk);
+ clk_prepare_enable(oc->_clk);
dispc_disable_outputs();
@@ -498,7 +498,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk)
- clk_disable(oc->_clk);
+ clk_disable_unprepare(oc->_clk);
r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 2286410..a33f89d 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -749,7 +749,7 @@ static int __init gpmc_init(void)
BUG();
}
- clk_enable(gpmc_l3_clk);
+ clk_prepare_enable(gpmc_l3_clk);
l = gpmc_read_reg(GPMC_REVISION);
printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7731936..f904993 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -608,6 +608,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
oh->name, oh->main_clk);
return -EINVAL;
}
+ clk_prepare(oh->_clk);
if (!oh->_clk->clkdm)
pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
@@ -645,6 +646,7 @@ static int _init_interface_clks(struct omap_hwmod *oh)
ret = -EINVAL;
}
os->_clk = c;
+ clk_prepare(os->_clk);
}
return ret;
@@ -672,6 +674,7 @@ static int _init_opt_clks(struct omap_hwmod *oh)
ret = -EINVAL;
}
oc->_clk = c;
+ clk_prepare(oc->_clk);
}
return ret;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 2edeffc..8eee8bc 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -340,11 +340,13 @@ int __init omap2_pm_init(void)
printk(KERN_ERR "could not get osc_ck\n");
return -ENODEV;
}
+ clk_prepare(osc_ck);
if (cpu_is_omap242x()) {
emul_ck = clk_get(NULL, "emul_ck");
if (IS_ERR(emul_ck)) {
printk(KERN_ERR "could not get emul_ck\n");
+ clk_unprepare(osc_ck);
clk_put(osc_ck);
return -ENODEV;
}
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
index 1481078..cff7d24 100644
--- a/arch/arm/mach-omap2/usb-fs.c
+++ b/arch/arm/mach-omap2/usb-fs.c
@@ -344,7 +344,7 @@ void __init omap2_usbfs_init(struct omap_usb_config *pdata)
if (IS_ERR(ick))
return;
- clk_enable(ick);
+ clk_prepare_enable(ick);
pdata->usb0_init = omap2_usb0_init;
pdata->usb1_init = omap2_usb1_init;
pdata->usb2_init = omap2_usb2_init;
@@ -352,7 +352,7 @@ void __init omap2_usbfs_init(struct omap_usb_config *pdata)
ohci_device_init(pdata);
otg_device_init(pdata);
omap_otg_init(pdata);
- clk_disable(ick);
+ clk_disable_unprepare(ick);
clk_put(ick);
}
--
1.7.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
2012-07-02 10:24 [PATCH v3 0/3] Prepare for OMAP2+ movement to Common Clk Rajendra Nayak
2012-07-02 10:24 ` [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare Rajendra Nayak
@ 2012-07-02 10:24 ` Rajendra Nayak
2012-07-02 10:24 ` [PATCH v3 3/3] ARM: omap: clk: Remove all direct dereferencing of struct clk Rajendra Nayak
2 siblings, 0 replies; 16+ messages in thread
From: Rajendra Nayak @ 2012-07-02 10:24 UTC (permalink / raw)
To: linux-arm-kernel
Moving to Common clk framework for OMAP would mean we no longer use
internal lookup mechanism like omap_clk_get_by_name().
get rid of all its usage mostly from hwmod and omap_device
code.
Also use IS_ERR_OR_NULL() for error checking.
Moving to clk_get() also means the respective platforms
need the clkdev tables updated with an entry for all clocks
used by hwmod to have clock name same as the alias.
Based on original changes from Mike Turquette.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/clock2420_data.c | 17 +++++++++++++++++
arch/arm/mach-omap2/clock2430_data.c | 21 +++++++++++++++++++++
arch/arm/mach-omap2/clock3xxx_data.c | 24 ++++++++++++++++++++++++
arch/arm/mach-omap2/clock44xx_data.c | 17 +++++++++++++++++
arch/arm/mach-omap2/omap_hwmod.c | 12 ++++++------
arch/arm/plat-omap/omap_device.c | 6 +++---
6 files changed, 88 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index bace930..b3a659b 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1808,6 +1808,7 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
+ CLK(NULL, "dss_ick", &dss_ick, CK_242X),
CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
@@ -1847,12 +1848,16 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
+ CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
+ CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
+ CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
+ CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
@@ -1863,12 +1868,15 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
+ CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
+ CLK(NULL, "cam_fck", &cam_fck, CK_242X),
CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
+ CLK(NULL, "cam_ick", &cam_ick, CK_242X),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
@@ -1877,16 +1885,22 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
+ CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
+ CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
CLK(NULL, "fac_ick", &fac_ick, CK_242X),
CLK(NULL, "fac_fck", &fac_fck, CK_242X),
CLK(NULL, "eac_ick", &eac_ick, CK_242X),
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
+ CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
+ CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
+ CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
+ CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
@@ -1896,8 +1910,11 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
CLK(NULL, "des_ick", &des_ick, CK_242X),
CLK("omap-sham", "ick", &sha_ick, CK_242X),
+ CLK(NULL, "sha_ick", &sha_ick, CK_242X),
CLK("omap_rng", "ick", &rng_ick, CK_242X),
+ CLK(NULL, "rng_ick", &rng_ick, CK_242X),
CLK("omap-aes", "ick", &aes_ick, CK_242X),
+ CLK(NULL, "aes_ick", &aes_ick, CK_242X),
CLK(NULL, "pka_ick", &pka_ick, CK_242X),
CLK(NULL, "usb_fck", &usb_fck, CK_242X),
CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 3b4d09a..400a38b 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1897,6 +1897,7 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
+ CLK(NULL, "dss_ick", &dss_ick, CK_243X),
CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
@@ -1936,20 +1937,28 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
+ CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
+ CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
+ CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
+ CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
+ CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
+ CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
+ CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
+ CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
@@ -1960,13 +1969,16 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
+ CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
CLK(NULL, "icr_ick", &icr_ick, CK_243X),
CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
+ CLK(NULL, "cam_fck", &cam_fck, CK_243X),
CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
+ CLK(NULL, "cam_ick", &cam_ick, CK_243X),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
@@ -1975,10 +1987,14 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "fac_ick", &fac_ick, CK_243X),
CLK(NULL, "fac_fck", &fac_fck, CK_243X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
+ CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
+ CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
+ CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
+ CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
@@ -1991,15 +2007,20 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "pka_ick", &pka_ick, CK_243X),
CLK(NULL, "usb_fck", &usb_fck, CK_243X),
CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
+ CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
+ CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
+ CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
+ CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
+ CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 1efdec2..f079df8 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3260,6 +3260,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
+ CLK(NULL, "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_3XXX),
CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
@@ -3329,6 +3330,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
+ CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
@@ -3336,6 +3338,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
+ CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1),
+ CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
@@ -3344,27 +3348,40 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
+ CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX),
+ CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX),
CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
+ CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX),
CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
+ CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX),
+ CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX),
+ CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX),
+ CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX),
CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
+ CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX),
+ CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX),
+ CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX),
CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
+ CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX),
+ CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX),
CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
@@ -3383,7 +3400,9 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
+ CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1),
CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
@@ -3408,6 +3427,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
+ CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
@@ -3456,6 +3476,9 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
+ CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX),
+ CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX),
+ CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
@@ -3479,6 +3502,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
+ CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index ba6f9a0..81e563d 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3228,6 +3228,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
+ CLK(NULL, "dss_fck", &dss_fck, CK_443X),
CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
@@ -3284,6 +3285,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
+ CLK(NULL, "rng_ick", &rng_ick, CK_443X),
CLK("omap_rng", "ick", &rng_ick, CK_443X),
CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
@@ -3300,20 +3302,32 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
+ CLK(NULL, "timer1_fck", &timer1_fck, CK_443X),
CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
+ CLK(NULL, "timer10_fck", &timer10_fck, CK_443X),
CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
+ CLK(NULL, "timer11_fck", &timer11_fck, CK_443X),
CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
+ CLK(NULL, "timer2_fck", &timer2_fck, CK_443X),
CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
+ CLK(NULL, "timer3_fck", &timer3_fck, CK_443X),
CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
+ CLK(NULL, "timer4_fck", &timer4_fck, CK_443X),
CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
+ CLK(NULL, "timer5_fck", &timer5_fck, CK_443X),
CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
+ CLK(NULL, "timer6_fck", &timer6_fck, CK_443X),
CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
+ CLK(NULL, "timer7_fck", &timer7_fck, CK_443X),
CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
+ CLK(NULL, "timer8_fck", &timer8_fck, CK_443X),
CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
+ CLK(NULL, "timer9_fck", &timer9_fck, CK_443X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
+ CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
@@ -3325,14 +3339,17 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
+ CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
+ CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X),
CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
+ CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index f904993..2cf4c95 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -602,8 +602,8 @@ static int _init_main_clk(struct omap_hwmod *oh)
if (!oh->main_clk)
return 0;
- oh->_clk = omap_clk_get_by_name(oh->main_clk);
- if (!oh->_clk) {
+ oh->_clk = clk_get(NULL, oh->main_clk);
+ if (IS_ERR_OR_NULL(oh->_clk)) {
pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
oh->name, oh->main_clk);
return -EINVAL;
@@ -639,8 +639,8 @@ static int _init_interface_clks(struct omap_hwmod *oh)
if (!os->clk)
continue;
- c = omap_clk_get_by_name(os->clk);
- if (!c) {
+ c = clk_get(NULL, os->clk);
+ if (IS_ERR_OR_NULL(c)) {
pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
oh->name, os->clk);
ret = -EINVAL;
@@ -667,8 +667,8 @@ static int _init_opt_clks(struct omap_hwmod *oh)
int ret = 0;
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
- c = omap_clk_get_by_name(oc->clk);
- if (!c) {
+ c = clk_get(NULL, oc->clk);
+ if (IS_ERR_OR_NULL(c)) {
pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
oh->name, oc->clk);
ret = -EINVAL;
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..af822d5 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -266,10 +266,10 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
return;
}
- r = omap_clk_get_by_name(clk_name);
- if (IS_ERR(r)) {
+ r = clk_get(NULL, clk_name);
+ if (IS_ERR_OR_NULL(r)) {
dev_err(&od->pdev->dev,
- "omap_clk_get_by_name for %s failed\n", clk_name);
+ "clk_get for %s failed\n", clk_name);
return;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/3] ARM: omap: clk: Remove all direct dereferencing of struct clk
2012-07-02 10:24 [PATCH v3 0/3] Prepare for OMAP2+ movement to Common Clk Rajendra Nayak
2012-07-02 10:24 ` [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare Rajendra Nayak
2012-07-02 10:24 ` [PATCH v3 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage Rajendra Nayak
@ 2012-07-02 10:24 ` Rajendra Nayak
2012-07-30 7:12 ` Paul Walmsley
2 siblings, 1 reply; 16+ messages in thread
From: Rajendra Nayak @ 2012-07-02 10:24 UTC (permalink / raw)
To: linux-arm-kernel
While we move to Common Clk Framework (CCF), direct deferencing of struct
clk wouldn't be possible anymore. Hence get rid of all such instances
in the current clock code and use macros/helpers similar to the ones that
are provided by CCF.
While here also concatenate some strings split across multiple lines
which seem to be needed anyway.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/clkt2xxx_apll.c | 2 +-
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 4 +-
arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 20 +++---
arch/arm/mach-omap2/clkt_clksel.c | 89 ++++++++++++++++---------
arch/arm/mach-omap2/clkt_dpll.c | 26 ++++---
arch/arm/mach-omap2/clock.c | 11 ++-
arch/arm/mach-omap2/dpll3xxx.c | 45 ++++++++------
arch/arm/mach-omap2/omap_hwmod.c | 6 +-
arch/arm/mach-omap2/pm.c | 2 +-
arch/arm/plat-omap/include/plat/clock.h | 4 +
10 files changed, 127 insertions(+), 82 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index b19a1f7..c2d1521 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
- OMAP24XX_CM_IDLEST_VAL, clk->name);
+ OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
/*
* REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 3d9d746..3a27426 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -75,7 +75,7 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
for (ptr = rate_table; ptr->mpu_speed; ptr++) {
if (!(ptr->flags & cpu_mask))
continue;
- if (ptr->xtal_speed != sclk->rate)
+ if (ptr->xtal_speed != __clk_get_rate(sclk))
continue;
highest_rate = ptr->mpu_speed;
@@ -99,7 +99,7 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
if (!(prcm->flags & cpu_mask))
continue;
- if (prcm->xtal_speed != sclk->rate)
+ if (prcm->xtal_speed != __clk_get_rate(sclk))
continue;
if (prcm->mpu_speed <= rate) {
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index d6e34dd..0fd8b70 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
struct omap_sdrc_params *sdrc_cs0;
struct omap_sdrc_params *sdrc_cs1;
int ret;
+ unsigned long clkrate;
if (!clk || !rate)
return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (validrate != rate)
return -EINVAL;
- sdrcrate = sdrc_ick_p->rate;
- if (rate > clk->rate)
- sdrcrate <<= ((rate / clk->rate) >> 1);
+ sdrcrate = __clk_get_rate(sdrc_ick_p);
+ clkrate = __clk_get_rate(clk);
+ if (rate > clkrate)
+ sdrcrate <<= ((rate / clkrate) >> 1);
else
- sdrcrate >>= ((clk->rate / rate) >> 1);
+ sdrcrate >>= ((clkrate / rate) >> 1);
ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
/*
* XXX This only needs to be done when the CPU frequency changes
*/
- _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+ _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
c += 1; /* for safety */
c *= SDRC_MPURATE_LOOPS;
@@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (c == 0)
c = 1;
- pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
- validrate);
+ pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
+ clkrate, validrate);
pr_debug("clock: SDRC CS0 timing params used:"
" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
@@ -104,14 +106,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (sdrc_cs1)
omap3_configure_core_dpll(
- new_div, unlock_dll, c, rate > clk->rate,
+ new_div, unlock_dll, c, rate > clkrate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
else
omap3_configure_core_dpll(
- new_div, unlock_dll, c, rate > clk->rate,
+ new_div, unlock_dll, c, rate > clkrate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
0, 0, 0, 0);
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 04d551b..c8d8888 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -71,8 +71,9 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
if (!clks->parent) {
/* This indicates a data problem */
- WARN(1, "clock: Could not find parent clock %s in clksel array "
- "of clock %s\n", src_clk->name, clk->name);
+ WARN(1, "clock: Could not find parent clock %s in clksel array of clock %s\n",
+ __clk_get_name(src_clk),
+ __clk_get_name(clk));
return NULL;
}
@@ -126,8 +127,9 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
if (max_div == 0) {
/* This indicates an error in the clksel data */
- WARN(1, "clock: Could not find divisor for clock %s parent %s"
- "\n", clk->name, src_clk->parent->name);
+ WARN(1, "clock: Could not find divisor for clock %s parent %s\n",
+ __clk_get_name(clk),
+ __clk_get_name(__clk_get_parent(src_clk)));
return 0;
}
@@ -176,8 +178,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
{
const struct clksel *clks;
const struct clksel_rate *clkr;
+ struct clk *parent;
- clks = _get_clksel_by_parent(clk, clk->parent);
+ parent = __clk_get_parent(clk);
+ clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return 0;
@@ -191,8 +195,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
if (!clkr->div) {
/* This indicates a data error */
- WARN(1, "clock: Could not find fieldval %d for clock %s parent "
- "%s\n", field_val, clk->name, clk->parent->name);
+ WARN(1, "clock: Could not find fieldval %d for clock %s parent %s\n",
+ field_val, __clk_get_name(clk), __clk_get_name(parent));
return 0;
}
@@ -213,11 +217,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
{
const struct clksel *clks;
const struct clksel_rate *clkr;
+ struct clk *parent;
/* should never happen */
WARN_ON(div == 0);
- clks = _get_clksel_by_parent(clk, clk->parent);
+ parent = __clk_get_parent(clk);
+ clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return ~0;
@@ -230,8 +236,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
}
if (!clkr->div) {
- pr_err("clock: Could not find divisor %d for clock %s parent "
- "%s\n", div, clk->name, clk->parent->name);
+ pr_err("clock: Could not find divisor %d for clock %s parent %s\n",
+ div, __clk_get_name(clk), __clk_get_name(parent));
return ~0;
}
@@ -281,16 +287,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
const struct clksel *clks;
const struct clksel_rate *clkr;
u32 last_div = 0;
+ struct clk *parent;
+ unsigned long parent_rate;
+ const char *clk_name;
+
+ parent = __clk_get_parent(clk);
+ parent_rate = __clk_get_rate(parent);
+ clk_name = __clk_get_name(clk);
if (!clk->clksel || !clk->clksel_mask)
return ~0;
pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
- clk->name, target_rate);
+ clk_name, target_rate);
*new_div = 1;
- clks = _get_clksel_by_parent(clk, clk->parent);
+ clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return ~0;
@@ -300,12 +313,12 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
/* Sanity check */
if (clkr->div <= last_div)
- pr_err("clock: clksel_rate table not sorted "
- "for clock %s", clk->name);
+ pr_err("clock: clksel_rate table not sorted for clock %s",
+ clk_name);
last_div = clkr->div;
- test_rate = clk->parent->rate / clkr->div;
+ test_rate = parent_rate / clkr->div;
if (test_rate <= target_rate)
break; /* found it */
@@ -314,16 +327,16 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
if (!clkr->div) {
pr_err("clock: Could not find divisor for target "
"rate %ld for clock %s parent %s\n", target_rate,
- clk->name, clk->parent->name);
+ clk_name, __clk_get_name(parent));
return ~0;
}
*new_div = clkr->div;
pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
- (clk->parent->rate / clkr->div));
+ (parent_rate / clkr->div));
- return clk->parent->rate / clkr->div;
+ return parent_rate / clkr->div;
}
/*
@@ -345,10 +358,15 @@ void omap2_init_clksel_parent(struct clk *clk)
const struct clksel *clks;
const struct clksel_rate *clkr;
u32 r, found = 0;
+ struct clk *parent;
+ const char *clk_name;
if (!clk->clksel || !clk->clksel_mask)
return;
+ parent = __clk_get_parent(clk);
+ clk_name = __clk_get_name(clk);
+
r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
r >>= __ffs(clk->clksel_mask);
@@ -358,12 +376,14 @@ void omap2_init_clksel_parent(struct clk *clk)
continue;
if (clkr->val == r) {
- if (clk->parent != clks->parent) {
+ if (parent != clks->parent) {
pr_debug("clock: inited %s parent "
"to %s (was %s)\n",
- clk->name, clks->parent->name,
- ((clk->parent) ?
- clk->parent->name : "NULL"));
+ clk_name,
+ __clk_get_name(clks->parent),
+ ((parent) ?
+ __clk_get_name(parent) :
+ "NULL"));
clk_reparent(clk, clks->parent);
};
found = 1;
@@ -373,7 +393,7 @@ void omap2_init_clksel_parent(struct clk *clk)
/* This indicates a data error */
WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
- clk->name, r);
+ clk_name, r);
return;
}
@@ -391,15 +411,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
{
unsigned long rate;
u32 div = 0;
+ struct clk *parent;
div = _read_divisor(clk);
if (div == 0)
- return clk->rate;
+ return __clk_get_rate(clk);
- rate = clk->parent->rate / div;
+ parent = __clk_get_parent(clk);
+ rate = __clk_get_rate(parent) / div;
- pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
- rate, div);
+ pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
+ __clk_get_name(clk), rate, div);
return rate;
}
@@ -454,9 +476,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
_write_clksel_reg(clk, field_val);
- clk->rate = clk->parent->rate / new_div;
+ clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
- pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
+ pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
+ __clk_get_rate(clk));
return 0;
}
@@ -498,13 +521,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
clk_reparent(clk, new_parent);
/* CLKSEL clocks follow their parents' rates, divided by a divisor */
- clk->rate = new_parent->rate;
+ clk->rate = __clk_get_rate(new_parent);
if (parent_div > 0)
- clk->rate /= parent_div;
+ __clk_get_rate(clk) /= parent_div;
pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
- clk->name, clk->parent->name, clk->rate);
+ __clk_get_name(clk),
+ __clk_get_name(__clk_get_parent(clk)),
+ __clk_get_rate(clk));
return 0;
}
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cd7fd0f..8c3349e 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
dd = clk->dpll_data;
/* DPLL divider must result in a valid jitter correction val */
- fint = clk->parent->rate / n;
+ fint = __clk_get_rate(__clk_get_parent(clk)) / n;
if (cpu_is_omap24xx()) {
/* Should not be called for OMAP2, so warn if it is called */
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
if (cpu_is_omap24xx()) {
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
- return dd->clk_bypass->rate;
+ return __clk_get_rate(dd->clk_bypass);
} else if (cpu_is_omap34xx()) {
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
- return dd->clk_bypass->rate;
+ return __clk_get_rate(dd->clk_bypass);
} else if (cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
- return dd->clk_bypass->rate;
+ return __clk_get_rate(dd->clk_bypass);
}
v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
dpll_div = v & dd->div1_mask;
dpll_div >>= __ffs(dd->div1_mask);
- dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+ dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
do_div(dpll_clk, dpll_div + 1);
return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
unsigned long scaled_rt_rp;
unsigned long new_rate = 0;
struct dpll_data *dd;
+ unsigned long ref_rate;
+ const char *clk_name;
if (!clk || !clk->dpll_data)
return ~0;
dd = clk->dpll_data;
+ ref_rate = __clk_get_rate(dd->clk_ref);
+ clk_name = __clk_get_name(clk);
pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
- clk->name, target_rate);
+ clk_name, target_rate);
- scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+ scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
break;
r = _dpll_test_mult(&m, n, &new_rate, target_rate,
- dd->clk_ref->rate);
+ ref_rate);
/* m can't be set low enough for this n - try with a larger n */
if (r == DPLL_MULT_UNDERFLOW)
continue;
pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
- clk->name, m, n, new_rate);
+ clk_name, m, n, new_rate);
if (target_rate == new_rate) {
dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
}
if (target_rate != new_rate) {
- pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
- target_rate);
+ pr_debug("clock: %s: cannot round to rate %ld\n",
+ clk_name, target_rate);
return ~0;
}
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 5c4e665..b938cf0 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -76,7 +76,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
- clk->name);
+ __clk_get_name(clk));
}
/* Public functions */
@@ -92,18 +92,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
void omap2_init_clk_clkdm(struct clk *clk)
{
struct clockdomain *clkdm;
+ const char *clk_name;
if (!clk->clkdm_name)
return;
+ clk_name = __clk_get_name(clk);
+
clkdm = clkdm_lookup(clk->clkdm_name);
if (clkdm) {
pr_debug("clock: associated clk %s to clkdm %s\n",
- clk->name, clk->clkdm_name);
+ clk_name, clk->clkdm_name);
clk->clkdm = clkdm;
} else {
- pr_debug("clock: could not associate clk %s to "
- "clkdm %s\n", clk->name, clk->clkdm_name);
+ pr_debug("clock: could not associate clk %s to clkdm %s\n",
+ clk_name, clk->clkdm_name);
}
}
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f0f10be..d390f40 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
const struct dpll_data *dd;
int i = 0;
int ret = -EINVAL;
+ const char *clk_name;
dd = clk->dpll_data;
+ clk_name = __clk_get_name(clk);
state <<= __ffs(dd->idlest_mask);
@@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
if (i == MAX_DPLL_WAIT_TRIES) {
printk(KERN_ERR "clock: %s failed transition to '%s'\n",
- clk->name, (state) ? "locked" : "bypassed");
+ clk_name, (state) ? "locked" : "bypassed");
} else {
pr_debug("clock: %s transition to '%s' in %d loops\n",
- clk->name, (state) ? "locked" : "bypassed", i);
+ clk_name, (state) ? "locked" : "bypassed", i);
ret = 0;
}
@@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
unsigned long fint;
u16 f = 0;
- fint = clk->dpll_data->clk_ref->rate / n;
+ fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
pr_debug("clock: fint is %lu\n", fint);
@@ -138,7 +140,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
u8 ai;
int r;
- pr_debug("clock: locking DPLL %s\n", clk->name);
+ pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
ai = omap3_dpll_autoidle_read(clk);
@@ -177,7 +179,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
return -EINVAL;
pr_debug("clock: configuring DPLL %s for low-power bypass\n",
- clk->name);
+ __clk_get_name(clk));
ai = omap3_dpll_autoidle_read(clk);
@@ -207,7 +209,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
return -EINVAL;
- pr_debug("clock: stopping DPLL %s\n", clk->name);
+ pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
ai = omap3_dpll_autoidle_read(clk);
@@ -235,7 +237,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
{
unsigned long fint, clkinp; /* watch out for overflow */
- clkinp = clk->parent->rate;
+ clkinp = __clk_get_rate(__clk_get_parent(clk));
fint = (clkinp / n) * m;
if (fint < 1000000000)
@@ -261,7 +263,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
unsigned long clkinp, sd; /* watch out for overflow */
int mod1, mod2;
- clkinp = clk->parent->rate;
+ clkinp = __clk_get_rate(__clk_get_parent(clk));
/*
* target sigma-delta to near 250MHz
@@ -370,16 +372,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
{
int r;
struct dpll_data *dd;
+ struct clk *parent;
dd = clk->dpll_data;
if (!dd)
return -EINVAL;
- if (clk->rate == dd->clk_bypass->rate) {
- WARN_ON(clk->parent != dd->clk_bypass);
+ parent = __clk_get_parent(clk);
+
+ if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
+ WARN_ON(parent != dd->clk_bypass);
r = _omap3_noncore_dpll_bypass(clk);
} else {
- WARN_ON(clk->parent != dd->clk_ref);
+ WARN_ON(parent != dd->clk_ref);
r = _omap3_noncore_dpll_lock(clk);
}
/*
@@ -446,7 +451,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
omap2_clk_enable(dd->clk_bypass);
omap2_clk_enable(dd->clk_ref);
- if (dd->clk_bypass->rate == rate &&
+ if (__clk_get_rate(dd->clk_bypass) == rate &&
(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
@@ -469,7 +474,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
}
pr_debug("clock: %s: set rate: locking rate to %lu.\n",
- clk->name, rate);
+ __clk_get_name(clk), rate);
ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
dd->last_rounded_n, freqsel);
@@ -547,7 +552,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
- clk->name);
+ __clk_get_name(clk));
return;
}
@@ -581,7 +586,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
- clk->name);
+ __clk_get_name(clk));
return;
}
@@ -607,11 +612,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
unsigned long rate;
u32 v;
struct clk *pclk;
+ unsigned long parent_rate;
/* Walk up the parents of clk, looking for a DPLL */
- pclk = clk->parent;
+ pclk = __clk_get_parent(clk);
while (pclk && !pclk->dpll_data)
- pclk = pclk->parent;
+ pclk = __clk_get_parent(pclk);
/* clk does not have a DPLL as a parent? */
WARN_ON(!pclk);
@@ -620,11 +626,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
WARN_ON(!dd->enable_mask);
+ parent_rate = __clk_get_rate(__clk_get_parent(clk));
v = __raw_readl(dd->control_reg) & dd->enable_mask;
v >>= __ffs(dd->enable_mask);
if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
- rate = clk->parent->rate;
+ rate = parent_rate;
else
- rate = clk->parent->rate * 2;
+ rate = parent_rate * 2;
return rate;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 2cf4c95..2b973c6 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -612,7 +612,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
if (!oh->_clk->clkdm)
pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
- oh->main_clk, oh->_clk->name);
+ oh->name, oh->main_clk);
return ret;
}
@@ -753,7 +753,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk) {
pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
- oc->_clk->name);
+ __clk_get_name(oc->_clk));
clk_enable(oc->_clk);
}
}
@@ -768,7 +768,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk) {
pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
- oc->_clk->name);
+ __clk_get_name(oc->_clk));
clk_disable(oc->_clk);
}
}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5ced..40012e3 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -188,7 +188,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
goto exit;
}
- freq = clk->rate;
+ freq = clk_get_rate(clk);
clk_put(clk);
rcu_read_lock();
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index d0ef57c..1d20ec7 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -19,6 +19,10 @@ struct module;
struct clk;
struct clockdomain;
+#define __clk_get_name(clk) (clk->name)
+#define __clk_get_parent(clk) (clk->parent)
+#define __clk_get_rate(clk) (clk->rate)
+
/**
* struct clkops - some clock function pointers
* @enable: fn ptr that enables the current clock in hardware
--
1.7.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/3] ARM: omap: clk: Remove all direct dereferencing of struct clk
2012-07-02 10:24 ` [PATCH v3 3/3] ARM: omap: clk: Remove all direct dereferencing of struct clk Rajendra Nayak
@ 2012-07-30 7:12 ` Paul Walmsley
2012-07-30 7:36 ` Rajendra Nayak
0 siblings, 1 reply; 16+ messages in thread
From: Paul Walmsley @ 2012-07-30 7:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rajendra
On Mon, 2 Jul 2012, Rajendra Nayak wrote:
> While we move to Common Clk Framework (CCF), direct deferencing of struct
> clk wouldn't be possible anymore. Hence get rid of all such instances
> in the current clock code and use macros/helpers similar to the ones that
> are provided by CCF.
>
> While here also concatenate some strings split across multiple lines
> which seem to be needed anyway.
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
This one has some checkpatch warnings:
WARNING: quoted string split across lines
#482: FILE: arch/arm/mach-omap2/clock.c:109:
pr_debug("clock: could not associate clk %s to "
+ "clkdm %s\n", clk_name, clk->clkdm_name);
ERROR: Macros with complex values should be enclosed in parenthesis
#709: FILE: arch/arm/plat-omap/include/plat/clock.h:22:
+#define __clk_get_name(clk) clk->name
ERROR: Macros with complex values should be enclosed in parenthesis
#710: FILE: arch/arm/plat-omap/include/plat/clock.h:23:
+#define __clk_get_parent(clk) clk->parent
... etc.
These have been fixed in the version below, and a few other minor changes
made. The patch below has been queued for 3.7. Please don't forget to
make sure a patch doesn't cause checkpatch.pl warnings before posting.
- Paul
From: Rajendra Nayak <rnayak@ti.com>
Date: Wed, 27 Jun 2012 14:18:35 +0530
Subject: [PATCH] ARM: OMAP2+: clk: Remove all direct dereferencing of struct
clk
While we move to Common Clk Framework (CCF), direct deferencing of struct
clk wouldn't be possible anymore. Hence get rid of all such instances
in the current clock code and use macros/helpers similar to the ones that
are provided by CCF.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul at pwsan.com: simplified some compound expressions; resolved checkpatch
warnings; reformatted some messages]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Mike Turquette <mturquette@linaro.org>
---
arch/arm/mach-omap2/clkt2xxx_apll.c | 2 +-
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 10 ++-
arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 18 +++---
arch/arm/mach-omap2/clkt_clksel.c | 90 ++++++++++++++++----------
arch/arm/mach-omap2/clkt_dpll.c | 24 ++++---
arch/arm/mach-omap2/clock.c | 11 ++--
arch/arm/mach-omap2/dpll3xxx.c | 48 ++++++++------
arch/arm/mach-omap2/omap_hwmod.c | 6 +-
arch/arm/mach-omap2/pm.c | 2 +-
arch/arm/plat-omap/include/plat/clock.h | 5 ++
10 files changed, 133 insertions(+), 83 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index b19a1f7..c2d15212 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
- OMAP24XX_CM_IDLEST_VAL, clk->name);
+ OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
/*
* REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 3d9d746..da03fa4 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
{
const struct prcm_config *ptr;
- long highest_rate;
+ long highest_rate, sys_clk_rate;
highest_rate = -EINVAL;
+ sys_clk_rate = __clk_get_rate(sclk);
for (ptr = rate_table; ptr->mpu_speed; ptr++) {
if (!(ptr->flags & cpu_mask))
continue;
- if (ptr->xtal_speed != sclk->rate)
+ if (ptr->xtal_speed != sys_clk_rate)
continue;
highest_rate = ptr->mpu_speed;
@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
const struct prcm_config *prcm;
unsigned long found_speed = 0;
unsigned long flags;
+ long sys_clk_rate;
+
+ sys_clk_rate = __clk_get_rate(sclk);
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
if (!(prcm->flags & cpu_mask))
continue;
- if (prcm->xtal_speed != sclk->rate)
+ if (prcm->xtal_speed != sys_clk_rate)
continue;
if (prcm->mpu_speed <= rate) {
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index d6e34dd..51601db 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
struct omap_sdrc_params *sdrc_cs0;
struct omap_sdrc_params *sdrc_cs1;
int ret;
+ unsigned long clkrate;
if (!clk || !rate)
return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (validrate != rate)
return -EINVAL;
- sdrcrate = sdrc_ick_p->rate;
- if (rate > clk->rate)
- sdrcrate <<= ((rate / clk->rate) >> 1);
+ sdrcrate = __clk_get_rate(sdrc_ick_p);
+ clkrate = __clk_get_rate(clk);
+ if (rate > clkrate)
+ sdrcrate <<= ((rate / clkrate) >> 1);
else
- sdrcrate >>= ((clk->rate / rate) >> 1);
+ sdrcrate >>= ((clkrate / rate) >> 1);
ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
/*
* XXX This only needs to be done when the CPU frequency changes
*/
- _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+ _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
c += 1; /* for safety */
c *= SDRC_MPURATE_LOOPS;
@@ -90,7 +92,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (c == 0)
c = 1;
- pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+ pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clkrate,
validrate);
pr_debug("clock: SDRC CS0 timing params used:"
" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
@@ -104,14 +106,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (sdrc_cs1)
omap3_configure_core_dpll(
- new_div, unlock_dll, c, rate > clk->rate,
+ new_div, unlock_dll, c, rate > clkrate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
else
omap3_configure_core_dpll(
- new_div, unlock_dll, c, rate > clk->rate,
+ new_div, unlock_dll, c, rate > clkrate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
0, 0, 0, 0);
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 04d551b..ffa8e51 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -71,8 +71,8 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
if (!clks->parent) {
/* This indicates a data problem */
- WARN(1, "clock: Could not find parent clock %s in clksel array "
- "of clock %s\n", src_clk->name, clk->name);
+ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
+ __clk_get_name(clk), __clk_get_name(src_clk));
return NULL;
}
@@ -126,8 +126,9 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
if (max_div == 0) {
/* This indicates an error in the clksel data */
- WARN(1, "clock: Could not find divisor for clock %s parent %s"
- "\n", clk->name, src_clk->parent->name);
+ WARN(1, "clock: %s: could not find divisor for parent %s\n",
+ __clk_get_name(clk),
+ __clk_get_name(__clk_get_parent(src_clk)));
return 0;
}
@@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
{
const struct clksel *clks;
const struct clksel_rate *clkr;
+ struct clk *parent;
- clks = _get_clksel_by_parent(clk, clk->parent);
+ parent = __clk_get_parent(clk);
+ clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return 0;
@@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
if (!clkr->div) {
/* This indicates a data error */
- WARN(1, "clock: Could not find fieldval %d for clock %s parent "
- "%s\n", field_val, clk->name, clk->parent->name);
+ WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
+ __clk_get_name(clk), field_val, __clk_get_name(parent));
return 0;
}
@@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
{
const struct clksel *clks;
const struct clksel_rate *clkr;
+ struct clk *parent;
/* should never happen */
WARN_ON(div == 0);
- clks = _get_clksel_by_parent(clk, clk->parent);
+ parent = __clk_get_parent(clk);
+ clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return ~0;
@@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
}
if (!clkr->div) {
- pr_err("clock: Could not find divisor %d for clock %s parent "
- "%s\n", div, clk->name, clk->parent->name);
+ pr_err("clock: %s: could not find divisor %d for parent %s\n",
+ __clk_get_name(clk), div, __clk_get_name(parent));
return ~0;
}
@@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
const struct clksel *clks;
const struct clksel_rate *clkr;
u32 last_div = 0;
+ struct clk *parent;
+ unsigned long parent_rate;
+ const char *clk_name;
+
+ parent = __clk_get_parent(clk);
+ parent_rate = __clk_get_rate(parent);
+ clk_name = __clk_get_name(clk);
if (!clk->clksel || !clk->clksel_mask)
return ~0;
pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
- clk->name, target_rate);
+ clk_name, target_rate);
*new_div = 1;
- clks = _get_clksel_by_parent(clk, clk->parent);
+ clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return ~0;
@@ -300,30 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
/* Sanity check */
if (clkr->div <= last_div)
- pr_err("clock: clksel_rate table not sorted "
- "for clock %s", clk->name);
+ pr_err("clock: %s: clksel_rate table not sorted\n",
+ clk_name);
last_div = clkr->div;
- test_rate = clk->parent->rate / clkr->div;
+ test_rate = parent_rate / clkr->div;
if (test_rate <= target_rate)
break; /* found it */
}
if (!clkr->div) {
- pr_err("clock: Could not find divisor for target "
- "rate %ld for clock %s parent %s\n", target_rate,
- clk->name, clk->parent->name);
+ pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
+ clk_name, target_rate, __clk_get_name(parent));
return ~0;
}
*new_div = clkr->div;
pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
- (clk->parent->rate / clkr->div));
+ (parent_rate / clkr->div));
- return clk->parent->rate / clkr->div;
+ return parent_rate / clkr->div;
}
/*
@@ -345,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
const struct clksel *clks;
const struct clksel_rate *clkr;
u32 r, found = 0;
+ struct clk *parent;
+ const char *clk_name;
if (!clk->clksel || !clk->clksel_mask)
return;
+ parent = __clk_get_parent(clk);
+ clk_name = __clk_get_name(clk);
+
r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
r >>= __ffs(clk->clksel_mask);
@@ -358,12 +374,14 @@ void omap2_init_clksel_parent(struct clk *clk)
continue;
if (clkr->val == r) {
- if (clk->parent != clks->parent) {
+ if (parent != clks->parent) {
pr_debug("clock: inited %s parent "
"to %s (was %s)\n",
- clk->name, clks->parent->name,
- ((clk->parent) ?
- clk->parent->name : "NULL"));
+ clk_name,
+ __clk_get_name(clks->parent),
+ ((parent) ?
+ __clk_get_name(parent) :
+ "NULL"));
clk_reparent(clk, clks->parent);
};
found = 1;
@@ -373,7 +391,7 @@ void omap2_init_clksel_parent(struct clk *clk)
/* This indicates a data error */
WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
- clk->name, r);
+ clk_name, r);
return;
}
@@ -391,14 +409,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
{
unsigned long rate;
u32 div = 0;
+ struct clk *parent;
div = _read_divisor(clk);
if (div == 0)
- return clk->rate;
+ return __clk_get_rate(clk);
- rate = clk->parent->rate / div;
+ parent = __clk_get_parent(clk);
+ rate = __clk_get_rate(parent) / div;
- pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
+ pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
+ __clk_get_name(clk),
rate, div);
return rate;
@@ -454,9 +475,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
_write_clksel_reg(clk, field_val);
- clk->rate = clk->parent->rate / new_div;
+ clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
- pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
+ pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
+ __clk_get_rate(clk));
return 0;
}
@@ -498,13 +520,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
clk_reparent(clk, new_parent);
/* CLKSEL clocks follow their parents' rates, divided by a divisor */
- clk->rate = new_parent->rate;
+ clk->rate = __clk_get_rate(new_parent);
if (parent_div > 0)
- clk->rate /= parent_div;
+ __clk_get_rate(clk) /= parent_div;
pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
- clk->name, clk->parent->name, clk->rate);
+ __clk_get_name(clk),
+ __clk_get_name(__clk_get_parent(clk)),
+ __clk_get_rate(clk));
return 0;
}
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cd7fd0f..6a8a012 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
dd = clk->dpll_data;
/* DPLL divider must result in a valid jitter correction val */
- fint = clk->parent->rate / n;
+ fint = __clk_get_rate(__clk_get_parent(clk)) / n;
if (cpu_is_omap24xx()) {
/* Should not be called for OMAP2, so warn if it is called */
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
if (cpu_is_omap24xx()) {
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
- return dd->clk_bypass->rate;
+ return __clk_get_rate(dd->clk_bypass);
} else if (cpu_is_omap34xx()) {
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
- return dd->clk_bypass->rate;
+ return __clk_get_rate(dd->clk_bypass);
} else if (cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
- return dd->clk_bypass->rate;
+ return __clk_get_rate(dd->clk_bypass);
}
v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
dpll_div = v & dd->div1_mask;
dpll_div >>= __ffs(dd->div1_mask);
- dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+ dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
do_div(dpll_clk, dpll_div + 1);
return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
unsigned long scaled_rt_rp;
unsigned long new_rate = 0;
struct dpll_data *dd;
+ unsigned long ref_rate;
+ const char *clk_name;
if (!clk || !clk->dpll_data)
return ~0;
dd = clk->dpll_data;
+ ref_rate = __clk_get_rate(dd->clk_ref);
+ clk_name = __clk_get_name(clk);
pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
- clk->name, target_rate);
+ clk_name, target_rate);
- scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+ scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
break;
r = _dpll_test_mult(&m, n, &new_rate, target_rate,
- dd->clk_ref->rate);
+ ref_rate);
/* m can't be set low enough for this n - try with a larger n */
if (r == DPLL_MULT_UNDERFLOW)
continue;
pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
- clk->name, m, n, new_rate);
+ clk_name, m, n, new_rate);
if (target_rate == new_rate) {
dd->last_rounded_m = m;
@@ -350,7 +354,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
}
if (target_rate != new_rate) {
- pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
+ pr_debug("clock: %s: cannot round to rate %ld\n", clk_name,
target_rate);
return ~0;
}
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ea3f565..5083d72 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -76,7 +76,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
- clk->name);
+ __clk_get_name(clk));
}
/* Public functions */
@@ -92,18 +92,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
void omap2_init_clk_clkdm(struct clk *clk)
{
struct clockdomain *clkdm;
+ const char *clk_name;
if (!clk->clkdm_name)
return;
+ clk_name = __clk_get_name(clk);
+
clkdm = clkdm_lookup(clk->clkdm_name);
if (clkdm) {
pr_debug("clock: associated clk %s to clkdm %s\n",
- clk->name, clk->clkdm_name);
+ clk_name, clk->clkdm_name);
clk->clkdm = clkdm;
} else {
- pr_debug("clock: could not associate clk %s to "
- "clkdm %s\n", clk->name, clk->clkdm_name);
+ pr_debug("clock: could not associate clk %s to clkdm %s\n",
+ clk_name, clk->clkdm_name);
}
}
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index b9c8d2f..47c2bf7 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
const struct dpll_data *dd;
int i = 0;
int ret = -EINVAL;
+ const char *clk_name;
dd = clk->dpll_data;
+ clk_name = __clk_get_name(clk);
state <<= __ffs(dd->idlest_mask);
@@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
if (i == MAX_DPLL_WAIT_TRIES) {
printk(KERN_ERR "clock: %s failed transition to '%s'\n",
- clk->name, (state) ? "locked" : "bypassed");
+ clk_name, (state) ? "locked" : "bypassed");
} else {
pr_debug("clock: %s transition to '%s' in %d loops\n",
- clk->name, (state) ? "locked" : "bypassed", i);
+ clk_name, (state) ? "locked" : "bypassed", i);
ret = 0;
}
@@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
unsigned long fint;
u16 f = 0;
- fint = clk->dpll_data->clk_ref->rate / n;
+ fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
pr_debug("clock: fint is %lu\n", fint);
@@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
u8 state = 1;
int r = 0;
- pr_debug("clock: locking DPLL %s\n", clk->name);
+ pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
dd = clk->dpll_data;
state <<= __ffs(dd->idlest_mask);
@@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
return -EINVAL;
pr_debug("clock: configuring DPLL %s for low-power bypass\n",
- clk->name);
+ __clk_get_name(clk));
ai = omap3_dpll_autoidle_read(clk);
@@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
return -EINVAL;
- pr_debug("clock: stopping DPLL %s\n", clk->name);
+ pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
ai = omap3_dpll_autoidle_read(clk);
@@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
{
unsigned long fint, clkinp; /* watch out for overflow */
- clkinp = clk->parent->rate;
+ clkinp = __clk_get_rate(__clk_get_parent(clk));
fint = (clkinp / n) * m;
if (fint < 1000000000)
@@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
unsigned long clkinp, sd; /* watch out for overflow */
int mod1, mod2;
- clkinp = clk->parent->rate;
+ clkinp = __clk_get_rate(__clk_get_parent(clk));
/*
* target sigma-delta to near 250MHz
@@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
{
int r;
struct dpll_data *dd;
+ struct clk *parent;
dd = clk->dpll_data;
if (!dd)
return -EINVAL;
- if (clk->rate == dd->clk_bypass->rate) {
- WARN_ON(clk->parent != dd->clk_bypass);
+ parent = __clk_get_parent(clk);
+
+ if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
+ WARN_ON(parent != dd->clk_bypass);
r = _omap3_noncore_dpll_bypass(clk);
} else {
- WARN_ON(clk->parent != dd->clk_ref);
+ WARN_ON(parent != dd->clk_ref);
r = _omap3_noncore_dpll_lock(clk);
}
/*
@@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
{
struct clk *new_parent = NULL;
- unsigned long hw_rate;
+ unsigned long hw_rate, bypass_rate;
u16 freqsel = 0;
struct dpll_data *dd;
int ret;
@@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
omap2_clk_enable(dd->clk_bypass);
omap2_clk_enable(dd->clk_ref);
- if (dd->clk_bypass->rate == rate &&
+ bypass_rate = __clk_get_rate(dd->clk_bypass);
+ if (bypass_rate == rate &&
(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
@@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
}
pr_debug("clock: %s: set rate: locking rate to %lu.\n",
- clk->name, rate);
+ __clk_get_name(clk), rate);
ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
dd->last_rounded_n, freqsel);
@@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
- clk->name);
+ __clk_get_name(clk));
return;
}
@@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
- clk->name);
+ __clk_get_name(clk));
return;
}
@@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
unsigned long rate;
u32 v;
struct clk *pclk;
+ unsigned long parent_rate;
/* Walk up the parents of clk, looking for a DPLL */
- pclk = clk->parent;
+ pclk = __clk_get_parent(clk);
while (pclk && !pclk->dpll_data)
- pclk = pclk->parent;
+ pclk = __clk_get_parent(pclk);
/* clk does not have a DPLL as a parent? */
WARN_ON(!pclk);
@@ -630,12 +637,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
WARN_ON(!dd->enable_mask);
+ parent_rate = __clk_get_rate(__clk_get_parent(clk));
v = __raw_readl(dd->control_reg) & dd->enable_mask;
v >>= __ffs(dd->enable_mask);
if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
- rate = clk->parent->rate;
+ rate = parent_rate;
else
- rate = clk->parent->rate * 2;
+ rate = parent_rate * 2;
return rate;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ca8e51..d730e62 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -686,7 +686,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
if (!oh->_clk->clkdm)
pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
- oh->main_clk, oh->_clk->name);
+ oh->name, oh->main_clk);
return ret;
}
@@ -825,7 +825,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk) {
pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
- oc->_clk->name);
+ __clk_get_name(oc->_clk));
clk_enable(oc->_clk);
}
}
@@ -840,7 +840,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk) {
pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
- oc->_clk->name);
+ __clk_get_name(oc->_clk));
clk_disable(oc->_clk);
}
}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5ced..40012e3 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -188,7 +188,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
goto exit;
}
- freq = clk->rate;
+ freq = clk_get_rate(clk);
clk_put(clk);
rcu_read_lock();
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 656b986..e2e2d04 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -19,6 +19,11 @@ struct module;
struct clk;
struct clockdomain;
+/* Temporary, needed during the common clock framework conversion */
+#define __clk_get_name(clk) (clk->name)
+#define __clk_get_parent(clk) (clk->parent)
+#define __clk_get_rate(clk) (clk->rate)
+
/**
* struct clkops - some clock function pointers
* @enable: fn ptr that enables the current clock in hardware
--
1.7.10.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/3] ARM: omap: clk: Remove all direct dereferencing of struct clk
2012-07-30 7:12 ` Paul Walmsley
@ 2012-07-30 7:36 ` Rajendra Nayak
2012-07-30 18:56 ` Paul Walmsley
0 siblings, 1 reply; 16+ messages in thread
From: Rajendra Nayak @ 2012-07-30 7:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi Paul,
On Monday 30 July 2012 12:42 PM, Paul Walmsley wrote:
> Hi Rajendra
>
> On Mon, 2 Jul 2012, Rajendra Nayak wrote:
>
>> While we move to Common Clk Framework (CCF), direct deferencing of
>> struct clk wouldn't be possible anymore. Hence get rid of all such
>> instances in the current clock code and use macros/helpers similar
>> to the ones that are provided by CCF.
>>
>> While here also concatenate some strings split across multiple
>> lines which seem to be needed anyway.
>>
>> Signed-off-by: Rajendra Nayak<rnayak@ti.com>
>
> This one has some checkpatch warnings:
>
> WARNING: quoted string split across lines #482: FILE:
> arch/arm/mach-omap2/clock.c:109: pr_debug("clock: could not associate
> clk %s to " + "clkdm %s\n", clk_name, clk->clkdm_name);
Are you sure you are using the v3 of this patch? You already mentioned
about these in the v2 [1] and I fixed all these in v3. I went back and
looked at the v3 of this patch, and it does not complain me about any
of these warnings or errors.
regards,
Rajendra
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-July/107103.html
>
> ERROR: Macros with complex values should be enclosed in parenthesis
> #709: FILE: arch/arm/plat-omap/include/plat/clock.h:22: +#define
> __clk_get_name(clk) clk->name
>
> ERROR: Macros with complex values should be enclosed in parenthesis
> #710: FILE: arch/arm/plat-omap/include/plat/clock.h:23: +#define
> __clk_get_parent(clk) clk->parent
>
> ... etc.
>
> These have been fixed in the version below, and a few other minor
> changes made. The patch below has been queued for 3.7. Please don't
> forget to make sure a patch doesn't cause checkpatch.pl warnings
> before posting.
>
>
> - Paul
>
> From: Rajendra Nayak<rnayak@ti.com> Date: Wed, 27 Jun 2012 14:18:35
> +0530 Subject: [PATCH] ARM: OMAP2+: clk: Remove all direct
> dereferencing of struct clk
>
> While we move to Common Clk Framework (CCF), direct deferencing of
> struct clk wouldn't be possible anymore. Hence get rid of all such
> instances in the current clock code and use macros/helpers similar to
> the ones that are provided by CCF.
>
> Signed-off-by: Rajendra Nayak<rnayak@ti.com> [paul at pwsan.com:
> simplified some compound expressions; resolved checkpatch warnings;
> reformatted some messages] Signed-off-by: Paul
> Walmsley<paul@pwsan.com> Cc: Mike Turquette<mturquette@linaro.org>
> --- arch/arm/mach-omap2/clkt2xxx_apll.c | 2 +-
> arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 10 ++-
> arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 18 +++---
> arch/arm/mach-omap2/clkt_clksel.c | 90
> ++++++++++++++++---------- arch/arm/mach-omap2/clkt_dpll.c
> | 24 ++++--- arch/arm/mach-omap2/clock.c | 11
> ++-- arch/arm/mach-omap2/dpll3xxx.c | 48
> ++++++++------ arch/arm/mach-omap2/omap_hwmod.c | 6
> +- arch/arm/mach-omap2/pm.c | 2 +-
> arch/arm/plat-omap/include/plat/clock.h | 5 ++ 10 files
> changed, 133 insertions(+), 83 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c
> b/arch/arm/mach-omap2/clkt2xxx_apll.c index b19a1f7..c2d15212 100644
> --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++
> b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -59,7 +59,7 @@ static int
> omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
> omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
>
> omap2_cm_wait_idlest(cm_idlest_pll, status_mask, -
> OMAP24XX_CM_IDLEST_VAL, clk->name); + OMAP24XX_CM_IDLEST_VAL,
> __clk_get_name(clk));
>
> /* * REVISIT: Should we return an error code if
> omap2_wait_clock_ready() diff --git
> a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 3d9d746..da03fa4
> 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++
> b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -68,14 +68,15 @@
> unsigned long omap2_table_mpu_recalc(struct clk *clk) long
> omap2_round_to_table_rate(struct clk *clk, unsigned long rate) {
> const struct prcm_config *ptr; - long highest_rate; + long
> highest_rate, sys_clk_rate;
>
> highest_rate = -EINVAL; + sys_clk_rate = __clk_get_rate(sclk);
>
> for (ptr = rate_table; ptr->mpu_speed; ptr++) { if (!(ptr->flags&
> cpu_mask)) continue; - if (ptr->xtal_speed != sclk->rate) + if
> (ptr->xtal_speed != sys_clk_rate) continue;
>
> highest_rate = ptr->mpu_speed; @@ -94,12 +95,15 @@ int
> omap2_select_table_rate(struct clk *clk, unsigned long rate) const
> struct prcm_config *prcm; unsigned long found_speed = 0; unsigned
> long flags; + long sys_clk_rate; + + sys_clk_rate =
> __clk_get_rate(sclk);
>
> for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags&
> cpu_mask)) continue;
>
> - if (prcm->xtal_speed != sclk->rate) + if (prcm->xtal_speed !=
> sys_clk_rate) continue;
>
> if (prcm->mpu_speed<= rate) { diff --git
> a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
> b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index d6e34dd..51601db
> 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++
> b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -56,6 +56,7 @@ int
> omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
> struct omap_sdrc_params *sdrc_cs0; struct omap_sdrc_params
> *sdrc_cs1; int ret; + unsigned long clkrate;
>
> if (!clk || !rate) return -EINVAL; @@ -64,11 +65,12 @@ int
> omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if
> (validrate != rate) return -EINVAL;
>
> - sdrcrate = sdrc_ick_p->rate; - if (rate> clk->rate) - sdrcrate<<=
> ((rate / clk->rate)>> 1); + sdrcrate = __clk_get_rate(sdrc_ick_p); +
> clkrate = __clk_get_rate(clk); + if (rate> clkrate) + sdrcrate<<=
> ((rate / clkrate)>> 1); else - sdrcrate>>= ((clk->rate / rate)>>
> 1); + sdrcrate>>= ((clkrate / rate)>> 1);
>
> ret = omap2_sdrc_get_params(sdrcrate,&sdrc_cs0,&sdrc_cs1); if (ret)
> @@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk,
> unsigned long rate) /* * XXX This only needs to be done when the CPU
> frequency changes */ - _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; +
> _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ; c =
> (_mpurate<< SDRC_MPURATE_SCALE)>> SDRC_MPURATE_BASE_SHIFT; c += 1;
> /* for safety */ c *= SDRC_MPURATE_LOOPS; @@ -90,7 +92,7 @@ int
> omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if
> (c == 0) c = 1;
>
> - pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
> clk->rate, + pr_debug("clock: changing CORE DPLL rate from %lu to
> %lu\n", clkrate, validrate); pr_debug("clock: SDRC CS0 timing params
> used:" " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", @@ -104,14
> +106,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned
> long rate)
>
> if (sdrc_cs1) omap3_configure_core_dpll( - new_div, unlock_dll,
> c, rate> clk->rate, + new_div, unlock_dll, c, rate> clkrate,
> sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb,
> sdrc_cs0->mr, sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
> sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); else
> omap3_configure_core_dpll( - new_div, unlock_dll, c, rate>
> clk->rate, + new_div, unlock_dll, c, rate> clkrate,
> sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb,
> sdrc_cs0->mr, 0, 0, 0, 0); diff --git
> a/arch/arm/mach-omap2/clkt_clksel.c
> b/arch/arm/mach-omap2/clkt_clksel.c index 04d551b..ffa8e51 100644 ---
> a/arch/arm/mach-omap2/clkt_clksel.c +++
> b/arch/arm/mach-omap2/clkt_clksel.c @@ -71,8 +71,8 @@ static const
> struct clksel *_get_clksel_by_parent(struct clk *clk,
>
> if (!clks->parent) { /* This indicates a data problem */ - WARN(1,
> "clock: Could not find parent clock %s in clksel array " - "of
> clock %s\n", src_clk->name, clk->name); + WARN(1, "clock: %s: could
> not find parent clock %s in clksel array\n", +
> __clk_get_name(clk), __clk_get_name(src_clk)); return NULL; }
>
> @@ -126,8 +126,9 @@ static u8 _get_div_and_fieldval(struct clk
> *src_clk, struct clk *clk,
>
> if (max_div == 0) { /* This indicates an error in the clksel data */
> - WARN(1, "clock: Could not find divisor for clock %s parent %s" -
> "\n", clk->name, src_clk->parent->name); + WARN(1, "clock: %s: could
> not find divisor for parent %s\n", + __clk_get_name(clk), +
> __clk_get_name(__clk_get_parent(src_clk))); return 0; }
>
> @@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk,
> u32 field_val) { const struct clksel *clks; const struct clksel_rate
> *clkr; + struct clk *parent;
>
> - clks = _get_clksel_by_parent(clk, clk->parent); + parent =
> __clk_get_parent(clk); + clks = _get_clksel_by_parent(clk, parent);
> if (!clks) return 0;
>
> @@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk,
> u32 field_val)
>
> if (!clkr->div) { /* This indicates a data error */ - WARN(1,
> "clock: Could not find fieldval %d for clock %s parent " -
> "%s\n", field_val, clk->name, clk->parent->name); + WARN(1, "clock:
> %s: could not find fieldval %d for parent %s\n", +
> __clk_get_name(clk), field_val, __clk_get_name(parent)); return 0; }
>
> @@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk,
> u32 div) { const struct clksel *clks; const struct clksel_rate
> *clkr; + struct clk *parent;
>
> /* should never happen */ WARN_ON(div == 0);
>
> - clks = _get_clksel_by_parent(clk, clk->parent); + parent =
> __clk_get_parent(clk); + clks = _get_clksel_by_parent(clk, parent);
> if (!clks) return ~0;
>
> @@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk,
> u32 div) }
>
> if (!clkr->div) { - pr_err("clock: Could not find divisor %d for
> clock %s parent " - "%s\n", div, clk->name,
> clk->parent->name); + pr_err("clock: %s: could not find divisor %d
> for parent %s\n", + __clk_get_name(clk), div,
> __clk_get_name(parent)); return ~0; }
>
> @@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk
> *clk, unsigned long target_rate, const struct clksel *clks; const
> struct clksel_rate *clkr; u32 last_div = 0; + struct clk *parent; +
> unsigned long parent_rate; + const char *clk_name; + + parent =
> __clk_get_parent(clk); + parent_rate = __clk_get_rate(parent); +
> clk_name = __clk_get_name(clk);
>
> if (!clk->clksel || !clk->clksel_mask) return ~0;
>
> pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", -
> clk->name, target_rate); + clk_name, target_rate);
>
> *new_div = 1;
>
> - clks = _get_clksel_by_parent(clk, clk->parent); + clks =
> _get_clksel_by_parent(clk, parent); if (!clks) return ~0;
>
> @@ -300,30 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk
> *clk, unsigned long target_rate,
>
> /* Sanity check */ if (clkr->div<= last_div) - pr_err("clock:
> clksel_rate table not sorted " - "for clock %s",
> clk->name); + pr_err("clock: %s: clksel_rate table not sorted\n", +
> clk_name);
>
> last_div = clkr->div;
>
> - test_rate = clk->parent->rate / clkr->div; + test_rate =
> parent_rate / clkr->div;
>
> if (test_rate<= target_rate) break; /* found it */ }
>
> if (!clkr->div) { - pr_err("clock: Could not find divisor for target
> " - "rate %ld for clock %s parent %s\n", target_rate, -
> clk->name, clk->parent->name); + pr_err("clock: %s: could not find
> divisor for target rate %ld for parent %s\n", + clk_name,
> target_rate, __clk_get_name(parent)); return ~0; }
>
> *new_div = clkr->div;
>
> pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, -
> (clk->parent->rate / clkr->div)); + (parent_rate / clkr->div));
>
> - return clk->parent->rate / clkr->div; + return parent_rate /
> clkr->div; }
>
> /* @@ -345,10 +356,15 @@ void omap2_init_clksel_parent(struct clk
> *clk) const struct clksel *clks; const struct clksel_rate *clkr; u32
> r, found = 0; + struct clk *parent; + const char *clk_name;
>
> if (!clk->clksel || !clk->clksel_mask) return;
>
> + parent = __clk_get_parent(clk); + clk_name = __clk_get_name(clk);
> + r = __raw_readl(clk->clksel_reg)& clk->clksel_mask; r>>=
> __ffs(clk->clksel_mask);
>
> @@ -358,12 +374,14 @@ void omap2_init_clksel_parent(struct clk *clk)
> continue;
>
> if (clkr->val == r) { - if (clk->parent != clks->parent) { + if
> (parent != clks->parent) { pr_debug("clock: inited %s parent " "to %s
> (was %s)\n", - clk->name, clks->parent->name, -
> ((clk->parent) ? - clk->parent->name : "NULL")); +
> clk_name, + __clk_get_name(clks->parent), + ((parent) ? +
> __clk_get_name(parent) : + "NULL")); clk_reparent(clk,
> clks->parent); }; found = 1; @@ -373,7 +391,7 @@ void
> omap2_init_clksel_parent(struct clk *clk)
>
> /* This indicates a data error */ WARN(!found, "clock: %s: init
> parent: could not find regval %0x\n", - clk->name, r); +
> clk_name, r);
>
> return; } @@ -391,14 +409,17 @@ unsigned long
> omap2_clksel_recalc(struct clk *clk) { unsigned long rate; u32 div =
> 0; + struct clk *parent;
>
> div = _read_divisor(clk); if (div == 0) - return clk->rate; +
> return __clk_get_rate(clk);
>
> - rate = clk->parent->rate / div; + parent = __clk_get_parent(clk); +
> rate = __clk_get_rate(parent) / div;
>
> - pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name, +
> pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", +
> __clk_get_name(clk), rate, div);
>
> return rate; @@ -454,9 +475,10 @@ int omap2_clksel_set_rate(struct
> clk *clk, unsigned long rate)
>
> _write_clksel_reg(clk, field_val);
>
> - clk->rate = clk->parent->rate / new_div; + clk->rate =
> __clk_get_rate(__clk_get_parent(clk)) / new_div;
>
> - pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate); +
> pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk), +
> __clk_get_rate(clk));
>
> return 0; } @@ -498,13 +520,15 @@ int omap2_clksel_set_parent(struct
> clk *clk, struct clk *new_parent) clk_reparent(clk, new_parent);
>
> /* CLKSEL clocks follow their parents' rates, divided by a divisor
> */ - clk->rate = new_parent->rate; + clk->rate =
> __clk_get_rate(new_parent);
>
> if (parent_div> 0) - clk->rate /= parent_div; +
> __clk_get_rate(clk) /= parent_div;
>
> pr_debug("clock: %s: set parent to %s (new rate %ld)\n", -
> clk->name, clk->parent->name, clk->rate); + __clk_get_name(clk), +
> __clk_get_name(__clk_get_parent(clk)), + __clk_get_rate(clk));
>
> return 0; } diff --git a/arch/arm/mach-omap2/clkt_dpll.c
> b/arch/arm/mach-omap2/clkt_dpll.c index cd7fd0f..6a8a012 100644 ---
> a/arch/arm/mach-omap2/clkt_dpll.c +++
> b/arch/arm/mach-omap2/clkt_dpll.c @@ -87,7 +87,7 @@ static int
> _dpll_test_fint(struct clk *clk, u8 n) dd = clk->dpll_data;
>
> /* DPLL divider must result in a valid jitter correction val */ -
> fint = clk->parent->rate / n; + fint =
> __clk_get_rate(__clk_get_parent(clk)) / n;
>
> if (cpu_is_omap24xx()) { /* Should not be called for OMAP2, so warn
> if it is called */ @@ -252,16 +252,16 @@ u32
> omap2_get_dpll_rate(struct clk *clk) if (cpu_is_omap24xx()) { if (v
> == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) -
> return dd->clk_bypass->rate; + return
> __clk_get_rate(dd->clk_bypass); } else if (cpu_is_omap34xx()) { if (v
> == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) -
> return dd->clk_bypass->rate; + return
> __clk_get_rate(dd->clk_bypass); } else if (cpu_is_omap44xx()) { if (v
> == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v
> == OMAP4XXX_EN_DPLL_MNBYPASS) - return dd->clk_bypass->rate; +
> return __clk_get_rate(dd->clk_bypass); }
>
> v = __raw_readl(dd->mult_div1_reg); @@ -270,7 +270,7 @@ u32
> omap2_get_dpll_rate(struct clk *clk) dpll_div = v& dd->div1_mask;
> dpll_div>>= __ffs(dd->div1_mask);
>
> - dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; + dpll_clk =
> (long long) __clk_get_rate(dd->clk_ref) * dpll_mult; do_div(dpll_clk,
> dpll_div + 1);
>
> return dpll_clk; @@ -296,16 +296,20 @@ long
> omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
> unsigned long scaled_rt_rp; unsigned long new_rate = 0; struct
> dpll_data *dd; + unsigned long ref_rate; + const char *clk_name;
>
> if (!clk || !clk->dpll_data) return ~0;
>
> dd = clk->dpll_data;
>
> + ref_rate = __clk_get_rate(dd->clk_ref); + clk_name =
> __clk_get_name(clk); pr_debug("clock: %s: starting DPLL round_rate,
> target rate %ld\n", - clk->name, target_rate); + clk_name,
> target_rate);
>
> - scaled_rt_rp = target_rate / (dd->clk_ref->rate /
> DPLL_SCALE_FACTOR); + scaled_rt_rp = target_rate / (ref_rate /
> DPLL_SCALE_FACTOR); scaled_max_m = dd->max_multiplier *
> DPLL_SCALE_FACTOR;
>
> dd->last_rounded_rate = 0; @@ -332,14 +336,14 @@ long
> omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
> break;
>
> r = _dpll_test_mult(&m, n,&new_rate, target_rate, -
> dd->clk_ref->rate); + ref_rate);
>
> /* m can't be set low enough for this n - try with a larger n */ if
> (r == DPLL_MULT_UNDERFLOW) continue;
>
> pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n", -
> clk->name, m, n, new_rate); + clk_name, m, n, new_rate);
>
> if (target_rate == new_rate) { dd->last_rounded_m = m; @@ -350,7
> +354,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long
> target_rate) }
>
> if (target_rate != new_rate) { - pr_debug("clock: %s: cannot round
> to rate %ld\n", clk->name, + pr_debug("clock: %s: cannot round to
> rate %ld\n", clk_name, target_rate); return ~0; } diff --git
> a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index
> ea3f565..5083d72 100644 --- a/arch/arm/mach-omap2/clock.c +++
> b/arch/arm/mach-omap2/clock.c @@ -76,7 +76,7 @@ static void
> _omap2_module_wait_ready(struct clk *clk)
> clk->ops->find_idlest(clk,&idlest_reg,&idlest_bit,&idlest_val);
>
> omap2_cm_wait_idlest(idlest_reg, (1<< idlest_bit), idlest_val, -
> clk->name); + __clk_get_name(clk)); }
>
> /* Public functions */ @@ -92,18 +92,21 @@ static void
> _omap2_module_wait_ready(struct clk *clk) void
> omap2_init_clk_clkdm(struct clk *clk) { struct clockdomain *clkdm; +
> const char *clk_name;
>
> if (!clk->clkdm_name) return;
>
> + clk_name = __clk_get_name(clk); + clkdm =
> clkdm_lookup(clk->clkdm_name); if (clkdm) { pr_debug("clock:
> associated clk %s to clkdm %s\n", - clk->name, clk->clkdm_name); +
> clk_name, clk->clkdm_name); clk->clkdm = clkdm; } else { -
> pr_debug("clock: could not associate clk %s to " - "clkdm %s\n",
> clk->name, clk->clkdm_name); + pr_debug("clock: could not associate
> clk %s to clkdm %s\n", + clk_name, clk->clkdm_name); } }
>
> diff --git a/arch/arm/mach-omap2/dpll3xxx.c
> b/arch/arm/mach-omap2/dpll3xxx.c index b9c8d2f..47c2bf7 100644 ---
> a/arch/arm/mach-omap2/dpll3xxx.c +++
> b/arch/arm/mach-omap2/dpll3xxx.c @@ -63,8 +63,10 @@ static int
> _omap3_wait_dpll_status(struct clk *clk, u8 state) const struct
> dpll_data *dd; int i = 0; int ret = -EINVAL; + const char *clk_name;
>
> dd = clk->dpll_data; + clk_name = __clk_get_name(clk);
>
> state<<= __ffs(dd->idlest_mask);
>
> @@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk
> *clk, u8 state)
>
> if (i == MAX_DPLL_WAIT_TRIES) { printk(KERN_ERR "clock: %s failed
> transition to '%s'\n", - clk->name, (state) ? "locked" :
> "bypassed"); + clk_name, (state) ? "locked" : "bypassed"); }
> else { pr_debug("clock: %s transition to '%s' in %d loops\n", -
> clk->name, (state) ? "locked" : "bypassed", i); + clk_name,
> (state) ? "locked" : "bypassed", i);
>
> ret = 0; } @@ -93,7 +95,7 @@ static u16
> _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) unsigned long
> fint; u16 f = 0;
>
> - fint = clk->dpll_data->clk_ref->rate / n; + fint =
> __clk_get_rate(clk->dpll_data->clk_ref) / n;
>
> pr_debug("clock: fint is %lu\n", fint);
>
> @@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk
> *clk) u8 state = 1; int r = 0;
>
> - pr_debug("clock: locking DPLL %s\n", clk->name); + pr_debug("clock:
> locking DPLL %s\n", __clk_get_name(clk));
>
> dd = clk->dpll_data; state<<= __ffs(dd->idlest_mask); @@ -187,7
> +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
> return -EINVAL;
>
> pr_debug("clock: configuring DPLL %s for low-power bypass\n", -
> clk->name); + __clk_get_name(clk));
>
> ai = omap3_dpll_autoidle_read(clk);
>
> @@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk
> *clk) if (!(clk->dpll_data->modes& (1<< DPLL_LOW_POWER_STOP)))
> return -EINVAL;
>
> - pr_debug("clock: stopping DPLL %s\n", clk->name); +
> pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
>
> ai = omap3_dpll_autoidle_read(clk);
>
> @@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco,
> u16 m, u8 n) { unsigned long fint, clkinp; /* watch out for overflow
> */
>
> - clkinp = clk->parent->rate; + clkinp =
> __clk_get_rate(__clk_get_parent(clk)); fint = (clkinp / n) * m;
>
> if (fint< 1000000000) @@ -271,7 +273,7 @@ static void
> _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) unsigned long
> clkinp, sd; /* watch out for overflow */ int mod1, mod2;
>
> - clkinp = clk->parent->rate; + clkinp =
> __clk_get_rate(__clk_get_parent(clk));
>
> /* * target sigma-delta to near 250MHz @@ -380,16 +382,19 @@ int
> omap3_noncore_dpll_enable(struct clk *clk) { int r; struct dpll_data
> *dd; + struct clk *parent;
>
> dd = clk->dpll_data; if (!dd) return -EINVAL;
>
> - if (clk->rate == dd->clk_bypass->rate) { - WARN_ON(clk->parent !=
> dd->clk_bypass); + parent = __clk_get_parent(clk); + + if
> (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { +
> WARN_ON(parent != dd->clk_bypass); r =
> _omap3_noncore_dpll_bypass(clk); } else { - WARN_ON(clk->parent !=
> dd->clk_ref); + WARN_ON(parent != dd->clk_ref); r =
> _omap3_noncore_dpll_lock(clk); } /* @@ -432,7 +437,7 @@ void
> omap3_noncore_dpll_disable(struct clk *clk) int
> omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) {
> struct clk *new_parent = NULL; - unsigned long hw_rate; + unsigned
> long hw_rate, bypass_rate; u16 freqsel = 0; struct dpll_data *dd; int
> ret; @@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk
> *clk, unsigned long rate) omap2_clk_enable(dd->clk_bypass);
> omap2_clk_enable(dd->clk_ref);
>
> - if (dd->clk_bypass->rate == rate&& + bypass_rate =
> __clk_get_rate(dd->clk_bypass); + if (bypass_rate == rate&&
> (clk->dpll_data->modes& (1<< DPLL_LOW_POWER_BYPASS))) {
> pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
>
> @@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk,
> unsigned long rate) }
>
> pr_debug("clock: %s: set rate: locking rate to %lu.\n", -
> clk->name, rate); + __clk_get_name(clk), rate);
>
> ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
> dd->last_rounded_n, freqsel); @@ -557,7 +563,7 @@ void
> omap3_dpll_allow_idle(struct clk *clk)
>
> if (!dd->autoidle_reg) { pr_debug("clock: DPLL %s: autoidle not
> supported\n", - clk->name); + __clk_get_name(clk)); return; }
>
> @@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
>
> if (!dd->autoidle_reg) { pr_debug("clock: DPLL %s: autoidle not
> supported\n", - clk->name); + __clk_get_name(clk)); return; }
>
> @@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk
> *clk) unsigned long rate; u32 v; struct clk *pclk; + unsigned long
> parent_rate;
>
> /* Walk up the parents of clk, looking for a DPLL */ - pclk =
> clk->parent; + pclk = __clk_get_parent(clk); while (pclk&&
> !pclk->dpll_data) - pclk = pclk->parent; + pclk =
> __clk_get_parent(pclk);
>
> /* clk does not have a DPLL as a parent? */ WARN_ON(!pclk); @@
> -630,12 +637,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk
> *clk)
>
> WARN_ON(!dd->enable_mask);
>
> + parent_rate = __clk_get_rate(__clk_get_parent(clk)); v =
> __raw_readl(dd->control_reg)& dd->enable_mask; v>>=
> __ffs(dd->enable_mask); if ((v != OMAP3XXX_EN_DPLL_LOCKED) ||
> (dd->flags& DPLL_J_TYPE)) - rate = clk->parent->rate; + rate =
> parent_rate; else - rate = clk->parent->rate * 2; + rate =
> parent_rate * 2; return rate; }
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c
> b/arch/arm/mach-omap2/omap_hwmod.c index 6ca8e51..d730e62 100644 ---
> a/arch/arm/mach-omap2/omap_hwmod.c +++
> b/arch/arm/mach-omap2/omap_hwmod.c @@ -686,7 +686,7 @@ static int
> _init_main_clk(struct omap_hwmod *oh)
>
> if (!oh->_clk->clkdm) pr_warning("omap_hwmod: %s: missing clockdomain
> for %s.\n", - oh->main_clk, oh->_clk->name); + oh->name,
> oh->main_clk);
>
> return ret; } @@ -825,7 +825,7 @@ static void
> _enable_optional_clocks(struct omap_hwmod *oh) for (i =
> oh->opt_clks_cnt, oc = oh->opt_clks; i> 0; i--, oc++) if (oc->_clk)
> { pr_debug("omap_hwmod: enable %s:%s\n", oc->role, -
> oc->_clk->name); + __clk_get_name(oc->_clk));
> clk_enable(oc->_clk); } } @@ -840,7 +840,7 @@ static void
> _disable_optional_clocks(struct omap_hwmod *oh) for (i =
> oh->opt_clks_cnt, oc = oh->opt_clks; i> 0; i--, oc++) if (oc->_clk)
> { pr_debug("omap_hwmod: disable %s:%s\n", oc->role, -
> oc->_clk->name); + __clk_get_name(oc->_clk));
> clk_disable(oc->_clk); } } diff --git a/arch/arm/mach-omap2/pm.c
> b/arch/arm/mach-omap2/pm.c index 9cb5ced..40012e3 100644 ---
> a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -188,7
> +188,7 @@ static int __init omap2_set_init_voltage(char *vdd_name,
> char *clk_name, goto exit; }
>
> - freq = clk->rate; + freq = clk_get_rate(clk); clk_put(clk);
>
> rcu_read_lock(); diff --git a/arch/arm/plat-omap/include/plat/clock.h
> b/arch/arm/plat-omap/include/plat/clock.h index 656b986..e2e2d04
> 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++
> b/arch/arm/plat-omap/include/plat/clock.h @@ -19,6 +19,11 @@ struct
> module; struct clk; struct clockdomain;
>
> +/* Temporary, needed during the common clock framework conversion
> */ +#define __clk_get_name(clk) (clk->name) +#define
> __clk_get_parent(clk) (clk->parent) +#define __clk_get_rate(clk)
> (clk->rate) + /** * struct clkops - some clock function pointers *
> @enable: fn ptr that enables the current clock in hardware
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 3/3] ARM: omap: clk: Remove all direct dereferencing of struct clk
2012-07-30 7:36 ` Rajendra Nayak
@ 2012-07-30 18:56 ` Paul Walmsley
2012-07-31 6:05 ` Rajendra Nayak
0 siblings, 1 reply; 16+ messages in thread
From: Paul Walmsley @ 2012-07-30 18:56 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 30 Jul 2012, Rajendra Nayak wrote:
> Are you sure you are using the v3 of this patch? You already mentioned
> about these in the v2 [1] and I fixed all these in v3. I went back and
> looked at the v3 of this patch, and it does not complain me about any
> of these warnings or errors.
Yep that's probably what happened. Here's the updated patch, starting
from your v3.
- Paul
From: Rajendra Nayak <rnayak@ti.com>
Date: Mon, 30 Jul 2012 12:52:55 -0600
Subject: [PATCH] ARM: OMAP2+: clock: Remove all direct dereferencing of
struct clk
While we move to Common Clk Framework (CCF), direct deferencing of struct
clk wouldn't be possible anymore. Hence get rid of all such instances
in the current clock code and use macros/helpers similar to the ones that
are provided by CCF.
While here also concatenate some strings split across multiple lines
which seem to be needed anyway.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul at pwsan.com: simplified some compound expressions; reformatted some
messages]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Mike Turquette <mturquette@linaro.org>
---
arch/arm/mach-omap2/clkt2xxx_apll.c | 2 +-
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 10 ++-
arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 20 +++---
arch/arm/mach-omap2/clkt_clksel.c | 91 ++++++++++++++++----------
arch/arm/mach-omap2/clkt_dpll.c | 26 ++++----
arch/arm/mach-omap2/clock.c | 11 ++--
arch/arm/mach-omap2/dpll3xxx.c | 48 ++++++++------
arch/arm/mach-omap2/omap_hwmod.c | 6 +-
arch/arm/mach-omap2/pm.c | 2 +-
arch/arm/plat-omap/include/plat/clock.h | 5 ++
10 files changed, 135 insertions(+), 86 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index b19a1f7..c2d15212 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
- OMAP24XX_CM_IDLEST_VAL, clk->name);
+ OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
/*
* REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 3d9d746..da03fa4 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
{
const struct prcm_config *ptr;
- long highest_rate;
+ long highest_rate, sys_clk_rate;
highest_rate = -EINVAL;
+ sys_clk_rate = __clk_get_rate(sclk);
for (ptr = rate_table; ptr->mpu_speed; ptr++) {
if (!(ptr->flags & cpu_mask))
continue;
- if (ptr->xtal_speed != sclk->rate)
+ if (ptr->xtal_speed != sys_clk_rate)
continue;
highest_rate = ptr->mpu_speed;
@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
const struct prcm_config *prcm;
unsigned long found_speed = 0;
unsigned long flags;
+ long sys_clk_rate;
+
+ sys_clk_rate = __clk_get_rate(sclk);
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
if (!(prcm->flags & cpu_mask))
continue;
- if (prcm->xtal_speed != sclk->rate)
+ if (prcm->xtal_speed != sys_clk_rate)
continue;
if (prcm->mpu_speed <= rate) {
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index d6e34dd..0fd8b70 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
struct omap_sdrc_params *sdrc_cs0;
struct omap_sdrc_params *sdrc_cs1;
int ret;
+ unsigned long clkrate;
if (!clk || !rate)
return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (validrate != rate)
return -EINVAL;
- sdrcrate = sdrc_ick_p->rate;
- if (rate > clk->rate)
- sdrcrate <<= ((rate / clk->rate) >> 1);
+ sdrcrate = __clk_get_rate(sdrc_ick_p);
+ clkrate = __clk_get_rate(clk);
+ if (rate > clkrate)
+ sdrcrate <<= ((rate / clkrate) >> 1);
else
- sdrcrate >>= ((clk->rate / rate) >> 1);
+ sdrcrate >>= ((clkrate / rate) >> 1);
ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
/*
* XXX This only needs to be done when the CPU frequency changes
*/
- _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+ _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
c += 1; /* for safety */
c *= SDRC_MPURATE_LOOPS;
@@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (c == 0)
c = 1;
- pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
- validrate);
+ pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
+ clkrate, validrate);
pr_debug("clock: SDRC CS0 timing params used:"
" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
@@ -104,14 +106,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (sdrc_cs1)
omap3_configure_core_dpll(
- new_div, unlock_dll, c, rate > clk->rate,
+ new_div, unlock_dll, c, rate > clkrate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
else
omap3_configure_core_dpll(
- new_div, unlock_dll, c, rate > clk->rate,
+ new_div, unlock_dll, c, rate > clkrate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
0, 0, 0, 0);
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 04d551b..33382fb 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -71,8 +71,8 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
if (!clks->parent) {
/* This indicates a data problem */
- WARN(1, "clock: Could not find parent clock %s in clksel array "
- "of clock %s\n", src_clk->name, clk->name);
+ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
+ __clk_get_name(clk), __clk_get_name(src_clk));
return NULL;
}
@@ -126,8 +126,9 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
if (max_div == 0) {
/* This indicates an error in the clksel data */
- WARN(1, "clock: Could not find divisor for clock %s parent %s"
- "\n", clk->name, src_clk->parent->name);
+ WARN(1, "clock: %s: could not find divisor for parent %s\n",
+ __clk_get_name(clk),
+ __clk_get_name(__clk_get_parent(src_clk)));
return 0;
}
@@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
{
const struct clksel *clks;
const struct clksel_rate *clkr;
+ struct clk *parent;
- clks = _get_clksel_by_parent(clk, clk->parent);
+ parent = __clk_get_parent(clk);
+ clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return 0;
@@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
if (!clkr->div) {
/* This indicates a data error */
- WARN(1, "clock: Could not find fieldval %d for clock %s parent "
- "%s\n", field_val, clk->name, clk->parent->name);
+ WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
+ __clk_get_name(clk), field_val, __clk_get_name(parent));
return 0;
}
@@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
{
const struct clksel *clks;
const struct clksel_rate *clkr;
+ struct clk *parent;
/* should never happen */
WARN_ON(div == 0);
- clks = _get_clksel_by_parent(clk, clk->parent);
+ parent = __clk_get_parent(clk);
+ clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return ~0;
@@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
}
if (!clkr->div) {
- pr_err("clock: Could not find divisor %d for clock %s parent "
- "%s\n", div, clk->name, clk->parent->name);
+ pr_err("clock: %s: could not find divisor %d for parent %s\n",
+ __clk_get_name(clk), div, __clk_get_name(parent));
return ~0;
}
@@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
const struct clksel *clks;
const struct clksel_rate *clkr;
u32 last_div = 0;
+ struct clk *parent;
+ unsigned long parent_rate;
+ const char *clk_name;
+
+ parent = __clk_get_parent(clk);
+ parent_rate = __clk_get_rate(parent);
+ clk_name = __clk_get_name(clk);
if (!clk->clksel || !clk->clksel_mask)
return ~0;
pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
- clk->name, target_rate);
+ clk_name, target_rate);
*new_div = 1;
- clks = _get_clksel_by_parent(clk, clk->parent);
+ clks = _get_clksel_by_parent(clk, parent);
if (!clks)
return ~0;
@@ -300,30 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
/* Sanity check */
if (clkr->div <= last_div)
- pr_err("clock: clksel_rate table not sorted "
- "for clock %s", clk->name);
+ pr_err("clock: %s: clksel_rate table not sorted\n",
+ clk_name);
last_div = clkr->div;
- test_rate = clk->parent->rate / clkr->div;
+ test_rate = parent_rate / clkr->div;
if (test_rate <= target_rate)
break; /* found it */
}
if (!clkr->div) {
- pr_err("clock: Could not find divisor for target "
- "rate %ld for clock %s parent %s\n", target_rate,
- clk->name, clk->parent->name);
+ pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
+ clk_name, target_rate, __clk_get_name(parent));
return ~0;
}
*new_div = clkr->div;
pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
- (clk->parent->rate / clkr->div));
+ (parent_rate / clkr->div));
- return clk->parent->rate / clkr->div;
+ return parent_rate / clkr->div;
}
/*
@@ -345,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
const struct clksel *clks;
const struct clksel_rate *clkr;
u32 r, found = 0;
+ struct clk *parent;
+ const char *clk_name;
if (!clk->clksel || !clk->clksel_mask)
return;
+ parent = __clk_get_parent(clk);
+ clk_name = __clk_get_name(clk);
+
r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
r >>= __ffs(clk->clksel_mask);
@@ -358,12 +374,14 @@ void omap2_init_clksel_parent(struct clk *clk)
continue;
if (clkr->val == r) {
- if (clk->parent != clks->parent) {
+ if (parent != clks->parent) {
pr_debug("clock: inited %s parent "
"to %s (was %s)\n",
- clk->name, clks->parent->name,
- ((clk->parent) ?
- clk->parent->name : "NULL"));
+ clk_name,
+ __clk_get_name(clks->parent),
+ ((parent) ?
+ __clk_get_name(parent) :
+ "NULL"));
clk_reparent(clk, clks->parent);
};
found = 1;
@@ -373,7 +391,7 @@ void omap2_init_clksel_parent(struct clk *clk)
/* This indicates a data error */
WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
- clk->name, r);
+ clk_name, r);
return;
}
@@ -391,15 +409,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
{
unsigned long rate;
u32 div = 0;
+ struct clk *parent;
div = _read_divisor(clk);
if (div == 0)
- return clk->rate;
+ return __clk_get_rate(clk);
- rate = clk->parent->rate / div;
+ parent = __clk_get_parent(clk);
+ rate = __clk_get_rate(parent) / div;
- pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
- rate, div);
+ pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
+ __clk_get_name(clk), rate, div);
return rate;
}
@@ -454,9 +474,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
_write_clksel_reg(clk, field_val);
- clk->rate = clk->parent->rate / new_div;
+ clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
- pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
+ pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
+ __clk_get_rate(clk));
return 0;
}
@@ -498,13 +519,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
clk_reparent(clk, new_parent);
/* CLKSEL clocks follow their parents' rates, divided by a divisor */
- clk->rate = new_parent->rate;
+ clk->rate = __clk_get_rate(new_parent);
if (parent_div > 0)
- clk->rate /= parent_div;
+ __clk_get_rate(clk) /= parent_div;
pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
- clk->name, clk->parent->name, clk->rate);
+ __clk_get_name(clk),
+ __clk_get_name(__clk_get_parent(clk)),
+ __clk_get_rate(clk));
return 0;
}
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cd7fd0f..8c3349e 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
dd = clk->dpll_data;
/* DPLL divider must result in a valid jitter correction val */
- fint = clk->parent->rate / n;
+ fint = __clk_get_rate(__clk_get_parent(clk)) / n;
if (cpu_is_omap24xx()) {
/* Should not be called for OMAP2, so warn if it is called */
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
if (cpu_is_omap24xx()) {
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
- return dd->clk_bypass->rate;
+ return __clk_get_rate(dd->clk_bypass);
} else if (cpu_is_omap34xx()) {
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
- return dd->clk_bypass->rate;
+ return __clk_get_rate(dd->clk_bypass);
} else if (cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
- return dd->clk_bypass->rate;
+ return __clk_get_rate(dd->clk_bypass);
}
v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
dpll_div = v & dd->div1_mask;
dpll_div >>= __ffs(dd->div1_mask);
- dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+ dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
do_div(dpll_clk, dpll_div + 1);
return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
unsigned long scaled_rt_rp;
unsigned long new_rate = 0;
struct dpll_data *dd;
+ unsigned long ref_rate;
+ const char *clk_name;
if (!clk || !clk->dpll_data)
return ~0;
dd = clk->dpll_data;
+ ref_rate = __clk_get_rate(dd->clk_ref);
+ clk_name = __clk_get_name(clk);
pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
- clk->name, target_rate);
+ clk_name, target_rate);
- scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+ scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
break;
r = _dpll_test_mult(&m, n, &new_rate, target_rate,
- dd->clk_ref->rate);
+ ref_rate);
/* m can't be set low enough for this n - try with a larger n */
if (r == DPLL_MULT_UNDERFLOW)
continue;
pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
- clk->name, m, n, new_rate);
+ clk_name, m, n, new_rate);
if (target_rate == new_rate) {
dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
}
if (target_rate != new_rate) {
- pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
- target_rate);
+ pr_debug("clock: %s: cannot round to rate %ld\n",
+ clk_name, target_rate);
return ~0;
}
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ea3f565..5083d72 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -76,7 +76,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
- clk->name);
+ __clk_get_name(clk));
}
/* Public functions */
@@ -92,18 +92,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
void omap2_init_clk_clkdm(struct clk *clk)
{
struct clockdomain *clkdm;
+ const char *clk_name;
if (!clk->clkdm_name)
return;
+ clk_name = __clk_get_name(clk);
+
clkdm = clkdm_lookup(clk->clkdm_name);
if (clkdm) {
pr_debug("clock: associated clk %s to clkdm %s\n",
- clk->name, clk->clkdm_name);
+ clk_name, clk->clkdm_name);
clk->clkdm = clkdm;
} else {
- pr_debug("clock: could not associate clk %s to "
- "clkdm %s\n", clk->name, clk->clkdm_name);
+ pr_debug("clock: could not associate clk %s to clkdm %s\n",
+ clk_name, clk->clkdm_name);
}
}
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index b9c8d2f..47c2bf7 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
const struct dpll_data *dd;
int i = 0;
int ret = -EINVAL;
+ const char *clk_name;
dd = clk->dpll_data;
+ clk_name = __clk_get_name(clk);
state <<= __ffs(dd->idlest_mask);
@@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
if (i == MAX_DPLL_WAIT_TRIES) {
printk(KERN_ERR "clock: %s failed transition to '%s'\n",
- clk->name, (state) ? "locked" : "bypassed");
+ clk_name, (state) ? "locked" : "bypassed");
} else {
pr_debug("clock: %s transition to '%s' in %d loops\n",
- clk->name, (state) ? "locked" : "bypassed", i);
+ clk_name, (state) ? "locked" : "bypassed", i);
ret = 0;
}
@@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
unsigned long fint;
u16 f = 0;
- fint = clk->dpll_data->clk_ref->rate / n;
+ fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
pr_debug("clock: fint is %lu\n", fint);
@@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
u8 state = 1;
int r = 0;
- pr_debug("clock: locking DPLL %s\n", clk->name);
+ pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
dd = clk->dpll_data;
state <<= __ffs(dd->idlest_mask);
@@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
return -EINVAL;
pr_debug("clock: configuring DPLL %s for low-power bypass\n",
- clk->name);
+ __clk_get_name(clk));
ai = omap3_dpll_autoidle_read(clk);
@@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
return -EINVAL;
- pr_debug("clock: stopping DPLL %s\n", clk->name);
+ pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
ai = omap3_dpll_autoidle_read(clk);
@@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
{
unsigned long fint, clkinp; /* watch out for overflow */
- clkinp = clk->parent->rate;
+ clkinp = __clk_get_rate(__clk_get_parent(clk));
fint = (clkinp / n) * m;
if (fint < 1000000000)
@@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
unsigned long clkinp, sd; /* watch out for overflow */
int mod1, mod2;
- clkinp = clk->parent->rate;
+ clkinp = __clk_get_rate(__clk_get_parent(clk));
/*
* target sigma-delta to near 250MHz
@@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
{
int r;
struct dpll_data *dd;
+ struct clk *parent;
dd = clk->dpll_data;
if (!dd)
return -EINVAL;
- if (clk->rate == dd->clk_bypass->rate) {
- WARN_ON(clk->parent != dd->clk_bypass);
+ parent = __clk_get_parent(clk);
+
+ if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
+ WARN_ON(parent != dd->clk_bypass);
r = _omap3_noncore_dpll_bypass(clk);
} else {
- WARN_ON(clk->parent != dd->clk_ref);
+ WARN_ON(parent != dd->clk_ref);
r = _omap3_noncore_dpll_lock(clk);
}
/*
@@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
{
struct clk *new_parent = NULL;
- unsigned long hw_rate;
+ unsigned long hw_rate, bypass_rate;
u16 freqsel = 0;
struct dpll_data *dd;
int ret;
@@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
omap2_clk_enable(dd->clk_bypass);
omap2_clk_enable(dd->clk_ref);
- if (dd->clk_bypass->rate == rate &&
+ bypass_rate = __clk_get_rate(dd->clk_bypass);
+ if (bypass_rate == rate &&
(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
@@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
}
pr_debug("clock: %s: set rate: locking rate to %lu.\n",
- clk->name, rate);
+ __clk_get_name(clk), rate);
ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
dd->last_rounded_n, freqsel);
@@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
- clk->name);
+ __clk_get_name(clk));
return;
}
@@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
- clk->name);
+ __clk_get_name(clk));
return;
}
@@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
unsigned long rate;
u32 v;
struct clk *pclk;
+ unsigned long parent_rate;
/* Walk up the parents of clk, looking for a DPLL */
- pclk = clk->parent;
+ pclk = __clk_get_parent(clk);
while (pclk && !pclk->dpll_data)
- pclk = pclk->parent;
+ pclk = __clk_get_parent(pclk);
/* clk does not have a DPLL as a parent? */
WARN_ON(!pclk);
@@ -630,12 +637,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
WARN_ON(!dd->enable_mask);
+ parent_rate = __clk_get_rate(__clk_get_parent(clk));
v = __raw_readl(dd->control_reg) & dd->enable_mask;
v >>= __ffs(dd->enable_mask);
if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
- rate = clk->parent->rate;
+ rate = parent_rate;
else
- rate = clk->parent->rate * 2;
+ rate = parent_rate * 2;
return rate;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ca8e51..d730e62 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -686,7 +686,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
if (!oh->_clk->clkdm)
pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
- oh->main_clk, oh->_clk->name);
+ oh->name, oh->main_clk);
return ret;
}
@@ -825,7 +825,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk) {
pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
- oc->_clk->name);
+ __clk_get_name(oc->_clk));
clk_enable(oc->_clk);
}
}
@@ -840,7 +840,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk) {
pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
- oc->_clk->name);
+ __clk_get_name(oc->_clk));
clk_disable(oc->_clk);
}
}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5ced..40012e3 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -188,7 +188,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
goto exit;
}
- freq = clk->rate;
+ freq = clk_get_rate(clk);
clk_put(clk);
rcu_read_lock();
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 656b986..e2e2d04 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -19,6 +19,11 @@ struct module;
struct clk;
struct clockdomain;
+/* Temporary, needed during the common clock framework conversion */
+#define __clk_get_name(clk) (clk->name)
+#define __clk_get_parent(clk) (clk->parent)
+#define __clk_get_rate(clk) (clk->rate)
+
/**
* struct clkops - some clock function pointers
* @enable: fn ptr that enables the current clock in hardware
--
1.7.10.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare
2012-07-02 10:24 ` [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare Rajendra Nayak
@ 2012-07-30 22:31 ` Paul Walmsley
2012-07-30 22:42 ` Turquette, Mike
0 siblings, 1 reply; 16+ messages in thread
From: Paul Walmsley @ 2012-07-30 22:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi
On Mon, 2 Jul 2012, Rajendra Nayak wrote:
> As part of Common Clk Framework (CCF) the clk_enable() operation
> was split into a clk_prepare() which could sleep, and a clk_enable()
> which should never sleep. Similarly the clk_disable() was
> split into clk_disable() and clk_unprepare(). This was
> needed to handle complex cases where in a clk gate/ungate
> would require a slow and a fast part to be implemented.
> None of the clocks below seem to be in the 'complex' clocks
> category and are just simple clocks which are enabled/disabled
> through simple register writes.
> Most of the instances also seem to be called in non-atomic
> context which means its safe to move all of those from
> using a clk_enable() to clk_prepare_enable() and clk_disable() to
> clk_disable_unprepare().
> For a few others where there is a possibility they get called from
> an interrupt or atomic context, there is an additonal clk_prepare()
> done before a clk_enable() and a clk_unprepare()
> after a clk_disable().
> This is in preparation of OMAP moving to CCF.
>
> Based on initial changes from Mike turquette.
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Looking at this one, it seems basically okay except for this part:
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 7731936..f904993 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -608,6 +608,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
> oh->name, oh->main_clk);
> return -EINVAL;
> }
> + clk_prepare(oh->_clk);
>
> if (!oh->_clk->clkdm)
> pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
> @@ -645,6 +646,7 @@ static int _init_interface_clks(struct omap_hwmod *oh)
> ret = -EINVAL;
> }
> os->_clk = c;
> + clk_prepare(os->_clk);
> }
>
> return ret;
> @@ -672,6 +674,7 @@ static int _init_opt_clks(struct omap_hwmod *oh)
> ret = -EINVAL;
> }
> oc->_clk = c;
> + clk_prepare(oc->_clk);
> }
>
> return ret;
Seems to me that the strategy here of calling clk_prepare() right after
the clk_get() is only going to work as long as clk_prepare() is a no-op.
Right now this code is called early in the boot before many subsystems are
available.
So if we make a change like this one, it seems like we would basically
expect it to break once we start doing anything meaningful with
clk_prepare(), like using clk_prepare() for voltage scaling or something
that requires I2C? We'd also probably want to mark this with some kind of
"HACK" comment.
- Paul
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare
2012-07-30 22:31 ` Paul Walmsley
@ 2012-07-30 22:42 ` Turquette, Mike
2012-07-30 23:02 ` Russell King - ARM Linux
2012-07-31 18:00 ` Paul Walmsley
0 siblings, 2 replies; 16+ messages in thread
From: Turquette, Mike @ 2012-07-30 22:42 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 30, 2012 at 3:31 PM, Paul Walmsley <paul@pwsan.com> wrote:
> So if we make a change like this one, it seems like we would basically
> expect it to break once we start doing anything meaningful with
> clk_prepare(), like using clk_prepare() for voltage scaling or something
> that requires I2C? We'd also probably want to mark this with some kind of
> "HACK" comment.
Hi Paul,
Did you have anything in mind to start using clk_prepare? I still
hope to get rid of it some day and replace that call with a
combination of clk_enable and a check like clk_enable_can_sleep.
Regards,
Mike
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare
2012-07-30 22:42 ` Turquette, Mike
@ 2012-07-30 23:02 ` Russell King - ARM Linux
2012-07-31 0:31 ` Turquette, Mike
2012-07-31 18:00 ` Paul Walmsley
1 sibling, 1 reply; 16+ messages in thread
From: Russell King - ARM Linux @ 2012-07-30 23:02 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 30, 2012 at 03:42:13PM -0700, Turquette, Mike wrote:
> On Mon, Jul 30, 2012 at 3:31 PM, Paul Walmsley <paul@pwsan.com> wrote:
> > So if we make a change like this one, it seems like we would basically
> > expect it to break once we start doing anything meaningful with
> > clk_prepare(), like using clk_prepare() for voltage scaling or something
> > that requires I2C? We'd also probably want to mark this with some kind of
> > "HACK" comment.
>
> Hi Paul,
>
> Did you have anything in mind to start using clk_prepare? I still
> hope to get rid of it some day and replace that call with a
> combination of clk_enable and a check like clk_enable_can_sleep.
Don't you dare.
We arrived at the clk_prepare()/clk_enable() split after lots of
discussion between different platform maintainers and their
requirements.
Shoving crap like "clk_enable_can_sleep()" down into drivers is
totally and utterly idiotic. We've had the situation *already*
where some drivers can be used on some platforms but not on others
because of differences in clk_enable() expectations.
Don't go back there. clk_prepare() and clk_enable() are separate
calls for a very good reason. One is sleepable, the other can be
called from any atomic contexts.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare
2012-07-30 23:02 ` Russell King - ARM Linux
@ 2012-07-31 0:31 ` Turquette, Mike
2012-07-31 8:21 ` Saravana Kannan
2012-07-31 9:23 ` Russell King - ARM Linux
0 siblings, 2 replies; 16+ messages in thread
From: Turquette, Mike @ 2012-07-31 0:31 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 30, 2012 at 4:02 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Mon, Jul 30, 2012 at 03:42:13PM -0700, Turquette, Mike wrote:
>> On Mon, Jul 30, 2012 at 3:31 PM, Paul Walmsley <paul@pwsan.com> wrote:
>> > So if we make a change like this one, it seems like we would basically
>> > expect it to break once we start doing anything meaningful with
>> > clk_prepare(), like using clk_prepare() for voltage scaling or something
>> > that requires I2C? We'd also probably want to mark this with some kind of
>> > "HACK" comment.
>>
>> Hi Paul,
>>
>> Did you have anything in mind to start using clk_prepare? I still
>> hope to get rid of it some day and replace that call with a
>> combination of clk_enable and a check like clk_enable_can_sleep.
>
> Don't you dare.
>
> We arrived at the clk_prepare()/clk_enable() split after lots of
> discussion between different platform maintainers and their
> requirements.
>
> Shoving crap like "clk_enable_can_sleep()" down into drivers is
> totally and utterly idiotic. We've had the situation *already*
> where some drivers can be used on some platforms but not on others
> because of differences in clk_enable() expectations.
>
How does having a dynamic run-time check cause a generic driver to run
on "some platforms but not on others"?
> Don't go back there. clk_prepare() and clk_enable() are separate
> calls for a very good reason. One is sleepable, the other can be
> called from any atomic contexts.
Two calls exist because of context differences. But in practice they
do the same thing: cause a line to toggle at a rate. If a run-time
check exists and the framework could handle this gracefully, why would
you still choose the split api?
Regards,
Mike
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 3/3] ARM: omap: clk: Remove all direct dereferencing of struct clk
2012-07-30 18:56 ` Paul Walmsley
@ 2012-07-31 6:05 ` Rajendra Nayak
0 siblings, 0 replies; 16+ messages in thread
From: Rajendra Nayak @ 2012-07-31 6:05 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday 31 July 2012 12:26 AM, Paul Walmsley wrote:
> On Mon, 30 Jul 2012, Rajendra Nayak wrote:
>
>> Are you sure you are using the v3 of this patch? You already mentioned
>> about these in the v2 [1] and I fixed all these in v3. I went back and
>> looked at the v3 of this patch, and it does not complain me about any
>> of these warnings or errors.
>
> Yep that's probably what happened. Here's the updated patch, starting
> from your v3.
Thanks Paul, looks good to me.
>
>
> - Paul
>
>
> From: Rajendra Nayak<rnayak@ti.com>
> Date: Mon, 30 Jul 2012 12:52:55 -0600
> Subject: [PATCH] ARM: OMAP2+: clock: Remove all direct dereferencing of
> struct clk
>
> While we move to Common Clk Framework (CCF), direct deferencing of struct
> clk wouldn't be possible anymore. Hence get rid of all such instances
> in the current clock code and use macros/helpers similar to the ones that
> are provided by CCF.
>
> While here also concatenate some strings split across multiple lines
> which seem to be needed anyway.
>
> Signed-off-by: Rajendra Nayak<rnayak@ti.com>
> [paul at pwsan.com: simplified some compound expressions; reformatted some
> messages]
> Signed-off-by: Paul Walmsley<paul@pwsan.com>
> Cc: Mike Turquette<mturquette@linaro.org>
> ---
> arch/arm/mach-omap2/clkt2xxx_apll.c | 2 +-
> arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 10 ++-
> arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 20 +++---
> arch/arm/mach-omap2/clkt_clksel.c | 91 ++++++++++++++++----------
> arch/arm/mach-omap2/clkt_dpll.c | 26 ++++----
> arch/arm/mach-omap2/clock.c | 11 ++--
> arch/arm/mach-omap2/dpll3xxx.c | 48 ++++++++------
> arch/arm/mach-omap2/omap_hwmod.c | 6 +-
> arch/arm/mach-omap2/pm.c | 2 +-
> arch/arm/plat-omap/include/plat/clock.h | 5 ++
> 10 files changed, 135 insertions(+), 86 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
> index b19a1f7..c2d15212 100644
> --- a/arch/arm/mach-omap2/clkt2xxx_apll.c
> +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
> @@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
> omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
>
> omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
> - OMAP24XX_CM_IDLEST_VAL, clk->name);
> + OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
>
> /*
> * REVISIT: Should we return an error code if omap2_wait_clock_ready()
> diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> index 3d9d746..da03fa4 100644
> --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> @@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
> long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
> {
> const struct prcm_config *ptr;
> - long highest_rate;
> + long highest_rate, sys_clk_rate;
>
> highest_rate = -EINVAL;
> + sys_clk_rate = __clk_get_rate(sclk);
>
> for (ptr = rate_table; ptr->mpu_speed; ptr++) {
> if (!(ptr->flags& cpu_mask))
> continue;
> - if (ptr->xtal_speed != sclk->rate)
> + if (ptr->xtal_speed != sys_clk_rate)
> continue;
>
> highest_rate = ptr->mpu_speed;
> @@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
> const struct prcm_config *prcm;
> unsigned long found_speed = 0;
> unsigned long flags;
> + long sys_clk_rate;
> +
> + sys_clk_rate = __clk_get_rate(sclk);
>
> for (prcm = rate_table; prcm->mpu_speed; prcm++) {
> if (!(prcm->flags& cpu_mask))
> continue;
>
> - if (prcm->xtal_speed != sclk->rate)
> + if (prcm->xtal_speed != sys_clk_rate)
> continue;
>
> if (prcm->mpu_speed<= rate) {
> diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
> index d6e34dd..0fd8b70 100644
> --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
> +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
> @@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
> struct omap_sdrc_params *sdrc_cs0;
> struct omap_sdrc_params *sdrc_cs1;
> int ret;
> + unsigned long clkrate;
>
> if (!clk || !rate)
> return -EINVAL;
> @@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
> if (validrate != rate)
> return -EINVAL;
>
> - sdrcrate = sdrc_ick_p->rate;
> - if (rate> clk->rate)
> - sdrcrate<<= ((rate / clk->rate)>> 1);
> + sdrcrate = __clk_get_rate(sdrc_ick_p);
> + clkrate = __clk_get_rate(clk);
> + if (rate> clkrate)
> + sdrcrate<<= ((rate / clkrate)>> 1);
> else
> - sdrcrate>>= ((clk->rate / rate)>> 1);
> + sdrcrate>>= ((clkrate / rate)>> 1);
>
> ret = omap2_sdrc_get_params(sdrcrate,&sdrc_cs0,&sdrc_cs1);
> if (ret)
> @@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
> /*
> * XXX This only needs to be done when the CPU frequency changes
> */
> - _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
> + _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
> c = (_mpurate<< SDRC_MPURATE_SCALE)>> SDRC_MPURATE_BASE_SHIFT;
> c += 1; /* for safety */
> c *= SDRC_MPURATE_LOOPS;
> @@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
> if (c == 0)
> c = 1;
>
> - pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
> - validrate);
> + pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
> + clkrate, validrate);
> pr_debug("clock: SDRC CS0 timing params used:"
> " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
> sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> @@ -104,14 +106,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
>
> if (sdrc_cs1)
> omap3_configure_core_dpll(
> - new_div, unlock_dll, c, rate> clk->rate,
> + new_div, unlock_dll, c, rate> clkrate,
> sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
> sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
> sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
> else
> omap3_configure_core_dpll(
> - new_div, unlock_dll, c, rate> clk->rate,
> + new_div, unlock_dll, c, rate> clkrate,
> sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
> 0, 0, 0, 0);
> diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
> index 04d551b..33382fb 100644
> --- a/arch/arm/mach-omap2/clkt_clksel.c
> +++ b/arch/arm/mach-omap2/clkt_clksel.c
> @@ -71,8 +71,8 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
>
> if (!clks->parent) {
> /* This indicates a data problem */
> - WARN(1, "clock: Could not find parent clock %s in clksel array "
> - "of clock %s\n", src_clk->name, clk->name);
> + WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
> + __clk_get_name(clk), __clk_get_name(src_clk));
> return NULL;
> }
>
> @@ -126,8 +126,9 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
>
> if (max_div == 0) {
> /* This indicates an error in the clksel data */
> - WARN(1, "clock: Could not find divisor for clock %s parent %s"
> - "\n", clk->name, src_clk->parent->name);
> + WARN(1, "clock: %s: could not find divisor for parent %s\n",
> + __clk_get_name(clk),
> + __clk_get_name(__clk_get_parent(src_clk)));
> return 0;
> }
>
> @@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
> {
> const struct clksel *clks;
> const struct clksel_rate *clkr;
> + struct clk *parent;
>
> - clks = _get_clksel_by_parent(clk, clk->parent);
> + parent = __clk_get_parent(clk);
> + clks = _get_clksel_by_parent(clk, parent);
> if (!clks)
> return 0;
>
> @@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
>
> if (!clkr->div) {
> /* This indicates a data error */
> - WARN(1, "clock: Could not find fieldval %d for clock %s parent "
> - "%s\n", field_val, clk->name, clk->parent->name);
> + WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
> + __clk_get_name(clk), field_val, __clk_get_name(parent));
> return 0;
> }
>
> @@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
> {
> const struct clksel *clks;
> const struct clksel_rate *clkr;
> + struct clk *parent;
>
> /* should never happen */
> WARN_ON(div == 0);
>
> - clks = _get_clksel_by_parent(clk, clk->parent);
> + parent = __clk_get_parent(clk);
> + clks = _get_clksel_by_parent(clk, parent);
> if (!clks)
> return ~0;
>
> @@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
> }
>
> if (!clkr->div) {
> - pr_err("clock: Could not find divisor %d for clock %s parent "
> - "%s\n", div, clk->name, clk->parent->name);
> + pr_err("clock: %s: could not find divisor %d for parent %s\n",
> + __clk_get_name(clk), div, __clk_get_name(parent));
> return ~0;
> }
>
> @@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
> const struct clksel *clks;
> const struct clksel_rate *clkr;
> u32 last_div = 0;
> + struct clk *parent;
> + unsigned long parent_rate;
> + const char *clk_name;
> +
> + parent = __clk_get_parent(clk);
> + parent_rate = __clk_get_rate(parent);
> + clk_name = __clk_get_name(clk);
>
> if (!clk->clksel || !clk->clksel_mask)
> return ~0;
>
> pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
> - clk->name, target_rate);
> + clk_name, target_rate);
>
> *new_div = 1;
>
> - clks = _get_clksel_by_parent(clk, clk->parent);
> + clks = _get_clksel_by_parent(clk, parent);
> if (!clks)
> return ~0;
>
> @@ -300,30 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
>
> /* Sanity check */
> if (clkr->div<= last_div)
> - pr_err("clock: clksel_rate table not sorted "
> - "for clock %s", clk->name);
> + pr_err("clock: %s: clksel_rate table not sorted\n",
> + clk_name);
>
> last_div = clkr->div;
>
> - test_rate = clk->parent->rate / clkr->div;
> + test_rate = parent_rate / clkr->div;
>
> if (test_rate<= target_rate)
> break; /* found it */
> }
>
> if (!clkr->div) {
> - pr_err("clock: Could not find divisor for target "
> - "rate %ld for clock %s parent %s\n", target_rate,
> - clk->name, clk->parent->name);
> + pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
> + clk_name, target_rate, __clk_get_name(parent));
> return ~0;
> }
>
> *new_div = clkr->div;
>
> pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
> - (clk->parent->rate / clkr->div));
> + (parent_rate / clkr->div));
>
> - return clk->parent->rate / clkr->div;
> + return parent_rate / clkr->div;
> }
>
> /*
> @@ -345,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
> const struct clksel *clks;
> const struct clksel_rate *clkr;
> u32 r, found = 0;
> + struct clk *parent;
> + const char *clk_name;
>
> if (!clk->clksel || !clk->clksel_mask)
> return;
>
> + parent = __clk_get_parent(clk);
> + clk_name = __clk_get_name(clk);
> +
> r = __raw_readl(clk->clksel_reg)& clk->clksel_mask;
> r>>= __ffs(clk->clksel_mask);
>
> @@ -358,12 +374,14 @@ void omap2_init_clksel_parent(struct clk *clk)
> continue;
>
> if (clkr->val == r) {
> - if (clk->parent != clks->parent) {
> + if (parent != clks->parent) {
> pr_debug("clock: inited %s parent "
> "to %s (was %s)\n",
> - clk->name, clks->parent->name,
> - ((clk->parent) ?
> - clk->parent->name : "NULL"));
> + clk_name,
> + __clk_get_name(clks->parent),
> + ((parent) ?
> + __clk_get_name(parent) :
> + "NULL"));
> clk_reparent(clk, clks->parent);
> };
> found = 1;
> @@ -373,7 +391,7 @@ void omap2_init_clksel_parent(struct clk *clk)
>
> /* This indicates a data error */
> WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
> - clk->name, r);
> + clk_name, r);
>
> return;
> }
> @@ -391,15 +409,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
> {
> unsigned long rate;
> u32 div = 0;
> + struct clk *parent;
>
> div = _read_divisor(clk);
> if (div == 0)
> - return clk->rate;
> + return __clk_get_rate(clk);
>
> - rate = clk->parent->rate / div;
> + parent = __clk_get_parent(clk);
> + rate = __clk_get_rate(parent) / div;
>
> - pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
> - rate, div);
> + pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
> + __clk_get_name(clk), rate, div);
>
> return rate;
> }
> @@ -454,9 +474,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
>
> _write_clksel_reg(clk, field_val);
>
> - clk->rate = clk->parent->rate / new_div;
> + clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
>
> - pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
> + pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
> + __clk_get_rate(clk));
>
> return 0;
> }
> @@ -498,13 +519,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
> clk_reparent(clk, new_parent);
>
> /* CLKSEL clocks follow their parents' rates, divided by a divisor */
> - clk->rate = new_parent->rate;
> + clk->rate = __clk_get_rate(new_parent);
>
> if (parent_div> 0)
> - clk->rate /= parent_div;
> + __clk_get_rate(clk) /= parent_div;
>
> pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
> - clk->name, clk->parent->name, clk->rate);
> + __clk_get_name(clk),
> + __clk_get_name(__clk_get_parent(clk)),
> + __clk_get_rate(clk));
>
> return 0;
> }
> diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
> index cd7fd0f..8c3349e 100644
> --- a/arch/arm/mach-omap2/clkt_dpll.c
> +++ b/arch/arm/mach-omap2/clkt_dpll.c
> @@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
> dd = clk->dpll_data;
>
> /* DPLL divider must result in a valid jitter correction val */
> - fint = clk->parent->rate / n;
> + fint = __clk_get_rate(__clk_get_parent(clk)) / n;
>
> if (cpu_is_omap24xx()) {
> /* Should not be called for OMAP2, so warn if it is called */
> @@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
> if (cpu_is_omap24xx()) {
> if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
> v == OMAP2XXX_EN_DPLL_FRBYPASS)
> - return dd->clk_bypass->rate;
> + return __clk_get_rate(dd->clk_bypass);
> } else if (cpu_is_omap34xx()) {
> if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
> v == OMAP3XXX_EN_DPLL_FRBYPASS)
> - return dd->clk_bypass->rate;
> + return __clk_get_rate(dd->clk_bypass);
> } else if (cpu_is_omap44xx()) {
> if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
> v == OMAP4XXX_EN_DPLL_FRBYPASS ||
> v == OMAP4XXX_EN_DPLL_MNBYPASS)
> - return dd->clk_bypass->rate;
> + return __clk_get_rate(dd->clk_bypass);
> }
>
> v = __raw_readl(dd->mult_div1_reg);
> @@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
> dpll_div = v& dd->div1_mask;
> dpll_div>>= __ffs(dd->div1_mask);
>
> - dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
> + dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
> do_div(dpll_clk, dpll_div + 1);
>
> return dpll_clk;
> @@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
> unsigned long scaled_rt_rp;
> unsigned long new_rate = 0;
> struct dpll_data *dd;
> + unsigned long ref_rate;
> + const char *clk_name;
>
> if (!clk || !clk->dpll_data)
> return ~0;
>
> dd = clk->dpll_data;
>
> + ref_rate = __clk_get_rate(dd->clk_ref);
> + clk_name = __clk_get_name(clk);
> pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
> - clk->name, target_rate);
> + clk_name, target_rate);
>
> - scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
> + scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
> scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
>
> dd->last_rounded_rate = 0;
> @@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
> break;
>
> r = _dpll_test_mult(&m, n,&new_rate, target_rate,
> - dd->clk_ref->rate);
> + ref_rate);
>
> /* m can't be set low enough for this n - try with a larger n */
> if (r == DPLL_MULT_UNDERFLOW)
> continue;
>
> pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
> - clk->name, m, n, new_rate);
> + clk_name, m, n, new_rate);
>
> if (target_rate == new_rate) {
> dd->last_rounded_m = m;
> @@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
> }
>
> if (target_rate != new_rate) {
> - pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
> - target_rate);
> + pr_debug("clock: %s: cannot round to rate %ld\n",
> + clk_name, target_rate);
> return ~0;
> }
>
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index ea3f565..5083d72 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -76,7 +76,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
> clk->ops->find_idlest(clk,&idlest_reg,&idlest_bit,&idlest_val);
>
> omap2_cm_wait_idlest(idlest_reg, (1<< idlest_bit), idlest_val,
> - clk->name);
> + __clk_get_name(clk));
> }
>
> /* Public functions */
> @@ -92,18 +92,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
> void omap2_init_clk_clkdm(struct clk *clk)
> {
> struct clockdomain *clkdm;
> + const char *clk_name;
>
> if (!clk->clkdm_name)
> return;
>
> + clk_name = __clk_get_name(clk);
> +
> clkdm = clkdm_lookup(clk->clkdm_name);
> if (clkdm) {
> pr_debug("clock: associated clk %s to clkdm %s\n",
> - clk->name, clk->clkdm_name);
> + clk_name, clk->clkdm_name);
> clk->clkdm = clkdm;
> } else {
> - pr_debug("clock: could not associate clk %s to "
> - "clkdm %s\n", clk->name, clk->clkdm_name);
> + pr_debug("clock: could not associate clk %s to clkdm %s\n",
> + clk_name, clk->clkdm_name);
> }
> }
>
> diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
> index b9c8d2f..47c2bf7 100644
> --- a/arch/arm/mach-omap2/dpll3xxx.c
> +++ b/arch/arm/mach-omap2/dpll3xxx.c
> @@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
> const struct dpll_data *dd;
> int i = 0;
> int ret = -EINVAL;
> + const char *clk_name;
>
> dd = clk->dpll_data;
> + clk_name = __clk_get_name(clk);
>
> state<<= __ffs(dd->idlest_mask);
>
> @@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
>
> if (i == MAX_DPLL_WAIT_TRIES) {
> printk(KERN_ERR "clock: %s failed transition to '%s'\n",
> - clk->name, (state) ? "locked" : "bypassed");
> + clk_name, (state) ? "locked" : "bypassed");
> } else {
> pr_debug("clock: %s transition to '%s' in %d loops\n",
> - clk->name, (state) ? "locked" : "bypassed", i);
> + clk_name, (state) ? "locked" : "bypassed", i);
>
> ret = 0;
> }
> @@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
> unsigned long fint;
> u16 f = 0;
>
> - fint = clk->dpll_data->clk_ref->rate / n;
> + fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
>
> pr_debug("clock: fint is %lu\n", fint);
>
> @@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
> u8 state = 1;
> int r = 0;
>
> - pr_debug("clock: locking DPLL %s\n", clk->name);
> + pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
>
> dd = clk->dpll_data;
> state<<= __ffs(dd->idlest_mask);
> @@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
> return -EINVAL;
>
> pr_debug("clock: configuring DPLL %s for low-power bypass\n",
> - clk->name);
> + __clk_get_name(clk));
>
> ai = omap3_dpll_autoidle_read(clk);
>
> @@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
> if (!(clk->dpll_data->modes& (1<< DPLL_LOW_POWER_STOP)))
> return -EINVAL;
>
> - pr_debug("clock: stopping DPLL %s\n", clk->name);
> + pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
>
> ai = omap3_dpll_autoidle_read(clk);
>
> @@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
> {
> unsigned long fint, clkinp; /* watch out for overflow */
>
> - clkinp = clk->parent->rate;
> + clkinp = __clk_get_rate(__clk_get_parent(clk));
> fint = (clkinp / n) * m;
>
> if (fint< 1000000000)
> @@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
> unsigned long clkinp, sd; /* watch out for overflow */
> int mod1, mod2;
>
> - clkinp = clk->parent->rate;
> + clkinp = __clk_get_rate(__clk_get_parent(clk));
>
> /*
> * target sigma-delta to near 250MHz
> @@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
> {
> int r;
> struct dpll_data *dd;
> + struct clk *parent;
>
> dd = clk->dpll_data;
> if (!dd)
> return -EINVAL;
>
> - if (clk->rate == dd->clk_bypass->rate) {
> - WARN_ON(clk->parent != dd->clk_bypass);
> + parent = __clk_get_parent(clk);
> +
> + if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
> + WARN_ON(parent != dd->clk_bypass);
> r = _omap3_noncore_dpll_bypass(clk);
> } else {
> - WARN_ON(clk->parent != dd->clk_ref);
> + WARN_ON(parent != dd->clk_ref);
> r = _omap3_noncore_dpll_lock(clk);
> }
> /*
> @@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
> int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
> {
> struct clk *new_parent = NULL;
> - unsigned long hw_rate;
> + unsigned long hw_rate, bypass_rate;
> u16 freqsel = 0;
> struct dpll_data *dd;
> int ret;
> @@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
> omap2_clk_enable(dd->clk_bypass);
> omap2_clk_enable(dd->clk_ref);
>
> - if (dd->clk_bypass->rate == rate&&
> + bypass_rate = __clk_get_rate(dd->clk_bypass);
> + if (bypass_rate == rate&&
> (clk->dpll_data->modes& (1<< DPLL_LOW_POWER_BYPASS))) {
> pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
>
> @@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
> }
>
> pr_debug("clock: %s: set rate: locking rate to %lu.\n",
> - clk->name, rate);
> + __clk_get_name(clk), rate);
>
> ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
> dd->last_rounded_n, freqsel);
> @@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
>
> if (!dd->autoidle_reg) {
> pr_debug("clock: DPLL %s: autoidle not supported\n",
> - clk->name);
> + __clk_get_name(clk));
> return;
> }
>
> @@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
>
> if (!dd->autoidle_reg) {
> pr_debug("clock: DPLL %s: autoidle not supported\n",
> - clk->name);
> + __clk_get_name(clk));
> return;
> }
>
> @@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
> unsigned long rate;
> u32 v;
> struct clk *pclk;
> + unsigned long parent_rate;
>
> /* Walk up the parents of clk, looking for a DPLL */
> - pclk = clk->parent;
> + pclk = __clk_get_parent(clk);
> while (pclk&& !pclk->dpll_data)
> - pclk = pclk->parent;
> + pclk = __clk_get_parent(pclk);
>
> /* clk does not have a DPLL as a parent? */
> WARN_ON(!pclk);
> @@ -630,12 +637,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
>
> WARN_ON(!dd->enable_mask);
>
> + parent_rate = __clk_get_rate(__clk_get_parent(clk));
> v = __raw_readl(dd->control_reg)& dd->enable_mask;
> v>>= __ffs(dd->enable_mask);
> if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags& DPLL_J_TYPE))
> - rate = clk->parent->rate;
> + rate = parent_rate;
> else
> - rate = clk->parent->rate * 2;
> + rate = parent_rate * 2;
> return rate;
> }
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 6ca8e51..d730e62 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -686,7 +686,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
>
> if (!oh->_clk->clkdm)
> pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
> - oh->main_clk, oh->_clk->name);
> + oh->name, oh->main_clk);
>
> return ret;
> }
> @@ -825,7 +825,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
> for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i> 0; i--, oc++)
> if (oc->_clk) {
> pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
> - oc->_clk->name);
> + __clk_get_name(oc->_clk));
> clk_enable(oc->_clk);
> }
> }
> @@ -840,7 +840,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
> for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i> 0; i--, oc++)
> if (oc->_clk) {
> pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
> - oc->_clk->name);
> + __clk_get_name(oc->_clk));
> clk_disable(oc->_clk);
> }
> }
> diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
> index 9cb5ced..40012e3 100644
> --- a/arch/arm/mach-omap2/pm.c
> +++ b/arch/arm/mach-omap2/pm.c
> @@ -188,7 +188,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
> goto exit;
> }
>
> - freq = clk->rate;
> + freq = clk_get_rate(clk);
> clk_put(clk);
>
> rcu_read_lock();
> diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
> index 656b986..e2e2d04 100644
> --- a/arch/arm/plat-omap/include/plat/clock.h
> +++ b/arch/arm/plat-omap/include/plat/clock.h
> @@ -19,6 +19,11 @@ struct module;
> struct clk;
> struct clockdomain;
>
> +/* Temporary, needed during the common clock framework conversion */
> +#define __clk_get_name(clk) (clk->name)
> +#define __clk_get_parent(clk) (clk->parent)
> +#define __clk_get_rate(clk) (clk->rate)
> +
> /**
> * struct clkops - some clock function pointers
> * @enable: fn ptr that enables the current clock in hardware
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare
2012-07-31 0:31 ` Turquette, Mike
@ 2012-07-31 8:21 ` Saravana Kannan
2012-07-31 9:27 ` Russell King - ARM Linux
2012-07-31 9:23 ` Russell King - ARM Linux
1 sibling, 1 reply; 16+ messages in thread
From: Saravana Kannan @ 2012-07-31 8:21 UTC (permalink / raw)
To: linux-arm-kernel
On 07/30/2012 05:31 PM, Turquette, Mike wrote:
> On Mon, Jul 30, 2012 at 4:02 PM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
>> On Mon, Jul 30, 2012 at 03:42:13PM -0700, Turquette, Mike wrote:
>>> On Mon, Jul 30, 2012 at 3:31 PM, Paul Walmsley <paul@pwsan.com> wrote:
>>>> So if we make a change like this one, it seems like we would basically
>>>> expect it to break once we start doing anything meaningful with
>>>> clk_prepare(), like using clk_prepare() for voltage scaling or something
>>>> that requires I2C? We'd also probably want to mark this with some kind of
>>>> "HACK" comment.
>>>
>>> Hi Paul,
>>>
>>> Did you have anything in mind to start using clk_prepare? I still
>>> hope to get rid of it some day and replace that call with a
>>> combination of clk_enable and a check like clk_enable_can_sleep.
>>
>> Don't you dare.
>>
>> We arrived at the clk_prepare()/clk_enable() split after lots of
>> discussion between different platform maintainers and their
>> requirements.
>>
>> Shoving crap like "clk_enable_can_sleep()" down into drivers is
>> totally and utterly idiotic. We've had the situation *already*
>> where some drivers can be used on some platforms but not on others
>> because of differences in clk_enable() expectations.
>>
>
> How does having a dynamic run-time check cause a generic driver to run
> on "some platforms but not on others"?
>
>> Don't go back there. clk_prepare() and clk_enable() are separate
>> calls for a very good reason. One is sleepable, the other can be
>> called from any atomic contexts.
>
> Two calls exist because of context differences. But in practice they
> do the same thing: cause a line to toggle at a rate. If a run-time
> check exists and the framework could handle this gracefully, why would
> you still choose the split api?
No. IMO, the two calls exist because getting a line to toggle at a rate
can involve both slow and fast steps. It's not just a either/or or a
random choice to allow doing it in one context vs. another.
Drivers shouldn't care what the actual steps are. Having drivers care
how long each steps take or what they are (by using the can_sleep APIs)
in each architecture/platform is a bad abstraction.
The main point of the clock prepare/enable/disable/unprepare APIs is
about power management. So, the drivers just need to know when they have
enough time to do the quick part of the enable/disable and the slow part
of the enable/disable (prepare/unprepare) and make the calls in those
locations in code/execution flow. That, IMO is the ideal abstraction.
If drivers need to ensure the clock is fully gated for functional
correctness, then they need to take the time (meaning, postpone the
action to a non-atomic context) and do the full gating by completely
unpreparing the clock.
I have heard this idea about removing the clk_prepare/unprepare API too
many times and it makes me uncomfortable. I would really prefer we (the
community) take this discussion to the end and put an end to it. We
either agree to stick with the clk_prepare APIs or figure out the newer
APIs. I don't want to keep having to deal with the "we really should be
removing the clk_prepare() APIs" wrench thrown into the discussion every
time we discuss anything related to a locking issue.
Thanks,
Saravana
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare
2012-07-31 0:31 ` Turquette, Mike
2012-07-31 8:21 ` Saravana Kannan
@ 2012-07-31 9:23 ` Russell King - ARM Linux
1 sibling, 0 replies; 16+ messages in thread
From: Russell King - ARM Linux @ 2012-07-31 9:23 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 30, 2012 at 05:31:23PM -0700, Turquette, Mike wrote:
> On Mon, Jul 30, 2012 at 4:02 PM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> > On Mon, Jul 30, 2012 at 03:42:13PM -0700, Turquette, Mike wrote:
> >> On Mon, Jul 30, 2012 at 3:31 PM, Paul Walmsley <paul@pwsan.com> wrote:
> >> > So if we make a change like this one, it seems like we would basically
> >> > expect it to break once we start doing anything meaningful with
> >> > clk_prepare(), like using clk_prepare() for voltage scaling or something
> >> > that requires I2C? We'd also probably want to mark this with some kind of
> >> > "HACK" comment.
> >>
> >> Hi Paul,
> >>
> >> Did you have anything in mind to start using clk_prepare? I still
> >> hope to get rid of it some day and replace that call with a
> >> combination of clk_enable and a check like clk_enable_can_sleep.
> >
> > Don't you dare.
> >
> > We arrived at the clk_prepare()/clk_enable() split after lots of
> > discussion between different platform maintainers and their
> > requirements.
> >
> > Shoving crap like "clk_enable_can_sleep()" down into drivers is
> > totally and utterly idiotic. We've had the situation *already*
> > where some drivers can be used on some platforms but not on others
> > because of differences in clk_enable() expectations.
> >
>
> How does having a dynamic run-time check cause a generic driver to run
> on "some platforms but not on others"?
What you're asking is for drivers which use clk_prepare() and clk_enable()
correctly to be littered with:
- clk_prepare(clk);
+ if (clk_enable_can_sleep(clk))
+ clk_enable(clk);
and, in atomic contexts:
- clk_enable(clk);
+ if (!clk_enable_can_sleep(clk))
+ clk_enable(clk);
which is total bollocks - drivers should not need to know about this
clk_enable_can_sleep() crap.
> Two calls exist because of context differences. But in practice they
> do the same thing: cause a line to toggle at a rate. If a run-time
> check exists and the framework could handle this gracefully, why would
> you still choose the split api?
How can it handle it gracefully?
Take a look at something like amba-pl011.c for a clue. Remove the
clk_prepare() and clk_unprepare() calls. Then consider a clk
implementation which does not support clk_enable()/clk_disable() from
atomic contexts. Now think about how the pl011 driver enable the clock
for console output from atomic contexts? Answer, it can't.
We've been here before with this stuff, and this is exactly why we split
clk_enable() into the two separate calls we have today.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare
2012-07-31 8:21 ` Saravana Kannan
@ 2012-07-31 9:27 ` Russell King - ARM Linux
0 siblings, 0 replies; 16+ messages in thread
From: Russell King - ARM Linux @ 2012-07-31 9:27 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 31, 2012 at 01:21:24AM -0700, Saravana Kannan wrote:
> I have heard this idea about removing the clk_prepare/unprepare API too
> many times and it makes me uncomfortable. I would really prefer we (the
> community) take this discussion to the end and put an end to it. We
> either agree to stick with the clk_prepare APIs or figure out the newer
> APIs. I don't want to keep having to deal with the "we really should be
> removing the clk_prepare() APIs" wrench thrown into the discussion every
> time we discuss anything related to a locking issue.
Well, part of the motivation to remove it comes from the fact that we
have this "clk_prepare_enable()" thing which _everyone_ simply converts
their existing clk_enable() call to without _thinking_ one little bit
about the rest of the picture.
It's that which is making the justification for getting rid of the split
API soo easy. If people put more thought into it then the separation of
the two calls would be much clearer, and there would be more of a
justification to prevent its removal.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare
2012-07-30 22:42 ` Turquette, Mike
2012-07-30 23:02 ` Russell King - ARM Linux
@ 2012-07-31 18:00 ` Paul Walmsley
1 sibling, 0 replies; 16+ messages in thread
From: Paul Walmsley @ 2012-07-31 18:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mike,
On Mon, 30 Jul 2012, Turquette, Mike wrote:
> On Mon, Jul 30, 2012 at 3:31 PM, Paul Walmsley <paul@pwsan.com> wrote:
>
> > So if we make a change like this one, it seems like we would basically
> > expect it to break once we start doing anything meaningful with
> > clk_prepare(), like using clk_prepare() for voltage scaling or
> > something that requires I2C? We'd also probably want to mark this
> > with some kind of "HACK" comment.
>
> Did you have anything in mind to start using clk_prepare? I still hope
> to get rid of it some day and replace that call with a combination of
> clk_enable and a check like clk_enable_can_sleep.
Nothing that requires immediate attention. Mostly am just trying to think
through how to reconcile the clock and device management code that we have
with what other SoC programmers are apparently implementing in their
platform code.
- Paul
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2012-07-31 18:00 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-07-02 10:24 [PATCH v3 0/3] Prepare for OMAP2+ movement to Common Clk Rajendra Nayak
2012-07-02 10:24 ` [PATCH v3 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare Rajendra Nayak
2012-07-30 22:31 ` Paul Walmsley
2012-07-30 22:42 ` Turquette, Mike
2012-07-30 23:02 ` Russell King - ARM Linux
2012-07-31 0:31 ` Turquette, Mike
2012-07-31 8:21 ` Saravana Kannan
2012-07-31 9:27 ` Russell King - ARM Linux
2012-07-31 9:23 ` Russell King - ARM Linux
2012-07-31 18:00 ` Paul Walmsley
2012-07-02 10:24 ` [PATCH v3 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage Rajendra Nayak
2012-07-02 10:24 ` [PATCH v3 3/3] ARM: omap: clk: Remove all direct dereferencing of struct clk Rajendra Nayak
2012-07-30 7:12 ` Paul Walmsley
2012-07-30 7:36 ` Rajendra Nayak
2012-07-30 18:56 ` Paul Walmsley
2012-07-31 6:05 ` Rajendra Nayak
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