[PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

[PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

[Kukjin Kim]

From: Changhwan Youn <chaos.youn@samsung.com>

This patch is applied according to the commit 1a8e41cd672f894bbd74874eac601e6cedf838fb
(ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register).

Actually, S5PV310 has same cache controller(PL310).

Following is from Catalin Marinas' commit.

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Cc: <stable@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-s5pv310/cpu.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 82ce4aa..b2a37d0 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
 	__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 		     S5P_VA_L2CC + L2X0_POWER_CTRL);
 
-	l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
+	l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 
 	return 0;
 }
-- 
1.6.2.5

[PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

[Catalin Marinas]

On Wed, 2010-11-17 at 06:55 +0000, Kukjin Kim wrote:
> --- a/arch/arm/mach-s5pv310/cpu.c
> +++ b/arch/arm/mach-s5pv310/cpu.c
> @@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
>         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
>                      S5P_VA_L2CC + L2X0_POWER_CTRL);
> 
> -       l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
> +       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);

The patch is fine.

But I think we should also set this bit in the cache-l2x0.c file if
PL310. That's such a fundamental issue and it's easy to miss in the
platform code.

-- 
Catalin

[PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

[shiraz hashim]

Hi Catalin,

On Wed, Nov 17, 2010 at 2:37 PM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
>
> On Wed, 2010-11-17 at 06:55 +0000, Kukjin Kim wrote:
> > --- a/arch/arm/mach-s5pv310/cpu.c
> > +++ b/arch/arm/mach-s5pv310/cpu.c
> > @@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
> >         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
> >                      S5P_VA_L2CC + L2X0_POWER_CTRL);
> >
> > -       l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
> > +       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
>
> The patch is fine.
>
> But I think we should also set this bit in the cache-l2x0.c file if
> PL310. That's such a fundamental issue and it's easy to miss in the
> platform code.

Sorry for reviving this old patch but any reasons why it didn't
go to the cache-l2x0.c directly (for PL310).

--
regards
Shiraz Hashim

[PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

[Catalin Marinas]

On Mon, Aug 13, 2012 at 08:21:14AM +0100, shiraz hashim wrote:
> On Wed, Nov 17, 2010 at 2:37 PM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
> >
> > On Wed, 2010-11-17 at 06:55 +0000, Kukjin Kim wrote:
> > > --- a/arch/arm/mach-s5pv310/cpu.c
> > > +++ b/arch/arm/mach-s5pv310/cpu.c
> > > @@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
> > >         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
> > >                      S5P_VA_L2CC + L2X0_POWER_CTRL);
> > >
> > > -       l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
> > > +       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
> >
> > The patch is fine.
> >
> > But I think we should also set this bit in the cache-l2x0.c file if
> > PL310. That's such a fundamental issue and it's easy to miss in the
> > platform code.
> 
> Sorry for reviving this old patch but any reasons why it didn't
> go to the cache-l2x0.c directly (for PL310).

The cache-l2x0.c patch has been around for a while:

http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6529/1

It may no longer apply cleanly but I haven't revived it since it wasn't
accepted at the time.

-- 
Catalin