[PATCH v3 0/4] Add support to enable ARM PMU for EXYNOS

[PATCH v3 0/4] Add support to enable ARM PMU for EXYNOS

[Chanho Park]

This patchset fixes irq numbers of ARM Performance Monitoring unit and enable it
for Perf(Performance Counter) on the exynos 4 and 5. The exynos4 and 5 use 2
more cpu cores which has its own pmu.
The exynos uses combiner-irq type for arm-pmu. Especially, the exynos4412 has 4
extra combined irq groups. So, we need to change a max combiner number.
To enable perf, we need also to implement a set_irq_affinity function about the
combiner-irq. After applying this patch, we can use the perf for the exynos
machine.

Changes from v2:
 - Convert to dt binding of exynos5250

Changes from v1:
 - Split arm-pmu init of exynos from plat-samsung
 - Correct combined irqs of exynos4412
 - Use soc_is_xxx function instead of CONFIG_XXX to identify dynamically

Chanho Park (4):
  ARM: EXYNOS: Add set_irq_affinity function for combiner_irq
  ARM: EXYNOS: Correct combined IRQs for exynos4412
  ARM: EXYNOS: Enable PMUs for exynos4
  ARM: EXYNOS: Add arm-pmu DT binding for exynos5250

 arch/arm/boot/dts/exynos5250.dtsi        |    6 ++
 arch/arm/mach-exynos/common.c            |  106 ++++++++++++++++++++++++++----
 arch/arm/mach-exynos/include/mach/irqs.h |   10 ++-
 arch/arm/plat-samsung/devs.c             |    2 +-
 4 files changed, 109 insertions(+), 15 deletions(-)

-- 
1.7.9.5

[PATCH v3 1/4] ARM: EXYNOS: Add set_irq_affinity function for combiner_irq

[Chanho Park]

This patch adds set_irq_affinity function for combiner_irq. We need this
function to enable a arm-pmu because the pmu of exynos has combined type irqs.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/common.c |   30 +++++++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cd..f194bbc 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -405,6 +405,7 @@ struct combiner_chip_data {
 	unsigned int irq_offset;
 	unsigned int irq_mask;
 	void __iomem *base;
+	unsigned int parent_irq;
 };
 
 static struct irq_domain *combiner_irq_domain;
@@ -461,10 +462,28 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
+#ifdef CONFIG_SMP
+static int combiner_set_affinity(struct irq_data *d,
+				 const struct cpumask *mask_val, bool force)
+{
+	struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
+	struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
+	struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
+
+	if (chip && chip->irq_set_affinity)
+		return chip->irq_set_affinity(data, mask_val, force);
+	else
+		return -EINVAL;
+}
+#endif
+
 static struct irq_chip combiner_chip = {
-	.name		= "COMBINER",
-	.irq_mask	= combiner_mask_irq,
-	.irq_unmask	= combiner_unmask_irq,
+	.name			= "COMBINER",
+	.irq_mask		= combiner_mask_irq,
+	.irq_unmask		= combiner_unmask_irq,
+#ifdef CONFIG_SMP
+	.irq_set_affinity	= combiner_set_affinity,
+#endif
 };
 
 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
@@ -484,12 +503,13 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
 }
 
 static void __init combiner_init_one(unsigned int combiner_nr,
-				     void __iomem *base)
+				     void __iomem *base, unsigned int irq)
 {
 	combiner_data[combiner_nr].base = base;
 	combiner_data[combiner_nr].irq_offset = irq_find_mapping(
 		combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
 	combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
+	combiner_data[combiner_nr].parent_irq = irq;
 
 	/* Disable all interrupts */
 	__raw_writel(combiner_data[combiner_nr].irq_mask,
@@ -573,12 +593,12 @@ static void __init combiner_init(void __iomem *combiner_base,
 	}
 
 	for (i = 0; i < max_nr; i++) {
-		combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
 		irq = IRQ_SPI(i);
 #ifdef CONFIG_OF
 		if (np)
 			irq = irq_of_parse_and_map(np, i);
 #endif
+		combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq);
 		combiner_cascade_irq(i, irq);
 	}
 }
-- 
1.7.9.5

[PATCH v3 2/4] ARM: EXYNOS: Correct combined IRQs for exynos4412

[Chanho Park]

This patch corrects combined IRQs for exynos4412 platform. The exynos4412 has
four extra combined irq group. Each irq is mapped to IRQ_SPI(xx). Unfortunately,
extra combined IRQs isn't sequential. So, we need to map the irq manually.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/common.c            |   31 ++++++++++++++++++++++++------
 arch/arm/mach-exynos/include/mach/irqs.h |    2 +-
 2 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f194bbc..be61564 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -560,23 +560,39 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
 	.map	= combiner_irq_domain_map,
 };
 
+static unsigned int get_combiner_extra_irq(int group)
+{
+	switch (group) {
+	case 16:
+		return IRQ_SPI(107);
+	case 17:
+		return IRQ_SPI(108);
+	case 18:
+		return IRQ_SPI(48);
+	case 19:
+		return IRQ_SPI(42);
+	default:
+		return 0;
+	}
+}
+
 static void __init combiner_init(void __iomem *combiner_base,
 				 struct device_node *np)
 {
 	int i, irq, irq_base;
 	unsigned int max_nr, nr_irq;
 
+	max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
+					EXYNOS4_MAX_COMBINER_NR;
+
 	if (np) {
 		if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
 			pr_warning("%s: number of combiners not specified, "
 				"setting default as %d.\n",
-				__func__, EXYNOS4_MAX_COMBINER_NR);
-			max_nr = EXYNOS4_MAX_COMBINER_NR;
+				__func__, max_nr);
 		}
-	} else {
-		max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
-						EXYNOS4_MAX_COMBINER_NR;
 	}
+
 	nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 
 	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
@@ -593,7 +609,10 @@ static void __init combiner_init(void __iomem *combiner_base,
 	}
 
 	for (i = 0; i < max_nr; i++) {
-		irq = IRQ_SPI(i);
+		if (i < 16 || soc_is_exynos5250())
+			irq = IRQ_SPI(i);
+		else
+			irq = get_combiner_extra_irq(i);
 #ifdef CONFIG_OF
 		if (np)
 			irq = irq_of_parse_and_map(np, i);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 35bced6..357ed7f 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -165,7 +165,7 @@
 #define EXYNOS4_IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
 #define EXYNOS4_IRQ_FIMD0_SYSTEM	COMBINER_IRQ(11, 2)
 
-#define EXYNOS4_MAX_COMBINER_NR		16
+#define EXYNOS4_MAX_COMBINER_NR		20
 
 #define EXYNOS4_IRQ_GPIO1_NR_GROUPS	16
 #define EXYNOS4_IRQ_GPIO2_NR_GROUPS	9
-- 
1.7.9.5

[PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4

[Chanho Park]

This patch define irq numbers of ARM performance monitoring unit for exynos4.
The number of CPU cores and PMU irq numbers are vary according to soc types.
So we need to identify each soc type using soc_is_xxx function and define the
pmu irqs dynamically. In case of exynos4412, there are 4 cpu cores and pmus.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/common.c            |   45 ++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++--
 arch/arm/plat-samsung/devs.c             |    2 +-
 3 files changed, 52 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index be61564..24b78bd 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -30,11 +30,13 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/cacheflush.h>
+#include <asm/pmu.h>
 
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
 #include <mach/regs-gpio.h>
 #include <mach/pmu.h>
+#include <mach/irqs.h>
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
@@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
 	return 0;
 }
 arch_initcall(exynos_init_irq_eint);
+
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+static struct resource exynos42xx_pmu_resource[] = {
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+};
+
+static struct platform_device exynos42xx_device_pmu = {
+	.name		= "arm-pmu",
+	.num_resources	= ARRAY_SIZE(exynos42xx_pmu_resource),
+	.resource	= exynos42xx_pmu_resource,
+};
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS4412)
+static struct resource exynos44xx_pmu_resource[] = {
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
+};
+
+static struct platform_device exynos44xx_device_pmu = {
+	.name		= "arm-pmu",
+	.num_resources	= ARRAY_SIZE(exynos44xx_pmu_resource),
+	.resource	= exynos44xx_pmu_resource,
+};
+#endif
+
+static int __init exynos_armpmu_init(void)
+{
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+	if (soc_is_exynos4210() || soc_is_exynos4212())
+		platform_device_register(&exynos42xx_device_pmu);
+#endif
+#if defined(CONFIG_SOC_EXYNOS4412)
+	if (soc_is_exynos4412())
+		platform_device_register(&exynos44xx_device_pmu);
+#endif
+
+	return 0;
+}
+arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 357ed7f..5e75b19 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -128,7 +128,7 @@
 #define EXYNOS4_IRQ_ADC1		IRQ_SPI(107)
 #define EXYNOS4_IRQ_PEN1		IRQ_SPI(108)
 #define EXYNOS4_IRQ_KEYPAD		IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMU			IRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU		IRQ_SPI(110)
 #define EXYNOS4_IRQ_GPS			IRQ_SPI(111)
 #define EXYNOS4_IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
 #define EXYNOS4_IRQ_SLIMBUS		IRQ_SPI(113)
@@ -136,6 +136,11 @@
 #define EXYNOS4_IRQ_TSI			IRQ_SPI(115)
 #define EXYNOS4_IRQ_SATA		IRQ_SPI(116)
 
+#define EXYNOS4_IRQ_PMU			COMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1		COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2		COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3		COMBINER_IRQ(19, 2)
+
 #define EXYNOS4_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
 #define EXYNOS4_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
 #define EXYNOS4_IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
@@ -230,7 +235,6 @@
 #define IRQ_TC				EXYNOS4_IRQ_PEN0
 
 #define IRQ_KEYPAD			EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMU				EXYNOS4_IRQ_PMU
 
 #define IRQ_FIMD0_FIFO			EXYNOS4_IRQ_FIMD0_FIFO
 #define IRQ_FIMD0_VSYNC			EXYNOS4_IRQ_FIMD0_VSYNC
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index fc49f3d..3b44dad 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1125,7 +1125,7 @@ struct platform_device s5p_device_onenand = {
 
 /* PMU */
 
-#ifdef CONFIG_PLAT_S5P
+#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
 static struct resource s5p_pmu_resource[] = {
 	DEFINE_RES_IRQ(IRQ_PMU)
 };
-- 
1.7.9.5

[PATCH v3 4/4] ARM: EXYNOS: Add arm-pmu DT binding for exynos5250

[Chanho Park]

This patch enables arm-pmu to bind device tree for exynos5250. The exynos5250
has two pmus which have combiner irq type.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8..45746cbf 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -52,6 +52,12 @@
 			     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
 	};
 
+	pmu {
+		compatible = "arm,cortex-a15-pmu";
+		interrupt-parent = <&combiner>;
+		interrupts = <1 2>, <22 4>;
+	};
+
 	watchdog {
 		compatible = "samsung,s3c2410-wdt";
 		reg = <0x101D0000 0x100>;
-- 
1.7.9.5

[PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4

[Sachin Kamat]

Hi Chanho,

On 29 August 2012 06:44, Chanho Park <chanho61.park@samsung.com> wrote:
> This patch define irq numbers of ARM performance monitoring unit for exynos4.
> The number of CPU cores and PMU irq numbers are vary according to soc types.
> So we need to identify each soc type using soc_is_xxx function and define the
> pmu irqs dynamically. In case of exynos4412, there are 4 cpu cores and pmus.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/common.c            |   45 ++++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++--
>  arch/arm/plat-samsung/devs.c             |    2 +-
>  3 files changed, 52 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index be61564..24b78bd 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -30,11 +30,13 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  #include <asm/cacheflush.h>
> +#include <asm/pmu.h>
>
>  #include <mach/regs-irq.h>
>  #include <mach/regs-pmu.h>
>  #include <mach/regs-gpio.h>
>  #include <mach/pmu.h>
> +#include <mach/irqs.h>
>
>  #include <plat/cpu.h>
>  #include <plat/clock.h>
> @@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
>         return 0;
>  }
>  arch_initcall(exynos_init_irq_eint);
> +
> +#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
> +static struct resource exynos42xx_pmu_resource[] = {
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> +};
> +
> +static struct platform_device exynos42xx_device_pmu = {
> +       .name           = "arm-pmu",
> +       .num_resources  = ARRAY_SIZE(exynos42xx_pmu_resource),
> +       .resource       = exynos42xx_pmu_resource,
> +};
> +#endif
> +
> +#if defined(CONFIG_SOC_EXYNOS4412)
> +static struct resource exynos44xx_pmu_resource[] = {
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
> +};
> +
> +static struct platform_device exynos44xx_device_pmu = {
> +       .name           = "arm-pmu",
> +       .num_resources  = ARRAY_SIZE(exynos44xx_pmu_resource),
> +       .resource       = exynos44xx_pmu_resource,
> +};
> +#endif
> +
> +static int __init exynos_armpmu_init(void)
> +{
> +#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
> +       if (soc_is_exynos4210() || soc_is_exynos4212())
> +               platform_device_register(&exynos42xx_device_pmu);
> +#endif
> +#if defined(CONFIG_SOC_EXYNOS4412)
> +       if (soc_is_exynos4412())
> +               platform_device_register(&exynos44xx_device_pmu);
> +#endif

Do we need both compile time and run-time checks here?


> +
> +       return 0;
> +}
> +arch_initcall(exynos_armpmu_init);
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
> index 357ed7f..5e75b19 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -128,7 +128,7 @@
>  #define EXYNOS4_IRQ_ADC1               IRQ_SPI(107)
>  #define EXYNOS4_IRQ_PEN1               IRQ_SPI(108)
>  #define EXYNOS4_IRQ_KEYPAD             IRQ_SPI(109)
> -#define EXYNOS4_IRQ_PMU                        IRQ_SPI(110)
> +#define EXYNOS4_IRQ_POWER_PMU          IRQ_SPI(110)
>  #define EXYNOS4_IRQ_GPS                        IRQ_SPI(111)
>  #define EXYNOS4_IRQ_INTFEEDCTRL_SSS    IRQ_SPI(112)
>  #define EXYNOS4_IRQ_SLIMBUS            IRQ_SPI(113)
> @@ -136,6 +136,11 @@
>  #define EXYNOS4_IRQ_TSI                        IRQ_SPI(115)
>  #define EXYNOS4_IRQ_SATA               IRQ_SPI(116)
>
> +#define EXYNOS4_IRQ_PMU                        COMBINER_IRQ(2, 2)
> +#define EXYNOS4_IRQ_PMU_CPU1           COMBINER_IRQ(3, 2)
> +#define EXYNOS4_IRQ_PMU_CPU2           COMBINER_IRQ(18, 2)
> +#define EXYNOS4_IRQ_PMU_CPU3           COMBINER_IRQ(19, 2)
> +
>  #define EXYNOS4_IRQ_SYSMMU_MDMA0_0     COMBINER_IRQ(4, 0)
>  #define EXYNOS4_IRQ_SYSMMU_SSS_0       COMBINER_IRQ(4, 1)
>  #define EXYNOS4_IRQ_SYSMMU_FIMC0_0     COMBINER_IRQ(4, 2)
> @@ -230,7 +235,6 @@
>  #define IRQ_TC                         EXYNOS4_IRQ_PEN0
>
>  #define IRQ_KEYPAD                     EXYNOS4_IRQ_KEYPAD
> -#define IRQ_PMU                                EXYNOS4_IRQ_PMU
>
>  #define IRQ_FIMD0_FIFO                 EXYNOS4_IRQ_FIMD0_FIFO
>  #define IRQ_FIMD0_VSYNC                        EXYNOS4_IRQ_FIMD0_VSYNC
> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
> index fc49f3d..3b44dad 100644
> --- a/arch/arm/plat-samsung/devs.c
> +++ b/arch/arm/plat-samsung/devs.c
> @@ -1125,7 +1125,7 @@ struct platform_device s5p_device_onenand = {
>
>  /* PMU */
>
> -#ifdef CONFIG_PLAT_S5P
> +#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
>  static struct resource s5p_pmu_resource[] = {
>         DEFINE_RES_IRQ(IRQ_PMU)
>  };
> --
> 1.7.9.5
>



-- 
With warm regards,
Sachin

[PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4

[Chanho Park]

> -----Original Message-----
> From: Sachin Kamat [mailto:sachin.kamat at linaro.org]
> Sent: Wednesday, August 29, 2012 12:39 PM
> To: Chanho Park
> Cc: kgene.kim at samsung.com; linux-arm-kernel at lists.infradead.org; linux-
> samsung-soc at vger.kernel.org; linux at arm.linux.org.uk;
> will.deacon at arm.com; thomas.abraham at linaro.org; Kyungmin Park
> Subject: Re: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
> 
> Hi Chanho,
> 
> On 29 August 2012 06:44, Chanho Park <chanho61.park@samsung.com>
> wrote:
> > This patch define irq numbers of ARM performance monitoring unit for
> exynos4.
> > The number of CPU cores and PMU irq numbers are vary according to soc
> types.
> > So we need to identify each soc type using soc_is_xxx function and
> > define the pmu irqs dynamically. In case of exynos4412, there are 4 cpu
> cores and pmus.
> >
> > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > ---
> >  arch/arm/mach-exynos/common.c            |   45
> ++++++++++++++++++++++++++++++
> >  arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++--
> >  arch/arm/plat-samsung/devs.c             |    2 +-
> >  3 files changed, 52 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/common.c
> > b/arch/arm/mach-exynos/common.c index be61564..24b78bd 100644
> > --- a/arch/arm/mach-exynos/common.c
> > +++ b/arch/arm/mach-exynos/common.c
> > @@ -30,11 +30,13 @@
> >  #include <asm/mach/map.h>
> >  #include <asm/mach/irq.h>
> >  #include <asm/cacheflush.h>
> > +#include <asm/pmu.h>
> >
> >  #include <mach/regs-irq.h>
> >  #include <mach/regs-pmu.h>
> >  #include <mach/regs-gpio.h>
> >  #include <mach/pmu.h>
> > +#include <mach/irqs.h>
> >
> >  #include <plat/cpu.h>
> >  #include <plat/clock.h>
> > @@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
> >         return 0;
> >  }
> >  arch_initcall(exynos_init_irq_eint);
> > +
> > +#if defined(CONFIG_CPU_EXYNOS4210) ||
> defined(CONFIG_SOC_EXYNOS4212)
> > +static struct resource exynos42xx_pmu_resource[] = {
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> > +};
> > +
> > +static struct platform_device exynos42xx_device_pmu = {
> > +       .name           = "arm-pmu",
> > +       .num_resources  = ARRAY_SIZE(exynos42xx_pmu_resource),
> > +       .resource       = exynos42xx_pmu_resource,
> > +};
> > +#endif
> > +
> > +#if defined(CONFIG_SOC_EXYNOS4412)
> > +static struct resource exynos44xx_pmu_resource[] = {
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
> > +};
> > +
> > +static struct platform_device exynos44xx_device_pmu = {
> > +       .name           = "arm-pmu",
> > +       .num_resources  = ARRAY_SIZE(exynos44xx_pmu_resource),
> > +       .resource       = exynos44xx_pmu_resource,
> > +};
> > +#endif
> > +
> > +static int __init exynos_armpmu_init(void) { #if
> > +defined(CONFIG_CPU_EXYNOS4210) ||
> defined(CONFIG_SOC_EXYNOS4212)
> > +       if (soc_is_exynos4210() || soc_is_exynos4212())
> > +               platform_device_register(&exynos42xx_device_pmu);
> > +#endif
> > +#if defined(CONFIG_SOC_EXYNOS4412)
> > +       if (soc_is_exynos4412())
> > +               platform_device_register(&exynos44xx_device_pmu);
> > +#endif
> 
> Do we need both compile time and run-time checks here?

I think we can reduce code size and avoid unnecessary comparison using compile time check if 
turn off these kernel configurations.
And runtime check is helpful when turned on all SoC types in the kernel configurations.

Best regards,
Chanho Park

> 
> 
> > +
> > +       return 0;
> > +}
> > +arch_initcall(exynos_armpmu_init);
> > diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
> > b/arch/arm/mach-exynos/include/mach/irqs.h
> > index 357ed7f..5e75b19 100644
> > --- a/arch/arm/mach-exynos/include/mach/irqs.h
> > +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> > @@ -128,7 +128,7 @@
> >  #define EXYNOS4_IRQ_ADC1               IRQ_SPI(107)
> >  #define EXYNOS4_IRQ_PEN1               IRQ_SPI(108)
> >  #define EXYNOS4_IRQ_KEYPAD             IRQ_SPI(109)
> > -#define EXYNOS4_IRQ_PMU                        IRQ_SPI(110)
> > +#define EXYNOS4_IRQ_POWER_PMU          IRQ_SPI(110)
> >  #define EXYNOS4_IRQ_GPS                        IRQ_SPI(111)
> >  #define EXYNOS4_IRQ_INTFEEDCTRL_SSS    IRQ_SPI(112)
> >  #define EXYNOS4_IRQ_SLIMBUS            IRQ_SPI(113)
> > @@ -136,6 +136,11 @@
> >  #define EXYNOS4_IRQ_TSI                        IRQ_SPI(115)
> >  #define EXYNOS4_IRQ_SATA               IRQ_SPI(116)
> >
> > +#define EXYNOS4_IRQ_PMU                        COMBINER_IRQ(2, 2)
> > +#define EXYNOS4_IRQ_PMU_CPU1           COMBINER_IRQ(3, 2)
> > +#define EXYNOS4_IRQ_PMU_CPU2           COMBINER_IRQ(18, 2)
> > +#define EXYNOS4_IRQ_PMU_CPU3           COMBINER_IRQ(19, 2)
> > +
> >  #define EXYNOS4_IRQ_SYSMMU_MDMA0_0     COMBINER_IRQ(4, 0)
> >  #define EXYNOS4_IRQ_SYSMMU_SSS_0       COMBINER_IRQ(4, 1)
> >  #define EXYNOS4_IRQ_SYSMMU_FIMC0_0     COMBINER_IRQ(4, 2)
> > @@ -230,7 +235,6 @@
> >  #define IRQ_TC                         EXYNOS4_IRQ_PEN0
> >
> >  #define IRQ_KEYPAD                     EXYNOS4_IRQ_KEYPAD
> > -#define IRQ_PMU                                EXYNOS4_IRQ_PMU
> >
> >  #define IRQ_FIMD0_FIFO                 EXYNOS4_IRQ_FIMD0_FIFO
> >  #define IRQ_FIMD0_VSYNC                        EXYNOS4_IRQ_FIMD0_VSYNC
> > diff --git a/arch/arm/plat-samsung/devs.c
> > b/arch/arm/plat-samsung/devs.c index fc49f3d..3b44dad 100644
> > --- a/arch/arm/plat-samsung/devs.c
> > +++ b/arch/arm/plat-samsung/devs.c
> > @@ -1125,7 +1125,7 @@ struct platform_device s5p_device_onenand = {
> >
> >  /* PMU */
> >
> > -#ifdef CONFIG_PLAT_S5P
> > +#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
> >  static struct resource s5p_pmu_resource[] = {
> >         DEFINE_RES_IRQ(IRQ_PMU)
> >  };
> > --
> > 1.7.9.5
> >
> 
> 
> 
> --
> With warm regards,
> Sachin

[PATCH v3 1/4] ARM: EXYNOS: Add set_irq_affinity function for combiner_irq

[Thomas Abraham]

On 29 August 2012 06:44, Chanho Park <chanho61.park@samsung.com> wrote:
> This patch adds set_irq_affinity function for combiner_irq. We need this
> function to enable a arm-pmu because the pmu of exynos has combined type irqs.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/common.c |   30 +++++++++++++++++++++++++-----
>  1 file changed, 25 insertions(+), 5 deletions(-)

Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>

>
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 4eb39cd..f194bbc 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -405,6 +405,7 @@ struct combiner_chip_data {
>         unsigned int irq_offset;
>         unsigned int irq_mask;
>         void __iomem *base;
> +       unsigned int parent_irq;
>  };
>
>  static struct irq_domain *combiner_irq_domain;
> @@ -461,10 +462,28 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
>         chained_irq_exit(chip, desc);
>  }
>
> +#ifdef CONFIG_SMP
> +static int combiner_set_affinity(struct irq_data *d,
> +                                const struct cpumask *mask_val, bool force)
> +{
> +       struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
> +       struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
> +       struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
> +
> +       if (chip && chip->irq_set_affinity)
> +               return chip->irq_set_affinity(data, mask_val, force);
> +       else
> +               return -EINVAL;
> +}
> +#endif
> +
>  static struct irq_chip combiner_chip = {
> -       .name           = "COMBINER",
> -       .irq_mask       = combiner_mask_irq,
> -       .irq_unmask     = combiner_unmask_irq,
> +       .name                   = "COMBINER",
> +       .irq_mask               = combiner_mask_irq,
> +       .irq_unmask             = combiner_unmask_irq,
> +#ifdef CONFIG_SMP
> +       .irq_set_affinity       = combiner_set_affinity,
> +#endif
>  };
>
>  static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
> @@ -484,12 +503,13 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
>  }
>
>  static void __init combiner_init_one(unsigned int combiner_nr,
> -                                    void __iomem *base)
> +                                    void __iomem *base, unsigned int irq)
>  {
>         combiner_data[combiner_nr].base = base;
>         combiner_data[combiner_nr].irq_offset = irq_find_mapping(
>                 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
>         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
> +       combiner_data[combiner_nr].parent_irq = irq;
>
>         /* Disable all interrupts */
>         __raw_writel(combiner_data[combiner_nr].irq_mask,
> @@ -573,12 +593,12 @@ static void __init combiner_init(void __iomem *combiner_base,
>         }
>
>         for (i = 0; i < max_nr; i++) {
> -               combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
>                 irq = IRQ_SPI(i);
>  #ifdef CONFIG_OF
>                 if (np)
>                         irq = irq_of_parse_and_map(np, i);
>  #endif
> +               combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq);
>                 combiner_cascade_irq(i, irq);
>         }
>  }
> --
> 1.7.9.5
>

[PATCH v3 2/4] ARM: EXYNOS: Correct combined IRQs for exynos4412

[Thomas Abraham]

On 29 August 2012 06:44, Chanho Park <chanho61.park@samsung.com> wrote:
> This patch corrects combined IRQs for exynos4412 platform. The exynos4412 has
> four extra combined irq group. Each irq is mapped to IRQ_SPI(xx). Unfortunately,
> extra combined IRQs isn't sequential. So, we need to map the irq manually.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/common.c            |   31 ++++++++++++++++++++++++------
>  arch/arm/mach-exynos/include/mach/irqs.h |    2 +-
>  2 files changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index f194bbc..be61564 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -560,23 +560,39 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
>         .map    = combiner_irq_domain_map,
>  };
>
> +static unsigned int get_combiner_extra_irq(int group)
> +{
> +       switch (group) {
> +       case 16:
> +               return IRQ_SPI(107);
> +       case 17:
> +               return IRQ_SPI(108);
> +       case 18:
> +               return IRQ_SPI(48);
> +       case 19:
> +               return IRQ_SPI(42);
> +       default:
> +               return 0;
> +       }
> +}
> +
>  static void __init combiner_init(void __iomem *combiner_base,
>                                  struct device_node *np)
>  {
>         int i, irq, irq_base;
>         unsigned int max_nr, nr_irq;
>
> +       max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
> +                                       EXYNOS4_MAX_COMBINER_NR;
> +
>         if (np) {
>                 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
>                         pr_warning("%s: number of combiners not specified, "
>                                 "setting default as %d.\n",
> -                               __func__, EXYNOS4_MAX_COMBINER_NR);
> -                       max_nr = EXYNOS4_MAX_COMBINER_NR;
> +                               __func__, max_nr);
>                 }
> -       } else {
> -               max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
> -                                               EXYNOS4_MAX_COMBINER_NR;
>         }
> +
>         nr_irq = max_nr * MAX_IRQ_IN_COMBINER;

Along with this change, this patch should update the default value
"samsung,combiner-nr" binding in device tree binding documentation for
combiner. It should state that is Exynos5 will use 32 and Exynos4 will
use 20 as the default value.

>
>         irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
> @@ -593,7 +609,10 @@ static void __init combiner_init(void __iomem *combiner_base,
>         }
>
>         for (i = 0; i < max_nr; i++) {
> -               irq = IRQ_SPI(i);
> +               if (i < 16 || soc_is_exynos5250())
> +                       irq = IRQ_SPI(i);
> +               else
> +                       irq = get_combiner_extra_irq(i);
>  #ifdef CONFIG_OF
>                 if (np)
>                         irq = irq_of_parse_and_map(np, i);
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
> index 35bced6..357ed7f 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -165,7 +165,7 @@
>  #define EXYNOS4_IRQ_FIMD0_VSYNC                COMBINER_IRQ(11, 1)
>  #define EXYNOS4_IRQ_FIMD0_SYSTEM       COMBINER_IRQ(11, 2)
>
> -#define EXYNOS4_MAX_COMBINER_NR                16
> +#define EXYNOS4_MAX_COMBINER_NR                20

Will this not break Exynos4210 which has only 16 combiners? This is
fine in case max-combiner values is listed in dt mode, but in non-dt
mode or if max-combiner is not specified in dt, this will not be
correct.

>
>  #define EXYNOS4_IRQ_GPIO1_NR_GROUPS    16
>  #define EXYNOS4_IRQ_GPIO2_NR_GROUPS    9
> --
> 1.7.9.5
>

[PATCH v3 4/4] ARM: EXYNOS: Add arm-pmu DT binding for exynos5250

[Thomas Abraham]

On 29 August 2012 06:44, Chanho Park <chanho61.park@samsung.com> wrote:
> This patch enables arm-pmu to bind device tree for exynos5250. The exynos5250
> has two pmus which have combiner irq type.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 004aaa8..45746cbf 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -52,6 +52,12 @@
>                              <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
>         };
>
> +       pmu {
> +               compatible = "arm,cortex-a15-pmu";
> +               interrupt-parent = <&combiner>;
> +               interrupts = <1 2>, <22 4>;
> +       };
> +
>         watchdog {
>                 compatible = "samsung,s3c2410-wdt";
>                 reg = <0x101D0000 0x100>;
> --
> 1.7.9.5
>

Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>

Probably, this should be doable for Exynos4 as well.

[PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4

[Will Deacon]

On Wed, Aug 29, 2012 at 02:14:56AM +0100, Chanho Park wrote:
> This patch define irq numbers of ARM performance monitoring unit for exynos4.
> The number of CPU cores and PMU irq numbers are vary according to soc types.
> So we need to identify each soc type using soc_is_xxx function and define the
> pmu irqs dynamically. In case of exynos4412, there are 4 cpu cores and pmus.
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/common.c            |   45 ++++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++--
>  arch/arm/plat-samsung/devs.c             |    2 +-
>  3 files changed, 52 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index be61564..24b78bd 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -30,11 +30,13 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  #include <asm/cacheflush.h>
> +#include <asm/pmu.h>

Why do you need this header file?

>  #include <mach/regs-irq.h>
>  #include <mach/regs-pmu.h>
>  #include <mach/regs-gpio.h>
>  #include <mach/pmu.h>
> +#include <mach/irqs.h>
>  
>  #include <plat/cpu.h>
>  #include <plat/clock.h>
> @@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
>  	return 0;
>  }
>  arch_initcall(exynos_init_irq_eint);
> +
> +#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
> +static struct resource exynos42xx_pmu_resource[] = {
> +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> +};
> +
> +static struct platform_device exynos42xx_device_pmu = {
> +	.name		= "arm-pmu",
> +	.num_resources	= ARRAY_SIZE(exynos42xx_pmu_resource),
> +	.resource	= exynos42xx_pmu_resource,
> +};
> +#endif

Given that you don't pass an id and your device-tree binding is that for
Cortex A15, I assume this patch series is based on my perf/updates branch?

That's good because it reduces the potential for conflicts, but you should
make sure that whoever you send this to is aware of the dependency.

Cheers,

Will

[PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4

[Chanho Park]

> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-
> kernel-bounces at lists.infradead.org] On Behalf Of Will Deacon
> Sent: Thursday, August 30, 2012 6:34 AM
> To: Chanho Park
> Cc: linux-samsung-soc at vger.kernel.org; linux at arm.linux.org.uk;
> sachin.kamat at linaro.org; Kyungmin Park; kgene.kim at samsung.com;
> thomas.abraham at linaro.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
> 
> On Wed, Aug 29, 2012 at 02:14:56AM +0100, Chanho Park wrote:
> > This patch define irq numbers of ARM performance monitoring unit for
> exynos4.
> > The number of CPU cores and PMU irq numbers are vary according to soc
> types.
> > So we need to identify each soc type using soc_is_xxx function and
> > define the pmu irqs dynamically. In case of exynos4412, there are 4 cpu
> cores and pmus.
> >
> > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > ---
> >  arch/arm/mach-exynos/common.c            |   45
> ++++++++++++++++++++++++++++++
> >  arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++--
> >  arch/arm/plat-samsung/devs.c             |    2 +-
> >  3 files changed, 52 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/common.c
> > b/arch/arm/mach-exynos/common.c index be61564..24b78bd 100644
> > --- a/arch/arm/mach-exynos/common.c
> > +++ b/arch/arm/mach-exynos/common.c
> > @@ -30,11 +30,13 @@
> >  #include <asm/mach/map.h>
> >  #include <asm/mach/irq.h>
> >  #include <asm/cacheflush.h>
> > +#include <asm/pmu.h>
> 
> Why do you need this header file?

Oh, I'll remove  it. Thanks.

> 
> >  #include <mach/regs-irq.h>
> >  #include <mach/regs-pmu.h>
> >  #include <mach/regs-gpio.h>
> >  #include <mach/pmu.h>
> > +#include <mach/irqs.h>
> >
> >  #include <plat/cpu.h>
> >  #include <plat/clock.h>
> > @@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
> >  	return 0;
> >  }
> >  arch_initcall(exynos_init_irq_eint);
> > +
> > +#if defined(CONFIG_CPU_EXYNOS4210) ||
> defined(CONFIG_SOC_EXYNOS4212)
> > +static struct resource exynos42xx_pmu_resource[] = {
> > +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> > +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> > +};
> > +
> > +static struct platform_device exynos42xx_device_pmu = {
> > +	.name		= "arm-pmu",
> > +	.num_resources	= ARRAY_SIZE(exynos42xx_pmu_resource),
> > +	.resource	= exynos42xx_pmu_resource,
> > +};
> > +#endif
> 
> Given that you don't pass an id and your device-tree binding is that for
> Cortex A15, I assume this patch series is based on my perf/updates branch?
> 
> That's good because it reduces the potential for conflicts, but you should
> make sure that whoever you send this to is aware of the dependency.

Yes. This patch is based on your latest patchset to avoid conflict because I saw Kukjin had acked your patch.
I think he'll resolve the dependency. If not, I'll re-submit this patch after applied your patch.

Best regards,
Chanho Park

> 
> Cheers,
> 
> Will
> 
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> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v3 2/4] ARM: EXYNOS: Correct combined IRQs for exynos4412

[Chanho Park]

> -----Original Message-----
> From: Thomas Abraham [mailto:thomas.abraham at linaro.org]
> Sent: Wednesday, August 29, 2012 8:10 PM
> To: Chanho Park
> Cc: kgene.kim at samsung.com; linux-arm-kernel at lists.infradead.org; linux-
> samsung-soc at vger.kernel.org; linux at arm.linux.org.uk;
> sachin.kamat at linaro.org; will.deacon at arm.com; Kyungmin Park
> Subject: Re: [PATCH v3 2/4] ARM: EXYNOS: Correct combined IRQs for
> exynos4412
> 
> On 29 August 2012 06:44, Chanho Park <chanho61.park@samsung.com>
> wrote:
> > This patch corrects combined IRQs for exynos4412 platform. The
> > exynos4412 has four extra combined irq group. Each irq is mapped to
> > IRQ_SPI(xx). Unfortunately, extra combined IRQs isn't sequential. So, we
> need to map the irq manually.
> >
> > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > ---
> >  arch/arm/mach-exynos/common.c            |   31
> ++++++++++++++++++++++++------
> >  arch/arm/mach-exynos/include/mach/irqs.h |    2 +-
> >  2 files changed, 26 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/common.c
> > b/arch/arm/mach-exynos/common.c index f194bbc..be61564 100644
> > --- a/arch/arm/mach-exynos/common.c
> > +++ b/arch/arm/mach-exynos/common.c
> > @@ -560,23 +560,39 @@ static struct irq_domain_ops
> combiner_irq_domain_ops = {
> >         .map    = combiner_irq_domain_map,
> >  };
> >
> > +static unsigned int get_combiner_extra_irq(int group) {
> > +       switch (group) {
> > +       case 16:
> > +               return IRQ_SPI(107);
> > +       case 17:
> > +               return IRQ_SPI(108);
> > +       case 18:
> > +               return IRQ_SPI(48);
> > +       case 19:
> > +               return IRQ_SPI(42);
> > +       default:
> > +               return 0;
> > +       }
> > +}
> > +
> >  static void __init combiner_init(void __iomem *combiner_base,
> >                                  struct device_node *np)  {
> >         int i, irq, irq_base;
> >         unsigned int max_nr, nr_irq;
> >
> > +       max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
> > +                                       EXYNOS4_MAX_COMBINER_NR;
> > +
> >         if (np) {
> >                 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr))
> {
> >                         pr_warning("%s: number of combiners not specified, "
> >                                 "setting default as %d.\n",
> > -                               __func__, EXYNOS4_MAX_COMBINER_NR);
> > -                       max_nr = EXYNOS4_MAX_COMBINER_NR;
> > +                               __func__, max_nr);
> >                 }
> > -       } else {
> > -               max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
> > -                                               EXYNOS4_MAX_COMBINER_NR;
> >         }
> > +
> >         nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
> 
> Along with this change, this patch should update the default value
> "samsung,combiner-nr" binding in device tree binding documentation for
> combiner. It should state that is Exynos5 will use 32 and Exynos4 will use 20 as
> the default value.
> 
> >
> >         irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
> > @@ -593,7 +609,10 @@ static void __init combiner_init(void __iomem
> *combiner_base,
> >         }
> >
> >         for (i = 0; i < max_nr; i++) {
> > -               irq = IRQ_SPI(i);
> > +               if (i < 16 || soc_is_exynos5250())
> > +                       irq = IRQ_SPI(i);
> > +               else
> > +                       irq = get_combiner_extra_irq(i);
> >  #ifdef CONFIG_OF
> >                 if (np)
> >                         irq = irq_of_parse_and_map(np, i); diff --git
> > a/arch/arm/mach-exynos/include/mach/irqs.h
> > b/arch/arm/mach-exynos/include/mach/irqs.h
> > index 35bced6..357ed7f 100644
> > --- a/arch/arm/mach-exynos/include/mach/irqs.h
> > +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> > @@ -165,7 +165,7 @@
> >  #define EXYNOS4_IRQ_FIMD0_VSYNC                COMBINER_IRQ(11, 1)
> >  #define EXYNOS4_IRQ_FIMD0_SYSTEM       COMBINER_IRQ(11, 2)
> >
> > -#define EXYNOS4_MAX_COMBINER_NR                16
> > +#define EXYNOS4_MAX_COMBINER_NR                20
> 
> Will this not break Exynos4210 which has only 16 combiners? This is fine in
> case max-combiner values is listed in dt mode, but in non-dt mode or if max-
> combiner is not specified in dt, this will not be correct.

I didn't have test about exynos4210 because I don't have the 4210 board.
However, there is no problem of exynos4212 which has 18 combiner.
On second thought, it might break by accessing undefined area.
Ok, I'll resolve it and resubmit patch.

Best regards,
Chanho Park

> 
> >
> >  #define EXYNOS4_IRQ_GPIO1_NR_GROUPS    16
> >  #define EXYNOS4_IRQ_GPIO2_NR_GROUPS    9
> > --
> > 1.7.9.5
> >