[PATCH v8 0/3] GPMC driver conversion

[PATCH v8 0/3] GPMC driver conversion

[Afzal Mohammed]

Hi,

Basic gpmc driver conversion series. Driver that is now created out of
gpmc code is a simple one, it handles tasks that were earlier executed
by gpmc_init. Now instead of relying on cpu_is_* checks, it obtains
resources and clk handle in the standard Linux way. The existing gpmc
interface works as was without this series.

HWMOD patch also has been brought into this series back with v7 series

As this creates only a basic driver, further gpmc driver work can be
based over this, while having a driver first in place.

This series is based on l-o/testing-cleanup as on 5-Sep-12,
i.e. over commit,

e3a5c14 ARM: OMAP1: Move SoC specific headers from plat to mach for omap1

per Tony's suggestion.

It is available
@git://gitorious.org/x0148406-public/linux-kernel.git gpmc-drv-v8

This series has been tested on omap3evm (rev G).


GPMC (General Purpose Memory Controller) in brief:
GPMC is an unified memory controller dedicated to interfacing external
memory devices like
 Asynchronous SRAM like memories and application specific integrated circuit devices.
 Asynchronous, synchronous, and page mode burst NOR flash devices NAND flash
 Pseudo-SRAM devices

GPMC details can be referred in AM335X Technical Reference Manual
@ http://www.ti.com/lit/pdf/spruh73

Regards
Afzal

v8:
    Use feature flag to decide whether wr_access and wr_data_mux_bus
    timings has to be configured (PATCH 3/3)

v7:
    Create a simple driver that gets resources & clk the standard Linux way
    Pull in HMWOD patch back into this series
v6: Capability flag added that stores features based on revision
    Macros used for finding revision
    Return value from memory setup function corrected
    Comments added to clarify handling of device type, size
    Bool type time setting patch removed as has been taken care in [2]
    Handle variable number of waitpin
    Warn if driver is unable to configure interrupt
    Enhance some of commit messages
    Handle shared writeprotect case
    Fix a bug in gpmc_create_device
    Get clk from hwmod
    Remove unwanted code
v5: Make this a purely driver conversion series, i.e. gpmc-mtd
    interactions has been made as a separate series, so is adding
    hwmod entry for OMAP2/3.
    And modifying gpmc peripheral platform initialization has been
    separated out of this series, so is migrating boards to use new
    driver interface. GPMC driver conversion which was done in a few
    patches in v4 has been tranformed to series of small patches.
    Also care has been taken care that old interface will not break
    with any of these patches, so both interfaces can coexist.
    This helps in converting boards one-by-one gradually. Acquiring
    CS has been thrown out. And conclusive comments on v4 has been
    addressed.
v4: Handle wait pin (except for interrupts), enhance configuration
    & timing interface of GPMC to take care of all boards. Dynamic
    allocation of interrupt instead of static. Convert remaining
    peripherals to work with GPMC driver. Handle acquiring NAND CS#,
    adapt to HWMOD, update HWMOD OMAP2/3 entries, other minor
    commenst on v3.
v3: Single device structure passed from platform for peripherals using
    multiple CS instead of using multiple device structure having a few
    redundant data, handle interrupts, GPMC NAND handling by GPMC NAND
    driver instead of GPMC driver
v2: Avoid code movement that kept similar code together (for easy review)


Afzal Mohammed (3):
  ARM: OMAP2/3: hwmod data: add gpmc
  ARM: OMAP2+: gpmc: Adapt to HWMOD
  ARM: OMAP2+: gpmc: minimal driver support

 arch/arm/mach-omap2/gpmc.c                         |  197 +++++++++++++++-----
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |   18 ++
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |   18 ++
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   44 +++++-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   54 ++++++
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |    1 +
 arch/arm/mach-omap2/prcm-common.h                  |    2 +
 7 files changed, 284 insertions(+), 50 deletions(-)

[PATCH v8 1/3] ARM: OMAP2/3: hwmod data: add gpmc

[Afzal Mohammed]

Add gpmc hwmod and associated interconnect data

Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |   18 +++++++
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |   18 +++++++
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   44 ++++++++++++++++-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   54 ++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |    1 +
 arch/arm/mach-omap2/prcm-common.h                  |    2 +
 6 files changed, 136 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index e7b90a0..b22c35b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -537,6 +537,15 @@ static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
 	{ }
 };
 
+static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
+	{
+		.pa_start	= 0x6800A000,
+		.pa_end		= 0x6800AFFF,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
 	.master		= &omap2xxx_l4_wkup_hwmod,
 	.slave		= &omap2xxx_counter_32k_hwmod,
@@ -545,6 +554,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
+	.master		= &omap2xxx_l3_main_hwmod,
+	.slave		= &omap2xxx_gpmc_hwmod,
+	.clk		= "core_l3_ck",
+	.addr		= omap2420_gpmc_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 	&omap2xxx_l3_main__l4_core,
 	&omap2xxx_mpu__l3_main,
@@ -588,6 +605,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 	&omap2420_l4_core__msdi1,
 	&omap2420_l4_core__hdq1w,
 	&omap2420_l4_wkup__counter_32k,
+	&omap2420_l3__gpmc,
 	NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 5fe65ae..8340516 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -888,6 +888,15 @@ static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
 	{ }
 };
 
+static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
+	{
+		.pa_start	= 0x6E000000,
+		.pa_end		= 0x6E000FFF,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
 	.master		= &omap2xxx_l4_wkup_hwmod,
 	.slave		= &omap2xxx_counter_32k_hwmod,
@@ -896,6 +905,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
+	.master		= &omap2xxx_l3_main_hwmod,
+	.slave		= &omap2xxx_gpmc_hwmod,
+	.clk		= "core_l3_ck",
+	.addr		= omap2430_gpmc_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
 	&omap2xxx_l3_main__l4_core,
 	&omap2xxx_mpu__l3_main,
@@ -946,6 +963,7 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
 	&omap2430_l4_core__mcbsp5,
 	&omap2430_l4_core__hdq1w,
 	&omap2430_l4_wkup__counter_32k,
+	&omap2430_l3__gpmc,
 	NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 055f735..dcdcbcc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -173,6 +173,26 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
 };
 
 /*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0014,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
+	.name	= "gpmc",
+	.sysc	= &omap2xxx_gpmc_sysc,
+};
+
+/*
  * IP blocks
  */
 
@@ -724,7 +744,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 	.dev_attr	= &omap_mcspi2_dev_attr,
 };
 
-
 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 	.name	= "counter",
 };
@@ -743,3 +762,26 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 	},
 	.class		= &omap2xxx_counter_hwmod_class,
 };
+
+/* gpmc */
+static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
+	{ .irq = 20 },
+	{ .irq = -1 }
+};
+
+struct omap_hwmod omap2xxx_gpmc_hwmod = {
+	.name		= "gpmc",
+	.class		= &omap2xxx_gpmc_hwmod_class,
+	.mpu_irqs	= omap2xxx_gpmc_irqs,
+	.main_clk	= "gpmc_fck",
+	.flags		= HWMOD_INIT_NO_IDLE |
+				HWMOD_INIT_NO_RESET |
+				HWMOD_NO_IDLEST,
+	.prcm		= {
+		.omap2	= {
+			.prcm_reg_id = 3,
+			.module_bit = OMAP24XX_EN_GPMC_MASK,
+			.module_offs = CORE_MOD,
+		},
+	},
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3e7d6c1..ce02b56 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2059,6 +2059,42 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
 };
 
 /*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0014,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
+	.name	= "gpmc",
+	.sysc	= &omap3xxx_gpmc_sysc,
+};
+
+static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
+	{ .irq = 20 },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod omap3xxx_gpmc_hwmod = {
+	.name		= "gpmc",
+	.class		= &omap3xxx_gpmc_hwmod_class,
+	.clkdm_name	= "l3_init_clkdm",
+	.mpu_irqs	= omap3xxx_gpmc_irqs,
+	.main_clk	= "gpmc_fck",
+	.flags		= HWMOD_INIT_NO_IDLE |
+				HWMOD_INIT_NO_RESET |
+				HWMOD_NO_IDLEST,
+};
+
+/*
  * interfaces
  */
 
@@ -3159,6 +3195,15 @@ static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
 	{ }
 };
 
+static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
+	{
+		.pa_start	= 0x6E000000,
+		.pa_end		= 0x6E000FFF,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
 	.master		= &omap3xxx_l4_wkup_hwmod,
 	.slave		= &omap3xxx_counter_32k_hwmod,
@@ -3268,6 +3313,14 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
 	.user		= OCP_USER_MPU,
 };
 
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
+	.master		= &omap3xxx_l3_main_hwmod,
+	.slave		= &omap3xxx_gpmc_hwmod,
+	.clk		= "core_l3_ick",
+	.addr		= omap3xxx_gpmc_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
 	&omap3xxx_l3_main__l4_core,
 	&omap3xxx_l3_main__l4_per,
@@ -3313,6 +3366,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
 	&omap34xx_l4_core__mcspi3,
 	&omap34xx_l4_core__mcspi4,
 	&omap3xxx_l4_wkup__counter_32k,
+	&omap3xxx_l3_main__gpmc,
 	NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index dddb677..6a033b8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -77,6 +77,7 @@ extern struct omap_hwmod omap2xxx_gpio4_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
 extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
+extern struct omap_hwmod omap2xxx_gpmc_hwmod;
 
 /* Common interface data across OMAP2xxx */
 extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index e5f0503..72df974 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -109,6 +109,8 @@
 #define OMAP2430_EN_MDM_INTC_MASK			(1 << 11)
 #define OMAP2430_EN_USBHS_SHIFT				6
 #define OMAP2430_EN_USBHS_MASK				(1 << 6)
+#define OMAP24XX_EN_GPMC_SHIFT				1
+#define OMAP24XX_EN_GPMC_MASK				(1 << 1)
 
 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
 #define OMAP2420_ST_MMC_SHIFT				26
-- 
1.7.1

[PATCH v8 2/3] ARM: OMAP2+: gpmc: Adapt to HWMOD

[Afzal Mohammed]

Create API for platforms to adapt GPMC to HWMOD

Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
 arch/arm/mach-omap2/gpmc.c |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index dbc1ebc..c45f185 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -29,11 +29,14 @@
 
 #include <plat/gpmc.h>
 #include <plat/sdrc.h>
+#include <plat/omap_device.h>
 
 #include "soc.h"
 
 #include "common.h"
 
+#define	DEVICE_NAME		"omap-gpmc"
+
 /* GPMC register offsets */
 #define GPMC_REVISION		0x00
 #define GPMC_SYSCONFIG		0x10
@@ -897,6 +900,29 @@ static int __init gpmc_init(void)
 }
 postcore_initcall(gpmc_init);
 
+static int __init omap_gpmc_init(void)
+{
+	struct omap_hwmod *oh;
+	struct platform_device *pdev;
+	char *oh_name = "gpmc";
+
+	oh = omap_hwmod_lookup(oh_name);
+	if (!oh) {
+		pr_err("Could not look up %s\n", oh_name);
+		return -ENODEV;
+	}
+
+	pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
+	if (IS_ERR(pdev)) {
+		WARN(1, "Can't build omap_device for %s:%s.\n",
+						DEVICE_NAME, oh->name);
+		return PTR_ERR(pdev);
+	}
+
+	return 0;
+}
+postcore_initcall(omap_gpmc_init);
+
 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 {
 	int i;
-- 
1.7.1

[PATCH v8 3/3] ARM: OMAP2+: gpmc: minimal driver support

[Afzal Mohammed]

Create a minimal driver out of gpmc code.
Responsibilities handled by earlier gpmc
initialization is now achieved in probe.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
 arch/arm/mach-omap2/gpmc.c |  171 +++++++++++++++++++++++++++++++-------------
 1 files changed, 122 insertions(+), 49 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index c45f185..4ae2bb8 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach-types.h>
 
@@ -85,6 +86,12 @@
 #define ENABLE_PREFETCH		(0x1 << 7)
 #define DMA_MPU_MODE		2
 
+#define	GPMC_REVISION_MAJOR(l)		((l >> 4) & 0xf)
+#define	GPMC_REVISION_MINOR(l)		(l & 0xf)
+
+#define	GPMC_HAS_WR_ACCESS		0x1
+#define	GPMC_HAS_WR_DATA_MUX_BUS	0x2
+
 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  */
 #define	GPMC_NR_IRQ		2
@@ -130,7 +137,10 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 static unsigned int gpmc_cs_map;	/* flag for cs which are initialized */
 static int gpmc_ecc_used = -EINVAL;	/* cs using ecc engine */
-
+static struct device *gpmc_dev;
+static int gpmc_irq;
+static resource_size_t phys_base, mem_size;
+static unsigned gpmc_capability;
 static void __iomem *gpmc_base;
 
 static struct clk *gpmc_l3_clk;
@@ -320,10 +330,10 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 
 	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 
-	if (cpu_is_omap34xx()) {
+	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
+	if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
-	}
 
 	/* caller is expected to have initialized CONFIG1 to cover
 	 * at least sync vs async
@@ -433,6 +443,19 @@ static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 	return r;
 }
 
+static int gpmc_cs_delete_mem(int cs)
+{
+	struct resource	*res = &gpmc_cs_mem[cs];
+	int r;
+
+	spin_lock(&gpmc_mem_lock);
+	r = release_resource(&gpmc_cs_mem[cs]);
+	res->start = res->end = 0;
+	spin_unlock(&gpmc_mem_lock);
+
+	return r;
+}
+
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
 	struct resource *res = &gpmc_cs_mem[cs];
@@ -769,7 +792,7 @@ static void gpmc_irq_noop(struct irq_data *data) { }
 
 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
 
-static int gpmc_setup_irq(int gpmc_irq)
+static int gpmc_setup_irq(void)
 {
 	int i;
 	u32 regval;
@@ -813,7 +836,37 @@ static int gpmc_setup_irq(int gpmc_irq)
 	return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
 }
 
-static void __init gpmc_mem_init(void)
+static __exit int gpmc_free_irq(void)
+{
+	int i;
+
+	if (gpmc_irq)
+		free_irq(gpmc_irq, NULL);
+
+	for (i = 0; i < GPMC_NR_IRQ; i++) {
+		irq_set_handler(gpmc_client_irq[i].irq, NULL);
+		irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
+		irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
+	}
+
+	irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
+
+	return 0;
+}
+
+static void __devexit gpmc_mem_exit(void)
+{
+	int cs;
+
+	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+		if (!gpmc_cs_mem_enabled(cs))
+			continue;
+		gpmc_cs_delete_mem(cs);
+	}
+
+}
+
+static void __devinit gpmc_mem_init(void)
 {
 	int cs;
 	unsigned long boot_rom_space = 0;
@@ -840,65 +893,85 @@ static void __init gpmc_mem_init(void)
 	}
 }
 
-static int __init gpmc_init(void)
+static __devinit int gpmc_probe(struct platform_device *pdev)
 {
 	u32 l;
-	int ret = -EINVAL;
-	int gpmc_irq;
-	char *ck = NULL;
-
-	if (cpu_is_omap24xx()) {
-		ck = "core_l3_ck";
-		if (cpu_is_omap2420())
-			l = OMAP2420_GPMC_BASE;
-		else
-			l = OMAP34XX_GPMC_BASE;
-		gpmc_irq = 20 + OMAP_INTC_START;
-	} else if (cpu_is_omap34xx()) {
-		ck = "gpmc_fck";
-		l = OMAP34XX_GPMC_BASE;
-		gpmc_irq = 20 + OMAP_INTC_START;
-	} else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
-		/* Base address and irq number are same for OMAP4/5 */
-		ck = "gpmc_ck";
-		l = OMAP44XX_GPMC_BASE;
-		gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START;
-	}
+	struct resource *res;
 
-	if (WARN_ON(!ck))
-		return ret;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL)
+		return -ENOENT;
 
-	gpmc_l3_clk = clk_get(NULL, ck);
-	if (IS_ERR(gpmc_l3_clk)) {
-		printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
-		BUG();
-	}
+	phys_base = res->start;
+	mem_size = resource_size(res);
 
-	gpmc_base = ioremap(l, SZ_4K);
+	gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
 	if (!gpmc_base) {
-		clk_put(gpmc_l3_clk);
-		printk(KERN_ERR "Could not get GPMC register memory\n");
-		BUG();
+		dev_err(&pdev->dev, "error: request memory / ioremap\n");
+		return -EADDRNOTAVAIL;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res == NULL)
+		dev_warn(&pdev->dev, "Failed to get resource: irq\n");
+	else
+		gpmc_irq = res->start;
+
+	gpmc_l3_clk = clk_get(&pdev->dev, "fck");
+	if (IS_ERR(gpmc_l3_clk)) {
+		dev_err(&pdev->dev, "error: clk_get\n");
+		gpmc_irq = 0;
+		return PTR_ERR(gpmc_l3_clk);
 	}
 
 	clk_enable(gpmc_l3_clk);
 
+	gpmc_dev = &pdev->dev;
+
 	l = gpmc_read_reg(GPMC_REVISION);
-	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
-	/* Set smart idle mode and automatic L3 clock gating */
-	l = gpmc_read_reg(GPMC_SYSCONFIG);
-	l &= 0x03 << 3;
-	l |= (0x02 << 3) | (1 << 0);
-	gpmc_write_reg(GPMC_SYSCONFIG, l);
+	if (GPMC_REVISION_MAJOR(l) > 0x4)
+		gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
+	dev_info(gpmc_dev, "GPMC revision %d.%d\n",
+				GPMC_REVISION_MAJOR(l), GPMC_REVISION_MINOR(l));
+
 	gpmc_mem_init();
 
-	ret = gpmc_setup_irq(gpmc_irq);
-	if (ret)
-		pr_err("gpmc: irq-%d could not claim: err %d\n",
-						gpmc_irq, ret);
-	return ret;
+	if (IS_ERR_VALUE(gpmc_setup_irq()))
+		dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
+
+	return 0;
+}
+
+static __exit int gpmc_remove(struct platform_device *pdev)
+{
+	gpmc_free_irq();
+	gpmc_mem_exit();
+	gpmc_dev = NULL;
+	return 0;
+}
+
+static struct platform_driver gpmc_driver = {
+	.probe		= gpmc_probe,
+	.remove		= __devexit_p(gpmc_remove),
+	.driver		= {
+		.name	= DEVICE_NAME,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static __init int gpmc_init(void)
+{
+	return platform_driver_register(&gpmc_driver);
+}
+
+static __exit void gpmc_exit(void)
+{
+	platform_driver_unregister(&gpmc_driver);
+
 }
+
 postcore_initcall(gpmc_init);
+module_exit(gpmc_exit);
 
 static int __init omap_gpmc_init(void)
 {
-- 
1.7.1

[PATCH v8 1/3] ARM: OMAP2/3: hwmod data: add gpmc

[Jon Hunter]

Hi Afzal,

On 09/05/2012 07:37 AM, Afzal Mohammed wrote:
> Add gpmc hwmod and associated interconnect data
> 
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod_2420_data.c         |   18 +++++++
>  arch/arm/mach-omap2/omap_hwmod_2430_data.c         |   18 +++++++
>  arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   44 ++++++++++++++++-
>  arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   54 ++++++++++++++++++++
>  arch/arm/mach-omap2/omap_hwmod_common_data.h       |    1 +
>  arch/arm/mach-omap2/prcm-common.h                  |    2 +
>  6 files changed, 136 insertions(+), 1 deletions(-)

[snip]

> diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
> index 3e7d6c1..ce02b56 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
> @@ -2059,6 +2059,42 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
>  };
>  
>  /*
> + * 'gpmc' class
> + * general purpose memory controller
> + */
> +
> +static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
> +	.rev_offs	= 0x0000,
> +	.sysc_offs	= 0x0010,
> +	.syss_offs	= 0x0014,
> +	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
> +			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
> +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> +	.sysc_fields	= &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
> +	.name	= "gpmc",
> +	.sysc	= &omap3xxx_gpmc_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
> +	{ .irq = 20 },
> +	{ .irq = -1 }
> +};
> +
> +static struct omap_hwmod omap3xxx_gpmc_hwmod = {
> +	.name		= "gpmc",
> +	.class		= &omap3xxx_gpmc_hwmod_class,
> +	.clkdm_name	= "l3_init_clkdm",

This all looks good, but I believe that the gpmc clock-domain should be
the core_l3_clkdm.

Cheers
Jon

[PATCH v8 1/3] ARM: OMAP2/3: hwmod data: add gpmc

[Jon Hunter]

Hi Afzal,

On 09/05/2012 07:37 AM, Afzal Mohammed wrote:
> Add gpmc hwmod and associated interconnect data
> 
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod_2420_data.c         |   18 +++++++
>  arch/arm/mach-omap2/omap_hwmod_2430_data.c         |   18 +++++++
>  arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   44 ++++++++++++++++-
>  arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   54 ++++++++++++++++++++
>  arch/arm/mach-omap2/omap_hwmod_common_data.h       |    1 +
>  arch/arm/mach-omap2/prcm-common.h                  |    2 +
>  6 files changed, 136 insertions(+), 1 deletions(-)

[snip]

> diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
> index 3e7d6c1..ce02b56 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
> @@ -2059,6 +2059,42 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
>  };
>  
>  /*
> + * 'gpmc' class
> + * general purpose memory controller
> + */
> +
> +static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
> +	.rev_offs	= 0x0000,
> +	.sysc_offs	= 0x0010,
> +	.syss_offs	= 0x0014,
> +	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
> +			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
> +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
> +	.sysc_fields	= &omap_hwmod_sysc_type1,
> +};
> +
> +static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
> +	.name	= "gpmc",
> +	.sysc	= &omap3xxx_gpmc_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
> +	{ .irq = 20 },
> +	{ .irq = -1 }
> +};
> +
> +static struct omap_hwmod omap3xxx_gpmc_hwmod = {
> +	.name		= "gpmc",
> +	.class		= &omap3xxx_gpmc_hwmod_class,
> +	.clkdm_name	= "l3_init_clkdm",

This all looks good, but I believe that the gpmc clock-domain should be
the core_l3_clkdm.

Cheers
Jon

[PATCH v8 2/3] ARM: OMAP2+: gpmc: Adapt to HWMOD

[Jon Hunter]

Hi Afzal,

On 09/05/2012 07:37 AM, Afzal Mohammed wrote:
> Create API for platforms to adapt GPMC to HWMOD
> 
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> ---
>  arch/arm/mach-omap2/gpmc.c |   26 ++++++++++++++++++++++++++
>  1 files changed, 26 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
> index dbc1ebc..c45f185 100644
> --- a/arch/arm/mach-omap2/gpmc.c
> +++ b/arch/arm/mach-omap2/gpmc.c
> @@ -29,11 +29,14 @@
>  
>  #include <plat/gpmc.h>
>  #include <plat/sdrc.h>
> +#include <plat/omap_device.h>
>  
>  #include "soc.h"
>  
>  #include "common.h"
>  
> +#define	DEVICE_NAME		"omap-gpmc"
> +
>  /* GPMC register offsets */
>  #define GPMC_REVISION		0x00
>  #define GPMC_SYSCONFIG		0x10
> @@ -897,6 +900,29 @@ static int __init gpmc_init(void)
>  }
>  postcore_initcall(gpmc_init);
>  
> +static int __init omap_gpmc_init(void)
> +{
> +	struct omap_hwmod *oh;
> +	struct platform_device *pdev;
> +	char *oh_name = "gpmc";
> +
> +	oh = omap_hwmod_lookup(oh_name);
> +	if (!oh) {
> +		pr_err("Could not look up %s\n", oh_name);
> +		return -ENODEV;
> +	}
> +
> +	pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
> +	if (IS_ERR(pdev)) {
> +		WARN(1, "Can't build omap_device for %s:%s.\n",
> +						DEVICE_NAME, oh->name);
> +		return PTR_ERR(pdev);
> +	}
> +
> +	return 0;

Nit-pick, I see some devices writing the above as ...

	WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);

 	return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;

> +}
> +postcore_initcall(omap_gpmc_init);
> +
>  static irqreturn_t gpmc_handle_irq(int irq, void *dev)
>  {
>  	int i;
> 

Otherwise ...

Reviewed-by: Jon Hunter <jon-hunter@ti.com>

Cheers
Jon

[PATCH v8 3/3] ARM: OMAP2+: gpmc: minimal driver support

[Jon Hunter]

Hi Afzal,

On 09/05/2012 07:37 AM, Afzal Mohammed wrote:
> Create a minimal driver out of gpmc code.
> Responsibilities handled by earlier gpmc
> initialization is now achieved in probe.
> 
> Signed-off-by: Afzal Mohammed <afzal@ti.com>

Reviewed-by: Jon Hunter <jon-hunter@ti.com>

Cheers
Jon

[PATCH v8 1/3] ARM: OMAP2/3: hwmod data: add gpmc

[Tony Lindgren]

* Afzal Mohammed <afzal@ti.com> [120905 05:38]:
> Add gpmc hwmod and associated interconnect data
>  
> +static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
> +	{
> +		.pa_start	= 0x6800A000,
> +		.pa_end		= 0x6800AFFF,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +	{ }
> +};

Nit, please lowercase all the hex numbers, that's the standard
in Linux.

Tony

[PATCH v8 0/3] GPMC driver conversion

[Tony Lindgren]

* Afzal Mohammed <afzal@ti.com> [120905 05:37]:
> Hi,
> 
> Basic gpmc driver conversion series. Driver that is now created out of
> gpmc code is a simple one, it handles tasks that were earlier executed
> by gpmc_init. Now instead of relying on cpu_is_* checks, it obtains
> resources and clk handle in the standard Linux way. The existing gpmc
> interface works as was without this series.
> 
> HWMOD patch also has been brought into this series back with v7 series
> 
> As this creates only a basic driver, further gpmc driver work can be
> based over this, while having a driver first in place.
> 
> This series is based on l-o/testing-cleanup as on 5-Sep-12,
> i.e. over commit,
> 
> e3a5c14 ARM: OMAP1: Move SoC specific headers from plat to mach for omap1
> 
> per Tony's suggestion.
> 
> It is available
> @git://gitorious.org/x0148406-public/linux-kernel.git gpmc-drv-v8

Great, this all looks good to me. I suggest that on top of this
we add minimal devicetree binding that does not even attempt to
deal with the timings yet.

Then once the minimal devicetree binding is in place, we can
call the current GPMC timing functions using the compatible flags
and auxdata in the gpmc.c driver.

That way we get all the legacy boards booting with GPMC support
for smsc911x etc, and can even remove some less used board-*.c
files.

Then we just add the generic GPMC timings when we're happy with
those.

Regards,

Tony

[PATCH v8 0/3] GPMC driver conversion

[Florian Vaussard]

Hello,

Le 08/09/2012 00:10, Tony Lindgren a ?crit :
> * Afzal Mohammed <afzal@ti.com> [120905 05:37]:
>> Hi,
>>
>> Basic gpmc driver conversion series. Driver that is now created out of
>> gpmc code is a simple one, it handles tasks that were earlier executed
>> by gpmc_init. Now instead of relying on cpu_is_* checks, it obtains
>> resources and clk handle in the standard Linux way. The existing gpmc
>> interface works as was without this series.
>>
>> HWMOD patch also has been brought into this series back with v7 series
>>
>> As this creates only a basic driver, further gpmc driver work can be
>> based over this, while having a driver first in place.
>>
>> This series is based on l-o/testing-cleanup as on 5-Sep-12,
>> i.e. over commit,
>>
>> e3a5c14 ARM: OMAP1: Move SoC specific headers from plat to mach for omap1
>>
>> per Tony's suggestion.
>>
>> It is available
>> @git://gitorious.org/x0148406-public/linux-kernel.git gpmc-drv-v8
> Great, this all looks good to me. I suggest that on top of this
> we add minimal devicetree binding that does not even attempt to
> deal with the timings yet.
>
> Then once the minimal devicetree binding is in place, we can
> call the current GPMC timing functions using the compatible flags
> and auxdata in the gpmc.c driver.
>
> That way we get all the legacy boards booting with GPMC support
> for smsc911x etc, and can even remove some less used board-*.c
> files.

This would be great. If you happen to have DT bindings for GPMC,
I would be happy to test them with my Overo board, as well as
with my CAN chips on a custom board.

Regards,
Florian

[PATCH v8 2/3] ARM: OMAP2+: gpmc: Adapt to HWMOD

[Mohammed, Afzal]

Hi Jon,

On Thu, Sep 06, 2012 at 01:25:23, Hunter, Jon wrote:

> Nit-pick, I see some devices writing the above as ...
> 
> 	WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
> 
>  	return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;

> Otherwise ...
> 
> Reviewed-by: Jon Hunter <jon-hunter@ti.com>

Thanks for your reviews, updated series has been posted

Regards
Afzal

[PATCH v8 0/3] GPMC driver conversion

[Mohammed, Afzal]

Hi Tony,

On Sat, Sep 08, 2012 at 03:40:34, Tony Lindgren wrote:

> Great, this all looks good to me. I suggest that on top of this
> we add minimal devicetree binding that does not even attempt to
> deal with the timings yet.
> 
> Then once the minimal devicetree binding is in place, we can
> call the current GPMC timing functions using the compatible flags
> and auxdata in the gpmc.c driver.
> 
> That way we get all the legacy boards booting with GPMC support
> for smsc911x etc, and can even remove some less used board-*.c
> files.

Thanks. I agree with your suggestion and would be proceeding so
as to achieve minimal devicetree support.

And a newer version of this series has been posted.

> Then we just add the generic GPMC timings when we're happy with
> those.

Meanwhile can you send me the gpmc debug logs for n800 where tusb
patch on generic timing was causing the hang along with logs
without the culprit tusb patch so that we could arrive at generic
gpmc timings.

Regards
Afzal

[PATCH v8 0/3] GPMC driver conversion

[Tony Lindgren]

* Mohammed, Afzal <afzal@ti.com> [120911 03:54]:
> Hi Tony,
> 
> On Sat, Sep 08, 2012 at 03:40:34, Tony Lindgren wrote:
> 
> > Great, this all looks good to me. I suggest that on top of this
> > we add minimal devicetree binding that does not even attempt to
> > deal with the timings yet.
> > 
> > Then once the minimal devicetree binding is in place, we can
> > call the current GPMC timing functions using the compatible flags
> > and auxdata in the gpmc.c driver.
> > 
> > That way we get all the legacy boards booting with GPMC support
> > for smsc911x etc, and can even remove some less used board-*.c
> > files.
> 
> Thanks. I agree with your suggestion and would be proceeding so
> as to achieve minimal devicetree support.
> 
> And a newer version of this series has been posted.

OK great!
 
> > Then we just add the generic GPMC timings when we're happy with
> > those.
> 
> Meanwhile can you send me the gpmc debug logs for n800 where tusb
> patch on generic timing was causing the hang along with logs
> without the culprit tusb patch so that we could arrive at generic
> gpmc timings.

Yes sorry been meaning to do that but keep getting distracted
continuously somehow..

Tony