* [PATCH 0/6] atmel SoC SPI controller with DT
@ 2012-09-26 6:50 Wenyou Yang
2012-09-26 6:50 ` [PATCH 1/6] of_spi: add generic binding support to specify cs gpio Wenyou Yang
` (6 more replies)
0 siblings, 7 replies; 15+ messages in thread
From: Wenyou Yang @ 2012-09-26 6:50 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
I merged the works from Nicolas, Richard, Jean-Christophe's patchset
for atmel SPI controller.
It's based on v3.6-rc7.
Best Regards,
Wenyou Yang
Wenyou Yang (6):
of_spi: add generic binding support to specify cs gpio
spi: atmel: add dmaengine and dt support
ARM: at91: add clocks for spi DT entries
ARM: dts: add spi nodes for atmel SoCs
ARM: dts: add spi nodes for atmel boards
spi: atmel: add dt property for DMA configuration for sam9x5 and
sam9n12
Documentation/devicetree/bindings/spi/spi-bus.txt | 6 +
.../devicetree/bindings/spi/spi_atmel.txt | 29 +
arch/arm/boot/dts/at91sam9260.dtsi | 34 +
arch/arm/boot/dts/at91sam9263.dtsi | 34 +
arch/arm/boot/dts/at91sam9263ek.dts | 10 +
arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 10 +
arch/arm/boot/dts/at91sam9g25ek.dts | 10 +
arch/arm/boot/dts/at91sam9g45.dtsi | 34 +
arch/arm/boot/dts/at91sam9m10g45ek.dts | 10 +
arch/arm/boot/dts/at91sam9n12.dtsi | 36 +
arch/arm/boot/dts/at91sam9n12ek.dts | 10 +
arch/arm/boot/dts/at91sam9x5.dtsi | 38 +
arch/arm/mach-at91/at91sam9260.c | 2 +
arch/arm/mach-at91/at91sam9g45.c | 2 +
arch/arm/mach-at91/at91sam9n12.c | 2 +
arch/arm/mach-at91/at91sam9x5.c | 3 +
drivers/spi/spi-atmel.c | 792 ++++++++++++++++++--
drivers/spi/spi.c | 55 +-
include/linux/spi/spi.h | 3 +
19 files changed, 1045 insertions(+), 75 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt
--
1.7.9.5
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/6] of_spi: add generic binding support to specify cs gpio
2012-09-26 6:50 [PATCH 0/6] atmel SoC SPI controller with DT Wenyou Yang
@ 2012-09-26 6:50 ` Wenyou Yang
2012-09-26 6:50 ` [PATCH 2/6] spi: atmel: add dmaengine and dt support Wenyou Yang
` (5 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Wenyou Yang @ 2012-09-26 6:50 UTC (permalink / raw)
To: linux-arm-kernel
This will allow to use gpio for chip select with no modification in the
driver binding
When use the cs-gpios, the gpio number will be passed via the cs_gpio field
and the number of chip select will automatically increased.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
Documentation/devicetree/bindings/spi/spi-bus.txt | 6 +++
drivers/spi/spi.c | 55 +++++++++++++++++++--
include/linux/spi/spi.h | 3 ++
3 files changed, 61 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
index e782add..c253379 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -12,6 +12,7 @@ The SPI master node requires the following properties:
- #size-cells - should be zero.
- compatible - name of SPI bus controller following generic names
recommended practice.
+- cs-gpios - (optional) gpios chip select.
No other properties are required in the SPI bus node. It is assumed
that a driver for an SPI bus device will understand that it is an SPI bus.
However, the binding does not attempt to define the specific method for
@@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
chip selects. Individual drivers can define additional properties to
support describing the chip select layout.
+If cs-gpios is used the number of chip select will automatically increased.
+
SPI slave nodes must be children of the SPI master node and can
contain the following properties.
- reg - (required) chip select address of device.
@@ -34,6 +37,9 @@ contain the following properties.
- spi-cs-high - (optional) Empty property indicating device requires
chip select active high
+If a gpio chipselect is used for the SPI slave the gpio number will be passed
+via the controller_data
+
SPI example for an MPC5200 SPI bus:
spi at f00 {
#address-cells = <1>;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 84c2861..74e6577 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -30,6 +30,7 @@
#include <linux/slab.h>
#include <linux/mod_devicetable.h>
#include <linux/spi/spi.h>
+#include <linux/of_gpio.h>
#include <linux/pm_runtime.h>
#include <linux/export.h>
#include <linux/sched.h>
@@ -327,6 +328,7 @@ struct spi_device *spi_alloc_device(struct spi_master *master)
spi->dev.parent = &master->dev;
spi->dev.bus = &spi_bus_type;
spi->dev.release = spidev_release;
+ spi->cs_gpio = -EINVAL;
device_initialize(&spi->dev);
return spi;
}
@@ -344,15 +346,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
int spi_add_device(struct spi_device *spi)
{
static DEFINE_MUTEX(spi_add_lock);
- struct device *dev = spi->master->dev.parent;
+ struct spi_master *master = spi->master;
+ struct device *dev = master->dev.parent;
struct device *d;
int status;
/* Chipselects are numbered 0..max; validate. */
- if (spi->chip_select >= spi->master->num_chipselect) {
+ if (spi->chip_select >= master->num_chipselect) {
dev_err(dev, "cs%d >= max %d\n",
spi->chip_select,
- spi->master->num_chipselect);
+ master->num_chipselect);
return -EINVAL;
}
@@ -376,6 +379,9 @@ int spi_add_device(struct spi_device *spi)
goto done;
}
+ if (master->cs_gpios)
+ spi->cs_gpio = master->cs_gpios[spi->chip_select];
+
/* Drivers may modify this initial i/o setup, but will
* normally rely on the device being setup. Devices
* using SPI_CS_HIGH can't coexist well otherwise...
@@ -946,6 +952,45 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
}
EXPORT_SYMBOL_GPL(spi_alloc_master);
+#ifdef CONFIG_OF
+static int of_spi_register_master(struct spi_master *master)
+{
+ int nb, i;
+ int *cs;
+ struct device_node *np = master->dev.of_node;
+
+ if (!np)
+ return 0;
+
+ nb = of_gpio_named_count(np, "cs-gpios");
+
+ if (nb < 1)
+ return 0;
+
+ cs = devm_kzalloc(&master->dev,
+ sizeof(int) * (master->num_chipselect + nb),
+ GFP_KERNEL);
+ master->cs_gpios = cs;
+
+ if (!master->cs_gpios)
+ return -ENOMEM;
+
+ memset(cs, -EINVAL, master->num_chipselect);
+ cs += master->num_chipselect;
+ master->num_chipselect += nb;
+
+ for (i = 0; i < nb; i++)
+ cs[i] = of_get_named_gpio(np, "cs-gpios", i);
+
+ return 0;
+}
+#else
+static int of_spi_register_master(struct spi_master *master)
+{
+ return 0;
+}
+#endif
+
/**
* spi_register_master - register SPI master controller
* @master: initialized master, originally from spi_alloc_master()
@@ -977,6 +1022,10 @@ int spi_register_master(struct spi_master *master)
if (!dev)
return -ENODEV;
+ status = of_spi_register_master(master);
+ if (status)
+ return status;
+
/* even if it's just one always-selected device, there must
* be@least one chipselect
*/
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index fa702ae..f629189 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -90,6 +90,7 @@ struct spi_device {
void *controller_state;
void *controller_data;
char modalias[SPI_NAME_SIZE];
+ int cs_gpio; /* chip select gpio */
/*
* likely need more hooks for more protocol options affecting how
@@ -362,6 +363,8 @@ struct spi_master {
int (*transfer_one_message)(struct spi_master *master,
struct spi_message *mesg);
int (*unprepare_transfer_hardware)(struct spi_master *master);
+ /* gpio chip select */
+ int *cs_gpios;
};
static inline void *spi_master_get_devdata(struct spi_master *master)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/6] spi: atmel: add dmaengine and dt support
2012-09-26 6:50 [PATCH 0/6] atmel SoC SPI controller with DT Wenyou Yang
2012-09-26 6:50 ` [PATCH 1/6] of_spi: add generic binding support to specify cs gpio Wenyou Yang
@ 2012-09-26 6:50 ` Wenyou Yang
2012-09-26 7:05 ` Uwe Kleine-König
2012-09-26 6:50 ` [PATCH 3/6] ARM: at91: add clocks for spi DT entries Wenyou Yang
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Wenyou Yang @ 2012-09-26 6:50 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
.../devicetree/bindings/spi/spi_atmel.txt | 29 +
drivers/spi/spi-atmel.c | 739 ++++++++++++++++++--
2 files changed, 696 insertions(+), 72 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt
diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
new file mode 100644
index 0000000..5a64825
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -0,0 +1,29 @@
+Atmel SPI device
+
+Required properties:
+- compatible : should be "atmel,at91rm9200-spi".
+- reg: Address and length of the register set for the device
+- interrupts: Should contain macb interrupt
+- cs-gpio: Should contain the GPIOs used for chipselect.
+- has_dma_support: The chip has dma engine support for spi: 1 - support, 0 - no support
+- has_pdc_support: The chip has pdc support for spi: 1 - support, 0 - no support
+- is_ver2: If is th spi IP version 2, 1 - yes, 0 - no
+- dma: handle to the dma controller that should be used
+
+spi0: spi at f0000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xf0000000 0x100>;
+ interrupts = <13 4>;
+ cs-gpios = <&pioA 14 0
+ &pioA 7 0 /* conflicts with TXD2 */
+ &pioA 1 0 /* conflicts with RXD0 */
+ &pioB 3 0 /* conflicts with ERXDV */
+ >;
+ has_dma_support = <1>;
+ has_pdc_support = <0>;
+ is_ver2 = <1>;
+ dma = <&dma0 0x10002212>;
+ status = "disabled";
+};
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 16d6a83..9930438 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -15,15 +15,19 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
#include <asm/io.h>
#include <mach/board.h>
#include <asm/gpio.h>
#include <mach/cpu.h>
+#include <mach/at_hdmac.h>
/* SPI register offsets */
#define SPI_CR 0x0000
@@ -179,6 +183,38 @@
#define spi_writel(port,reg,value) \
__raw_writel((value), (port)->regs + SPI_##reg)
+/*
+ * Version 2 of the SPI controller has
+ * - CR.LASTXFER
+ * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
+ * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
+ * - SPI_CSRx.CSAAT
+ * - SPI_CSRx.SBCR allows faster clocking
+ *
+ * We can determine the controller version by reading the VERSION
+ * register, but I haven't checked that it exists on all chips, and
+ * this is cheaper anyway.
+ */
+struct atmel_spi_data {
+ u8 has_dma_support;
+ u8 has_pdc_support;
+ u8 is_ver2; /* 1-yes, 0-not */
+ struct at_dma_slave dma_slave;
+};
+
+/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
+ * cache operations; better heuristics consider wordsize and bitrate.
+ */
+#define DMA_MIN_BYTES 16
+
+struct atmel_spi_dma {
+ struct dma_chan *chan_rx;
+ struct dma_chan *chan_tx;
+ struct scatterlist sgrx;
+ struct scatterlist sgtx;
+ struct dma_async_tx_descriptor *data_desc_rx;
+ struct dma_async_tx_descriptor *data_desc_tx;
+};
/*
* The core SPI transfer engine just talks to a register bank to set up
@@ -187,7 +223,9 @@
*/
struct atmel_spi {
spinlock_t lock;
+ unsigned long flags;
+ resource_size_t phybase;
void __iomem *regs;
int irq;
struct clk *clk;
@@ -196,13 +234,23 @@ struct atmel_spi {
u8 stopping;
struct list_head queue;
+ struct tasklet_struct tasklet;
struct spi_transfer *current_transfer;
unsigned long current_remaining_bytes;
struct spi_transfer *next_transfer;
unsigned long next_remaining_bytes;
+ int done_status;
+ struct atmel_spi_data data;
+ bool use_dma;
+ bool use_pdc;
+
+ /* scratch buffer */
void *buffer;
dma_addr_t buffer_dma;
+
+ /* dmaengine data */
+ struct atmel_spi_dma dma;
};
/* Controller-specific per-slave state */
@@ -214,22 +262,7 @@ struct atmel_spi_device {
#define BUFFER_SIZE PAGE_SIZE
#define INVALID_DMA_ADDRESS 0xffffffff
-/*
- * Version 2 of the SPI controller has
- * - CR.LASTXFER
- * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
- * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
- * - SPI_CSRx.CSAAT
- * - SPI_CSRx.SBCR allows faster clocking
- *
- * We can determine the controller version by reading the VERSION
- * register, but I haven't checked that it exists on all chips, and
- * this is cheaper anyway.
- */
-static bool atmel_spi_is_v2(void)
-{
- return !cpu_is_at91rm9200();
-}
+static struct dma_slave_config slave_config;
/*
* Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
@@ -250,7 +283,7 @@ static bool atmel_spi_is_v2(void)
* nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
* and (c) will trigger that first erratum in some cases.
*
- * TODO: Test if the atmel_spi_is_v2() branch below works on
+ * TODO: Test if the as->data.is_ver2 == 0 branch below works on
* AT91RM9200 if we use some other register than CSR0. However, don't
* do this unconditionally since AP7000 has an errata where the BITS
* field in CSR0 overrides all other CSRs.
@@ -262,7 +295,7 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
unsigned active = spi->mode & SPI_CS_HIGH;
u32 mr;
- if (atmel_spi_is_v2()) {
+ if (as->data.is_ver2 == 1) {
/*
* Always use CSR0. This ensures that the clock
* switches to the correct idle polarity before we
@@ -317,10 +350,29 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
asd->npcs_pin, active ? " (low)" : "",
mr);
- if (atmel_spi_is_v2() || spi->chip_select != 0)
+ if ((as->data.is_ver2 == 1) || spi->chip_select != 0)
gpio_set_value(asd->npcs_pin, !active);
}
+static void atmel_spi_lock(struct atmel_spi *as)
+{
+ spin_lock_irqsave(&as->lock, as->flags);
+}
+
+static void atmel_spi_unlock(struct atmel_spi *as)
+{
+ spin_unlock_irqrestore(&as->lock, as->flags);
+}
+
+static inline bool atmel_spi_use_dma(struct atmel_spi *as,
+ struct spi_transfer *xfer)
+{
+ if ((as->use_dma) && (xfer->len >= DMA_MIN_BYTES))
+ return true;
+ else
+ return false;
+}
+
static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
struct spi_transfer *xfer)
{
@@ -332,6 +384,255 @@ static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
return xfer->delay_usecs == 0 && !xfer->cs_change;
}
+/*
+ * Next transfer using PIO.
+ * lock is held, spi tasklet is blocked
+ */
+static void atmel_spi_next_xfer_pio(struct spi_master *master,
+ struct spi_transfer *xfer)
+{
+ struct atmel_spi *as = spi_master_get_devdata(master);
+
+ dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
+
+ as->current_remaining_bytes = xfer->len;
+
+ /* Make sure data is not remaining in RDR */
+ spi_readl(as, RDR);
+ while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
+ spi_readl(as, RDR);
+ cpu_relax();
+ }
+
+ if (xfer->tx_buf)
+ if (xfer->bits_per_word > 8)
+ spi_writel(as, TDR, *(u16 *)(xfer->tx_buf));
+ else
+ spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
+ else
+ spi_writel(as, TDR, 0);
+
+ dev_dbg(master->dev.parent,
+ " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
+ xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
+ xfer->bits_per_word);
+
+ /* Enable relevant interrupts */
+ spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
+}
+
+static bool filter(struct dma_chan *chan, void *slave)
+{
+ struct at_dma_slave *sl = slave;
+
+ if (sl->dma_dev == chan->device->dev) {
+ chan->private = sl;
+ return true;
+ } else {
+ return false;
+ }
+}
+
+static int atmel_spi_set_dma_xfer_width(struct atmel_spi *as, u8 bits_per_word)
+{
+ int err = 0;
+
+ if (bits_per_word > 8) {
+ slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ } else {
+ slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+ slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+ }
+
+ slave_config.direction = DMA_TO_DEVICE;
+ if (dmaengine_slave_config(as->dma.chan_tx, &slave_config)) {
+ dev_err(&as->pdev->dev,
+ "failed to configure tx dma channel\n");
+ err = -EINVAL;
+ }
+
+ slave_config.direction = DMA_FROM_DEVICE;
+ if (dmaengine_slave_config(as->dma.chan_rx, &slave_config)) {
+ dev_err(&as->pdev->dev,
+ "failed to configure rx dma channel\n");
+ err = -EINVAL;
+ }
+ return err;
+}
+
+static int __devinit atmel_spi_configure_dma(struct atmel_spi *as)
+{
+ struct at_dma_slave *sdata = (struct at_dma_slave *)&as->data.dma_slave;
+ int err;
+
+ slave_config.dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
+ slave_config.src_addr = (dma_addr_t)as->phybase + SPI_RDR;
+ slave_config.src_maxburst = 1;
+ slave_config.dst_maxburst = 1;
+ slave_config.device_fc = false;
+
+ if (sdata && sdata->dma_dev) {
+ dma_cap_mask_t mask;
+
+ /* Try to grab two DMA channels */
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+ as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
+ if (as->dma.chan_tx)
+ as->dma.chan_rx = dma_request_channel(mask,
+ filter, sdata);
+ }
+
+ if (!as->dma.chan_rx || !as->dma.chan_tx) {
+ dev_err(&as->pdev->dev, "DMA channel not available, " \
+ "unable to use SPI\n");
+ err = -EBUSY;
+ goto error;
+ }
+
+ err = atmel_spi_set_dma_xfer_width(as, 8);
+ if (err)
+ goto error;
+
+ dev_info(&as->pdev->dev, "Using %s (tx) and " \
+ " %s (rx) for DMA transfers\n",
+ dma_chan_name(as->dma.chan_tx),
+ dma_chan_name(as->dma.chan_rx));
+
+ return 0;
+error:
+ if (as->dma.chan_rx)
+ dma_release_channel(as->dma.chan_rx);
+ if (as->dma.chan_tx)
+ dma_release_channel(as->dma.chan_tx);
+ return err;
+}
+
+static void atmel_spi_stop_dma(struct atmel_spi *as)
+{
+ if (as->dma.chan_rx)
+ as->dma.chan_rx->device->device_control(as->dma.chan_rx,
+ DMA_TERMINATE_ALL, 0);
+ if (as->dma.chan_tx)
+ as->dma.chan_tx->device->device_control(as->dma.chan_tx,
+ DMA_TERMINATE_ALL, 0);
+}
+
+static void atmel_spi_release_dma(struct atmel_spi *as)
+{
+ if (as->dma.chan_rx)
+ dma_release_channel(as->dma.chan_rx);
+ if (as->dma.chan_tx)
+ dma_release_channel(as->dma.chan_tx);
+}
+
+/* This function is called by the DMA driver from tasklet context */
+static void dma_callback(void *data)
+{
+ struct spi_master *master = data;
+ struct atmel_spi *as = spi_master_get_devdata(master);
+
+ /* trigger SPI tasklet */
+ tasklet_schedule(&as->tasklet);
+}
+
+/*
+ * Submit next transfer for DMA.
+ * lock is held, spi tasklet is blocked
+ */
+static int atmel_spi_next_xfer_dma(struct spi_master *master,
+ struct spi_transfer *xfer)
+{
+ struct atmel_spi *as = spi_master_get_devdata(master);
+ struct dma_chan *rxchan = as->dma.chan_rx;
+ struct dma_chan *txchan = as->dma.chan_tx;
+ struct dma_async_tx_descriptor *rxdesc;
+ struct dma_async_tx_descriptor *txdesc;
+ dma_cookie_t cookie;
+
+ dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma\n");
+
+ /* Check that the channels are available */
+ if (!rxchan || !txchan)
+ return -ENODEV;
+
+ /* release lock for DMA operations */
+ atmel_spi_unlock(as);
+
+ /* prepare the RX dma transfer */
+ sg_init_table(&as->dma.sgrx, 1);
+ sg_dma_len(&as->dma.sgrx) = xfer->len;
+ if (xfer->rx_buf)
+ as->dma.sgrx.dma_address = xfer->rx_dma;
+ else
+ as->dma.sgrx.dma_address = as->buffer_dma;
+
+ /* prepare the TX dma transfer */
+ sg_init_table(&as->dma.sgtx, 1);
+ sg_dma_len(&as->dma.sgtx) = xfer->len;
+ if (xfer->tx_buf) {
+ as->dma.sgtx.dma_address = xfer->tx_dma;
+ } else {
+ as->dma.sgtx.dma_address = as->buffer_dma;
+ memset(as->buffer, 0, xfer->len);
+ }
+
+ if (atmel_spi_set_dma_xfer_width(as, xfer->bits_per_word))
+ goto err_dma;
+
+ /* Send both scatterlists */
+ rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
+ &as->dma.sgrx,
+ 1,
+ DMA_FROM_DEVICE,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
+ NULL);
+ if (!rxdesc)
+ goto err_dma;
+
+ txdesc = txchan->device->device_prep_slave_sg(txchan,
+ &as->dma.sgtx,
+ 1,
+ DMA_TO_DEVICE,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
+ NULL);
+ if (!txdesc)
+ goto err_dma;
+
+ dev_dbg(master->dev.parent,
+ " start dma xfer %p: len %u tx %p/%08x rx %p/%08x\n",
+ xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
+ xfer->rx_buf, xfer->rx_dma);
+
+ /* Enable relevant interrupts */
+ spi_writel(as, IER, SPI_BIT(OVRES));
+
+ /* Put the callback on the RX transfer only, that should finish last */
+ rxdesc->callback = dma_callback;
+ rxdesc->callback_param = master;
+
+ /* Submit and fire RX and TX with TX last so we're ready to read! */
+ cookie = rxdesc->tx_submit(rxdesc);
+ if (dma_submit_error(cookie))
+ goto err_dma;
+ cookie = txdesc->tx_submit(txdesc);
+ if (dma_submit_error(cookie))
+ goto err_dma;
+ rxchan->device->device_issue_pending(rxchan);
+ txchan->device->device_issue_pending(txchan);
+
+ /* take back lock */
+ atmel_spi_lock(as);
+ return 0;
+
+err_dma:
+ spi_writel(as, IDR, SPI_BIT(OVRES));
+ atmel_spi_stop_dma(as);
+ atmel_spi_lock(as);
+ return -ENOMEM;
+}
+
static void atmel_spi_next_xfer_data(struct spi_master *master,
struct spi_transfer *xfer,
dma_addr_t *tx_dma,
@@ -364,10 +665,10 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
}
/*
- * Submit next transfer for DMA.
+ * Submit next transfer for PDC.
* lock is held, spi irq is blocked
*/
-static void atmel_spi_next_xfer(struct spi_master *master,
+static void atmel_spi_next_xfer_pdc(struct spi_master *master,
struct spi_message *msg)
{
struct atmel_spi *as = spi_master_get_devdata(master);
@@ -464,6 +765,44 @@ static void atmel_spi_next_xfer(struct spi_master *master,
spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
}
+/*
+ * Choose way to submit next transfer and start it.
+ * lock is held, spi tasklet is blocked
+ */
+static void atmel_spi_next_xfer(struct spi_master *master,
+ struct spi_message *msg)
+{
+ struct atmel_spi *as = spi_master_get_devdata(master);
+ struct spi_transfer *xfer;
+
+ dev_vdbg(&msg->spi->dev, "atmel_spi_next_xfer\n");
+
+ if (as->use_pdc)
+ atmel_spi_next_xfer_pdc(master, msg);
+ else {
+ if (!as->current_transfer)
+ xfer = list_entry(msg->transfers.next,
+ struct spi_transfer, transfer_list);
+ else
+ xfer = list_entry(
+ as->current_transfer->transfer_list.next,
+ struct spi_transfer, transfer_list);
+
+ as->current_transfer = xfer;
+
+ /* quick (and *really* not optimal) workaround for DMA BUG */
+ if (atmel_spi_use_dma(as, xfer) && (xfer->len < BUFFER_SIZE)) {
+ if (!atmel_spi_next_xfer_dma(master, xfer))
+ return;
+ else
+ dev_err(&msg->spi->dev, "unable to use DMA, fallback to PIO\n");
+ }
+
+ /* use PIO if xfer is short or error appened using DMA */
+ atmel_spi_next_xfer_pio(master, xfer);
+ }
+}
+
static void atmel_spi_next_message(struct spi_master *master)
{
struct atmel_spi *as = spi_master_get_devdata(master);
@@ -541,43 +880,218 @@ static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
xfer->len, DMA_FROM_DEVICE);
}
+static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
+{
+ spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
+}
+
static void
atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
- struct spi_message *msg, int status, int stay)
+ struct spi_message *msg, int stay)
{
- if (!stay || status < 0)
+ if (!stay || as->done_status < 0)
cs_deactivate(as, msg->spi);
else
as->stay = msg->spi;
list_del(&msg->queue);
- msg->status = status;
+ msg->status = as->done_status;
dev_dbg(master->dev.parent,
"xfer complete: %u bytes transferred\n",
msg->actual_length);
- spin_unlock(&as->lock);
+ atmel_spi_unlock(as);
msg->complete(msg->context);
- spin_lock(&as->lock);
+ atmel_spi_lock(as);
as->current_transfer = NULL;
as->next_transfer = NULL;
+ as->done_status = 0;
/* continue if needed */
- if (list_empty(&as->queue) || as->stopping)
- spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
- else
+ if (list_empty(&as->queue) || as->stopping) {
+ if (as->use_pdc)
+ atmel_spi_disable_pdc_transfer(as);
+ } else
atmel_spi_next_message(master);
}
-static irqreturn_t
-atmel_spi_interrupt(int irq, void *dev_id)
+/* Called from IRQ
+ * lock is held
+ *
+ * Must update "current_remaining_bytes" to keep track of data
+ * to transfer.
+ */
+static void
+atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
{
- struct spi_master *master = dev_id;
+ u8 *txp;
+ u8 *rxp;
+ u16 *txp16;
+ u16 *rxp16;
+ unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
+
+ if (xfer->rx_buf) {
+ if (xfer->bits_per_word > 8) {
+ rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
+ *rxp16 = spi_readl(as, RDR);
+ } else {
+ rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
+ *rxp = spi_readl(as, RDR);
+ }
+ } else {
+ spi_readl(as, RDR);
+ }
+ if (xfer->bits_per_word > 8) {
+ as->current_remaining_bytes -= 2;
+ if (as->current_remaining_bytes < 0)
+ as->current_remaining_bytes = 0;
+ } else {
+ as->current_remaining_bytes--;
+ }
+
+ if (as->current_remaining_bytes) {
+ if (xfer->tx_buf) {
+ if (xfer->bits_per_word > 8) {
+ txp16 = (u16 *)(((u8 *)xfer->tx_buf)
+ + xfer_pos + 2);
+ spi_writel(as, TDR, *txp16);
+ } else {
+ txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
+ spi_writel(as, TDR, *txp);
+ }
+ } else {
+ spi_writel(as, TDR, 0);
+ }
+ }
+}
+
+/* Tasklet
+ * Called from DMA callback + pio transfer and overrun IRQ.
+ */
+static void atmel_spi_tasklet_func(unsigned long data)
+{
+ struct spi_master *master = (struct spi_master *)data;
struct atmel_spi *as = spi_master_get_devdata(master);
struct spi_message *msg;
struct spi_transfer *xfer;
+
+ dev_vdbg(master->dev.parent, "atmel_spi_tasklet_func\n");
+
+ atmel_spi_lock(as);
+
+ xfer = as->current_transfer;
+
+ if (xfer == NULL)
+ /* already been there */
+ goto tasklet_out;
+
+ msg = list_entry(as->queue.next, struct spi_message, queue);
+
+ if (as->done_status < 0) {
+ /* error happened (overrun) */
+ if (atmel_spi_use_dma(as, xfer))
+ atmel_spi_stop_dma(as);
+ } else {
+ /* only update length if no error */
+ msg->actual_length += xfer->len;
+ }
+
+ if (atmel_spi_use_dma(as, xfer)) {
+ if (!msg->is_dma_mapped)
+ atmel_spi_dma_unmap_xfer(master, xfer);
+ }
+
+ if (xfer->delay_usecs)
+ udelay(xfer->delay_usecs);
+
+ if (atmel_spi_xfer_is_last(msg, xfer) || as->done_status < 0) {
+ /* report completed (or erroneous) message */
+ atmel_spi_msg_done(master, as, msg, xfer->cs_change);
+ } else {
+ if (xfer->cs_change) {
+ cs_deactivate(as, msg->spi);
+ udelay(1);
+ cs_activate(as, msg->spi);
+ }
+
+ /*
+ * Not done yet. Submit the next transfer.
+ *
+ * FIXME handle protocol options for xfer
+ */
+ atmel_spi_next_xfer(master, msg);
+ }
+
+tasklet_out:
+ atmel_spi_unlock(as);
+}
+
+static int atmel_spi_interrupt_dma(struct atmel_spi *as,
+ struct spi_master *master)
+{
+ u32 status, pending, imr;
+ struct spi_transfer *xfer;
+ int ret = IRQ_NONE;
+
+ imr = spi_readl(as, IMR);
+ status = spi_readl(as, SR);
+ pending = status & imr;
+
+ if (pending & SPI_BIT(OVRES)) {
+ ret = IRQ_HANDLED;
+ spi_writel(as, IDR, SPI_BIT(OVRES));
+ dev_warn(master->dev.parent, "overrun\n");
+
+ /*
+ * When we get an overrun, we disregard the current
+ * transfer. Data will not be copied back from any
+ * bounce buffer and msg->actual_len will not be
+ * updated with the last xfer.
+ *
+ * We will also not process any remaning transfers in
+ * the message.
+ *
+ * All actions are done in tasklet with done_status indication
+ */
+ as->done_status = -EIO;
+ smp_wmb();
+
+ /* Clear any overrun happening while cleaning up */
+ spi_readl(as, SR);
+
+ tasklet_schedule(&as->tasklet);
+
+ } else if (pending & SPI_BIT(RDRF)) {
+ atmel_spi_lock(as);
+
+ if (as->current_remaining_bytes) {
+ ret = IRQ_HANDLED;
+ xfer = as->current_transfer;
+ atmel_spi_pump_pio_data(as, xfer);
+ if (!as->current_remaining_bytes) {
+ /* no more data to xfer, kick tasklet */
+ spi_writel(as, IDR, pending);
+ tasklet_schedule(&as->tasklet);
+ }
+ }
+
+ atmel_spi_unlock(as);
+ } else {
+ WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
+ ret = IRQ_HANDLED;
+ spi_writel(as, IDR, pending);
+ }
+
+ return ret;
+}
+
+static int atmel_spi_interrupt_pdc(struct atmel_spi *as,
+ struct spi_master *master)
+{
+ struct spi_message *msg;
+ struct spi_transfer *xfer;
u32 status, pending, imr;
int ret = IRQ_NONE;
@@ -610,8 +1124,6 @@ atmel_spi_interrupt(int irq, void *dev_id)
* First, stop the transfer and unmap the DMA buffers.
*/
spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
- if (!msg->is_dma_mapped)
- atmel_spi_dma_unmap_xfer(master, xfer);
/* REVISIT: udelay in irq is unfriendly */
if (xfer->delay_usecs)
@@ -640,7 +1152,8 @@ atmel_spi_interrupt(int irq, void *dev_id)
/* Clear any overrun happening while cleaning up */
spi_readl(as, SR);
- atmel_spi_msg_done(master, as, msg, -EIO, 0);
+ as->done_status = -EIO;
+ atmel_spi_msg_done(master, as, msg, 0);
} else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
ret = IRQ_HANDLED;
@@ -649,16 +1162,13 @@ atmel_spi_interrupt(int irq, void *dev_id)
if (as->current_remaining_bytes == 0) {
msg->actual_length += xfer->len;
- if (!msg->is_dma_mapped)
- atmel_spi_dma_unmap_xfer(master, xfer);
-
/* REVISIT: udelay in irq is unfriendly */
if (xfer->delay_usecs)
udelay(xfer->delay_usecs);
if (atmel_spi_xfer_is_last(msg, xfer)) {
/* report completed message */
- atmel_spi_msg_done(master, as, msg, 0,
+ atmel_spi_msg_done(master, as, msg,
xfer->cs_change);
} else {
if (xfer->cs_change) {
@@ -688,6 +1198,27 @@ atmel_spi_interrupt(int irq, void *dev_id)
return ret;
}
+/* Interrupt
+ *
+ * No need for locking in this Interrupt handler: done_status is the
+ * only information modified. What we need is the update of this field
+ * before tasklet runs. This is ensured by using barrier.
+ */
+static irqreturn_t
+atmel_spi_interrupt(int irq, void *dev_id)
+{
+ struct spi_master *master = dev_id;
+ struct atmel_spi *as = spi_master_get_devdata(master);
+ int ret;
+
+ if (as->use_pdc)
+ ret = atmel_spi_interrupt_pdc(as, master);
+ else
+ ret = atmel_spi_interrupt_dma(as, master);
+
+ return ret;
+}
+
static int atmel_spi_setup(struct spi_device *spi)
{
struct atmel_spi *as;
@@ -695,7 +1226,7 @@ static int atmel_spi_setup(struct spi_device *spi)
u32 scbr, csr;
unsigned int bits = spi->bits_per_word;
unsigned long bus_hz;
- unsigned int npcs_pin;
+ int npcs_pin;
int ret;
as = spi_master_get_devdata(spi->master);
@@ -718,16 +1249,16 @@ static int atmel_spi_setup(struct spi_device *spi)
}
/* see notes above re chipselect */
- if (!atmel_spi_is_v2()
- && spi->chip_select == 0
- && (spi->mode & SPI_CS_HIGH)) {
+ if ((as->data.is_ver2 == 0)
+ && spi->chip_select == 0
+ && (spi->mode & SPI_CS_HIGH)) {
dev_dbg(&spi->dev, "setup: can't be active-high\n");
return -EINVAL;
}
/* v1 chips start out at half the peripheral bus speed. */
bus_hz = clk_get_rate(as->clk);
- if (!atmel_spi_is_v2())
+ if (as->data.is_ver2 == 0)
bus_hz /= 2;
if (spi->max_speed_hz) {
@@ -767,7 +1298,9 @@ static int atmel_spi_setup(struct spi_device *spi)
csr |= SPI_BF(DLYBCT, 0);
/* chipselect must have been muxed as GPIO (e.g. in board setup) */
- npcs_pin = (unsigned int)spi->controller_data;
+ if (!gpio_is_valid(spi->cs_gpio))
+ spi->cs_gpio = (int)spi->controller_data;
+ npcs_pin = spi->cs_gpio;
asd = spi->controller_state;
if (!asd) {
asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
@@ -784,13 +1317,11 @@ static int atmel_spi_setup(struct spi_device *spi)
spi->controller_state = asd;
gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
} else {
- unsigned long flags;
-
- spin_lock_irqsave(&as->lock, flags);
+ atmel_spi_lock(as);
if (as->stay == spi)
as->stay = NULL;
cs_deactivate(as, spi);
- spin_unlock_irqrestore(&as->lock, flags);
+ atmel_spi_unlock(as);
}
asd->csr = csr;
@@ -799,7 +1330,7 @@ static int atmel_spi_setup(struct spi_device *spi)
"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
- if (!atmel_spi_is_v2())
+ if (as->data.is_ver2 == 0)
spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
return 0;
@@ -809,7 +1340,6 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
{
struct atmel_spi *as;
struct spi_transfer *xfer;
- unsigned long flags;
struct device *controller = spi->master->dev.parent;
u8 bits;
struct atmel_spi_device *asd;
@@ -840,6 +1370,12 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
return -ENOPROTOOPT;
}
}
+ if (xfer->bits_per_word > 8) {
+ if (xfer->len % 2) {
+ dev_dbg(&spi->dev, "buffer len should be 16 bits aligned\n");
+ return -EINVAL;
+ }
+ }
/* FIXME implement these protocol options!! */
if (xfer->speed_hz) {
@@ -849,13 +1385,9 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
/*
* DMA map early, for performance (empties dcache ASAP) and
- * better fault reporting. This is a DMA-only driver.
- *
- * NOTE that if dma_unmap_single() ever starts to do work on
- * platforms supported by this driver, we would need to clean
- * up mappings for previously-mapped transfers.
+ * better fault reporting.
*/
- if (!msg->is_dma_mapped) {
+ if (!msg->is_dma_mapped && atmel_spi_use_dma(as, xfer)) {
if (atmel_spi_dma_map_xfer(as, xfer) < 0)
return -ENOMEM;
}
@@ -874,11 +1406,11 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
msg->status = -EINPROGRESS;
msg->actual_length = 0;
- spin_lock_irqsave(&as->lock, flags);
+ atmel_spi_lock(as);
list_add_tail(&msg->queue, &as->queue);
if (!as->current_transfer)
atmel_spi_next_message(spi->master);
- spin_unlock_irqrestore(&as->lock, flags);
+ atmel_spi_unlock(as);
return 0;
}
@@ -887,25 +1419,55 @@ static void atmel_spi_cleanup(struct spi_device *spi)
{
struct atmel_spi *as = spi_master_get_devdata(spi->master);
struct atmel_spi_device *asd = spi->controller_state;
- unsigned gpio = (unsigned) spi->controller_data;
- unsigned long flags;
+ unsigned gpio = spi->cs_gpio;
if (!asd)
return;
- spin_lock_irqsave(&as->lock, flags);
+ atmel_spi_lock(as);
if (as->stay == spi) {
as->stay = NULL;
cs_deactivate(as, spi);
}
- spin_unlock_irqrestore(&as->lock, flags);
+ atmel_spi_unlock(as);
spi->controller_state = NULL;
gpio_free(gpio);
kfree(asd);
}
-/*-------------------------------------------------------------------------*/
+static int of_get_atmel_spi_data(struct device_node *np, struct atmel_spi *as)
+{
+ const __be32 *val;
+
+ val = of_get_property(np, "has_dma_support", NULL);
+ if (!val) {
+ pr_err("%s: have no 'has_dma_support' property\n",
+ np->full_name);
+ return -EINVAL;
+ }
+
+ as->data.has_dma_support = be32_to_cpup(val);
+
+ val = of_get_property(np, "has_pdc_support", NULL);
+ if (!val) {
+ pr_err("%s: have no 'has_pdc_support' property\n",
+ np->full_name);
+ return -EINVAL;
+ }
+
+ as->data.has_pdc_support = be32_to_cpup(val);
+
+ val = of_get_property(np, "is_ver2", NULL);
+ if (!val) {
+ pr_err("%s: have no 'is_ver2' property\n", np->full_name);
+ return -EINVAL;
+ }
+
+ as->data.is_ver2 = be32_to_cpup(val);
+
+ return 0;
+}
static int __devinit atmel_spi_probe(struct platform_device *pdev)
{
@@ -938,7 +1500,8 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
master->bus_num = pdev->id;
- master->num_chipselect = 4;
+ master->dev.of_node = pdev->dev.of_node;
+ master->num_chipselect = master->dev.of_node ? 0 : 4;
master->setup = atmel_spi_setup;
master->transfer = atmel_spi_transfer;
master->cleanup = atmel_spi_cleanup;
@@ -957,10 +1520,13 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
spin_lock_init(&as->lock);
INIT_LIST_HEAD(&as->queue);
+ tasklet_init(&as->tasklet, atmel_spi_tasklet_func,
+ (unsigned long)master);
as->pdev = pdev;
as->regs = ioremap(regs->start, resource_size(regs));
if (!as->regs)
goto out_free_buffer;
+ as->phybase = regs->start;
as->irq = irq;
as->clk = clk;
@@ -969,12 +1535,22 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
if (ret)
goto out_unmap_regs;
+ ret = of_get_atmel_spi_data(pdev->dev.of_node, as);
+ if (ret)
+ goto out_unmap_regs;
+
+ if (as->data.has_dma_support) {
+ if (atmel_spi_configure_dma(as) == 0)
+ as->use_dma = true;
+ } else if (as->data.has_pdc_support)
+ as->use_pdc = true;
+
/* Initialize the hardware */
clk_enable(clk);
spi_writel(as, CR, SPI_BIT(SWRST));
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
- spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
+
spi_writel(as, CR, SPI_BIT(SPIEN));
/* go! */
@@ -983,11 +1559,14 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
ret = spi_register_master(master);
if (ret)
- goto out_reset_hw;
+ goto out_free_dma;
return 0;
-out_reset_hw:
+out_free_dma:
+ if (as->use_dma)
+ atmel_spi_release_dma(as);
+
spi_writel(as, CR, SPI_BIT(SWRST));
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
clk_disable(clk);
@@ -995,6 +1574,7 @@ out_reset_hw:
out_unmap_regs:
iounmap(as->regs);
out_free_buffer:
+ tasklet_kill(&as->tasklet);
dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
as->buffer_dma);
out_free:
@@ -1008,10 +1588,16 @@ static int __devexit atmel_spi_remove(struct platform_device *pdev)
struct spi_master *master = platform_get_drvdata(pdev);
struct atmel_spi *as = spi_master_get_devdata(master);
struct spi_message *msg;
+ struct spi_transfer *xfer;
/* reset the hardware and block queue progress */
spin_lock_irq(&as->lock);
as->stopping = 1;
+ if (as->use_dma) {
+ atmel_spi_stop_dma(as);
+ atmel_spi_release_dma(as);
+ }
+
spi_writel(as, CR, SPI_BIT(SWRST));
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
spi_readl(as, SR);
@@ -1019,13 +1605,15 @@ static int __devexit atmel_spi_remove(struct platform_device *pdev)
/* Terminate remaining queued transfers */
list_for_each_entry(msg, &as->queue, queue) {
- /* REVISIT unmapping the dma is a NOP on ARM and AVR32
- * but we shouldn't depend on that...
- */
+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
+ if (!msg->is_dma_mapped && atmel_spi_use_dma(as, xfer))
+ atmel_spi_dma_unmap_xfer(master, xfer);
+ }
msg->status = -ESHUTDOWN;
msg->complete(msg->context);
}
+ tasklet_kill(&as->tasklet);
dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
as->buffer_dma);
@@ -1040,7 +1628,6 @@ static int __devexit atmel_spi_remove(struct platform_device *pdev)
}
#ifdef CONFIG_PM
-
static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
{
struct spi_master *master = platform_get_drvdata(pdev);
@@ -1064,11 +1651,19 @@ static int atmel_spi_resume(struct platform_device *pdev)
#define atmel_spi_resume NULL
#endif
+#if defined(CONFIG_OF)
+static const struct of_device_id atmel_spi_dt_ids[] = {
+ { .compatible = "atmel,at91rm9200-spi" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
+#endif
static struct platform_driver atmel_spi_driver = {
.driver = {
.name = "atmel_spi",
.owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(atmel_spi_dt_ids),
},
.suspend = atmel_spi_suspend,
.resume = atmel_spi_resume,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/6] ARM: at91: add clocks for spi DT entries
2012-09-26 6:50 [PATCH 0/6] atmel SoC SPI controller with DT Wenyou Yang
2012-09-26 6:50 ` [PATCH 1/6] of_spi: add generic binding support to specify cs gpio Wenyou Yang
2012-09-26 6:50 ` [PATCH 2/6] spi: atmel: add dmaengine and dt support Wenyou Yang
@ 2012-09-26 6:50 ` Wenyou Yang
2012-09-26 8:32 ` Nicolas Ferre
2012-09-26 6:50 ` [PATCH 4/6] ARM: dts: add spi nodes for atmel SoCs Wenyou Yang
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Wenyou Yang @ 2012-09-26 6:50 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/mach-at91/at91sam9260.c | 2 ++
arch/arm/mach-at91/at91sam9g45.c | 2 ++
arch/arm/mach-at91/at91sam9n12.c | 2 ++
arch/arm/mach-at91/at91sam9x5.c | 3 +++
4 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 30c7f26..90d38a8 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -227,6 +227,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
+ CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi0_clk),
+ CLKDEV_CON_DEV_ID("spi_clk", "fffac000.spi", &spi1_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index ef6cedd..9d0ec1c 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -254,6 +254,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
+ CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
+ CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 0849466..21b264b 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -169,6 +169,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
+ CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
+ CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
CLKDEV_CON_ID("pioA", &pioAB_clk),
CLKDEV_CON_ID("pioB", &pioAB_clk),
CLKDEV_CON_ID("pioC", &pioCD_clk),
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 477cf9d..b6f3a92 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -16,6 +16,7 @@
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include <mach/board.h>
+#include <mach/gpio.h>
#include "soc.h"
#include "generic.h"
@@ -231,6 +232,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
+ CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
+ CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
CLKDEV_CON_ID("pioA", &pioAB_clk),
CLKDEV_CON_ID("pioB", &pioAB_clk),
CLKDEV_CON_ID("pioC", &pioCD_clk),
--
1.7.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 4/6] ARM: dts: add spi nodes for atmel SoCs
2012-09-26 6:50 [PATCH 0/6] atmel SoC SPI controller with DT Wenyou Yang
` (2 preceding siblings ...)
2012-09-26 6:50 ` [PATCH 3/6] ARM: at91: add clocks for spi DT entries Wenyou Yang
@ 2012-09-26 6:50 ` Wenyou Yang
2012-09-26 6:51 ` [PATCH 5/6] ARM: dts: add spi nodes for atmel boards Wenyou Yang
` (2 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Wenyou Yang @ 2012-09-26 6:50 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/boot/dts/at91sam9260.dtsi | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9263.dtsi | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9g45.dtsi | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9n12.dtsi | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9x5.dtsi | 34 ++++++++++++++++++++++++++++++++++
5 files changed, 170 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 7c95f76..36be91f 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -236,6 +236,40 @@
trigger-external;
};
};
+
+ spi0: spi at fffc8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffc8000 0x100>;
+ interrupts = <12 4 3>;
+ cs-gpios = <&pioA 3 0
+ &pioC 11 0
+ &pioC 16 0
+ &pioC 17 0
+ >;
+ has_dma_support = <0>;
+ has_pdc_support = <1>;
+ is_ver2 = <1>;
+ status = "disabled";
+ };
+
+ spi1: spi at fffcc000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffcc000 0x100>;
+ interrupts = <13 4 3>;
+ cs-gpios = <&pioB 3 0
+ &pioC 5 0
+ &pioC 4 0
+ &pioC 3 0
+ >;
+ has_dma_support = <0>;
+ has_pdc_support = <1>;
+ is_ver2 = <1>;
+ status = "disabled";
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 195019b..bb375e4 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -185,6 +185,40 @@
interrupts = <24 4 2>;
status = "disabled";
};
+
+ spi0: spi at fffa4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffa4000 0x100>;
+ interrupts = <14 4 3>;
+ cs-gpios = <&pioA 5 0
+ &pioA 3 0
+ &pioA 4 0
+ &pioB 11 0
+ >;
+ has_dma_support = <0>;
+ has_pdc_support = <1>;
+ is_ver2 = <1>;
+ status = "disabled";
+ };
+
+ spi1: spi at fffa8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffa8000 0x100>;
+ interrupts = <15 4 3>;
+ cs-gpios = <&pioB 15 0
+ &pioB 16 0
+ &pioB 17 0
+ &pioB 18 0
+ >;
+ has_dma_support = <0>;
+ has_pdc_support = <1>;
+ is_ver2 = <1>;
+ status = "disabled";
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 63751b1..1d96d32 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -242,6 +242,40 @@
trigger-value = <0x6>;
};
};
+
+ spi0: spi at fffa4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffa4000 0x100>;
+ interrupts = <14 4 3>;
+ cs-gpios = <&pioB 3 0
+ &pioB 18 0
+ &pioB 19 0
+ &pioD 27 0
+ >;
+ has_dma_support = <0>;
+ has_pdc_support = <1>;
+ is_ver2 = <1>;
+ status = "disabled";
+ };
+
+ spi1: spi at fffa8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffa8000 0x100>;
+ interrupts = <15 4 3>;
+ cs-gpios = <&pioB 17 0
+ &pioD 28 0
+ &pioD 18 0
+ &pioD 19 0
+ >;
+ has_dma_support = <0>;
+ has_pdc_support = <1>;
+ is_ver2 = <1>;
+ status = "disabled";
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index ef9336a..c6868a2 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -182,6 +182,40 @@
atmel,use-dma-tx;
status = "disabled";
};
+
+ spi0: spi at f0000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xf0000000 0x100>;
+ interrupts = <13 4 3>;
+ cs-gpios = <&pioA 14 0
+ &pioA 7 0
+ &pioA 1 0
+ &pioB 3 0
+ >;
+ has_dma_support = <1>;
+ has_pdc_support = <0>;
+ is_ver2 = <1>;
+ status = "disabled";
+ };
+
+ spi1: spi at f0004000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xf0004000 0x100>;
+ interrupts = <14 4 3>;
+ cs-gpios = <&pioA 8 0
+ &pioA 0 0
+ &pioA 31 0
+ &pioA 30 0
+ >;
+ has_dma_support = <1>;
+ has_pdc_support = <0>;
+ is_ver2 = <1>;
+ status = "disabled";
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 8a387a8..f124473 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -233,6 +233,40 @@
trigger-value = <0x6>;
};
};
+
+ spi0: spi at f0000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xf0000000 0x100>;
+ interrupts = <13 4 3>;
+ cs-gpios = <&pioA 14 0
+ &pioA 7 0 /* conflicts with TXD2 */
+ &pioA 1 0 /* conflicts with RXD0 */
+ &pioB 3 0 /* conflicts with ERXDV */
+ >;
+ has_dma_support = <1>;
+ has_pdc_support = <0>;
+ is_ver2 = <1>;
+ status = "disabled";
+ };
+
+ spi1: spi at f0004000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xf0004000 0x100>;
+ interrupts = <14 4 3>;
+ cs-gpios = <&pioA 8 0 /* conflitcs with RXD2 */
+ &pioA 0 0 /* conflitcs with TXD0 */
+ &pioA 31 0 /* conflitcs with TWCK0 */
+ &pioA 30 0 /* conflitcs with TWD0 */
+ >;
+ has_dma_support = <1>;
+ has_pdc_support = <0>;
+ is_ver2 = <1>;
+ status = "disabled";
+ };
};
nand0: nand at 40000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 5/6] ARM: dts: add spi nodes for atmel boards
2012-09-26 6:50 [PATCH 0/6] atmel SoC SPI controller with DT Wenyou Yang
` (3 preceding siblings ...)
2012-09-26 6:50 ` [PATCH 4/6] ARM: dts: add spi nodes for atmel SoCs Wenyou Yang
@ 2012-09-26 6:51 ` Wenyou Yang
2012-09-26 6:51 ` [PATCH 6/6] spi: atmel: add dt property for DMA configuration for sam9x5 and sam9n12 Wenyou Yang
2012-09-26 14:15 ` [PATCH 0/6] atmel SoC SPI controller with DT Jean-Christophe PLAGNIOL-VILLARD
6 siblings, 0 replies; 15+ messages in thread
From: Wenyou Yang @ 2012-09-26 6:51 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/boot/dts/at91sam9263ek.dts | 10 ++++++++++
arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 10 ++++++++++
arch/arm/boot/dts/at91sam9g25ek.dts | 10 ++++++++++
arch/arm/boot/dts/at91sam9m10g45ek.dts | 10 ++++++++++
arch/arm/boot/dts/at91sam9n12ek.dts | 10 ++++++++++
5 files changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index f86ac4b..ba68551 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -50,6 +50,16 @@
atmel,vbus-gpio = <&pioA 25 0>;
status = "okay";
};
+
+ spi0: spi at fffa4000 {
+ status = "okay";
+ cs-gpios = <&pioA 5 0>;
+ m25p80 at 0 {
+ compatible = "atmel,at25df321a";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index b06c0db..1be036f 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -51,6 +51,16 @@
atmel,vbus-gpio = <&pioC 5 0>;
status = "okay";
};
+
+ spi0: spi at fffc8000 {
+ status = "okay";
+ cs-gpios = <&pioA 3 0>;
+ m25p80 at 0 {
+ compatible = "atmel,at25df321a";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 96514c1..93d0b3c 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -32,6 +32,16 @@
phy-mode = "rmii";
status = "okay";
};
+
+ spi0: spi at f0000000 {
+ status = "okay";
+ cs-gpios = <&pioA 14 0>;
+ m25p80 at 0 {
+ compatible = "atmel,at25df321a";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+ };
};
usb0: ohci at 00600000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a3633bd..919faae 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -46,6 +46,16 @@
phy-mode = "rmii";
status = "okay";
};
+
+ spi0: spi at fffa4000 {
+ status = "okay";
+ cs-gpios = <&pioB 3 0>;
+ m25p80 at 0 {
+ compatible = "atmel,at25df321a";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+ };
};
nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index f4e43e3..a82e4ac 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -37,6 +37,16 @@
dbgu: serial at fffff200 {
status = "okay";
};
+
+ spi0: spi at f0000000 {
+ status = "okay";
+ cs-gpios = <&pioA 14 0>;
+ m25p80 at 0 {
+ compatible = "atmel,at25df321a";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+ };
};
nand0: nand at 40000000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 6/6] spi: atmel: add dt property for DMA configuration for sam9x5 and sam9n12
2012-09-26 6:50 [PATCH 0/6] atmel SoC SPI controller with DT Wenyou Yang
` (4 preceding siblings ...)
2012-09-26 6:51 ` [PATCH 5/6] ARM: dts: add spi nodes for atmel boards Wenyou Yang
@ 2012-09-26 6:51 ` Wenyou Yang
2012-09-26 8:28 ` Nicolas Ferre
2012-09-26 14:15 ` [PATCH 0/6] atmel SoC SPI controller with DT Jean-Christophe PLAGNIOL-VILLARD
6 siblings, 1 reply; 15+ messages in thread
From: Wenyou Yang @ 2012-09-26 6:51 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/boot/dts/at91sam9n12.dtsi | 2 ++
arch/arm/boot/dts/at91sam9x5.dtsi | 4 +++
drivers/spi/spi-atmel.c | 55 +++++++++++++++++++++++++++++++++++-
3 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index c6868a2..b51f94d 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -98,6 +98,7 @@
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <20 4 0>;
+ #dma-cells = <1>;
};
pioA: gpio at fffff400 {
@@ -197,6 +198,7 @@
has_dma_support = <1>;
has_pdc_support = <0>;
is_ver2 = <1>;
+ dma = <&dma 0x10002212>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index f124473..ee46cb7 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -100,12 +100,14 @@
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <20 4 0>;
+ #dma-cells = <1>;
};
dma1: dma-controller at ffffee00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffee00 0x200>;
interrupts = <21 4 0>;
+ #dma-cells = <1>;
};
pioA: gpio at fffff400 {
@@ -248,6 +250,7 @@
has_dma_support = <1>;
has_pdc_support = <0>;
is_ver2 = <1>;
+ dma = <&dma0 0x10002212>;
status = "disabled";
};
@@ -265,6 +268,7 @@
has_dma_support = <1>;
has_pdc_support = <0>;
is_ver2 = <1>;
+ dma = <&dma1 0x10002212>;
status = "disabled";
};
};
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 9930438..ad19423 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -1436,6 +1436,57 @@ static void atmel_spi_cleanup(struct spi_device *spi)
kfree(asd);
}
+static int at91_spi_of_init(struct device_node *np,
+ struct at_dma_slave *atslave)
+{
+ struct of_phandle_args dma_spec;
+ struct device_node *dmac_np;
+ struct platform_device *dmac_pdev;
+ const __be32 *nbcells;
+ int ret;
+
+ ret = of_parse_phandle_with_args(np, "dma", "#dma-cells", 0, &dma_spec);
+ if (ret || !dma_spec.np) {
+ pr_err("%s: can't parse dma property (%d)\n",
+ np->full_name, ret);
+ goto err0;
+ }
+ dmac_np = dma_spec.np;
+
+ /* check property format */
+ nbcells = of_get_property(dmac_np, "#dma-cells", NULL);
+ if (!nbcells) {
+ pr_err("%s: #dma-cells property is required\n", np->full_name);
+ ret = -EINVAL;
+ goto err1;
+ }
+
+ if (dma_spec.args_count != be32_to_cpup(nbcells)
+ || dma_spec.args_count != 1) {
+ pr_err("%s: wrong #dma-cells for %s\n",
+ np->full_name, dmac_np->full_name);
+ ret = -EINVAL;
+ goto err1;
+ }
+
+ dmac_pdev = of_find_device_by_node(dmac_np);
+ if (!dmac_pdev) {
+ pr_err("%s: unable to find pdev from DMA controller\n",
+ dmac_np->full_name);
+ ret = -EINVAL;
+ goto err1;
+ }
+
+ atslave->dma_dev = &dmac_pdev->dev;
+ atslave->cfg = dma_spec.args[0];
+
+err1:
+ of_node_put(dma_spec.np);
+err0:
+ pr_debug("%s exited with status %d\n", __func__, ret);
+ return ret;
+}
+
static int of_get_atmel_spi_data(struct device_node *np, struct atmel_spi *as)
{
const __be32 *val;
@@ -1540,7 +1591,9 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
goto out_unmap_regs;
if (as->data.has_dma_support) {
- if (atmel_spi_configure_dma(as) == 0)
+ if ((at91_spi_of_init(pdev->dev.of_node,
+ &as->data.dma_slave) == 0)
+ && (atmel_spi_configure_dma(as) == 0))
as->use_dma = true;
} else if (as->data.has_pdc_support)
as->use_pdc = true;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/6] spi: atmel: add dmaengine and dt support
2012-09-26 6:50 ` [PATCH 2/6] spi: atmel: add dmaengine and dt support Wenyou Yang
@ 2012-09-26 7:05 ` Uwe Kleine-König
2012-09-27 7:13 ` Richard Genoud
0 siblings, 1 reply; 15+ messages in thread
From: Uwe Kleine-König @ 2012-09-26 7:05 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Wed, Sep 26, 2012 at 02:50:57PM +0800, Wenyou Yang wrote:
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
I don't remember ever having touched the spi-atmel driver, so I'm pretty
sure I never gave my S-o-b for anything in this patch. Please reread
Documentation/SubmittingPatches and double check you understood what
Signed-off-by means before resubmitting this patch with all wrong
S-o-b's removed.
Best regards
Uwe
> Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> ---
> .../devicetree/bindings/spi/spi_atmel.txt | 29 +
> drivers/spi/spi-atmel.c | 739 ++++++++++++++++++--
> 2 files changed, 696 insertions(+), 72 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt
>
> diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
> new file mode 100644
> index 0000000..5a64825
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
> @@ -0,0 +1,29 @@
> +Atmel SPI device
> +
> +Required properties:
> +- compatible : should be "atmel,at91rm9200-spi".
> +- reg: Address and length of the register set for the device
> +- interrupts: Should contain macb interrupt
> +- cs-gpio: Should contain the GPIOs used for chipselect.
> +- has_dma_support: The chip has dma engine support for spi: 1 - support, 0 - no support
> +- has_pdc_support: The chip has pdc support for spi: 1 - support, 0 - no support
> +- is_ver2: If is th spi IP version 2, 1 - yes, 0 - no
> +- dma: handle to the dma controller that should be used
> +
> +spi0: spi at f0000000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0xf0000000 0x100>;
> + interrupts = <13 4>;
> + cs-gpios = <&pioA 14 0
> + &pioA 7 0 /* conflicts with TXD2 */
> + &pioA 1 0 /* conflicts with RXD0 */
> + &pioB 3 0 /* conflicts with ERXDV */
> + >;
> + has_dma_support = <1>;
> + has_pdc_support = <0>;
> + is_ver2 = <1>;
> + dma = <&dma0 0x10002212>;
> + status = "disabled";
> +};
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 16d6a83..9930438 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -15,15 +15,19 @@
> #include <linux/platform_device.h>
> #include <linux/delay.h>
> #include <linux/dma-mapping.h>
> +#include <linux/dmaengine.h>
> #include <linux/err.h>
> #include <linux/interrupt.h>
> #include <linux/spi/spi.h>
> #include <linux/slab.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
>
> #include <asm/io.h>
> #include <mach/board.h>
> #include <asm/gpio.h>
> #include <mach/cpu.h>
> +#include <mach/at_hdmac.h>
>
> /* SPI register offsets */
> #define SPI_CR 0x0000
> @@ -179,6 +183,38 @@
> #define spi_writel(port,reg,value) \
> __raw_writel((value), (port)->regs + SPI_##reg)
>
> +/*
> + * Version 2 of the SPI controller has
> + * - CR.LASTXFER
> + * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
> + * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
> + * - SPI_CSRx.CSAAT
> + * - SPI_CSRx.SBCR allows faster clocking
> + *
> + * We can determine the controller version by reading the VERSION
> + * register, but I haven't checked that it exists on all chips, and
> + * this is cheaper anyway.
> + */
> +struct atmel_spi_data {
> + u8 has_dma_support;
> + u8 has_pdc_support;
> + u8 is_ver2; /* 1-yes, 0-not */
> + struct at_dma_slave dma_slave;
> +};
> +
> +/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
> + * cache operations; better heuristics consider wordsize and bitrate.
> + */
> +#define DMA_MIN_BYTES 16
> +
> +struct atmel_spi_dma {
> + struct dma_chan *chan_rx;
> + struct dma_chan *chan_tx;
> + struct scatterlist sgrx;
> + struct scatterlist sgtx;
> + struct dma_async_tx_descriptor *data_desc_rx;
> + struct dma_async_tx_descriptor *data_desc_tx;
> +};
>
> /*
> * The core SPI transfer engine just talks to a register bank to set up
> @@ -187,7 +223,9 @@
> */
> struct atmel_spi {
> spinlock_t lock;
> + unsigned long flags;
>
> + resource_size_t phybase;
> void __iomem *regs;
> int irq;
> struct clk *clk;
> @@ -196,13 +234,23 @@ struct atmel_spi {
>
> u8 stopping;
> struct list_head queue;
> + struct tasklet_struct tasklet;
> struct spi_transfer *current_transfer;
> unsigned long current_remaining_bytes;
> struct spi_transfer *next_transfer;
> unsigned long next_remaining_bytes;
> + int done_status;
> + struct atmel_spi_data data;
>
> + bool use_dma;
> + bool use_pdc;
> +
> + /* scratch buffer */
> void *buffer;
> dma_addr_t buffer_dma;
> +
> + /* dmaengine data */
> + struct atmel_spi_dma dma;
> };
>
> /* Controller-specific per-slave state */
> @@ -214,22 +262,7 @@ struct atmel_spi_device {
> #define BUFFER_SIZE PAGE_SIZE
> #define INVALID_DMA_ADDRESS 0xffffffff
>
> -/*
> - * Version 2 of the SPI controller has
> - * - CR.LASTXFER
> - * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
> - * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
> - * - SPI_CSRx.CSAAT
> - * - SPI_CSRx.SBCR allows faster clocking
> - *
> - * We can determine the controller version by reading the VERSION
> - * register, but I haven't checked that it exists on all chips, and
> - * this is cheaper anyway.
> - */
> -static bool atmel_spi_is_v2(void)
> -{
> - return !cpu_is_at91rm9200();
> -}
> +static struct dma_slave_config slave_config;
>
> /*
> * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
> @@ -250,7 +283,7 @@ static bool atmel_spi_is_v2(void)
> * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
> * and (c) will trigger that first erratum in some cases.
> *
> - * TODO: Test if the atmel_spi_is_v2() branch below works on
> + * TODO: Test if the as->data.is_ver2 == 0 branch below works on
> * AT91RM9200 if we use some other register than CSR0. However, don't
> * do this unconditionally since AP7000 has an errata where the BITS
> * field in CSR0 overrides all other CSRs.
> @@ -262,7 +295,7 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
> unsigned active = spi->mode & SPI_CS_HIGH;
> u32 mr;
>
> - if (atmel_spi_is_v2()) {
> + if (as->data.is_ver2 == 1) {
> /*
> * Always use CSR0. This ensures that the clock
> * switches to the correct idle polarity before we
> @@ -317,10 +350,29 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
> asd->npcs_pin, active ? " (low)" : "",
> mr);
>
> - if (atmel_spi_is_v2() || spi->chip_select != 0)
> + if ((as->data.is_ver2 == 1) || spi->chip_select != 0)
> gpio_set_value(asd->npcs_pin, !active);
> }
>
> +static void atmel_spi_lock(struct atmel_spi *as)
> +{
> + spin_lock_irqsave(&as->lock, as->flags);
> +}
> +
> +static void atmel_spi_unlock(struct atmel_spi *as)
> +{
> + spin_unlock_irqrestore(&as->lock, as->flags);
> +}
> +
> +static inline bool atmel_spi_use_dma(struct atmel_spi *as,
> + struct spi_transfer *xfer)
> +{
> + if ((as->use_dma) && (xfer->len >= DMA_MIN_BYTES))
> + return true;
> + else
> + return false;
> +}
> +
> static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
> struct spi_transfer *xfer)
> {
> @@ -332,6 +384,255 @@ static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
> return xfer->delay_usecs == 0 && !xfer->cs_change;
> }
>
> +/*
> + * Next transfer using PIO.
> + * lock is held, spi tasklet is blocked
> + */
> +static void atmel_spi_next_xfer_pio(struct spi_master *master,
> + struct spi_transfer *xfer)
> +{
> + struct atmel_spi *as = spi_master_get_devdata(master);
> +
> + dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
> +
> + as->current_remaining_bytes = xfer->len;
> +
> + /* Make sure data is not remaining in RDR */
> + spi_readl(as, RDR);
> + while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
> + spi_readl(as, RDR);
> + cpu_relax();
> + }
> +
> + if (xfer->tx_buf)
> + if (xfer->bits_per_word > 8)
> + spi_writel(as, TDR, *(u16 *)(xfer->tx_buf));
> + else
> + spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
> + else
> + spi_writel(as, TDR, 0);
> +
> + dev_dbg(master->dev.parent,
> + " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
> + xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
> + xfer->bits_per_word);
> +
> + /* Enable relevant interrupts */
> + spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
> +}
> +
> +static bool filter(struct dma_chan *chan, void *slave)
> +{
> + struct at_dma_slave *sl = slave;
> +
> + if (sl->dma_dev == chan->device->dev) {
> + chan->private = sl;
> + return true;
> + } else {
> + return false;
> + }
> +}
> +
> +static int atmel_spi_set_dma_xfer_width(struct atmel_spi *as, u8 bits_per_word)
> +{
> + int err = 0;
> +
> + if (bits_per_word > 8) {
> + slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
> + slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
> + } else {
> + slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
> + slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
> + }
> +
> + slave_config.direction = DMA_TO_DEVICE;
> + if (dmaengine_slave_config(as->dma.chan_tx, &slave_config)) {
> + dev_err(&as->pdev->dev,
> + "failed to configure tx dma channel\n");
> + err = -EINVAL;
> + }
> +
> + slave_config.direction = DMA_FROM_DEVICE;
> + if (dmaengine_slave_config(as->dma.chan_rx, &slave_config)) {
> + dev_err(&as->pdev->dev,
> + "failed to configure rx dma channel\n");
> + err = -EINVAL;
> + }
> + return err;
> +}
> +
> +static int __devinit atmel_spi_configure_dma(struct atmel_spi *as)
> +{
> + struct at_dma_slave *sdata = (struct at_dma_slave *)&as->data.dma_slave;
> + int err;
> +
> + slave_config.dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
> + slave_config.src_addr = (dma_addr_t)as->phybase + SPI_RDR;
> + slave_config.src_maxburst = 1;
> + slave_config.dst_maxburst = 1;
> + slave_config.device_fc = false;
> +
> + if (sdata && sdata->dma_dev) {
> + dma_cap_mask_t mask;
> +
> + /* Try to grab two DMA channels */
> + dma_cap_zero(mask);
> + dma_cap_set(DMA_SLAVE, mask);
> + as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
> + if (as->dma.chan_tx)
> + as->dma.chan_rx = dma_request_channel(mask,
> + filter, sdata);
> + }
> +
> + if (!as->dma.chan_rx || !as->dma.chan_tx) {
> + dev_err(&as->pdev->dev, "DMA channel not available, " \
> + "unable to use SPI\n");
> + err = -EBUSY;
> + goto error;
> + }
> +
> + err = atmel_spi_set_dma_xfer_width(as, 8);
> + if (err)
> + goto error;
> +
> + dev_info(&as->pdev->dev, "Using %s (tx) and " \
> + " %s (rx) for DMA transfers\n",
> + dma_chan_name(as->dma.chan_tx),
> + dma_chan_name(as->dma.chan_rx));
> +
> + return 0;
> +error:
> + if (as->dma.chan_rx)
> + dma_release_channel(as->dma.chan_rx);
> + if (as->dma.chan_tx)
> + dma_release_channel(as->dma.chan_tx);
> + return err;
> +}
> +
> +static void atmel_spi_stop_dma(struct atmel_spi *as)
> +{
> + if (as->dma.chan_rx)
> + as->dma.chan_rx->device->device_control(as->dma.chan_rx,
> + DMA_TERMINATE_ALL, 0);
> + if (as->dma.chan_tx)
> + as->dma.chan_tx->device->device_control(as->dma.chan_tx,
> + DMA_TERMINATE_ALL, 0);
> +}
> +
> +static void atmel_spi_release_dma(struct atmel_spi *as)
> +{
> + if (as->dma.chan_rx)
> + dma_release_channel(as->dma.chan_rx);
> + if (as->dma.chan_tx)
> + dma_release_channel(as->dma.chan_tx);
> +}
> +
> +/* This function is called by the DMA driver from tasklet context */
> +static void dma_callback(void *data)
> +{
> + struct spi_master *master = data;
> + struct atmel_spi *as = spi_master_get_devdata(master);
> +
> + /* trigger SPI tasklet */
> + tasklet_schedule(&as->tasklet);
> +}
> +
> +/*
> + * Submit next transfer for DMA.
> + * lock is held, spi tasklet is blocked
> + */
> +static int atmel_spi_next_xfer_dma(struct spi_master *master,
> + struct spi_transfer *xfer)
> +{
> + struct atmel_spi *as = spi_master_get_devdata(master);
> + struct dma_chan *rxchan = as->dma.chan_rx;
> + struct dma_chan *txchan = as->dma.chan_tx;
> + struct dma_async_tx_descriptor *rxdesc;
> + struct dma_async_tx_descriptor *txdesc;
> + dma_cookie_t cookie;
> +
> + dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma\n");
> +
> + /* Check that the channels are available */
> + if (!rxchan || !txchan)
> + return -ENODEV;
> +
> + /* release lock for DMA operations */
> + atmel_spi_unlock(as);
> +
> + /* prepare the RX dma transfer */
> + sg_init_table(&as->dma.sgrx, 1);
> + sg_dma_len(&as->dma.sgrx) = xfer->len;
> + if (xfer->rx_buf)
> + as->dma.sgrx.dma_address = xfer->rx_dma;
> + else
> + as->dma.sgrx.dma_address = as->buffer_dma;
> +
> + /* prepare the TX dma transfer */
> + sg_init_table(&as->dma.sgtx, 1);
> + sg_dma_len(&as->dma.sgtx) = xfer->len;
> + if (xfer->tx_buf) {
> + as->dma.sgtx.dma_address = xfer->tx_dma;
> + } else {
> + as->dma.sgtx.dma_address = as->buffer_dma;
> + memset(as->buffer, 0, xfer->len);
> + }
> +
> + if (atmel_spi_set_dma_xfer_width(as, xfer->bits_per_word))
> + goto err_dma;
> +
> + /* Send both scatterlists */
> + rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
> + &as->dma.sgrx,
> + 1,
> + DMA_FROM_DEVICE,
> + DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
> + NULL);
> + if (!rxdesc)
> + goto err_dma;
> +
> + txdesc = txchan->device->device_prep_slave_sg(txchan,
> + &as->dma.sgtx,
> + 1,
> + DMA_TO_DEVICE,
> + DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
> + NULL);
> + if (!txdesc)
> + goto err_dma;
> +
> + dev_dbg(master->dev.parent,
> + " start dma xfer %p: len %u tx %p/%08x rx %p/%08x\n",
> + xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
> + xfer->rx_buf, xfer->rx_dma);
> +
> + /* Enable relevant interrupts */
> + spi_writel(as, IER, SPI_BIT(OVRES));
> +
> + /* Put the callback on the RX transfer only, that should finish last */
> + rxdesc->callback = dma_callback;
> + rxdesc->callback_param = master;
> +
> + /* Submit and fire RX and TX with TX last so we're ready to read! */
> + cookie = rxdesc->tx_submit(rxdesc);
> + if (dma_submit_error(cookie))
> + goto err_dma;
> + cookie = txdesc->tx_submit(txdesc);
> + if (dma_submit_error(cookie))
> + goto err_dma;
> + rxchan->device->device_issue_pending(rxchan);
> + txchan->device->device_issue_pending(txchan);
> +
> + /* take back lock */
> + atmel_spi_lock(as);
> + return 0;
> +
> +err_dma:
> + spi_writel(as, IDR, SPI_BIT(OVRES));
> + atmel_spi_stop_dma(as);
> + atmel_spi_lock(as);
> + return -ENOMEM;
> +}
> +
> static void atmel_spi_next_xfer_data(struct spi_master *master,
> struct spi_transfer *xfer,
> dma_addr_t *tx_dma,
> @@ -364,10 +665,10 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
> }
>
> /*
> - * Submit next transfer for DMA.
> + * Submit next transfer for PDC.
> * lock is held, spi irq is blocked
> */
> -static void atmel_spi_next_xfer(struct spi_master *master,
> +static void atmel_spi_next_xfer_pdc(struct spi_master *master,
> struct spi_message *msg)
> {
> struct atmel_spi *as = spi_master_get_devdata(master);
> @@ -464,6 +765,44 @@ static void atmel_spi_next_xfer(struct spi_master *master,
> spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
> }
>
> +/*
> + * Choose way to submit next transfer and start it.
> + * lock is held, spi tasklet is blocked
> + */
> +static void atmel_spi_next_xfer(struct spi_master *master,
> + struct spi_message *msg)
> +{
> + struct atmel_spi *as = spi_master_get_devdata(master);
> + struct spi_transfer *xfer;
> +
> + dev_vdbg(&msg->spi->dev, "atmel_spi_next_xfer\n");
> +
> + if (as->use_pdc)
> + atmel_spi_next_xfer_pdc(master, msg);
> + else {
> + if (!as->current_transfer)
> + xfer = list_entry(msg->transfers.next,
> + struct spi_transfer, transfer_list);
> + else
> + xfer = list_entry(
> + as->current_transfer->transfer_list.next,
> + struct spi_transfer, transfer_list);
> +
> + as->current_transfer = xfer;
> +
> + /* quick (and *really* not optimal) workaround for DMA BUG */
> + if (atmel_spi_use_dma(as, xfer) && (xfer->len < BUFFER_SIZE)) {
> + if (!atmel_spi_next_xfer_dma(master, xfer))
> + return;
> + else
> + dev_err(&msg->spi->dev, "unable to use DMA, fallback to PIO\n");
> + }
> +
> + /* use PIO if xfer is short or error appened using DMA */
> + atmel_spi_next_xfer_pio(master, xfer);
> + }
> +}
> +
> static void atmel_spi_next_message(struct spi_master *master)
> {
> struct atmel_spi *as = spi_master_get_devdata(master);
> @@ -541,43 +880,218 @@ static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
> xfer->len, DMA_FROM_DEVICE);
> }
>
> +static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
> +{
> + spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
> +}
> +
> static void
> atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
> - struct spi_message *msg, int status, int stay)
> + struct spi_message *msg, int stay)
> {
> - if (!stay || status < 0)
> + if (!stay || as->done_status < 0)
> cs_deactivate(as, msg->spi);
> else
> as->stay = msg->spi;
>
> list_del(&msg->queue);
> - msg->status = status;
> + msg->status = as->done_status;
>
> dev_dbg(master->dev.parent,
> "xfer complete: %u bytes transferred\n",
> msg->actual_length);
>
> - spin_unlock(&as->lock);
> + atmel_spi_unlock(as);
> msg->complete(msg->context);
> - spin_lock(&as->lock);
> + atmel_spi_lock(as);
>
> as->current_transfer = NULL;
> as->next_transfer = NULL;
> + as->done_status = 0;
>
> /* continue if needed */
> - if (list_empty(&as->queue) || as->stopping)
> - spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
> - else
> + if (list_empty(&as->queue) || as->stopping) {
> + if (as->use_pdc)
> + atmel_spi_disable_pdc_transfer(as);
> + } else
> atmel_spi_next_message(master);
> }
>
> -static irqreturn_t
> -atmel_spi_interrupt(int irq, void *dev_id)
> +/* Called from IRQ
> + * lock is held
> + *
> + * Must update "current_remaining_bytes" to keep track of data
> + * to transfer.
> + */
> +static void
> +atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
> {
> - struct spi_master *master = dev_id;
> + u8 *txp;
> + u8 *rxp;
> + u16 *txp16;
> + u16 *rxp16;
> + unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
> +
> + if (xfer->rx_buf) {
> + if (xfer->bits_per_word > 8) {
> + rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
> + *rxp16 = spi_readl(as, RDR);
> + } else {
> + rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
> + *rxp = spi_readl(as, RDR);
> + }
> + } else {
> + spi_readl(as, RDR);
> + }
> + if (xfer->bits_per_word > 8) {
> + as->current_remaining_bytes -= 2;
> + if (as->current_remaining_bytes < 0)
> + as->current_remaining_bytes = 0;
> + } else {
> + as->current_remaining_bytes--;
> + }
> +
> + if (as->current_remaining_bytes) {
> + if (xfer->tx_buf) {
> + if (xfer->bits_per_word > 8) {
> + txp16 = (u16 *)(((u8 *)xfer->tx_buf)
> + + xfer_pos + 2);
> + spi_writel(as, TDR, *txp16);
> + } else {
> + txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
> + spi_writel(as, TDR, *txp);
> + }
> + } else {
> + spi_writel(as, TDR, 0);
> + }
> + }
> +}
> +
> +/* Tasklet
> + * Called from DMA callback + pio transfer and overrun IRQ.
> + */
> +static void atmel_spi_tasklet_func(unsigned long data)
> +{
> + struct spi_master *master = (struct spi_master *)data;
> struct atmel_spi *as = spi_master_get_devdata(master);
> struct spi_message *msg;
> struct spi_transfer *xfer;
> +
> + dev_vdbg(master->dev.parent, "atmel_spi_tasklet_func\n");
> +
> + atmel_spi_lock(as);
> +
> + xfer = as->current_transfer;
> +
> + if (xfer == NULL)
> + /* already been there */
> + goto tasklet_out;
> +
> + msg = list_entry(as->queue.next, struct spi_message, queue);
> +
> + if (as->done_status < 0) {
> + /* error happened (overrun) */
> + if (atmel_spi_use_dma(as, xfer))
> + atmel_spi_stop_dma(as);
> + } else {
> + /* only update length if no error */
> + msg->actual_length += xfer->len;
> + }
> +
> + if (atmel_spi_use_dma(as, xfer)) {
> + if (!msg->is_dma_mapped)
> + atmel_spi_dma_unmap_xfer(master, xfer);
> + }
> +
> + if (xfer->delay_usecs)
> + udelay(xfer->delay_usecs);
> +
> + if (atmel_spi_xfer_is_last(msg, xfer) || as->done_status < 0) {
> + /* report completed (or erroneous) message */
> + atmel_spi_msg_done(master, as, msg, xfer->cs_change);
> + } else {
> + if (xfer->cs_change) {
> + cs_deactivate(as, msg->spi);
> + udelay(1);
> + cs_activate(as, msg->spi);
> + }
> +
> + /*
> + * Not done yet. Submit the next transfer.
> + *
> + * FIXME handle protocol options for xfer
> + */
> + atmel_spi_next_xfer(master, msg);
> + }
> +
> +tasklet_out:
> + atmel_spi_unlock(as);
> +}
> +
> +static int atmel_spi_interrupt_dma(struct atmel_spi *as,
> + struct spi_master *master)
> +{
> + u32 status, pending, imr;
> + struct spi_transfer *xfer;
> + int ret = IRQ_NONE;
> +
> + imr = spi_readl(as, IMR);
> + status = spi_readl(as, SR);
> + pending = status & imr;
> +
> + if (pending & SPI_BIT(OVRES)) {
> + ret = IRQ_HANDLED;
> + spi_writel(as, IDR, SPI_BIT(OVRES));
> + dev_warn(master->dev.parent, "overrun\n");
> +
> + /*
> + * When we get an overrun, we disregard the current
> + * transfer. Data will not be copied back from any
> + * bounce buffer and msg->actual_len will not be
> + * updated with the last xfer.
> + *
> + * We will also not process any remaning transfers in
> + * the message.
> + *
> + * All actions are done in tasklet with done_status indication
> + */
> + as->done_status = -EIO;
> + smp_wmb();
> +
> + /* Clear any overrun happening while cleaning up */
> + spi_readl(as, SR);
> +
> + tasklet_schedule(&as->tasklet);
> +
> + } else if (pending & SPI_BIT(RDRF)) {
> + atmel_spi_lock(as);
> +
> + if (as->current_remaining_bytes) {
> + ret = IRQ_HANDLED;
> + xfer = as->current_transfer;
> + atmel_spi_pump_pio_data(as, xfer);
> + if (!as->current_remaining_bytes) {
> + /* no more data to xfer, kick tasklet */
> + spi_writel(as, IDR, pending);
> + tasklet_schedule(&as->tasklet);
> + }
> + }
> +
> + atmel_spi_unlock(as);
> + } else {
> + WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
> + ret = IRQ_HANDLED;
> + spi_writel(as, IDR, pending);
> + }
> +
> + return ret;
> +}
> +
> +static int atmel_spi_interrupt_pdc(struct atmel_spi *as,
> + struct spi_master *master)
> +{
> + struct spi_message *msg;
> + struct spi_transfer *xfer;
> u32 status, pending, imr;
> int ret = IRQ_NONE;
>
> @@ -610,8 +1124,6 @@ atmel_spi_interrupt(int irq, void *dev_id)
> * First, stop the transfer and unmap the DMA buffers.
> */
> spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
> - if (!msg->is_dma_mapped)
> - atmel_spi_dma_unmap_xfer(master, xfer);
>
> /* REVISIT: udelay in irq is unfriendly */
> if (xfer->delay_usecs)
> @@ -640,7 +1152,8 @@ atmel_spi_interrupt(int irq, void *dev_id)
> /* Clear any overrun happening while cleaning up */
> spi_readl(as, SR);
>
> - atmel_spi_msg_done(master, as, msg, -EIO, 0);
> + as->done_status = -EIO;
> + atmel_spi_msg_done(master, as, msg, 0);
> } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
> ret = IRQ_HANDLED;
>
> @@ -649,16 +1162,13 @@ atmel_spi_interrupt(int irq, void *dev_id)
> if (as->current_remaining_bytes == 0) {
> msg->actual_length += xfer->len;
>
> - if (!msg->is_dma_mapped)
> - atmel_spi_dma_unmap_xfer(master, xfer);
> -
> /* REVISIT: udelay in irq is unfriendly */
> if (xfer->delay_usecs)
> udelay(xfer->delay_usecs);
>
> if (atmel_spi_xfer_is_last(msg, xfer)) {
> /* report completed message */
> - atmel_spi_msg_done(master, as, msg, 0,
> + atmel_spi_msg_done(master, as, msg,
> xfer->cs_change);
> } else {
> if (xfer->cs_change) {
> @@ -688,6 +1198,27 @@ atmel_spi_interrupt(int irq, void *dev_id)
> return ret;
> }
>
> +/* Interrupt
> + *
> + * No need for locking in this Interrupt handler: done_status is the
> + * only information modified. What we need is the update of this field
> + * before tasklet runs. This is ensured by using barrier.
> + */
> +static irqreturn_t
> +atmel_spi_interrupt(int irq, void *dev_id)
> +{
> + struct spi_master *master = dev_id;
> + struct atmel_spi *as = spi_master_get_devdata(master);
> + int ret;
> +
> + if (as->use_pdc)
> + ret = atmel_spi_interrupt_pdc(as, master);
> + else
> + ret = atmel_spi_interrupt_dma(as, master);
> +
> + return ret;
> +}
> +
> static int atmel_spi_setup(struct spi_device *spi)
> {
> struct atmel_spi *as;
> @@ -695,7 +1226,7 @@ static int atmel_spi_setup(struct spi_device *spi)
> u32 scbr, csr;
> unsigned int bits = spi->bits_per_word;
> unsigned long bus_hz;
> - unsigned int npcs_pin;
> + int npcs_pin;
> int ret;
>
> as = spi_master_get_devdata(spi->master);
> @@ -718,16 +1249,16 @@ static int atmel_spi_setup(struct spi_device *spi)
> }
>
> /* see notes above re chipselect */
> - if (!atmel_spi_is_v2()
> - && spi->chip_select == 0
> - && (spi->mode & SPI_CS_HIGH)) {
> + if ((as->data.is_ver2 == 0)
> + && spi->chip_select == 0
> + && (spi->mode & SPI_CS_HIGH)) {
> dev_dbg(&spi->dev, "setup: can't be active-high\n");
> return -EINVAL;
> }
>
> /* v1 chips start out at half the peripheral bus speed. */
> bus_hz = clk_get_rate(as->clk);
> - if (!atmel_spi_is_v2())
> + if (as->data.is_ver2 == 0)
> bus_hz /= 2;
>
> if (spi->max_speed_hz) {
> @@ -767,7 +1298,9 @@ static int atmel_spi_setup(struct spi_device *spi)
> csr |= SPI_BF(DLYBCT, 0);
>
> /* chipselect must have been muxed as GPIO (e.g. in board setup) */
> - npcs_pin = (unsigned int)spi->controller_data;
> + if (!gpio_is_valid(spi->cs_gpio))
> + spi->cs_gpio = (int)spi->controller_data;
> + npcs_pin = spi->cs_gpio;
> asd = spi->controller_state;
> if (!asd) {
> asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
> @@ -784,13 +1317,11 @@ static int atmel_spi_setup(struct spi_device *spi)
> spi->controller_state = asd;
> gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
> } else {
> - unsigned long flags;
> -
> - spin_lock_irqsave(&as->lock, flags);
> + atmel_spi_lock(as);
> if (as->stay == spi)
> as->stay = NULL;
> cs_deactivate(as, spi);
> - spin_unlock_irqrestore(&as->lock, flags);
> + atmel_spi_unlock(as);
> }
>
> asd->csr = csr;
> @@ -799,7 +1330,7 @@ static int atmel_spi_setup(struct spi_device *spi)
> "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
> bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
>
> - if (!atmel_spi_is_v2())
> + if (as->data.is_ver2 == 0)
> spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
>
> return 0;
> @@ -809,7 +1340,6 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
> {
> struct atmel_spi *as;
> struct spi_transfer *xfer;
> - unsigned long flags;
> struct device *controller = spi->master->dev.parent;
> u8 bits;
> struct atmel_spi_device *asd;
> @@ -840,6 +1370,12 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
> return -ENOPROTOOPT;
> }
> }
> + if (xfer->bits_per_word > 8) {
> + if (xfer->len % 2) {
> + dev_dbg(&spi->dev, "buffer len should be 16 bits aligned\n");
> + return -EINVAL;
> + }
> + }
>
> /* FIXME implement these protocol options!! */
> if (xfer->speed_hz) {
> @@ -849,13 +1385,9 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
>
> /*
> * DMA map early, for performance (empties dcache ASAP) and
> - * better fault reporting. This is a DMA-only driver.
> - *
> - * NOTE that if dma_unmap_single() ever starts to do work on
> - * platforms supported by this driver, we would need to clean
> - * up mappings for previously-mapped transfers.
> + * better fault reporting.
> */
> - if (!msg->is_dma_mapped) {
> + if (!msg->is_dma_mapped && atmel_spi_use_dma(as, xfer)) {
> if (atmel_spi_dma_map_xfer(as, xfer) < 0)
> return -ENOMEM;
> }
> @@ -874,11 +1406,11 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
> msg->status = -EINPROGRESS;
> msg->actual_length = 0;
>
> - spin_lock_irqsave(&as->lock, flags);
> + atmel_spi_lock(as);
> list_add_tail(&msg->queue, &as->queue);
> if (!as->current_transfer)
> atmel_spi_next_message(spi->master);
> - spin_unlock_irqrestore(&as->lock, flags);
> + atmel_spi_unlock(as);
>
> return 0;
> }
> @@ -887,25 +1419,55 @@ static void atmel_spi_cleanup(struct spi_device *spi)
> {
> struct atmel_spi *as = spi_master_get_devdata(spi->master);
> struct atmel_spi_device *asd = spi->controller_state;
> - unsigned gpio = (unsigned) spi->controller_data;
> - unsigned long flags;
> + unsigned gpio = spi->cs_gpio;
>
> if (!asd)
> return;
>
> - spin_lock_irqsave(&as->lock, flags);
> + atmel_spi_lock(as);
> if (as->stay == spi) {
> as->stay = NULL;
> cs_deactivate(as, spi);
> }
> - spin_unlock_irqrestore(&as->lock, flags);
> + atmel_spi_unlock(as);
>
> spi->controller_state = NULL;
> gpio_free(gpio);
> kfree(asd);
> }
>
> -/*-------------------------------------------------------------------------*/
> +static int of_get_atmel_spi_data(struct device_node *np, struct atmel_spi *as)
> +{
> + const __be32 *val;
> +
> + val = of_get_property(np, "has_dma_support", NULL);
> + if (!val) {
> + pr_err("%s: have no 'has_dma_support' property\n",
> + np->full_name);
> + return -EINVAL;
> + }
> +
> + as->data.has_dma_support = be32_to_cpup(val);
> +
> + val = of_get_property(np, "has_pdc_support", NULL);
> + if (!val) {
> + pr_err("%s: have no 'has_pdc_support' property\n",
> + np->full_name);
> + return -EINVAL;
> + }
> +
> + as->data.has_pdc_support = be32_to_cpup(val);
> +
> + val = of_get_property(np, "is_ver2", NULL);
> + if (!val) {
> + pr_err("%s: have no 'is_ver2' property\n", np->full_name);
> + return -EINVAL;
> + }
> +
> + as->data.is_ver2 = be32_to_cpup(val);
> +
> + return 0;
> +}
>
> static int __devinit atmel_spi_probe(struct platform_device *pdev)
> {
> @@ -938,7 +1500,8 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
> master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
>
> master->bus_num = pdev->id;
> - master->num_chipselect = 4;
> + master->dev.of_node = pdev->dev.of_node;
> + master->num_chipselect = master->dev.of_node ? 0 : 4;
> master->setup = atmel_spi_setup;
> master->transfer = atmel_spi_transfer;
> master->cleanup = atmel_spi_cleanup;
> @@ -957,10 +1520,13 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
>
> spin_lock_init(&as->lock);
> INIT_LIST_HEAD(&as->queue);
> + tasklet_init(&as->tasklet, atmel_spi_tasklet_func,
> + (unsigned long)master);
> as->pdev = pdev;
> as->regs = ioremap(regs->start, resource_size(regs));
> if (!as->regs)
> goto out_free_buffer;
> + as->phybase = regs->start;
> as->irq = irq;
> as->clk = clk;
>
> @@ -969,12 +1535,22 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
> if (ret)
> goto out_unmap_regs;
>
> + ret = of_get_atmel_spi_data(pdev->dev.of_node, as);
> + if (ret)
> + goto out_unmap_regs;
> +
> + if (as->data.has_dma_support) {
> + if (atmel_spi_configure_dma(as) == 0)
> + as->use_dma = true;
> + } else if (as->data.has_pdc_support)
> + as->use_pdc = true;
> +
> /* Initialize the hardware */
> clk_enable(clk);
> spi_writel(as, CR, SPI_BIT(SWRST));
> spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
> spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
> - spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
> +
> spi_writel(as, CR, SPI_BIT(SPIEN));
>
> /* go! */
> @@ -983,11 +1559,14 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
>
> ret = spi_register_master(master);
> if (ret)
> - goto out_reset_hw;
> + goto out_free_dma;
>
> return 0;
>
> -out_reset_hw:
> +out_free_dma:
> + if (as->use_dma)
> + atmel_spi_release_dma(as);
> +
> spi_writel(as, CR, SPI_BIT(SWRST));
> spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
> clk_disable(clk);
> @@ -995,6 +1574,7 @@ out_reset_hw:
> out_unmap_regs:
> iounmap(as->regs);
> out_free_buffer:
> + tasklet_kill(&as->tasklet);
> dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
> as->buffer_dma);
> out_free:
> @@ -1008,10 +1588,16 @@ static int __devexit atmel_spi_remove(struct platform_device *pdev)
> struct spi_master *master = platform_get_drvdata(pdev);
> struct atmel_spi *as = spi_master_get_devdata(master);
> struct spi_message *msg;
> + struct spi_transfer *xfer;
>
> /* reset the hardware and block queue progress */
> spin_lock_irq(&as->lock);
> as->stopping = 1;
> + if (as->use_dma) {
> + atmel_spi_stop_dma(as);
> + atmel_spi_release_dma(as);
> + }
> +
> spi_writel(as, CR, SPI_BIT(SWRST));
> spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
> spi_readl(as, SR);
> @@ -1019,13 +1605,15 @@ static int __devexit atmel_spi_remove(struct platform_device *pdev)
>
> /* Terminate remaining queued transfers */
> list_for_each_entry(msg, &as->queue, queue) {
> - /* REVISIT unmapping the dma is a NOP on ARM and AVR32
> - * but we shouldn't depend on that...
> - */
> + list_for_each_entry(xfer, &msg->transfers, transfer_list) {
> + if (!msg->is_dma_mapped && atmel_spi_use_dma(as, xfer))
> + atmel_spi_dma_unmap_xfer(master, xfer);
> + }
> msg->status = -ESHUTDOWN;
> msg->complete(msg->context);
> }
>
> + tasklet_kill(&as->tasklet);
> dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
> as->buffer_dma);
>
> @@ -1040,7 +1628,6 @@ static int __devexit atmel_spi_remove(struct platform_device *pdev)
> }
>
> #ifdef CONFIG_PM
> -
> static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
> {
> struct spi_master *master = platform_get_drvdata(pdev);
> @@ -1064,11 +1651,19 @@ static int atmel_spi_resume(struct platform_device *pdev)
> #define atmel_spi_resume NULL
> #endif
>
> +#if defined(CONFIG_OF)
> +static const struct of_device_id atmel_spi_dt_ids[] = {
> + { .compatible = "atmel,at91rm9200-spi" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
> +#endif
>
> static struct platform_driver atmel_spi_driver = {
> .driver = {
> .name = "atmel_spi",
> .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(atmel_spi_dt_ids),
> },
> .suspend = atmel_spi_suspend,
> .resume = atmel_spi_resume,
> --
> 1.7.9.5
>
>
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 6/6] spi: atmel: add dt property for DMA configuration for sam9x5 and sam9n12
2012-09-26 6:51 ` [PATCH 6/6] spi: atmel: add dt property for DMA configuration for sam9x5 and sam9n12 Wenyou Yang
@ 2012-09-26 8:28 ` Nicolas Ferre
0 siblings, 0 replies; 15+ messages in thread
From: Nicolas Ferre @ 2012-09-26 8:28 UTC (permalink / raw)
To: linux-arm-kernel
On 09/26/2012 08:51 AM, Wenyou Yang :
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
This is not mainline material: we have a DMA-DT API, now.
> ---
> arch/arm/boot/dts/at91sam9n12.dtsi | 2 ++
> arch/arm/boot/dts/at91sam9x5.dtsi | 4 +++
> drivers/spi/spi-atmel.c | 55 +++++++++++++++++++++++++++++++++++-
> 3 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
> index c6868a2..b51f94d 100644
> --- a/arch/arm/boot/dts/at91sam9n12.dtsi
> +++ b/arch/arm/boot/dts/at91sam9n12.dtsi
> @@ -98,6 +98,7 @@
> compatible = "atmel,at91sam9g45-dma";
> reg = <0xffffec00 0x200>;
> interrupts = <20 4 0>;
> + #dma-cells = <1>;
> };
>
> pioA: gpio at fffff400 {
> @@ -197,6 +198,7 @@
> has_dma_support = <1>;
> has_pdc_support = <0>;
> is_ver2 = <1>;
> + dma = <&dma 0x10002212>;
> status = "disabled";
> };
>
> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> index f124473..ee46cb7 100644
> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> @@ -100,12 +100,14 @@
> compatible = "atmel,at91sam9g45-dma";
> reg = <0xffffec00 0x200>;
> interrupts = <20 4 0>;
> + #dma-cells = <1>;
> };
>
> dma1: dma-controller at ffffee00 {
> compatible = "atmel,at91sam9g45-dma";
> reg = <0xffffee00 0x200>;
> interrupts = <21 4 0>;
> + #dma-cells = <1>;
> };
>
> pioA: gpio at fffff400 {
> @@ -248,6 +250,7 @@
> has_dma_support = <1>;
> has_pdc_support = <0>;
> is_ver2 = <1>;
> + dma = <&dma0 0x10002212>;
> status = "disabled";
> };
>
> @@ -265,6 +268,7 @@
> has_dma_support = <1>;
> has_pdc_support = <0>;
> is_ver2 = <1>;
> + dma = <&dma1 0x10002212>;
> status = "disabled";
> };
> };
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 9930438..ad19423 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -1436,6 +1436,57 @@ static void atmel_spi_cleanup(struct spi_device *spi)
> kfree(asd);
> }
>
> +static int at91_spi_of_init(struct device_node *np,
> + struct at_dma_slave *atslave)
> +{
> + struct of_phandle_args dma_spec;
> + struct device_node *dmac_np;
> + struct platform_device *dmac_pdev;
> + const __be32 *nbcells;
> + int ret;
> +
> + ret = of_parse_phandle_with_args(np, "dma", "#dma-cells", 0, &dma_spec);
> + if (ret || !dma_spec.np) {
> + pr_err("%s: can't parse dma property (%d)\n",
> + np->full_name, ret);
> + goto err0;
> + }
> + dmac_np = dma_spec.np;
> +
> + /* check property format */
> + nbcells = of_get_property(dmac_np, "#dma-cells", NULL);
> + if (!nbcells) {
> + pr_err("%s: #dma-cells property is required\n", np->full_name);
> + ret = -EINVAL;
> + goto err1;
> + }
> +
> + if (dma_spec.args_count != be32_to_cpup(nbcells)
> + || dma_spec.args_count != 1) {
> + pr_err("%s: wrong #dma-cells for %s\n",
> + np->full_name, dmac_np->full_name);
> + ret = -EINVAL;
> + goto err1;
> + }
> +
> + dmac_pdev = of_find_device_by_node(dmac_np);
> + if (!dmac_pdev) {
> + pr_err("%s: unable to find pdev from DMA controller\n",
> + dmac_np->full_name);
> + ret = -EINVAL;
> + goto err1;
> + }
> +
> + atslave->dma_dev = &dmac_pdev->dev;
> + atslave->cfg = dma_spec.args[0];
> +
> +err1:
> + of_node_put(dma_spec.np);
> +err0:
> + pr_debug("%s exited with status %d\n", __func__, ret);
> + return ret;
> +}
> +
> static int of_get_atmel_spi_data(struct device_node *np, struct atmel_spi *as)
> {
> const __be32 *val;
> @@ -1540,7 +1591,9 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
> goto out_unmap_regs;
>
> if (as->data.has_dma_support) {
> - if (atmel_spi_configure_dma(as) == 0)
> + if ((at91_spi_of_init(pdev->dev.of_node,
> + &as->data.dma_slave) == 0)
> + && (atmel_spi_configure_dma(as) == 0))
> as->use_dma = true;
> } else if (as->data.has_pdc_support)
> as->use_pdc = true;
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/6] ARM: at91: add clocks for spi DT entries
2012-09-26 6:50 ` [PATCH 3/6] ARM: at91: add clocks for spi DT entries Wenyou Yang
@ 2012-09-26 8:32 ` Nicolas Ferre
0 siblings, 0 replies; 15+ messages in thread
From: Nicolas Ferre @ 2012-09-26 8:32 UTC (permalink / raw)
To: linux-arm-kernel
On 09/26/2012 08:50 AM, Wenyou Yang :
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> ---
> arch/arm/mach-at91/at91sam9260.c | 2 ++
> arch/arm/mach-at91/at91sam9g45.c | 2 ++
> arch/arm/mach-at91/at91sam9n12.c | 2 ++
> arch/arm/mach-at91/at91sam9x5.c | 3 +++
> 4 files changed, 9 insertions(+)
>
> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
> index 30c7f26..90d38a8 100644
> --- a/arch/arm/mach-at91/at91sam9260.c
> +++ b/arch/arm/mach-at91/at91sam9260.c
> @@ -227,6 +227,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
> CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
> CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
> CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
> + CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi0_clk),
> + CLKDEV_CON_DEV_ID("spi_clk", "fffac000.spi", &spi1_clk),
> /* fake hclk clock */
> CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
> CLKDEV_CON_ID("pioA", &pioA_clk),
> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
> index ef6cedd..9d0ec1c 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -254,6 +254,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
> CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
> CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
> CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
> + CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
> + CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
> /* fake hclk clock */
> CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
> CLKDEV_CON_ID("pioA", &pioA_clk),
> diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
> index 0849466..21b264b 100644
> --- a/arch/arm/mach-at91/at91sam9n12.c
> +++ b/arch/arm/mach-at91/at91sam9n12.c
> @@ -169,6 +169,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
> CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
> CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
> CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
> + CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
> + CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
> CLKDEV_CON_ID("pioA", &pioAB_clk),
> CLKDEV_CON_ID("pioB", &pioAB_clk),
> CLKDEV_CON_ID("pioC", &pioCD_clk),
> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> index 477cf9d..b6f3a92 100644
> --- a/arch/arm/mach-at91/at91sam9x5.c
> +++ b/arch/arm/mach-at91/at91sam9x5.c
> @@ -16,6 +16,7 @@
> #include <mach/at91_pmc.h>
> #include <mach/cpu.h>
> #include <mach/board.h>
> +#include <mach/gpio.h>
What is the purpose of this line in this patch?
>
> #include "soc.h"
> #include "generic.h"
> @@ -231,6 +232,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
> CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
> CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
> CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
> + CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
> + CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
> CLKDEV_CON_ID("pioA", &pioAB_clk),
> CLKDEV_CON_ID("pioB", &pioAB_clk),
> CLKDEV_CON_ID("pioC", &pioCD_clk),
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 0/6] atmel SoC SPI controller with DT
2012-09-26 6:50 [PATCH 0/6] atmel SoC SPI controller with DT Wenyou Yang
` (5 preceding siblings ...)
2012-09-26 6:51 ` [PATCH 6/6] spi: atmel: add dt property for DMA configuration for sam9x5 and sam9n12 Wenyou Yang
@ 2012-09-26 14:15 ` Jean-Christophe PLAGNIOL-VILLARD
6 siblings, 0 replies; 15+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-26 14:15 UTC (permalink / raw)
To: linux-arm-kernel
On 14:50 Wed 26 Sep , Wenyou Yang wrote:
> Hi,
>
> I merged the works from Nicolas, Richard, Jean-Christophe's patchset
> for atmel SPI controller.
NACK
your current patch series is based on Richard, Nicolas and I work which was
correctly splitted in patch per feature that your dropped
and you put yourself as author of other people work
with S.O.B where ther are not supposed to be
I'll not even bother to read the patch serie
Redo it correctly and resend it
Best Regards,
J.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/6] spi: atmel: add dmaengine and dt support
2012-09-26 7:05 ` Uwe Kleine-König
@ 2012-09-27 7:13 ` Richard Genoud
2012-09-27 7:39 ` Uwe Kleine-König
0 siblings, 1 reply; 15+ messages in thread
From: Richard Genoud @ 2012-09-27 7:13 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
2012/9/26 Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>:
> Hello,
>
> On Wed, Sep 26, 2012 at 02:50:57PM +0800, Wenyou Yang wrote:
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
>
> I don't remember ever having touched the spi-atmel driver, so I'm pretty
> sure I never gave my S-o-b for anything in this patch. Please reread
> Documentation/SubmittingPatches and double check you understood what
> Signed-off-by means before resubmitting this patch with all wrong
> S-o-b's removed.
By the way, what is the correct way to send a patch based on other's work ?
If I believe Documentation/SubmittingPatches, only the sender should
add his S-o-b.
But if you want to give credit to the original author(s), what's the best way ?
IMHO, I would CC them, let them add their
s-o-b/ack-b/nack-b/whatever-b if they want, and maybe add something
like that in the file header :
/*
* based on the original work of ...
*/
Or in the commit message itself
Is that right ?
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/6] spi: atmel: add dmaengine and dt support
2012-09-27 7:13 ` Richard Genoud
@ 2012-09-27 7:39 ` Uwe Kleine-König
2012-09-27 8:08 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 15+ messages in thread
From: Uwe Kleine-König @ 2012-09-27 7:39 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Sep 27, 2012 at 09:13:13AM +0200, Richard Genoud wrote:
> 2012/9/26 Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>:
> > Hello,
> >
> > On Wed, Sep 26, 2012 at 02:50:57PM +0800, Wenyou Yang wrote:
> >> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> >> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
> >
> > I don't remember ever having touched the spi-atmel driver, so I'm pretty
> > sure I never gave my S-o-b for anything in this patch. Please reread
> > Documentation/SubmittingPatches and double check you understood what
> > Signed-off-by means before resubmitting this patch with all wrong
> > S-o-b's removed.
>
> By the way, what is the correct way to send a patch based on other's work ?
> If I believe Documentation/SubmittingPatches, only the sender should
> add his S-o-b.
> But if you want to give credit to the original author(s), what's the best way ?
> IMHO, I would CC them, let them add their
> s-o-b/ack-b/nack-b/whatever-b if they want, and maybe add something
> like that in the file header :
> /*
> * based on the original work of ...
> */
> Or in the commit message itself
> Is that right ?
Yes. If you only did some trivia like rebasing to a new upstream version you
can additionally keep the original author as author.
Documentation/SubmittingPatches has some words about that, too. Grep for
"lucky at maintainer.example.org" to get the right paragraph.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/6] spi: atmel: add dmaengine and dt support
2012-09-27 7:39 ` Uwe Kleine-König
@ 2012-09-27 8:08 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-27 8:15 ` Gregory CLEMENT
0 siblings, 1 reply; 15+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-27 8:08 UTC (permalink / raw)
To: linux-arm-kernel
On 09:39 Thu 27 Sep , Uwe Kleine-K?nig wrote:
> On Thu, Sep 27, 2012 at 09:13:13AM +0200, Richard Genoud wrote:
> > 2012/9/26 Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>:
> > > Hello,
> > >
> > > On Wed, Sep 26, 2012 at 02:50:57PM +0800, Wenyou Yang wrote:
> > >> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> > >> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
> > >
> > > I don't remember ever having touched the spi-atmel driver, so I'm pretty
> > > sure I never gave my S-o-b for anything in this patch. Please reread
> > > Documentation/SubmittingPatches and double check you understood what
> > > Signed-off-by means before resubmitting this patch with all wrong
> > > S-o-b's removed.
> >
> > By the way, what is the correct way to send a patch based on other's work ?
> > If I believe Documentation/SubmittingPatches, only the sender should
> > add his S-o-b.
> > But if you want to give credit to the original author(s), what's the best way ?
> > IMHO, I would CC them, let them add their
> > s-o-b/ack-b/nack-b/whatever-b if they want, and maybe add something
> > like that in the file header :
> > /*
> > * based on the original work of ...
> > */
> > Or in the commit message itself
> > Is that right ?
> Yes. If you only did some trivia like rebasing to a new upstream version you
> can additionally keep the original author as author.
> Documentation/SubmittingPatches has some words about that, too. Grep for
> "lucky at maintainer.example.org" to get the right paragraph.
uasaully when we update a patch we do keeep the author and it's S.o.B and then
explain what we udapte + our own S.O.B
Best Regards,
J.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/6] spi: atmel: add dmaengine and dt support
2012-09-27 8:08 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-09-27 8:15 ` Gregory CLEMENT
0 siblings, 0 replies; 15+ messages in thread
From: Gregory CLEMENT @ 2012-09-27 8:15 UTC (permalink / raw)
To: linux-arm-kernel
2012/9/27 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>:
> On 09:39 Thu 27 Sep , Uwe Kleine-K?nig wrote:
>> On Thu, Sep 27, 2012 at 09:13:13AM +0200, Richard Genoud wrote:
>> > 2012/9/26 Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>:
>> > > Hello,
>> > >
>> > > On Wed, Sep 26, 2012 at 02:50:57PM +0800, Wenyou Yang wrote:
>> > >> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>> > >> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
>> > >
>> > > I don't remember ever having touched the spi-atmel driver, so I'm pretty
>> > > sure I never gave my S-o-b for anything in this patch. Please reread
>> > > Documentation/SubmittingPatches and double check you understood what
>> > > Signed-off-by means before resubmitting this patch with all wrong
>> > > S-o-b's removed.
>> >
>> > By the way, what is the correct way to send a patch based on other's work ?
>> > If I believe Documentation/SubmittingPatches, only the sender should
>> > add his S-o-b.
>> > But if you want to give credit to the original author(s), what's the best way ?
>> > IMHO, I would CC them, let them add their
>> > s-o-b/ack-b/nack-b/whatever-b if they want, and maybe add something
>> > like that in the file header :
>> > /*
>> > * based on the original work of ...
>> > */
>> > Or in the commit message itself
>> > Is that right ?
>> Yes. If you only did some trivia like rebasing to a new upstream version you
>> can additionally keep the original author as author.
>> Documentation/SubmittingPatches has some words about that, too. Grep for
>> "lucky at maintainer.example.org" to get the right paragraph.
> uasaully when we update a patch we do keeep the author and it's S.o.B and then
> explain what we udapte + our own S.O.B
>
Well with git you can only have one author.
> Best Regards,
> J.
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory CLEMENT
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2012-09-27 8:15 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-09-26 6:50 [PATCH 0/6] atmel SoC SPI controller with DT Wenyou Yang
2012-09-26 6:50 ` [PATCH 1/6] of_spi: add generic binding support to specify cs gpio Wenyou Yang
2012-09-26 6:50 ` [PATCH 2/6] spi: atmel: add dmaengine and dt support Wenyou Yang
2012-09-26 7:05 ` Uwe Kleine-König
2012-09-27 7:13 ` Richard Genoud
2012-09-27 7:39 ` Uwe Kleine-König
2012-09-27 8:08 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-27 8:15 ` Gregory CLEMENT
2012-09-26 6:50 ` [PATCH 3/6] ARM: at91: add clocks for spi DT entries Wenyou Yang
2012-09-26 8:32 ` Nicolas Ferre
2012-09-26 6:50 ` [PATCH 4/6] ARM: dts: add spi nodes for atmel SoCs Wenyou Yang
2012-09-26 6:51 ` [PATCH 5/6] ARM: dts: add spi nodes for atmel boards Wenyou Yang
2012-09-26 6:51 ` [PATCH 6/6] spi: atmel: add dt property for DMA configuration for sam9x5 and sam9n12 Wenyou Yang
2012-09-26 8:28 ` Nicolas Ferre
2012-09-26 14:15 ` [PATCH 0/6] atmel SoC SPI controller with DT Jean-Christophe PLAGNIOL-VILLARD
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