* [GIT PULL] ARM: cache flushing LoUIS API
@ 2012-09-25 12:57 Lorenzo Pieralisi
2012-09-27 11:48 ` Russell King - ARM Linux
0 siblings, 1 reply; 6+ messages in thread
From: Lorenzo Pieralisi @ 2012-09-25 12:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi Russell,
I know it is coming quite late in the cycle but please consider pulling
the patch series implementing the new cache maintenance LoUIS API, since
it provides a stepping stone to implementing power management on upcoming
A15 and A7 based platforms, leaving functionality for earlier processor
versions unchanged.
It has been tested on:
- OMAP4/5
# suspend/hotplug and CPU idle
- iMX6q
# suspend and hotplug
- TC2 big.LITTLE testchip
# CPU idle
Thanks,
Lorenzo
The following changes since commit 5698bd757d55b1bb87edd1a9744ab09c142abfc2:
Linux 3.6-rc6 (2012-09-16 14:58:51 -0700)
are available in the git repository at:
git://linux-arm.org/linux-2.6-lp.git cache-louis
for you to fetch changes up to 6323fa2256baa73d6a960ee57ec086b66aeecd0b:
ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API (2012-09-25 11:20:26 +0100)
----------------------------------------------------------------
Lorenzo Pieralisi (4):
ARM: mm: implement LoUIS API for cache maintenance ops
ARM: mm: rename jump labels in v7_flush_dcache_all function
ARM: kernel: update cpu_suspend code to use cache LoUIS operations
ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API
Santosh Shilimkar (1):
ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API
arch/arm/include/asm/cacheflush.h | 15 ++++++++++++
arch/arm/include/asm/glue-cache.h | 1 +
arch/arm/kernel/smp.c | 5 +++-
arch/arm/kernel/suspend.c | 17 +++++++++++++-
arch/arm/mm/cache-fa.S | 3 +++
arch/arm/mm/cache-v3.S | 3 +++
arch/arm/mm/cache-v4.S | 3 +++
arch/arm/mm/cache-v4wb.S | 3 +++
arch/arm/mm/cache-v4wt.S | 3 +++
arch/arm/mm/cache-v6.S | 3 +++
arch/arm/mm/cache-v7.S | 48 ++++++++++++++++++++++++++++++++++-----
arch/arm/mm/proc-arm1020.S | 3 +++
arch/arm/mm/proc-arm1020e.S | 3 +++
arch/arm/mm/proc-arm1022.S | 3 +++
arch/arm/mm/proc-arm1026.S | 3 +++
arch/arm/mm/proc-arm920.S | 3 +++
arch/arm/mm/proc-arm922.S | 3 +++
arch/arm/mm/proc-arm925.S | 3 +++
arch/arm/mm/proc-arm926.S | 3 +++
arch/arm/mm/proc-arm940.S | 3 +++
arch/arm/mm/proc-arm946.S | 3 +++
arch/arm/mm/proc-feroceon.S | 3 +++
arch/arm/mm/proc-macros.S | 1 +
arch/arm/mm/proc-mohawk.S | 3 +++
arch/arm/mm/proc-v7.S | 2 +-
arch/arm/mm/proc-xsc3.S | 3 +++
arch/arm/mm/proc-xscale.S | 3 +++
27 files changed, 140 insertions(+), 9 deletions(-)
^ permalink raw reply [flat|nested] 6+ messages in thread* [GIT PULL] ARM: cache flushing LoUIS API 2012-09-25 12:57 [GIT PULL] ARM: cache flushing LoUIS API Lorenzo Pieralisi @ 2012-09-27 11:48 ` Russell King - ARM Linux 2012-09-27 13:44 ` Lorenzo Pieralisi 2012-09-27 16:15 ` Lorenzo Pieralisi 0 siblings, 2 replies; 6+ messages in thread From: Russell King - ARM Linux @ 2012-09-27 11:48 UTC (permalink / raw) To: linux-arm-kernel On Tue, Sep 25, 2012 at 01:57:58PM +0100, Lorenzo Pieralisi wrote: > Hi Russell, > > I know it is coming quite late in the cycle but please consider pulling > the patch series implementing the new cache maintenance LoUIS API, since > it provides a stepping stone to implementing power management on upcoming > A15 and A7 based platforms, leaving functionality for earlier processor > versions unchanged. > > It has been tested on: > > - OMAP4/5 > # suspend/hotplug and CPU idle > - iMX6q > # suspend and hotplug > - TC2 big.LITTLE testchip > # CPU idle Ok, last night's PXA build regressed with this: arch/arm/mm/built-in.o: In function `xscale_dma_unmap_area': cache-xsc3l2.c:(.text+0x4194): undefined reference to `xscale_80200_A0_A1_flush_kern_cache_louis' That's because we missed that proc-xscale.S aliases a bunch of functions to xscale_80200_A0_A1_xxx from xscale_xxx. And looking at that, it seems that we also .type equivalent symbols - have you tested this on T2 builds to check whether it works correctly there? ^ permalink raw reply [flat|nested] 6+ messages in thread
* [GIT PULL] ARM: cache flushing LoUIS API 2012-09-27 11:48 ` Russell King - ARM Linux @ 2012-09-27 13:44 ` Lorenzo Pieralisi 2012-09-27 16:15 ` Lorenzo Pieralisi 1 sibling, 0 replies; 6+ messages in thread From: Lorenzo Pieralisi @ 2012-09-27 13:44 UTC (permalink / raw) To: linux-arm-kernel On Thu, Sep 27, 2012 at 12:48:05PM +0100, Russell King - ARM Linux wrote: > On Tue, Sep 25, 2012 at 01:57:58PM +0100, Lorenzo Pieralisi wrote: > > Hi Russell, > > > > I know it is coming quite late in the cycle but please consider pulling > > the patch series implementing the new cache maintenance LoUIS API, since > > it provides a stepping stone to implementing power management on upcoming > > A15 and A7 based platforms, leaving functionality for earlier processor > > versions unchanged. > > > > It has been tested on: > > > > - OMAP4/5 > > # suspend/hotplug and CPU idle > > - iMX6q > > # suspend and hotplug > > - TC2 big.LITTLE testchip > > # CPU idle > > Ok, last night's PXA build regressed with this: > > arch/arm/mm/built-in.o: In function `xscale_dma_unmap_area': > cache-xsc3l2.c:(.text+0x4194): undefined reference to `xscale_80200_A0_A1_flush_kern_cache_louis' > > That's because we missed that proc-xscale.S aliases a bunch of functions to > xscale_80200_A0_A1_xxx from xscale_xxx. And looking at that, it seems that > we also .type equivalent symbols - have you tested this on T2 builds to > check whether it works correctly there? Point taken for the regression, currently looking into that. I have not run tests on T2, I would be surprised if the set triggers any issue on T2 but I should have thought about that, my apologies. I will test it ASAP and get back to you, sorry again. Lorenzo ^ permalink raw reply [flat|nested] 6+ messages in thread
* [GIT PULL] ARM: cache flushing LoUIS API 2012-09-27 11:48 ` Russell King - ARM Linux 2012-09-27 13:44 ` Lorenzo Pieralisi @ 2012-09-27 16:15 ` Lorenzo Pieralisi 2012-09-27 22:27 ` Russell King - ARM Linux 2012-09-28 6:41 ` Shilimkar, Santosh 1 sibling, 2 replies; 6+ messages in thread From: Lorenzo Pieralisi @ 2012-09-27 16:15 UTC (permalink / raw) To: linux-arm-kernel [CC'ed Shawn to test T2 on iMX] On Thu, Sep 27, 2012 at 12:48:05PM +0100, Russell King - ARM Linux wrote: > On Tue, Sep 25, 2012 at 01:57:58PM +0100, Lorenzo Pieralisi wrote: > > Hi Russell, > > > > I know it is coming quite late in the cycle but please consider pulling > > the patch series implementing the new cache maintenance LoUIS API, since > > it provides a stepping stone to implementing power management on upcoming > > A15 and A7 based platforms, leaving functionality for earlier processor > > versions unchanged. > > > > It has been tested on: > > > > - OMAP4/5 > > # suspend/hotplug and CPU idle > > - iMX6q > > # suspend and hotplug > > - TC2 big.LITTLE testchip > > # CPU idle > > Ok, last night's PXA build regressed with this: > > arch/arm/mm/built-in.o: In function `xscale_dma_unmap_area': > cache-xsc3l2.c:(.text+0x4194): undefined reference to `xscale_80200_A0_A1_flush_kern_cache_louis' > > That's because we missed that proc-xscale.S aliases a bunch of functions to > xscale_80200_A0_A1_xxx from xscale_xxx. And looking at that, it seems that > we also .type equivalent symbols - have you tested this on T2 builds to > check whether it works correctly there? Tested T2 build on TC2 testchip and everything seems to be working fine. Santosh, Shawn, can you give T2 a go on OMAP and iMX6 please ? As for the xscale (and feroceon I think as well) regressions, I had a look and put together this patch, following the pattern in the respective .S files. It is true that we end up having a chain of equivalent symbols. Russell, Do you think it is sufficient/proper or you see other issues ? If it is ok I can fold it into the series and prepare a new pull request. Thanks a lot for your help and sorry again. Lorenzo -- >8 -- Subject: [PATCH] ARM: mm: fix cache LoUIS API for xscale and feroceon Some architectures like xscale and feroceon have cache API variants that map cache flushing functions as aliases to the base architecture. This patch adds the required aliases to complete the implementation of cache flushing LoUIS API. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> --- arch/arm/mm/proc-feroceon.S | 1 + arch/arm/mm/proc-xscale.S | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 85e5e3b..4106b09 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -434,6 +434,7 @@ ENDPROC(feroceon_dma_unmap_area) range_alias flush_icache_all range_alias flush_user_cache_all range_alias flush_kern_cache_all + range_alias flush_kern_cache_louis range_alias flush_user_cache_range range_alias coherent_kern_range range_alias coherent_user_range diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index b5ea31d..2551036 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -442,6 +442,7 @@ ENDPROC(xscale_dma_unmap_area) a0_alias flush_icache_all a0_alias flush_user_cache_all a0_alias flush_kern_cache_all + a0_alias flush_kern_cache_louis a0_alias flush_user_cache_range a0_alias coherent_kern_range a0_alias coherent_user_range -- 1.7.12 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [GIT PULL] ARM: cache flushing LoUIS API 2012-09-27 16:15 ` Lorenzo Pieralisi @ 2012-09-27 22:27 ` Russell King - ARM Linux 2012-09-28 6:41 ` Shilimkar, Santosh 1 sibling, 0 replies; 6+ messages in thread From: Russell King - ARM Linux @ 2012-09-27 22:27 UTC (permalink / raw) To: linux-arm-kernel On Thu, Sep 27, 2012 at 05:15:52PM +0100, Lorenzo Pieralisi wrote: > Russell, > > Do you think it is sufficient/proper or you see other issues ? > > If it is ok I can fold it into the series and prepare a new pull request. Looks fine to me. > > Thanks a lot for your help and sorry again. > Lorenzo > > -- >8 -- > Subject: [PATCH] ARM: mm: fix cache LoUIS API for xscale and feroceon > > Some architectures like xscale and feroceon have cache API variants that > map cache flushing functions as aliases to the base architecture. > This patch adds the required aliases to complete the implementation of > cache flushing LoUIS API. > > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> > --- > arch/arm/mm/proc-feroceon.S | 1 + > arch/arm/mm/proc-xscale.S | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S > index 85e5e3b..4106b09 100644 > --- a/arch/arm/mm/proc-feroceon.S > +++ b/arch/arm/mm/proc-feroceon.S > @@ -434,6 +434,7 @@ ENDPROC(feroceon_dma_unmap_area) > range_alias flush_icache_all > range_alias flush_user_cache_all > range_alias flush_kern_cache_all > + range_alias flush_kern_cache_louis > range_alias flush_user_cache_range > range_alias coherent_kern_range > range_alias coherent_user_range > diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S > index b5ea31d..2551036 100644 > --- a/arch/arm/mm/proc-xscale.S > +++ b/arch/arm/mm/proc-xscale.S > @@ -442,6 +442,7 @@ ENDPROC(xscale_dma_unmap_area) > a0_alias flush_icache_all > a0_alias flush_user_cache_all > a0_alias flush_kern_cache_all > + a0_alias flush_kern_cache_louis > a0_alias flush_user_cache_range > a0_alias coherent_kern_range > a0_alias coherent_user_range > -- > 1.7.12 > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [GIT PULL] ARM: cache flushing LoUIS API 2012-09-27 16:15 ` Lorenzo Pieralisi 2012-09-27 22:27 ` Russell King - ARM Linux @ 2012-09-28 6:41 ` Shilimkar, Santosh 1 sibling, 0 replies; 6+ messages in thread From: Shilimkar, Santosh @ 2012-09-28 6:41 UTC (permalink / raw) To: linux-arm-kernel Lorenzo, On Thu, Sep 27, 2012 at 9:45 PM, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote: > [CC'ed Shawn to test T2 on iMX] > > On Thu, Sep 27, 2012 at 12:48:05PM +0100, Russell King - ARM Linux wrote: >> On Tue, Sep 25, 2012 at 01:57:58PM +0100, Lorenzo Pieralisi wrote: >> > Hi Russell, >> > >> > I know it is coming quite late in the cycle but please consider pulling >> > the patch series implementing the new cache maintenance LoUIS API, since >> > it provides a stepping stone to implementing power management on upcoming >> > A15 and A7 based platforms, leaving functionality for earlier processor >> > versions unchanged. >> > >> > It has been tested on: >> > >> > - OMAP4/5 >> > # suspend/hotplug and CPU idle >> > - iMX6q >> > # suspend and hotplug >> > - TC2 big.LITTLE testchip >> > # CPU idle >> >> Ok, last night's PXA build regressed with this: >> >> arch/arm/mm/built-in.o: In function `xscale_dma_unmap_area': >> cache-xsc3l2.c:(.text+0x4194): undefined reference to `xscale_80200_A0_A1_flush_kern_cache_louis' >> >> That's because we missed that proc-xscale.S aliases a bunch of functions to >> xscale_80200_A0_A1_xxx from xscale_xxx. And looking at that, it seems that >> we also .type equivalent symbols - have you tested this on T2 builds to >> check whether it works correctly there? > > Tested T2 build on TC2 testchip and everything seems to be working fine. > > Santosh, Shawn, can you give T2 a go on OMAP and iMX6 please ? > Tested OMAP4/5 with T2 build and CPU power tests continue to work. All good. Note that for T2 build I need to take out OMAP2 devices from the build which are based of ARM_v6. Regards Santosh ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-09-28 6:41 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2012-09-25 12:57 [GIT PULL] ARM: cache flushing LoUIS API Lorenzo Pieralisi 2012-09-27 11:48 ` Russell King - ARM Linux 2012-09-27 13:44 ` Lorenzo Pieralisi 2012-09-27 16:15 ` Lorenzo Pieralisi 2012-09-27 22:27 ` Russell King - ARM Linux 2012-09-28 6:41 ` Shilimkar, Santosh
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