From: dave.martin@linaro.org (Dave Martin)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 RESEND 2/2] ARM: local timers: add timer support using IO mapped register
Date: Tue, 2 Oct 2012 16:03:33 +0100 [thread overview]
Message-ID: <20121002150333.GC2108@linaro.org> (raw)
In-Reply-To: <20121002134444.GB28600@e102568-lin.cambridge.arm.com>
On Tue, Oct 02, 2012 at 02:44:44PM +0100, Lorenzo Pieralisi wrote:
> On Tue, Oct 02, 2012 at 12:27:04PM +0100, Dave Martin wrote:
> > On Fri, Sep 28, 2012 at 06:15:53PM +0100, Lorenzo Pieralisi wrote:
> > > On Fri, Sep 28, 2012 at 04:57:46PM +0100, Dave Martin wrote:
>
> [...]
>
> > > There must be a common way for all devices to link to the topology, though.
> > >
> > > The topology must be descriptive enough to cater for all required cases
> > > and that's what Mark with PMU and all of us are trying to come up with, a solid
> > > way to represent with DT the topology of current and future ARM systems.
> > >
> > > First idea I implemented and related LAK posting:
> > >
> > > http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/080873.html
> > >
> > > Are "cluster" nodes really needed or "cpu" nodes are enough ? I do not
> > > know, let's get this discussion started, that's all I need.
> >
> > One thing which now occurs to me on this point it that if we want to describe
> > the CCI properly in the DT (yes) then we need a way to describe the mapping
> > between clusters and CCI slave ports. Currently that knowledge just has to
> > be a hard-coded hack somewhere: it's not probeable at all.
>
> That's definitely a good point. We can still define CCI ports as belonging
> to a range of CPUs, but that's a bit of a stretch IMHO.
>
> > I'm not sure how we do that, or how we describe the cache topology, without
> > the clusters being explicit in the DT
> >
> > ...unless you already have ideas ?
>
> Either we define the cluster node explicitly or we can always see it as a
> collection of CPUs, ie phandles to "cpu" nodes. That's what the decision
> we have to make is all about. I think that describing it explicitly make
> sense, but we need to check all possible use cases to see if that's
> worthwhile.
How is the cache topology described today (forgive my laziness in not
answering this question for myself)? The issues are somewhat similar.
I still have some misgivings about describing clusters in terms of sets of
CPUs. For example, when we boot up a cluster, we have to set up ... the
cluster. This is a distinct thing which we must set up in addition to
any of the actual CPUs.
There is a strict child/parent relationship between clusters and CPUs, so
a tree of nodes does seem the most natural description ... but I'm not
aware of all the background to this discussion.
Cheers
---Dave
next prev parent reply other threads:[~2012-10-02 15:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-15 7:41 [PATCH v2 RESEND 1/2] ARM: arch timer: Set the TVAL before timer is enabled Rohit Vaswani
2012-09-15 7:41 ` [PATCH v2 RESEND 2/2] ARM: local timers: add timer support using IO mapped register Rohit Vaswani
2012-09-25 19:08 ` Rohit Vaswani
2012-09-27 15:46 ` Marc Zyngier
2012-09-28 12:28 ` Mark Rutland
2012-09-28 15:57 ` Dave Martin
2012-09-28 17:15 ` Lorenzo Pieralisi
2012-10-02 11:27 ` Dave Martin
2012-10-02 13:44 ` Lorenzo Pieralisi
2012-10-02 15:03 ` Dave Martin [this message]
2012-09-15 17:00 ` [PATCH v2 RESEND 1/2] ARM: arch timer: Set the TVAL before timer is enabled David Brown
2012-09-15 19:53 ` Rohit Vaswani
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