[PATCH V5] Add support for Aurora L2 Cache Controller

[PATCH V5] Add support for Aurora L2 Cache Controller

[Gregory CLEMENT]

Hello,

This a the 5th version of the patch set (the sixth if we include the
RFC). This last series add the ultimate change asked by Russell after
his review. See the end of this email for the changelog.

The purpose of this patch set is to add support for Aurora L2 Cache
Controller used by Armada 370 and Armada XP SoCs. As it was initially
designed by Marvell engineer to be compatible with the ARM L2 Cache
Controller, we chose to reuse the existing code and to just extend it
to support the differences and improvements brought by the Aurora
controller.The diffstat looks like:

 Documentation/devicetree/bindings/arm/l2cc.txt |    9 +
 arch/arm/boot/dts/armada-370.dtsi              |    6 +
 arch/arm/boot/dts/armada-xp.dtsi               |    7 +
 arch/arm/include/asm/hardware/cache-l2x0.h     |    5 +
 arch/arm/mach-mvebu/Kconfig                    |    1 +
 arch/arm/mach-mvebu/irq-armada-370-xp.c        |    4 +
 arch/arm/mm/cache-aurora-l2.h                  |   55 +++++
 arch/arm/mm/cache-l2x0.c                       |  277 +++++++++++++++++++++---
 8 files changed, 336 insertions(+), 28 deletions(-)

The main differences and improvements are:

- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller 'outer cache' and 'system cache' (the
  last one meaning maintenance operations on L1 are broadcasted to the
  L2 and L2 performs the same operation).
- in outer cache mode, the cache maintenance operations are improved
  and can be done on a range inside a page and are not limited to a
  cache line.
- during resume the controller need to restore the ctrl register.

The first patch adds some modifications in the driver
infrastructure. As most of the outer cache functions can use the
Aurora improvements, we had to introduce new functions. So we thought
it was better to use a outer_cache_fns field inside l2x0_of_data and
just memcopy it into outer_cache depending of the type of the l2x0
cache.

Changelog:
V4 -> V5:
- Rebased L2 pach set onto v3.6-rc7.
- The header file cache-aurora-l2.h was co-located with its only user:
  moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
- Removed additional unnecessary blank lines in cache-l2x0.c.

V3 -> V4:
- Rebased L2 pach set onto v3.6-rc6.
- The assignment of outer_cache in l2x0_init, don't depend of
  CONFIG_OF but of variable. The value of this boolean variable is
  changed in l2x0_of_init. Then, if a system enable CONFIG_OF don't
  supply a DT file, relying on the old way to initialize the L2 cache,
  the assignment won't be disable.
- Removed unnecessary check in calc_range_end(). The alignment tested
  was already made before calling this function.

V2 -> V3:
- Use define instead of literal value for AURORA_CTRL_FW,
  AURORA_WAY_SIZE_SHIFT, L2X0_WAY_SIZE_SHIFT and L2X0_CTRL_EN.
- Used ALIGN, IS_ALUGNED and PAGE_ALIGN macro instead of bitwise
  operation.
- Calculate the number of way for Aurora instead of using a switch
  case.
- removed inaccurate BUG() call and replaced them by a pr_warn if
  needed.
- In aurora_inv_range round the start and end addresses to cache line
  size. The initial code was supposed to invalidate partial line cache
  but actually invalidate the full line, so there was no point to do
  it outside the aurora_pa_range call.
- Removed the dsb call in the aurora_*_range function: the
  cache_sync() call inside aurora_pa_range() is enough.
- And as usual tested on Armada 370 and Armada XP boards and ran
  benchmark without seeing any regression. Results are updated on the
  wiki page.

V1 -> V2:
- Rebased L2 pach set onto v3.6-rc4.
- Changed the compatible names to be more explicit, from
  aurora-cache-with-outer to aurora-outer-cache , and from
  aurora-cache-without-outer to aurora-system-cache.
- Add an isb() after the call to mcr in aurora_broadcast_l2_commands().
- Added the tested and reviewed-by from Lior Amsalem and Yehuda
  Yitschak.
- Tested on Armada 370 and Armada XP boards and ran benchmark without
  seeing any regression.

RFC -> V1:
- Rebased the series on to V3.6-rc3
- Added missing Signed-off-by
- Corrected a compilation warning that I have missed
- Ran benchmarks without seeing any regression

Benchmarks results are visible here:
https://github.com/MISL-EBU-System-SW/mainline-public/wiki/Non-official-cache-bench-results-on-the-mainline-Linux-port-%28-kernels-3.6-rcX%29-of-Armada-XP-and-Armada-370

The git branch aurora-L2-cache-ctrl is visible at
https://github.com/MISL-EBU-System-SW/mainline-public.git

Regards,

Gregory

[PATCH V5 1/6] arm: cache-l2x0: make outer_cache_fns a field of l2x0_of_data

[Gregory CLEMENT]

Instead of having multiple functions belonging to outer_cache and
filling this structure on the fly, use a outer_cache_fns field inside
l2x0_of_data and just memcopy it into outer_cache depending of the
type of the l2x0 cache. For non DT case, the former code was kept.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-and-reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>

Cc: Barry Song <21cnbao@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/mm/cache-l2x0.c |   55 +++++++++++++++++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2a8e380..8b9c0ae 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -39,8 +39,9 @@ struct l2x0_regs l2x0_saved_regs;
 struct l2x0_of_data {
 	void (*setup)(const struct device_node *, u32 *, u32 *);
 	void (*save)(void);
-	void (*resume)(void);
+	struct outer_cache_fns outer_cache;
 };
+static bool of_init = false;
 
 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
 {
@@ -376,13 +377,15 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		writel_relaxed(1, l2x0_base + L2X0_CTRL);
 	}
 
-	outer_cache.inv_range = l2x0_inv_range;
-	outer_cache.clean_range = l2x0_clean_range;
-	outer_cache.flush_range = l2x0_flush_range;
-	outer_cache.sync = l2x0_cache_sync;
-	outer_cache.flush_all = l2x0_flush_all;
-	outer_cache.inv_all = l2x0_inv_all;
-	outer_cache.disable = l2x0_disable;
+	if (!of_init) {
+		outer_cache.inv_range = l2x0_inv_range;
+		outer_cache.clean_range = l2x0_clean_range;
+		outer_cache.flush_range = l2x0_flush_range;
+		outer_cache.sync = l2x0_cache_sync;
+		outer_cache.flush_all = l2x0_flush_all;
+		outer_cache.inv_all = l2x0_inv_all;
+		outer_cache.disable = l2x0_disable;
+	}
 
 	printk(KERN_INFO "%s cache controller enabled\n", type);
 	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
@@ -533,15 +536,34 @@ static void pl310_resume(void)
 }
 
 static const struct l2x0_of_data pl310_data = {
-	pl310_of_setup,
-	pl310_save,
-	pl310_resume,
+	.setup = pl310_of_setup,
+	.save  = pl310_save,
+	.outer_cache = {
+		.resume      = pl310_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+		.set_debug   = pl310_set_debug,
+	},
 };
 
 static const struct l2x0_of_data l2x0_data = {
-	l2x0_of_setup,
-	NULL,
-	l2x0_resume,
+	.setup = l2x0_of_setup,
+	.save  = NULL,
+	.outer_cache = {
+		.resume      = l2x0_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
 };
 
 static const struct of_device_id l2x0_ids[] __initconst = {
@@ -581,9 +603,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	if (data->save)
 		data->save();
 
+	/* */
+	of_init = true;
 	l2x0_init(l2x0_base, aux_val, aux_mask);
 
-	outer_cache.resume = data->resume;
+	memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
+
 	return 0;
 }
 #endif
-- 
1.7.9.5

[PATCH V5 2/6] arm: cache-l2x0: add an optional register to save/restore

[Gregory CLEMENT]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-and-reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>

Cc: Barry Song <21cnbao@gmail.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 arch/arm/include/asm/hardware/cache-l2x0.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index c4c87bc..5f2c7b4 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -126,6 +126,7 @@ struct l2x0_regs {
 	unsigned long filter_end;
 	unsigned long prefetch_ctrl;
 	unsigned long pwr_ctrl;
+	unsigned long ctrl;
 };
 
 extern struct l2x0_regs l2x0_saved_regs;
-- 
1.7.9.5

[PATCH V5 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
as:
- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
  maintenance operations on L1 are broadcasted to the L2 and L2
  performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
  can be done on a range inside a page and are not limited to a cache
  line.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>

Cc: Barry Song <21cnbao@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 arch/arm/include/asm/hardware/cache-l2x0.h |    4 +
 arch/arm/mm/cache-aurora-l2.h              |   55 +++++++
 arch/arm/mm/cache-l2x0.c                   |  222 ++++++++++++++++++++++++++--
 3 files changed, 268 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mm/cache-aurora-l2.h

diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 5f2c7b4..3b2c40b 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -102,6 +102,10 @@
 
 #define L2X0_ADDR_FILTER_EN		1
 
+#define L2X0_CTRL_EN			1
+
+#define L2X0_WAY_SIZE_SHIFT		3
+
 #ifndef __ASSEMBLY__
 extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
 #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
diff --git a/arch/arm/mm/cache-aurora-l2.h b/arch/arm/mm/cache-aurora-l2.h
new file mode 100644
index 0000000..c861247
--- /dev/null
+++ b/arch/arm/mm/cache-aurora-l2.h
@@ -0,0 +1,55 @@
+/*
+ * AURORA shared L2 cache controller support
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
+#define __ASM_ARM_HARDWARE_AURORA_L2_H
+
+#define AURORA_SYNC_REG		    0x700
+#define AURORA_RANGE_BASE_ADDR_REG  0x720
+#define AURORA_FLUSH_PHY_ADDR_REG   0x7f0
+#define AURORA_INVAL_RANGE_REG	    0x774
+#define AURORA_CLEAN_RANGE_REG	    0x7b4
+#define AURORA_FLUSH_RANGE_REG	    0x7f4
+
+#define AURORA_ACR_REPLACEMENT_OFFSET	    27
+#define AURORA_ACR_REPLACEMENT_MASK	     \
+	(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR    \
+	(0 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_LFSR     \
+	(1 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
+	(3 << AURORA_ACR_REPLACEMENT_OFFSET)
+
+#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET	0
+#define AURORA_ACR_FORCE_WRITE_POLICY_MASK	\
+	(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_POLICY_DIS	\
+	(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_BACK_POLICY	\
+	(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_THRO_POLICY	\
+	(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+
+#define MAX_RANGE_SIZE		1024
+
+#define AURORA_WAY_SIZE_SHIFT	2
+
+#define AURORA_CTRL_FW		0x100
+
+/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
+ * the distinction between a number coming from hardware and a number
+ * coming from the device tree */
+#define AURORA_CACHE_ID	       0x100
+
+#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 8b9c0ae..612a102 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,6 +25,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "cache-aurora-l2.h"
 
 #define CACHE_LINE_SIZE		32
 
@@ -33,6 +34,11 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
+static int l2_wt_override;
+
+/* Aurora don't have the cache ID register available, so we have to
+ * pass it though the device tree */
+static u32  cache_id_part_number_from_dt;
 
 struct l2x0_regs l2x0_saved_regs;
 
@@ -169,7 +175,7 @@ static void l2x0_inv_all(void)
 	/* invalidate all ways */
 	raw_spin_lock_irqsave(&l2x0_lock, flags);
 	/* Invalidating when L2 is enabled is a nono */
-	BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
+	BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
 	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
 	cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
 	cache_sync();
@@ -277,6 +283,98 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
+/*
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive, while the hardware cache range operations use
+ * inclusive start and end addresses.
+ */
+static unsigned long calc_range_end(unsigned long start, unsigned long end)
+{
+	/*
+	 * Limit the number of cache lines processed at once,
+	 * since cache range operations stall the CPU pipeline
+	 * until completion.
+	 */
+	if (end > start + MAX_RANGE_SIZE)
+		end = start + MAX_RANGE_SIZE;
+
+	/*
+	 * Cache range operations can't straddle a page boundary.
+	 */
+	if (end > PAGE_ALIGN(start+1))
+		end = PAGE_ALIGN(start+1);
+
+	return end;
+}
+
+/*
+ * Make sure 'start' and 'end' reference the same page, as L2 is PIPT
+ * and range operations only do a TLB lookup on the start address.
+ */
+static void aurora_pa_range(unsigned long start, unsigned long end,
+			unsigned long offset)
+{
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&l2x0_lock, flags);
+	writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+	writel(end, l2x0_base + offset);
+	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+
+	cache_sync();
+}
+
+static void aurora_inv_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * round start and end adresses up to cache line size
+	 */
+	start &= ~(CACHE_LINE_SIZE - 1);
+	end = ALIGN(end, CACHE_LINE_SIZE);
+
+	/*
+	 * Invalidate all full cache lines between 'start' and 'end'.
+	 */
+	while (start < end) {
+		unsigned long range_end = calc_range_end(start, end);
+		aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+				AURORA_INVAL_RANGE_REG);
+		start = range_end;
+	}
+}
+
+static void aurora_clean_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * If L2 is forced to WT, the L2 will always be clean and we
+	 * don't need to do anything here.
+	 */
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = ALIGN(end, CACHE_LINE_SIZE);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_CLEAN_RANGE_REG);
+			start = range_end;
+		}
+	}
+}
+
+static void aurora_flush_range(unsigned long start, unsigned long end)
+{
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = ALIGN(end, CACHE_LINE_SIZE);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_FLUSH_RANGE_REG);
+			start = range_end;
+		}
+	}
+}
+
 static void l2x0_disable(void)
 {
 	unsigned long flags;
@@ -293,11 +391,18 @@ static void l2x0_unlock(u32 cache_id)
 	int lockregs;
 	int i;
 
-	if (cache_id == L2X0_CACHE_ID_PART_L310)
+	switch (cache_id) {
+	case L2X0_CACHE_ID_PART_L310:
 		lockregs = 8;
-	else
+		break;
+	case AURORA_CACHE_ID:
+		lockregs = 4;
+		break;
+	default:
 		/* L210 and unknown types */
 		lockregs = 1;
+		break;
+	}
 
 	for (i = 0; i < lockregs; i++) {
 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
@@ -313,18 +418,22 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	u32 cache_id;
 	u32 way_size = 0;
 	int ways;
+	int way_size_shift = L2X0_WAY_SIZE_SHIFT;
 	const char *type;
 
 	l2x0_base = base;
-
-	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+	if (cache_id_part_number_from_dt)
+		cache_id = cache_id_part_number_from_dt;
+	else
+		cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
+			& L2X0_CACHE_ID_PART_MASK;
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
 	aux &= aux_mask;
 	aux |= aux_val;
 
 	/* Determine the number of ways */
-	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+	switch (cache_id) {
 	case L2X0_CACHE_ID_PART_L310:
 		if (aux & (1 << 16))
 			ways = 16;
@@ -341,6 +450,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		ways = (aux >> 13) & 0xf;
 		type = "L210";
 		break;
+
+	case AURORA_CACHE_ID:
+		sync_reg_offset = AURORA_SYNC_REG;
+		ways = (aux >> 13) & 0xf;
+		ways = 2 << ((ways + 1) >> 2);
+		way_size_shift = AURORA_WAY_SIZE_SHIFT;
+		type = "Aurora";
+		break;
 	default:
 		/* Assume unknown chips have 8 ways */
 		ways = 8;
@@ -354,7 +471,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	 * L2 cache Size =  Way size * Number of ways
 	 */
 	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
-	way_size = 1 << (way_size + 3);
+	way_size = 1 << (way_size + way_size_shift);
+
 	l2x0_size = ways * way_size * SZ_1K;
 
 	/*
@@ -362,7 +480,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	 * If you are booting from non-secure mode
 	 * accessing the below registers will fault.
 	 */
-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		/* Make sure that I&D is not locked down when starting */
 		l2x0_unlock(cache_id);
 
@@ -374,7 +492,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		l2x0_inv_all();
 
 		/* enable L2X0 */
-		writel_relaxed(1, l2x0_base + L2X0_CTRL);
+		writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
 	}
 
 	if (!of_init) {
@@ -490,9 +608,15 @@ static void __init pl310_save(void)
 	}
 }
 
+static void aurora_save(void)
+{
+	l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
+	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+}
+
 static void l2x0_resume(void)
 {
-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		/* restore aux ctrl and enable l2 */
 		l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
 
@@ -501,7 +625,7 @@ static void l2x0_resume(void)
 
 		l2x0_inv_all();
 
-		writel_relaxed(1, l2x0_base + L2X0_CTRL);
+		writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
 	}
 }
 
@@ -509,7 +633,7 @@ static void pl310_resume(void)
 {
 	u32 l2x0_revision;
 
-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		/* restore pl310 setup */
 		writel_relaxed(l2x0_saved_regs.tag_latency,
 			l2x0_base + L2X0_TAG_LATENCY_CTRL);
@@ -535,6 +659,46 @@ static void pl310_resume(void)
 	l2x0_resume();
 }
 
+static void aurora_resume(void)
+{
+	if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+		writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
+		writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+	}
+}
+
+static void __init aurora_broadcast_l2_commands(void)
+{
+	__u32 u;
+	/* Enable Broadcasting of cache commands to L2*/
+	__asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
+	u |= AURORA_CTRL_FW;		/* Set the FW bit */
+	__asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
+	isb();
+}
+
+static void __init aurora_of_setup(const struct device_node *np,
+				u32 *aux_val, u32 *aux_mask)
+{
+	u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
+	u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
+
+	of_property_read_u32(np, "cache-id-part",
+			&cache_id_part_number_from_dt);
+
+	/* Determine and save the write policy */
+	l2_wt_override = of_property_read_bool(np, "wt-override");
+
+	if (l2_wt_override) {
+		val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
+		mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
+	}
+
+	*aux_val &= ~mask;
+	*aux_val |= val;
+	*aux_mask &= ~mask;
+}
+
 static const struct l2x0_of_data pl310_data = {
 	.setup = pl310_of_setup,
 	.save  = pl310_save,
@@ -566,10 +730,37 @@ static const struct l2x0_of_data l2x0_data = {
 	},
 };
 
+static const struct l2x0_of_data aurora_with_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+		.inv_range   = aurora_inv_range,
+		.clean_range = aurora_clean_range,
+		.flush_range = aurora_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
+};
+
+static const struct l2x0_of_data aurora_no_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+	},
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
 	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+	{ .compatible = "marvell,aurora-system-cache",
+	  .data = (void *)&aurora_no_outer_data},
+	{ .compatible = "marvell,aurora-outer-cache",
+	  .data = (void *)&aurora_with_outer_data},
 	{}
 };
 
@@ -595,9 +786,14 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	data = of_match_node(l2x0_ids, np)->data;
 
 	/* L2 configuration can only be changed if the cache is disabled */
-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		if (data->setup)
 			data->setup(np, &aux_val, &aux_mask);
+
+		/* For aurora cache in no outer mode select the
+		 * correct mode using the coprocessor*/
+		if (data == &aurora_no_outer_data)
+			aurora_broadcast_l2_commands();
 	}
 
 	if (data->save)
-- 
1.7.9.5

[PATCH V5 4/6] arm: mvebu: add L2 cache support

[Gregory CLEMENT]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-and-reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 arch/arm/mach-mvebu/Kconfig             |    1 +
 arch/arm/mach-mvebu/irq-armada-370-xp.c |    4 ++++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index caa2c5e..e20c5e9 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -6,6 +6,7 @@ config MACH_ARMADA_370_XP
 	bool "Marvell Armada 370 and Aramada XP boards"
 	select ARMADA_370_XP_TIMER
 	select CPU_V7
+	select CACHE_L2X0
 	help
 
 	  Say 'Y' here if you want your kernel to support boards based on
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 5f5f939..570be84 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -24,6 +24,7 @@
 #include <linux/irqdomain.h>
 #include <asm/mach/arch.h>
 #include <asm/exception.h>
+#include <asm/hardware/cache-l2x0.h>
 
 /* Interrupt Controller Registers Map */
 #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
@@ -130,4 +131,7 @@ static const struct of_device_id mpic_of_match[] __initconst = {
 void __init armada_370_xp_init_irq(void)
 {
 	of_irq_init(mpic_of_match);
+#ifdef CONFIG_CACHE_L2X0
+	l2x0_of_init(0, ~0UL);
+#endif
 }
-- 
1.7.9.5

[PATCH V5 5/6] arm: mvebu: add Aurora L2 Cache Controller to the DT

[Gregory CLEMENT]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 arch/arm/boot/dts/armada-370.dtsi |    6 ++++++
 arch/arm/boot/dts/armada-xp.dtsi  |    7 +++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc..fa60478 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -20,6 +20,12 @@
 / {
 	model = "Marvell Armada 370 family SoC";
 	compatible = "marvell,armada370", "marvell,armada-370-xp";
+	L2: l2-cache {
+		compatible = "marvell,aurora-outer-cache";
+		reg = <0xd0008000 0x1000>;
+		cache-id-part = <0x100>;
+		wt-override;
+	};
 
 	mpic: interrupt-controller at d0020000 {
 	      reg = <0xd0020a00 0x1d0>,
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 71d6b5d..0186f62 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,6 +22,13 @@
 	model = "Marvell Armada XP family SoC";
 	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
+	L2: l2-cache {
+		compatible = "marvell,aurora-system-cache";
+		reg = <0xd0008000 0x1000>;
+		cache-id-part = <0x100>;
+		wt-override;
+	};
+
 	mpic: interrupt-controller at d0020000 {
 	      reg = <0xd0020a00 0x1d0>,
 		    <0xd0021870 0x58>;
-- 
1.7.9.5

[PATCH V5 6/6] arm: l2x0: add aurora related properties to OF binding

[Gregory CLEMENT]

Aurora is a L2 Cache Controller designed to be compatible with the
L2x0 Cache Controller. L2X0 OF bindings are extended to support some
specificity of Aurora (no cache id part number available through
hardware, always write through mode, choice between outer cache and
system cache).

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Barry Song <21cnbao@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 Documentation/devicetree/bindings/arm/l2cc.txt |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index 7ca5216..76b0ee6 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -10,6 +10,12 @@ Required properties:
 	"arm,pl310-cache"
 	"arm,l220-cache"
 	"arm,l210-cache"
+	"marvell,aurora-system-cache": Marvell Controller designed to be
+     compatible with the ARM one, with system cache mode (meaning
+     maintenance operations on L1 are broadcasted to the L2 and L2
+     performs the same operation).
+	"marvell,"aurora-outer-cache: Marvell Controller designed to be
+	 compatible with the ARM one with outer cache mode.
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
@@ -29,6 +35,9 @@ Optional properties:
   filter. Addresses in the filter window are directed to the M1 port. Other
   addresses will go to the M0 port.
 - interrupts : 1 combined interrupt.
+- cache-id-part: cache id part number to be used if it is not present
+  on hardware
+- wt-override: If present then L2 is forced to Write through mode
 
 Example:
 
-- 
1.7.9.5

[PATCH V5] Add support for Aurora L2 Cache Controller

[Gregory CLEMENT]

> Changelog:
> V4 -> V5:
> - Rebased L2 pach set onto v3.6-rc7.
> - The header file cache-aurora-l2.h was co-located with its only user:
>   moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
> - Removed additional unnecessary blank lines in cache-l2x0.c.
> 
Russell,

will you take the all series from the git repository ? As the
last patches have been already acked-by Arnd and were initially pulled
by Jason Cooper, I think there should be no problem to get the whole
series.

Now if you only want to take the first three patches, will you pull
them from the git repository or do you prefer that I submit them
through your patch system?

Thanks,

Gregory

> 
> The git branch aurora-L2-cache-ctrl is visible at
> https://github.com/MISL-EBU-System-SW/mainline-public.git

[PATCH V5 1/6] arm: cache-l2x0: make outer_cache_fns a field of l2x0_of_data

[Jason Cooper]

On Wed, Sep 26, 2012 at 06:02:45PM +0200, Gregory CLEMENT wrote:
> Instead of having multiple functions belonging to outer_cache and
> filling this structure on the fly, use a outer_cache_fns field inside
> l2x0_of_data and just memcopy it into outer_cache depending of the
> type of the l2x0 cache. For non DT case, the former code was kept.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Tested-and-reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
> Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>
> 
> Cc: Barry Song <21cnbao@gmail.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Olof Johansson <olof@lixom.net>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>  arch/arm/mm/cache-l2x0.c |   55 +++++++++++++++++++++++++++++++++-------------
>  1 file changed, 40 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 2a8e380..8b9c0ae 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -39,8 +39,9 @@ struct l2x0_regs l2x0_saved_regs;
>  struct l2x0_of_data {
>  	void (*setup)(const struct device_node *, u32 *, u32 *);
>  	void (*save)(void);
> -	void (*resume)(void);
> +	struct outer_cache_fns outer_cache;
>  };
> +static bool of_init = false;
>  
>  static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
>  {
> @@ -376,13 +377,15 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
>  		writel_relaxed(1, l2x0_base + L2X0_CTRL);
>  	}
>  
> -	outer_cache.inv_range = l2x0_inv_range;
> -	outer_cache.clean_range = l2x0_clean_range;
> -	outer_cache.flush_range = l2x0_flush_range;
> -	outer_cache.sync = l2x0_cache_sync;
> -	outer_cache.flush_all = l2x0_flush_all;
> -	outer_cache.inv_all = l2x0_inv_all;
> -	outer_cache.disable = l2x0_disable;
> +	if (!of_init) {
> +		outer_cache.inv_range = l2x0_inv_range;
> +		outer_cache.clean_range = l2x0_clean_range;
> +		outer_cache.flush_range = l2x0_flush_range;
> +		outer_cache.sync = l2x0_cache_sync;
> +		outer_cache.flush_all = l2x0_flush_all;
> +		outer_cache.inv_all = l2x0_inv_all;
> +		outer_cache.disable = l2x0_disable;
> +	}
>  
>  	printk(KERN_INFO "%s cache controller enabled\n", type);
>  	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
> @@ -533,15 +536,34 @@ static void pl310_resume(void)
>  }
>  
>  static const struct l2x0_of_data pl310_data = {
> -	pl310_of_setup,
> -	pl310_save,
> -	pl310_resume,
> +	.setup = pl310_of_setup,
> +	.save  = pl310_save,
> +	.outer_cache = {
> +		.resume      = pl310_resume,
> +		.inv_range   = l2x0_inv_range,
> +		.clean_range = l2x0_clean_range,
> +		.flush_range = l2x0_flush_range,
> +		.sync        = l2x0_cache_sync,
> +		.flush_all   = l2x0_flush_all,
> +		.inv_all     = l2x0_inv_all,
> +		.disable     = l2x0_disable,
> +		.set_debug   = pl310_set_debug,
> +	},
>  };
>  
>  static const struct l2x0_of_data l2x0_data = {
> -	l2x0_of_setup,
> -	NULL,
> -	l2x0_resume,
> +	.setup = l2x0_of_setup,
> +	.save  = NULL,
> +	.outer_cache = {
> +		.resume      = l2x0_resume,
> +		.inv_range   = l2x0_inv_range,
> +		.clean_range = l2x0_clean_range,
> +		.flush_range = l2x0_flush_range,
> +		.sync        = l2x0_cache_sync,
> +		.flush_all   = l2x0_flush_all,
> +		.inv_all     = l2x0_inv_all,
> +		.disable     = l2x0_disable,
> +	},
>  };
>  
>  static const struct of_device_id l2x0_ids[] __initconst = {
> @@ -581,9 +603,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
>  	if (data->save)
>  		data->save();
>  
> +	/* */

Was there a comment here?

thx,

Jason.

> +	of_init = true;
>  	l2x0_init(l2x0_base, aux_val, aux_mask);
>  
> -	outer_cache.resume = data->resume;
> +	memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
> +
>  	return 0;
>  }
>  #endif
> -- 
> 1.7.9.5
> 

[PATCH V5] Add support for Aurora L2 Cache Controller

[Jason Cooper]

On Wed, Sep 26, 2012 at 06:08:12PM +0200, Gregory CLEMENT wrote:
> > Changelog:
> > V4 -> V5:
> > - Rebased L2 pach set onto v3.6-rc7.
> > - The header file cache-aurora-l2.h was co-located with its only user:
> >   moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
> > - Removed additional unnecessary blank lines in cache-l2x0.c.
> > 
> Russell,
> 
> will you take the all series from the git repository ? As the
> last patches have been already acked-by Arnd and were initially pulled
> by Jason Cooper, I think there should be no problem to get the whole
> series.
> 
> Now if you only want to take the first three patches, will you pull
> them from the git repository or do you prefer that I submit them
> through your patch system?

Russell,

If you're ok with it, I can take the whole series (incl 1,2,3) through
my tree.  Or, split it up as we did before (arch/arm/mm changes through
you, all else through us).

Gregory,

I'm inclined to make this v3.8 material, especially if pushing it
through two different trees.  Do you have any objection?

thx,

Jason.

[PATCH V5 1/6] arm: cache-l2x0: make outer_cache_fns a field of l2x0_of_data

[Gregory CLEMENT]

On 09/26/2012 06:14 PM, Jason Cooper wrote:
> On Wed, Sep 26, 2012 at 06:02:45PM +0200, Gregory CLEMENT wrote:
>> Instead of having multiple functions belonging to outer_cache and
>> filling this structure on the fly, use a outer_cache_fns field inside
>> l2x0_of_data and just memcopy it into outer_cache depending of the
>> type of the l2x0 cache. For non DT case, the former code was kept.
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>> Tested-and-reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
>> Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>
>>
>> Cc: Barry Song <21cnbao@gmail.com>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Cc: Rob Herring <rob.herring@calxeda.com>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Olof Johansson <olof@lixom.net>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>> ---
>>  arch/arm/mm/cache-l2x0.c |   55 +++++++++++++++++++++++++++++++++-------------
>>  1 file changed, 40 insertions(+), 15 deletions(-)
>>
>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>> index 2a8e380..8b9c0ae 100644
>> --- a/arch/arm/mm/cache-l2x0.c
>> +++ b/arch/arm/mm/cache-l2x0.c
>> @@ -39,8 +39,9 @@ struct l2x0_regs l2x0_saved_regs;
>>  struct l2x0_of_data {
>>  	void (*setup)(const struct device_node *, u32 *, u32 *);
>>  	void (*save)(void);
>> -	void (*resume)(void);
>> +	struct outer_cache_fns outer_cache;
>>  };
>> +static bool of_init = false;
>>  
>>  static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
>>  {
>> @@ -376,13 +377,15 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
>>  		writel_relaxed(1, l2x0_base + L2X0_CTRL);
>>  	}
>>  
>> -	outer_cache.inv_range = l2x0_inv_range;
>> -	outer_cache.clean_range = l2x0_clean_range;
>> -	outer_cache.flush_range = l2x0_flush_range;
>> -	outer_cache.sync = l2x0_cache_sync;
>> -	outer_cache.flush_all = l2x0_flush_all;
>> -	outer_cache.inv_all = l2x0_inv_all;
>> -	outer_cache.disable = l2x0_disable;
>> +	if (!of_init) {
>> +		outer_cache.inv_range = l2x0_inv_range;
>> +		outer_cache.clean_range = l2x0_clean_range;
>> +		outer_cache.flush_range = l2x0_flush_range;
>> +		outer_cache.sync = l2x0_cache_sync;
>> +		outer_cache.flush_all = l2x0_flush_all;
>> +		outer_cache.inv_all = l2x0_inv_all;
>> +		outer_cache.disable = l2x0_disable;
>> +	}
>>  
>>  	printk(KERN_INFO "%s cache controller enabled\n", type);
>>  	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
>> @@ -533,15 +536,34 @@ static void pl310_resume(void)
>>  }
>>  
>>  static const struct l2x0_of_data pl310_data = {
>> -	pl310_of_setup,
>> -	pl310_save,
>> -	pl310_resume,
>> +	.setup = pl310_of_setup,
>> +	.save  = pl310_save,
>> +	.outer_cache = {
>> +		.resume      = pl310_resume,
>> +		.inv_range   = l2x0_inv_range,
>> +		.clean_range = l2x0_clean_range,
>> +		.flush_range = l2x0_flush_range,
>> +		.sync        = l2x0_cache_sync,
>> +		.flush_all   = l2x0_flush_all,
>> +		.inv_all     = l2x0_inv_all,
>> +		.disable     = l2x0_disable,
>> +		.set_debug   = pl310_set_debug,
>> +	},
>>  };
>>  
>>  static const struct l2x0_of_data l2x0_data = {
>> -	l2x0_of_setup,
>> -	NULL,
>> -	l2x0_resume,
>> +	.setup = l2x0_of_setup,
>> +	.save  = NULL,
>> +	.outer_cache = {
>> +		.resume      = l2x0_resume,
>> +		.inv_range   = l2x0_inv_range,
>> +		.clean_range = l2x0_clean_range,
>> +		.flush_range = l2x0_flush_range,
>> +		.sync        = l2x0_cache_sync,
>> +		.flush_all   = l2x0_flush_all,
>> +		.inv_all     = l2x0_inv_all,
>> +		.disable     = l2x0_disable,
>> +	},
>>  };
>>  
>>  static const struct of_device_id l2x0_ids[] __initconst = {
>> @@ -581,9 +603,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
>>  	if (data->save)
>>  		data->save();
>>  
>> +	/* */
> 
> Was there a comment here?

No it was due to a bad combination of keys with my editor.
I have fixed in in the git repository now.

And the updated patch is the following:

Subject: [PATCH V5 1/6] arm: cache-l2x0: make outer_cache_fns a field of
 l2x0_of_data

Instead of having multiple functions belonging to outer_cache and
filling this structure on the fly, use a outer_cache_fns field inside
l2x0_of_data and just memcopy it into outer_cache depending of the
type of the l2x0 cache. For non DT case, the former code was kept.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-and-reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>

Cc: Barry Song <21cnbao@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/mm/cache-l2x0.c |   54 +++++++++++++++++++++++++++++++++-------------
 1 file changed, 39 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2a8e380..1f7aad6 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -39,8 +39,9 @@ struct l2x0_regs l2x0_saved_regs;
 struct l2x0_of_data {
        void (*setup)(const struct device_node *, u32 *, u32 *);
        void (*save)(void);
-       void (*resume)(void);
+       struct outer_cache_fns outer_cache;
 };
+static bool of_init = false;

 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
 {
@@ -376,13 +377,15 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
                writel_relaxed(1, l2x0_base + L2X0_CTRL);
        }

-       outer_cache.inv_range = l2x0_inv_range;
-       outer_cache.clean_range = l2x0_clean_range;
-       outer_cache.flush_range = l2x0_flush_range;
-       outer_cache.sync = l2x0_cache_sync;
-       outer_cache.flush_all = l2x0_flush_all;
-       outer_cache.inv_all = l2x0_inv_all;
-       outer_cache.disable = l2x0_disable;
+       if (!of_init) {
+               outer_cache.inv_range = l2x0_inv_range;
+               outer_cache.clean_range = l2x0_clean_range;
+               outer_cache.flush_range = l2x0_flush_range;
+               outer_cache.sync = l2x0_cache_sync;
+               outer_cache.flush_all = l2x0_flush_all;
+               outer_cache.inv_all = l2x0_inv_all;
+               outer_cache.disable = l2x0_disable;
+       }

        printk(KERN_INFO "%s cache controller enabled\n", type);
        printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
@@ -533,15 +536,34 @@ static void pl310_resume(void)
 }

 static const struct l2x0_of_data pl310_data = {
-       pl310_of_setup,
-       pl310_save,
-       pl310_resume,
+       .setup = pl310_of_setup,
+       .save  = pl310_save,
+       .outer_cache = {
+               .resume      = pl310_resume,
+               .inv_range   = l2x0_inv_range,
+               .clean_range = l2x0_clean_range,
+               .flush_range = l2x0_flush_range,
+               .sync        = l2x0_cache_sync,
+               .flush_all   = l2x0_flush_all,
+               .inv_all     = l2x0_inv_all,
+               .disable     = l2x0_disable,
+               .set_debug   = pl310_set_debug,
+       },
 };

 static const struct l2x0_of_data l2x0_data = {
-       l2x0_of_setup,
-       NULL,
-       l2x0_resume,
+       .setup = l2x0_of_setup,
+       .save  = NULL,
+       .outer_cache = {
+               .resume      = l2x0_resume,
+               .inv_range   = l2x0_inv_range,
+               .clean_range = l2x0_clean_range,
+               .flush_range = l2x0_flush_range,
+               .sync        = l2x0_cache_sync,
+               .flush_all   = l2x0_flush_all,
+               .inv_all     = l2x0_inv_all,
+               .disable     = l2x0_disable,
+       },
 };

 static const struct of_device_id l2x0_ids[] __initconst = {
@@ -581,9 +603,11 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
        if (data->save)
                data->save();

+       of_init = true;
        l2x0_init(l2x0_base, aux_val, aux_mask);

-       outer_cache.resume = data->resume;
+       memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
+
        return 0;
 }
 #endif
-- 
1.7.9.5

[PATCH V5] Add support for Aurora L2 Cache Controller

[Gregory CLEMENT]

On 09/26/2012 06:24 PM, Jason Cooper wrote:
> On Wed, Sep 26, 2012 at 06:08:12PM +0200, Gregory CLEMENT wrote:
>>> Changelog:
>>> V4 -> V5:
>>> - Rebased L2 pach set onto v3.6-rc7.
>>> - The header file cache-aurora-l2.h was co-located with its only user:
>>>   moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
>>> - Removed additional unnecessary blank lines in cache-l2x0.c.
>>>
>> Russell,
>>
>> will you take the all series from the git repository ? As the
>> last patches have been already acked-by Arnd and were initially pulled
>> by Jason Cooper, I think there should be no problem to get the whole
>> series.
>>
>> Now if you only want to take the first three patches, will you pull
>> them from the git repository or do you prefer that I submit them
>> through your patch system?
> 
> Russell,
> 
> If you're ok with it, I can take the whole series (incl 1,2,3) through
> my tree.  Or, split it up as we did before (arch/arm/mm changes through
> you, all else through us).
> 
> Gregory,
> 
> I'm inclined to make this v3.8 material, especially if pushing it
> through two different trees.  Do you have any objection?

Well I have pushed this series a long time ago and I have hopped it
would have been part of the v3.7.

The only issue I found when I tried to merge this branch with the
for-next of arm-soc  was a very trivial conflict in
arch/arm/mach-mvebu/Kconfig.

> 
> thx,
> 
> Jason.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH V5 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Catalin Marinas]

On 26 September 2012 17:02, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:
> +static void aurora_pa_range(unsigned long start, unsigned long end,
> +                       unsigned long offset)
> +{
> +       unsigned long flags;
> +
> +       raw_spin_lock_irqsave(&l2x0_lock, flags);
> +       writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
> +       writel(end, l2x0_base + offset);

Just use writel_relaxed() here for consistency and possible deadlock avoidance.

-- 
Catalin

[PATCH V5] Add support for Aurora L2 Cache Controller

[Jason Cooper]

On Wed, Sep 26, 2012 at 06:40:39PM +0200, Gregory CLEMENT wrote:
> On 09/26/2012 06:24 PM, Jason Cooper wrote:
> > On Wed, Sep 26, 2012 at 06:08:12PM +0200, Gregory CLEMENT wrote:
> >>> Changelog:
> >>> V4 -> V5:
> >>> - Rebased L2 pach set onto v3.6-rc7.
> >>> - The header file cache-aurora-l2.h was co-located with its only user:
> >>>   moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
> >>> - Removed additional unnecessary blank lines in cache-l2x0.c.
> >>>
> >> Russell,
> >>
> >> will you take the all series from the git repository ? As the
> >> last patches have been already acked-by Arnd and were initially pulled
> >> by Jason Cooper, I think there should be no problem to get the whole
> >> series.
> >>
> >> Now if you only want to take the first three patches, will you pull
> >> them from the git repository or do you prefer that I submit them
> >> through your patch system?
> > 
> > Russell,
> > 
> > If you're ok with it, I can take the whole series (incl 1,2,3) through
> > my tree.  Or, split it up as we did before (arch/arm/mm changes through
> > you, all else through us).
> > 
> > Gregory,
> > 
> > I'm inclined to make this v3.8 material, especially if pushing it
> > through two different trees.  Do you have any objection?
> 
> Well I have pushed this series a long time ago and I have hopped it
> would have been part of the v3.7.

It really hinges on if Russell is ok with keeping the series together.
I'd really prefer not to cause the dependency headache this late in the
release cycle.

So, if Russell is ok with me taking the whole series, v3.7.  If not,
v3.8.  Fair enough?

thx,

Jason.

[PATCH V5] Add support for Aurora L2 Cache Controller

[Gregory CLEMENT]

On 09/26/2012 08:48 PM, Jason Cooper wrote:
> On Wed, Sep 26, 2012 at 06:40:39PM +0200, Gregory CLEMENT wrote:
>> On 09/26/2012 06:24 PM, Jason Cooper wrote:
>>> On Wed, Sep 26, 2012 at 06:08:12PM +0200, Gregory CLEMENT wrote:
>>>>> Changelog:
>>>>> V4 -> V5:
>>>>> - Rebased L2 pach set onto v3.6-rc7.
>>>>> - The header file cache-aurora-l2.h was co-located with its only user:
>>>>>   moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
>>>>> - Removed additional unnecessary blank lines in cache-l2x0.c.
>>>>>
>>>> Russell,
>>>>
>>>> will you take the all series from the git repository ? As the
>>>> last patches have been already acked-by Arnd and were initially pulled
>>>> by Jason Cooper, I think there should be no problem to get the whole
>>>> series.
>>>>
>>>> Now if you only want to take the first three patches, will you pull
>>>> them from the git repository or do you prefer that I submit them
>>>> through your patch system?
>>>
>>> Russell,
>>>
>>> If you're ok with it, I can take the whole series (incl 1,2,3) through
>>> my tree.  Or, split it up as we did before (arch/arm/mm changes through
>>> you, all else through us).
>>>
>>> Gregory,
>>>
>>> I'm inclined to make this v3.8 material, especially if pushing it
>>> through two different trees.  Do you have any objection?
>>
>> Well I have pushed this series a long time ago and I have hopped it
>> would have been part of the v3.7.
> 
> It really hinges on if Russell is ok with keeping the series together.
> I'd really prefer not to cause the dependency headache this late in the
> release cycle.
> 
> So, if Russell is ok with me taking the whole series, v3.7.  If not,
> v3.8.  Fair enough?

Yes I don't want to overload you so late in the release cycle.
Thanks for you effort

> 
> thx,
> 
> Jason.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH V5 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

On 09/26/2012 07:11 PM, Catalin Marinas wrote:> On 26 September 2012 17:02, Gregory CLEMENT
> <gregory.clement@free-electrons.com> wrote:
>> +static void aurora_pa_range(unsigned long start, unsigned long end,
>> +                       unsigned long offset)
>> +{
>> +       unsigned long flags;
>> +
>> +       raw_spin_lock_irqsave(&l2x0_lock, flags);
>> +       writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
>> +       writel(end, l2x0_base + offset);
> 
> Just use writel_relaxed() here for consistency and possible deadlock avoidance.
> 

OK I fixed it in the git repo and I also send the updated patch.

Russell do you agree to take the series now?

Thanks.

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
as:
- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
  maintenance operations on L1 are broadcasted to the L2 and L2
  performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
  can be done on a range inside a page and are not limited to a cache
  line.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>

Cc: Barry Song <21cnbao@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
---
 arch/arm/include/asm/hardware/cache-l2x0.h |    4 +
 arch/arm/mm/cache-aurora-l2.h              |   55 +++++++
 arch/arm/mm/cache-l2x0.c                   |  222 ++++++++++++++++++++++++++--
 3 files changed, 268 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mm/cache-aurora-l2.h

diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 5f2c7b4..3b2c40b 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -102,6 +102,10 @@
 
 #define L2X0_ADDR_FILTER_EN		1
 
+#define L2X0_CTRL_EN			1
+
+#define L2X0_WAY_SIZE_SHIFT		3
+
 #ifndef __ASSEMBLY__
 extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
 #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
diff --git a/arch/arm/mm/cache-aurora-l2.h b/arch/arm/mm/cache-aurora-l2.h
new file mode 100644
index 0000000..c861247
--- /dev/null
+++ b/arch/arm/mm/cache-aurora-l2.h
@@ -0,0 +1,55 @@
+/*
+ * AURORA shared L2 cache controller support
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
+#define __ASM_ARM_HARDWARE_AURORA_L2_H
+
+#define AURORA_SYNC_REG		    0x700
+#define AURORA_RANGE_BASE_ADDR_REG  0x720
+#define AURORA_FLUSH_PHY_ADDR_REG   0x7f0
+#define AURORA_INVAL_RANGE_REG	    0x774
+#define AURORA_CLEAN_RANGE_REG	    0x7b4
+#define AURORA_FLUSH_RANGE_REG	    0x7f4
+
+#define AURORA_ACR_REPLACEMENT_OFFSET	    27
+#define AURORA_ACR_REPLACEMENT_MASK	     \
+	(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR    \
+	(0 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_LFSR     \
+	(1 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
+	(3 << AURORA_ACR_REPLACEMENT_OFFSET)
+
+#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET	0
+#define AURORA_ACR_FORCE_WRITE_POLICY_MASK	\
+	(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_POLICY_DIS	\
+	(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_BACK_POLICY	\
+	(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_THRO_POLICY	\
+	(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+
+#define MAX_RANGE_SIZE		1024
+
+#define AURORA_WAY_SIZE_SHIFT	2
+
+#define AURORA_CTRL_FW		0x100
+
+/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
+ * the distinction between a number coming from hardware and a number
+ * coming from the device tree */
+#define AURORA_CACHE_ID	       0x100
+
+#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 1f7aad6..6d5e5e7 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,6 +25,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "cache-aurora-l2.h"
 
 #define CACHE_LINE_SIZE		32
 
@@ -33,6 +34,11 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
+static int l2_wt_override;
+
+/* Aurora don't have the cache ID register available, so we have to
+ * pass it though the device tree */
+static u32  cache_id_part_number_from_dt;
 
 struct l2x0_regs l2x0_saved_regs;
 
@@ -169,7 +175,7 @@ static void l2x0_inv_all(void)
 	/* invalidate all ways */
 	raw_spin_lock_irqsave(&l2x0_lock, flags);
 	/* Invalidating when L2 is enabled is a nono */
-	BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
+	BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
 	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
 	cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
 	cache_sync();
@@ -277,6 +283,98 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
+/*
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive, while the hardware cache range operations use
+ * inclusive start and end addresses.
+ */
+static unsigned long calc_range_end(unsigned long start, unsigned long end)
+{
+	/*
+	 * Limit the number of cache lines processed at once,
+	 * since cache range operations stall the CPU pipeline
+	 * until completion.
+	 */
+	if (end > start + MAX_RANGE_SIZE)
+		end = start + MAX_RANGE_SIZE;
+
+	/*
+	 * Cache range operations can't straddle a page boundary.
+	 */
+	if (end > PAGE_ALIGN(start+1))
+		end = PAGE_ALIGN(start+1);
+
+	return end;
+}
+
+/*
+ * Make sure 'start' and 'end' reference the same page, as L2 is PIPT
+ * and range operations only do a TLB lookup on the start address.
+ */
+static void aurora_pa_range(unsigned long start, unsigned long end,
+			unsigned long offset)
+{
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&l2x0_lock, flags);
+	writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+	writel_relaxed(end, l2x0_base + offset);
+	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+
+	cache_sync();
+}
+
+static void aurora_inv_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * round start and end adresses up to cache line size
+	 */
+	start &= ~(CACHE_LINE_SIZE - 1);
+	end = ALIGN(end, CACHE_LINE_SIZE);
+
+	/*
+	 * Invalidate all full cache lines between 'start' and 'end'.
+	 */
+	while (start < end) {
+		unsigned long range_end = calc_range_end(start, end);
+		aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+				AURORA_INVAL_RANGE_REG);
+		start = range_end;
+	}
+}
+
+static void aurora_clean_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * If L2 is forced to WT, the L2 will always be clean and we
+	 * don't need to do anything here.
+	 */
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = ALIGN(end, CACHE_LINE_SIZE);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_CLEAN_RANGE_REG);
+			start = range_end;
+		}
+	}
+}
+
+static void aurora_flush_range(unsigned long start, unsigned long end)
+{
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = ALIGN(end, CACHE_LINE_SIZE);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_FLUSH_RANGE_REG);
+			start = range_end;
+		}
+	}
+}
+
 static void l2x0_disable(void)
 {
 	unsigned long flags;
@@ -293,11 +391,18 @@ static void l2x0_unlock(u32 cache_id)
 	int lockregs;
 	int i;
 
-	if (cache_id == L2X0_CACHE_ID_PART_L310)
+	switch (cache_id) {
+	case L2X0_CACHE_ID_PART_L310:
 		lockregs = 8;
-	else
+		break;
+	case AURORA_CACHE_ID:
+		lockregs = 4;
+		break;
+	default:
 		/* L210 and unknown types */
 		lockregs = 1;
+		break;
+	}
 
 	for (i = 0; i < lockregs; i++) {
 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
@@ -313,18 +418,22 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	u32 cache_id;
 	u32 way_size = 0;
 	int ways;
+	int way_size_shift = L2X0_WAY_SIZE_SHIFT;
 	const char *type;
 
 	l2x0_base = base;
-
-	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+	if (cache_id_part_number_from_dt)
+		cache_id = cache_id_part_number_from_dt;
+	else
+		cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
+			& L2X0_CACHE_ID_PART_MASK;
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
 	aux &= aux_mask;
 	aux |= aux_val;
 
 	/* Determine the number of ways */
-	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+	switch (cache_id) {
 	case L2X0_CACHE_ID_PART_L310:
 		if (aux & (1 << 16))
 			ways = 16;
@@ -341,6 +450,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		ways = (aux >> 13) & 0xf;
 		type = "L210";
 		break;
+
+	case AURORA_CACHE_ID:
+		sync_reg_offset = AURORA_SYNC_REG;
+		ways = (aux >> 13) & 0xf;
+		ways = 2 << ((ways + 1) >> 2);
+		way_size_shift = AURORA_WAY_SIZE_SHIFT;
+		type = "Aurora";
+		break;
 	default:
 		/* Assume unknown chips have 8 ways */
 		ways = 8;
@@ -354,7 +471,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	 * L2 cache Size =  Way size * Number of ways
 	 */
 	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
-	way_size = 1 << (way_size + 3);
+	way_size = 1 << (way_size + way_size_shift);
+
 	l2x0_size = ways * way_size * SZ_1K;
 
 	/*
@@ -362,7 +480,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	 * If you are booting from non-secure mode
 	 * accessing the below registers will fault.
 	 */
-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		/* Make sure that I&D is not locked down when starting */
 		l2x0_unlock(cache_id);
 
@@ -374,7 +492,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		l2x0_inv_all();
 
 		/* enable L2X0 */
-		writel_relaxed(1, l2x0_base + L2X0_CTRL);
+		writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
 	}
 
 	if (!of_init) {
@@ -490,9 +608,15 @@ static void __init pl310_save(void)
 	}
 }
 
+static void aurora_save(void)
+{
+	l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
+	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+}
+
 static void l2x0_resume(void)
 {
-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		/* restore aux ctrl and enable l2 */
 		l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
 
@@ -501,7 +625,7 @@ static void l2x0_resume(void)
 
 		l2x0_inv_all();
 
-		writel_relaxed(1, l2x0_base + L2X0_CTRL);
+		writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
 	}
 }
 
@@ -509,7 +633,7 @@ static void pl310_resume(void)
 {
 	u32 l2x0_revision;
 
-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		/* restore pl310 setup */
 		writel_relaxed(l2x0_saved_regs.tag_latency,
 			l2x0_base + L2X0_TAG_LATENCY_CTRL);
@@ -535,6 +659,46 @@ static void pl310_resume(void)
 	l2x0_resume();
 }
 
+static void aurora_resume(void)
+{
+	if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+		writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
+		writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+	}
+}
+
+static void __init aurora_broadcast_l2_commands(void)
+{
+	__u32 u;
+	/* Enable Broadcasting of cache commands to L2*/
+	__asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
+	u |= AURORA_CTRL_FW;		/* Set the FW bit */
+	__asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
+	isb();
+}
+
+static void __init aurora_of_setup(const struct device_node *np,
+				u32 *aux_val, u32 *aux_mask)
+{
+	u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
+	u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
+
+	of_property_read_u32(np, "cache-id-part",
+			&cache_id_part_number_from_dt);
+
+	/* Determine and save the write policy */
+	l2_wt_override = of_property_read_bool(np, "wt-override");
+
+	if (l2_wt_override) {
+		val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
+		mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
+	}
+
+	*aux_val &= ~mask;
+	*aux_val |= val;
+	*aux_mask &= ~mask;
+}
+
 static const struct l2x0_of_data pl310_data = {
 	.setup = pl310_of_setup,
 	.save  = pl310_save,
@@ -566,10 +730,37 @@ static const struct l2x0_of_data l2x0_data = {
 	},
 };
 
+static const struct l2x0_of_data aurora_with_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+		.inv_range   = aurora_inv_range,
+		.clean_range = aurora_clean_range,
+		.flush_range = aurora_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
+};
+
+static const struct l2x0_of_data aurora_no_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+	},
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
 	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+	{ .compatible = "marvell,aurora-system-cache",
+	  .data = (void *)&aurora_no_outer_data},
+	{ .compatible = "marvell,aurora-outer-cache",
+	  .data = (void *)&aurora_with_outer_data},
 	{}
 };
 
@@ -595,9 +786,14 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	data = of_match_node(l2x0_ids, np)->data;
 
 	/* L2 configuration can only be changed if the cache is disabled */
-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		if (data->setup)
 			data->setup(np, &aux_val, &aux_mask);
+
+		/* For aurora cache in no outer mode select the
+		 * correct mode using the coprocessor*/
+		if (data == &aurora_no_outer_data)
+			aurora_broadcast_l2_commands();
 	}
 
 	if (data->save)
-- 
1.7.9.5

[PATCH V5 4/6] arm: mvebu: add L2 cache support

[Olof Johansson]

Hi,

On Wed, Sep 26, 2012 at 06:02:48PM +0200, Gregory CLEMENT wrote:
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Tested-and-reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
> Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
> 
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Olof Johansson <olof@lixom.net>
> ---
>  arch/arm/mach-mvebu/Kconfig             |    1 +
>  arch/arm/mach-mvebu/irq-armada-370-xp.c |    4 ++++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index caa2c5e..e20c5e9 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -6,6 +6,7 @@ config MACH_ARMADA_370_XP
>  	bool "Marvell Armada 370 and Aramada XP boards"
>  	select ARMADA_370_XP_TIMER
>  	select CPU_V7
> +	select CACHE_L2X0
>  	help
>  
>  	  Say 'Y' here if you want your kernel to support boards based on
> diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
> index 5f5f939..570be84 100644
> --- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
> +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
> @@ -24,6 +24,7 @@
>  #include <linux/irqdomain.h>
>  #include <asm/mach/arch.h>
>  #include <asm/exception.h>
> +#include <asm/hardware/cache-l2x0.h>
>  
>  /* Interrupt Controller Registers Map */
>  #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
> @@ -130,4 +131,7 @@ static const struct of_device_id mpic_of_match[] __initconst = {
>  void __init armada_370_xp_init_irq(void)
>  {
>  	of_irq_init(mpic_of_match);
> +#ifdef CONFIG_CACHE_L2X0
> +	l2x0_of_init(0, ~0UL);
> +#endif

Nit: No need for ifdefs here, if CONFIG_CACHE_L2X0 or CONFIG_OF aren't
set, a stub inline of the function is provided by cache-l2x0.h.


-Olof

[PATCH V5] Add support for Aurora L2 Cache Controller

[Jason Cooper]

Gregory,

Unfortunately, this series is slipping to v3.8.  Please put patches 1,2
and 3 into Russell's patch tracker.  Once I see that he takes them in,
I'll resubmit my pullrq for the last three.

Sorry for all the confusion.

thx,

Jason.

On Wed, Sep 26, 2012 at 06:02:44PM +0200, Gregory CLEMENT wrote:
> Hello,
> 
> This a the 5th version of the patch set (the sixth if we include the
> RFC). This last series add the ultimate change asked by Russell after
> his review. See the end of this email for the changelog.
> 
> The purpose of this patch set is to add support for Aurora L2 Cache
> Controller used by Armada 370 and Armada XP SoCs. As it was initially
> designed by Marvell engineer to be compatible with the ARM L2 Cache
> Controller, we chose to reuse the existing code and to just extend it
> to support the differences and improvements brought by the Aurora
> controller.The diffstat looks like:
> 
>  Documentation/devicetree/bindings/arm/l2cc.txt |    9 +
>  arch/arm/boot/dts/armada-370.dtsi              |    6 +
>  arch/arm/boot/dts/armada-xp.dtsi               |    7 +
>  arch/arm/include/asm/hardware/cache-l2x0.h     |    5 +
>  arch/arm/mach-mvebu/Kconfig                    |    1 +
>  arch/arm/mach-mvebu/irq-armada-370-xp.c        |    4 +
>  arch/arm/mm/cache-aurora-l2.h                  |   55 +++++
>  arch/arm/mm/cache-l2x0.c                       |  277 +++++++++++++++++++++---
>  8 files changed, 336 insertions(+), 28 deletions(-)
> 
> The main differences and improvements are:
> 
> - no cache id part number available through hardware (need to get it
>   by the DT).
> - always write through mode available.
> - two flavors of the controller 'outer cache' and 'system cache' (the
>   last one meaning maintenance operations on L1 are broadcasted to the
>   L2 and L2 performs the same operation).
> - in outer cache mode, the cache maintenance operations are improved
>   and can be done on a range inside a page and are not limited to a
>   cache line.
> - during resume the controller need to restore the ctrl register.
> 
> The first patch adds some modifications in the driver
> infrastructure. As most of the outer cache functions can use the
> Aurora improvements, we had to introduce new functions. So we thought
> it was better to use a outer_cache_fns field inside l2x0_of_data and
> just memcopy it into outer_cache depending of the type of the l2x0
> cache.
> 
> Changelog:
> V4 -> V5:
> - Rebased L2 pach set onto v3.6-rc7.
> - The header file cache-aurora-l2.h was co-located with its only user:
>   moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
> - Removed additional unnecessary blank lines in cache-l2x0.c.
> 
> V3 -> V4:
> - Rebased L2 pach set onto v3.6-rc6.
> - The assignment of outer_cache in l2x0_init, don't depend of
>   CONFIG_OF but of variable. The value of this boolean variable is
>   changed in l2x0_of_init. Then, if a system enable CONFIG_OF don't
>   supply a DT file, relying on the old way to initialize the L2 cache,
>   the assignment won't be disable.
> - Removed unnecessary check in calc_range_end(). The alignment tested
>   was already made before calling this function.
> 
> V2 -> V3:
> - Use define instead of literal value for AURORA_CTRL_FW,
>   AURORA_WAY_SIZE_SHIFT, L2X0_WAY_SIZE_SHIFT and L2X0_CTRL_EN.
> - Used ALIGN, IS_ALUGNED and PAGE_ALIGN macro instead of bitwise
>   operation.
> - Calculate the number of way for Aurora instead of using a switch
>   case.
> - removed inaccurate BUG() call and replaced them by a pr_warn if
>   needed.
> - In aurora_inv_range round the start and end addresses to cache line
>   size. The initial code was supposed to invalidate partial line cache
>   but actually invalidate the full line, so there was no point to do
>   it outside the aurora_pa_range call.
> - Removed the dsb call in the aurora_*_range function: the
>   cache_sync() call inside aurora_pa_range() is enough.
> - And as usual tested on Armada 370 and Armada XP boards and ran
>   benchmark without seeing any regression. Results are updated on the
>   wiki page.
> 
> V1 -> V2:
> - Rebased L2 pach set onto v3.6-rc4.
> - Changed the compatible names to be more explicit, from
>   aurora-cache-with-outer to aurora-outer-cache , and from
>   aurora-cache-without-outer to aurora-system-cache.
> - Add an isb() after the call to mcr in aurora_broadcast_l2_commands().
> - Added the tested and reviewed-by from Lior Amsalem and Yehuda
>   Yitschak.
> - Tested on Armada 370 and Armada XP boards and ran benchmark without
>   seeing any regression.
> 
> RFC -> V1:
> - Rebased the series on to V3.6-rc3
> - Added missing Signed-off-by
> - Corrected a compilation warning that I have missed
> - Ran benchmarks without seeing any regression
> 
> Benchmarks results are visible here:
> https://github.com/MISL-EBU-System-SW/mainline-public/wiki/Non-official-cache-bench-results-on-the-mainline-Linux-port-%28-kernels-3.6-rcX%29-of-Armada-XP-and-Armada-370
> 
> The git branch aurora-L2-cache-ctrl is visible at
> https://github.com/MISL-EBU-System-SW/mainline-public.git
> 
> Regards,
> 
> Gregory
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Russell King - ARM Linux]

On Thu, Sep 27, 2012 at 11:35:23AM +0200, Gregory CLEMENT wrote:
> Aurora Cache Controller was designed to be compatible with the ARM L2
> Cache Controller. It comes with some difference or improvement such
> as:
> - no cache id part number available through hardware (need to get it
>   by the DT).
> - always write through mode available.
> - two flavors of the controller outer cache and system cache (meaning
>   maintenance operations on L1 are broadcasted to the L2 and L2
>   performs the same operation).
> - in outer cache mode, the cache maintenance operations are improved and
>   can be done on a range inside a page and are not limited to a cache
>   line.

This adds new build warnings:

arch/arm/mm/cache-l2x0.c:328:13: warning: 'aurora_inv_range' defined but not used
arch/arm/mm/cache-l2x0.c:347:13: warning: 'aurora_clean_range' defined but not used
arch/arm/mm/cache-l2x0.c:365:13: warning: 'aurora_flush_range' defined but not used

to the realview build (non-DT).  Please investigate, thanks.

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

On 10/23/2012 11:01 AM, Russell King - ARM Linux wrote:
> On Thu, Sep 27, 2012 at 11:35:23AM +0200, Gregory CLEMENT wrote:
>> Aurora Cache Controller was designed to be compatible with the ARM L2
>> Cache Controller. It comes with some difference or improvement such
>> as:
>> - no cache id part number available through hardware (need to get it
>>   by the DT).
>> - always write through mode available.
>> - two flavors of the controller outer cache and system cache (meaning
>>   maintenance operations on L1 are broadcasted to the L2 and L2
>>   performs the same operation).
>> - in outer cache mode, the cache maintenance operations are improved and
>>   can be done on a range inside a page and are not limited to a cache
>>   line.
> 
> This adds new build warnings:
> 
> arch/arm/mm/cache-l2x0.c:328:13: warning: 'aurora_inv_range' defined but not used
> arch/arm/mm/cache-l2x0.c:347:13: warning: 'aurora_clean_range' defined but not used
> arch/arm/mm/cache-l2x0.c:365:13: warning: 'aurora_flush_range' defined but not used
> 
> to the realview build (non-DT).  Please investigate, thanks.

OK I found the problem: aurora cache support is new so it is only
enable with device tree support. I moved all this functions in the
under OF_CONFIG (see the patch below). Do you want I submit it on the
patch system, or can you get it directly from this email?

Regards,

Gregory

---
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 5f2c7b4..3b2c40b 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -102,6 +102,10 @@

 #define L2X0_ADDR_FILTER_EN		1

+#define L2X0_CTRL_EN			1
+
+#define L2X0_WAY_SIZE_SHIFT		3
+
 #ifndef __ASSEMBLY__
 extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
 #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
diff --git a/arch/arm/mm/cache-aurora-l2.h b/arch/arm/mm/cache-aurora-l2.h
new file mode 100644
index 0000000..c861247
--- /dev/null
+++ b/arch/arm/mm/cache-aurora-l2.h
@@ -0,0 +1,55 @@
+/*
+ * AURORA shared L2 cache controller support
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
+#define __ASM_ARM_HARDWARE_AURORA_L2_H
+
+#define AURORA_SYNC_REG		    0x700
+#define AURORA_RANGE_BASE_ADDR_REG  0x720
+#define AURORA_FLUSH_PHY_ADDR_REG   0x7f0
+#define AURORA_INVAL_RANGE_REG	    0x774
+#define AURORA_CLEAN_RANGE_REG	    0x7b4
+#define AURORA_FLUSH_RANGE_REG	    0x7f4
+
+#define AURORA_ACR_REPLACEMENT_OFFSET	    27
+#define AURORA_ACR_REPLACEMENT_MASK	     \
+	(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR    \
+	(0 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_LFSR     \
+	(1 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
+	(3 << AURORA_ACR_REPLACEMENT_OFFSET)
+
+#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET	0
+#define AURORA_ACR_FORCE_WRITE_POLICY_MASK	\
+	(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_POLICY_DIS	\
+	(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_BACK_POLICY	\
+	(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_THRO_POLICY	\
+	(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+
+#define MAX_RANGE_SIZE		1024
+
+#define AURORA_WAY_SIZE_SHIFT	2
+
+#define AURORA_CTRL_FW		0x100
+
+/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
+ * the distinction between a number coming from hardware and a number
+ * coming from the device tree */
+#define AURORA_CACHE_ID	       0x100
+
+#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5e82433..1bc1920 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,6 +25,7 @@

 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "cache-aurora-l2.h"

 #define CACHE_LINE_SIZE		32

@@ -33,6 +34,11 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
+static int l2_wt_override;
+
+/* Aurora don't have the cache ID register available, so we have to
+ * pass it though the device tree */
+static u32  cache_id_part_number_from_dt;

 struct l2x0_regs l2x0_saved_regs;

@@ -169,7 +175,7 @@ static void l2x0_inv_all(void)
 	/* invalidate all ways */
 	raw_spin_lock_irqsave(&l2x0_lock, flags);
 	/* Invalidating when L2 is enabled is a nono */
-	BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
+	BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
 	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
 	cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
 	cache_sync();
@@ -293,11 +299,18 @@ static void l2x0_unlock(u32 cache_id)
 	int lockregs;
 	int i;

-	if (cache_id == L2X0_CACHE_ID_PART_L310)
+	switch (cache_id) {
+	case L2X0_CACHE_ID_PART_L310:
 		lockregs = 8;
-	else
+		break;
+	case AURORA_CACHE_ID:
+		lockregs = 4;
+		break;
+	default:
 		/* L210 and unknown types */
 		lockregs = 1;
+		break;
+	}

 	for (i = 0; i < lockregs; i++) {
 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
@@ -313,18 +326,22 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	u32 cache_id;
 	u32 way_size = 0;
 	int ways;
+	int way_size_shift = L2X0_WAY_SIZE_SHIFT;
 	const char *type;

 	l2x0_base = base;
-
-	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+	if (cache_id_part_number_from_dt)
+		cache_id = cache_id_part_number_from_dt;
+	else
+		cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
+			& L2X0_CACHE_ID_PART_MASK;
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);

 	aux &= aux_mask;
 	aux |= aux_val;

 	/* Determine the number of ways */
-	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+	switch (cache_id) {
 	case L2X0_CACHE_ID_PART_L310:
 		if (aux & (1 << 16))
 			ways = 16;
@@ -341,6 +358,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		ways = (aux >> 13) & 0xf;
 		type = "L210";
 		break;
+
+	case AURORA_CACHE_ID:
+		sync_reg_offset = AURORA_SYNC_REG;
+		ways = (aux >> 13) & 0xf;
+		ways = 2 << ((ways + 1) >> 2);
+		way_size_shift = AURORA_WAY_SIZE_SHIFT;
+		type = "Aurora";
+		break;
 	default:
 		/* Assume unknown chips have 8 ways */
 		ways = 8;
@@ -354,7 +379,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	 * L2 cache Size =  Way size * Number of ways
 	 */
 	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
-	way_size = 1 << (way_size + 3);
+	way_size = 1 << (way_size + way_size_shift);
+
 	l2x0_size = ways * way_size * SZ_1K;

 	/*
@@ -362,7 +388,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	 * If you are booting from non-secure mode
 	 * accessing the below registers will fault.
 	 */
-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		/* Make sure that I&D is not locked down when starting */
 		l2x0_unlock(cache_id);

@@ -372,7 +398,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		l2x0_inv_all();

 		/* enable L2X0 */
-		writel_relaxed(1, l2x0_base + L2X0_CTRL);
+		writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
 	}

 	/* Re-read it in case some bits are reserved. */
@@ -397,6 +423,98 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 }

 #ifdef CONFIG_OF
+/*
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive, while the hardware cache range operations use
+ * inclusive start and end addresses.
+ */
+static unsigned long calc_range_end(unsigned long start, unsigned long end)
+{
+	/*
+	 * Limit the number of cache lines processed@once,
+	 * since cache range operations stall the CPU pipeline
+	 * until completion.
+	 */
+	if (end > start + MAX_RANGE_SIZE)
+		end = start + MAX_RANGE_SIZE;
+
+	/*
+	 * Cache range operations can't straddle a page boundary.
+	 */
+	if (end > PAGE_ALIGN(start+1))
+		end = PAGE_ALIGN(start+1);
+
+	return end;
+}
+
+/*
+ * Make sure 'start' and 'end' reference the same page, as L2 is PIPT
+ * and range operations only do a TLB lookup on the start address.
+ */
+static void aurora_pa_range(unsigned long start, unsigned long end,
+			unsigned long offset)
+{
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&l2x0_lock, flags);
+	writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+	writel(end, l2x0_base + offset);
+	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+
+	cache_sync();
+}
+
+static void aurora_inv_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * round start and end adresses up to cache line size
+	 */
+	start &= ~(CACHE_LINE_SIZE - 1);
+	end = ALIGN(end, CACHE_LINE_SIZE);
+
+	/*
+	 * Invalidate all full cache lines between 'start' and 'end'.
+	 */
+	while (start < end) {
+		unsigned long range_end = calc_range_end(start, end);
+		aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+				AURORA_INVAL_RANGE_REG);
+		start = range_end;
+	}
+}
+
+static void aurora_clean_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * If L2 is forced to WT, the L2 will always be clean and we
+	 * don't need to do anything here.
+	 */
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = ALIGN(end, CACHE_LINE_SIZE);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_CLEAN_RANGE_REG);
+			start = range_end;
+		}
+	}
+}
+
+static void aurora_flush_range(unsigned long start, unsigned long end)
+{
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = ALIGN(end, CACHE_LINE_SIZE);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_FLUSH_RANGE_REG);
+			start = range_end;
+		}
+	}
+}
+
 static void __init l2x0_of_setup(const struct device_node *np,
 				 u32 *aux_val, u32 *aux_mask)
 {
@@ -494,9 +612,15 @@ static void __init pl310_save(void)
 	}
 }

+static void aurora_save(void)
+{
+	l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
+	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+}
+
 static void l2x0_resume(void)
 {
-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		/* restore aux ctrl and enable l2 */
 		l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));

@@ -505,7 +629,7 @@ static void l2x0_resume(void)

 		l2x0_inv_all();

-		writel_relaxed(1, l2x0_base + L2X0_CTRL);
+		writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
 	}
 }

@@ -513,7 +637,7 @@ static void pl310_resume(void)
 {
 	u32 l2x0_revision;

-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		/* restore pl310 setup */
 		writel_relaxed(l2x0_saved_regs.tag_latency,
 			l2x0_base + L2X0_TAG_LATENCY_CTRL);
@@ -539,6 +663,46 @@ static void pl310_resume(void)
 	l2x0_resume();
 }

+static void aurora_resume(void)
+{
+	if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+		writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
+		writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+	}
+}
+
+static void __init aurora_broadcast_l2_commands(void)
+{
+	__u32 u;
+	/* Enable Broadcasting of cache commands to L2*/
+	__asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
+	u |= AURORA_CTRL_FW;		/* Set the FW bit */
+	__asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
+	isb();
+}
+
+static void __init aurora_of_setup(const struct device_node *np,
+				u32 *aux_val, u32 *aux_mask)
+{
+	u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
+	u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
+
+	of_property_read_u32(np, "cache-id-part",
+			&cache_id_part_number_from_dt);
+
+	/* Determine and save the write policy */
+	l2_wt_override = of_property_read_bool(np, "wt-override");
+
+	if (l2_wt_override) {
+		val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
+		mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
+	}
+
+	*aux_val &= ~mask;
+	*aux_val |= val;
+	*aux_mask &= ~mask;
+}
+
 static const struct l2x0_of_data pl310_data = {
 	.setup = pl310_of_setup,
 	.save  = pl310_save,
@@ -570,10 +734,37 @@ static const struct l2x0_of_data l2x0_data = {
 	},
 };

+static const struct l2x0_of_data aurora_with_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+		.inv_range   = aurora_inv_range,
+		.clean_range = aurora_clean_range,
+		.flush_range = aurora_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
+};
+
+static const struct l2x0_of_data aurora_no_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+	},
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
 	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+	{ .compatible = "marvell,aurora-system-cache",
+	  .data = (void *)&aurora_no_outer_data},
+	{ .compatible = "marvell,aurora-outer-cache",
+	  .data = (void *)&aurora_with_outer_data},
 	{}
 };

@@ -599,9 +790,14 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	data = of_match_node(l2x0_ids, np)->data;

 	/* L2 configuration can only be changed if the cache is disabled */
-	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 		if (data->setup)
 			data->setup(np, &aux_val, &aux_mask);
+
+		/* For aurora cache in no outer mode select the
+		 * correct mode using the coprocessor*/
+		if (data == &aurora_no_outer_data)
+			aurora_broadcast_l2_commands();
 	}

 	if (data->save)
-- 
1.7.9.5

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Russell King - ARM Linux]

On Tue, Oct 23, 2012 at 11:43:02AM +0200, Gregory CLEMENT wrote:
> On 10/23/2012 11:01 AM, Russell King - ARM Linux wrote:
> > On Thu, Sep 27, 2012 at 11:35:23AM +0200, Gregory CLEMENT wrote:
> >> Aurora Cache Controller was designed to be compatible with the ARM L2
> >> Cache Controller. It comes with some difference or improvement such
> >> as:
> >> - no cache id part number available through hardware (need to get it
> >>   by the DT).
> >> - always write through mode available.
> >> - two flavors of the controller outer cache and system cache (meaning
> >>   maintenance operations on L1 are broadcasted to the L2 and L2
> >>   performs the same operation).
> >> - in outer cache mode, the cache maintenance operations are improved and
> >>   can be done on a range inside a page and are not limited to a cache
> >>   line.
> > 
> > This adds new build warnings:
> > 
> > arch/arm/mm/cache-l2x0.c:328:13: warning: 'aurora_inv_range' defined but not used
> > arch/arm/mm/cache-l2x0.c:347:13: warning: 'aurora_clean_range' defined but not used
> > arch/arm/mm/cache-l2x0.c:365:13: warning: 'aurora_flush_range' defined but not used
> > 
> > to the realview build (non-DT).  Please investigate, thanks.
> 
> OK I found the problem: aurora cache support is new so it is only
> enable with device tree support. I moved all this functions in the
> under OF_CONFIG (see the patch below). Do you want I submit it on the
> patch system, or can you get it directly from this email?

Easier by the patch system, and much less likely to get buried and lost
between now and when I do the update, thanks.

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

On 10/23/2012 12:00 PM, Russell King - ARM Linux wrote:
> On Tue, Oct 23, 2012 at 11:43:02AM +0200, Gregory CLEMENT wrote:
>> On 10/23/2012 11:01 AM, Russell King - ARM Linux wrote:
>>> On Thu, Sep 27, 2012 at 11:35:23AM +0200, Gregory CLEMENT wrote:
>>>> Aurora Cache Controller was designed to be compatible with the ARM L2
>>>> Cache Controller. It comes with some difference or improvement such
>>>> as:
>>>> - no cache id part number available through hardware (need to get it
>>>>   by the DT).
>>>> - always write through mode available.
>>>> - two flavors of the controller outer cache and system cache (meaning
>>>>   maintenance operations on L1 are broadcasted to the L2 and L2
>>>>   performs the same operation).
>>>> - in outer cache mode, the cache maintenance operations are improved and
>>>>   can be done on a range inside a page and are not limited to a cache
>>>>   line.
>>>
>>> This adds new build warnings:
>>>
>>> arch/arm/mm/cache-l2x0.c:328:13: warning: 'aurora_inv_range' defined but not used
>>> arch/arm/mm/cache-l2x0.c:347:13: warning: 'aurora_clean_range' defined but not used
>>> arch/arm/mm/cache-l2x0.c:365:13: warning: 'aurora_flush_range' defined but not used
>>>
>>> to the realview build (non-DT).  Please investigate, thanks.
>>
>> OK I found the problem: aurora cache support is new so it is only
>> enable with device tree support. I moved all this functions in the
>> under OF_CONFIG (see the patch below). Do you want I submit it on the
>> patch system, or can you get it directly from this email?
> 
> Easier by the patch system, and much less likely to get buried and lost
> between now and when I do the update, thanks.
> 
OK, the initial patch 7547/1 was superseded by the patch 7547/2 that I have just
pushed in the patch system. I hope I have done it right.

Thanks,

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Russell King - ARM Linux]

On Tue, Oct 23, 2012 at 12:23:10PM +0200, Gregory CLEMENT wrote:
> On 10/23/2012 12:00 PM, Russell King - ARM Linux wrote:
> > On Tue, Oct 23, 2012 at 11:43:02AM +0200, Gregory CLEMENT wrote:
> >> On 10/23/2012 11:01 AM, Russell King - ARM Linux wrote:
> >>> On Thu, Sep 27, 2012 at 11:35:23AM +0200, Gregory CLEMENT wrote:
> >>>> Aurora Cache Controller was designed to be compatible with the ARM L2
> >>>> Cache Controller. It comes with some difference or improvement such
> >>>> as:
> >>>> - no cache id part number available through hardware (need to get it
> >>>>   by the DT).
> >>>> - always write through mode available.
> >>>> - two flavors of the controller outer cache and system cache (meaning
> >>>>   maintenance operations on L1 are broadcasted to the L2 and L2
> >>>>   performs the same operation).
> >>>> - in outer cache mode, the cache maintenance operations are improved and
> >>>>   can be done on a range inside a page and are not limited to a cache
> >>>>   line.
> >>>
> >>> This adds new build warnings:
> >>>
> >>> arch/arm/mm/cache-l2x0.c:328:13: warning: 'aurora_inv_range' defined but not used
> >>> arch/arm/mm/cache-l2x0.c:347:13: warning: 'aurora_clean_range' defined but not used
> >>> arch/arm/mm/cache-l2x0.c:365:13: warning: 'aurora_flush_range' defined but not used
> >>>
> >>> to the realview build (non-DT).  Please investigate, thanks.
> >>
> >> OK I found the problem: aurora cache support is new so it is only
> >> enable with device tree support. I moved all this functions in the
> >> under OF_CONFIG (see the patch below). Do you want I submit it on the
> >> patch system, or can you get it directly from this email?
> > 
> > Easier by the patch system, and much less likely to get buried and lost
> > between now and when I do the update, thanks.
> > 
> OK, the initial patch 7547/1 was superseded by the patch 7547/2 that I have just
> pushed in the patch system. I hope I have done it right.

I know it's been a while, but it looks like it's still producing a warning.

arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used

This seems to be used only by the aurora code, which is wholely contained
within a CONFIG_OF block, and this is outside of said block...

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

On 11/04/2012 11:32 PM, Russell King - ARM Linux wrote:
> On Tue, Oct 23, 2012 at 12:23:10PM +0200, Gregory CLEMENT wrote:
>> On 10/23/2012 12:00 PM, Russell King - ARM Linux wrote:
>>> On Tue, Oct 23, 2012 at 11:43:02AM +0200, Gregory CLEMENT wrote:
>>>> On 10/23/2012 11:01 AM, Russell King - ARM Linux wrote:
>>>>> On Thu, Sep 27, 2012 at 11:35:23AM +0200, Gregory CLEMENT wrote:
>>>>>> Aurora Cache Controller was designed to be compatible with the ARM L2
>>>>>> Cache Controller. It comes with some difference or improvement such
>>>>>> as:
>>>>>> - no cache id part number available through hardware (need to get it
>>>>>>   by the DT).
>>>>>> - always write through mode available.
>>>>>> - two flavors of the controller outer cache and system cache (meaning
>>>>>>   maintenance operations on L1 are broadcasted to the L2 and L2
>>>>>>   performs the same operation).
>>>>>> - in outer cache mode, the cache maintenance operations are improved and
>>>>>>   can be done on a range inside a page and are not limited to a cache
>>>>>>   line.
>>>>>
>>>>> This adds new build warnings:
>>>>>
>>>>> arch/arm/mm/cache-l2x0.c:328:13: warning: 'aurora_inv_range' defined but not used
>>>>> arch/arm/mm/cache-l2x0.c:347:13: warning: 'aurora_clean_range' defined but not used
>>>>> arch/arm/mm/cache-l2x0.c:365:13: warning: 'aurora_flush_range' defined but not used
>>>>>
>>>>> to the realview build (non-DT).  Please investigate, thanks.
>>>>
>>>> OK I found the problem: aurora cache support is new so it is only
>>>> enable with device tree support. I moved all this functions in the
>>>> under OF_CONFIG (see the patch below). Do you want I submit it on the
>>>> patch system, or can you get it directly from this email?
>>>
>>> Easier by the patch system, and much less likely to get buried and lost
>>> between now and when I do the update, thanks.
>>>
>> OK, the initial patch 7547/1 was superseded by the patch 7547/2 that I have just
>> pushed in the patch system. I hope I have done it right.
> 
> I know it's been a while, but it looks like it's still producing a warning.
> 
> arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used
> 
> This seems to be used only by the aurora code, which is wholely contained
> within a CONFIG_OF block, and this is outside of said block...

The initial patch 7547/2 was superseded by the patch 7547/3 that I have just
pushed in the patch system. Last time first I fixed the code then I used the
versatile_defconfig configuration to test the compilation and didn't realize
that it did set CONFIG_OF by default.

> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Russell King - ARM Linux]

On Tue, Nov 06, 2012 at 12:50:29AM +0100, Gregory CLEMENT wrote:
> The initial patch 7547/2 was superseded by the patch 7547/3 that I have just
> pushed in the patch system. Last time first I fixed the code then I used the
> versatile_defconfig configuration to test the compilation and didn't realize
> that it did set CONFIG_OF by default.

Are you sure you put the right patch in there?

diff -u <(pdb getpatch 7547/2) <(pdb getpatch 7547/3)
--- /dev/fd/63	2012-11-06 00:23:54.451978759 +0000
+++ /dev/fd/62	2012-11-06 00:23:54.452978749 +0000
@@ -1,5 +1,5 @@
 ===============================================================================
-Patch: 7547/2: cache-l2x0: add support for Aurora L2 cache ctrl
+Patch: 7547/3: cache-l2x0: add support for Aurora L2 cache ctrl
 From: Gregory CLEMENT
 Email: gregory.clement@free-electrons.com
 Status: 3.7-rc1
@@ -10,6 +10,8 @@
  arch/arm/mm/cache-l2x0.c                   |  222 +++++++++++++++++++++++++++--
  3 files changed, 268 insertions(+), 13 deletions(-)
 -------------------------------------------------------------------------------
+diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
+index 5f2c7b4..3b2c40b 100644
 --- a/arch/arm/include/asm/hardware/cache-l2x0.h
 +++ b/arch/arm/include/asm/hardware/cache-l2x0.h
 @@ -102,6 +102,10 @@
@@ -443,3 +445,5 @@
  
  	if (data->save)
 
+
+

Looks mostly idential to me...

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Gregory CLEMENT]

On 11/06/2012 01:24 AM, Russell King - ARM Linux wrote:
> On Tue, Nov 06, 2012 at 12:50:29AM +0100, Gregory CLEMENT wrote:
>> The initial patch 7547/2 was superseded by the patch 7547/3 that I have just
>> pushed in the patch system. Last time first I fixed the code then I used the
>> versatile_defconfig configuration to test the compilation and didn't realize
>> that it did set CONFIG_OF by default.
> 
> Are you sure you put the right patch in there?
> 
> diff -u <(pdb getpatch 7547/2) <(pdb getpatch 7547/3)
> --- /dev/fd/63	2012-11-06 00:23:54.451978759 +0000
> +++ /dev/fd/62	2012-11-06 00:23:54.452978749 +0000
> @@ -1,5 +1,5 @@
>  ===============================================================================
> -Patch: 7547/2: cache-l2x0: add support for Aurora L2 cache ctrl
> +Patch: 7547/3: cache-l2x0: add support for Aurora L2 cache ctrl
>  From: Gregory CLEMENT
>  Email: gregory.clement at free-electrons.com
>  Status: 3.7-rc1
> @@ -10,6 +10,8 @@
>   arch/arm/mm/cache-l2x0.c                   |  222 +++++++++++++++++++++++++++--
>   3 files changed, 268 insertions(+), 13 deletions(-)
>  -------------------------------------------------------------------------------
> +diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
> +index 5f2c7b4..3b2c40b 100644
>  --- a/arch/arm/include/asm/hardware/cache-l2x0.h
>  +++ b/arch/arm/include/asm/hardware/cache-l2x0.h
>  @@ -102,6 +102,10 @@
> @@ -443,3 +445,5 @@
>   
>   	if (data->save)
>  
> +
> +
> 
> Looks mostly idential to me...
> 
Right, I amend the wrong commit :(

The patch 7547/4 should be the good one.

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Arnd Bergmann]

The newly introduced l2_wt_override should be in the same #ifdef
as the code using it, otherwise we get:

arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
On Tuesday 23 October 2012, Gregory CLEMENT wrote:
> @@ -33,6 +34,11 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock);
>  static u32 l2x0_way_mask;      /* Bitmask of active ways */
>  static u32 l2x0_size;
>  static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
> +static int l2_wt_override;
> +
> +/* Aurora don't have the cache ID register available, so we have to
> + * pass it though the device tree */
> +static u32  cache_id_part_number_from_dt;


diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 92ee4a0..6911b8b 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -34,7 +34,6 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
-static int l2_wt_override;
 
 /* Aurora don't have the cache ID register available, so we have to
  * pass it though the device tree */
@@ -424,6 +423,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 }
 
 #ifdef CONFIG_OF
+static int l2_wt_override;
+
 /*
  * Note that the end addresses passed to Linux primitives are
  * noninclusive, while the hardware cache range operations use

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Russell King - ARM Linux]

On Thu, Nov 08, 2012 at 02:08:41PM +0000, Arnd Bergmann wrote:
> The newly introduced l2_wt_override should be in the same #ifdef
> as the code using it, otherwise we get:
> 
> arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used

This should already be fixed.  I think your patch pre-dates 7547/4.

[PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Arnd Bergmann]

On Thursday 08 November 2012, Russell King - ARM Linux wrote:
> On Thu, Nov 08, 2012 at 02:08:41PM +0000, Arnd Bergmann wrote:
> > The newly introduced l2_wt_override should be in the same #ifdef
> > as the code using it, otherwise we get:
> > 
> > arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used
> 
> This should already be fixed.  I think your patch pre-dates 7547/4.

Yes, that's right. I was looking at yesterday's linux-next. It's fixed today.

Thanks,

	Arnd