* [PATCH] Set bit 22 in the PL310 (cache controller) AuxCtlr register [not found] ` <20121109095400.GC2357@mudshark.cambridge.arm.com> @ 2012-11-12 6:45 ` Shiraz Hashim 2012-11-12 10:56 ` Will Deacon 0 siblings, 1 reply; 3+ messages in thread From: Shiraz Hashim @ 2012-11-12 6:45 UTC (permalink / raw) To: linux-arm-kernel On Fri, Nov 09, 2012 at 09:54:01AM +0000, Will Deacon wrote: > On Fri, Nov 09, 2012 at 04:01:52AM +0000, Shiraz Hashim wrote: > > From: Catalin Marinas <catalin.marinas@arm.com> > > > > Clearing bit 22 in the PL310 Auxiliary Control register (shared > > attribute override enable) has the side effect of transforming Normal > > Shared Non-cacheable reads into Cacheable no-allocate reads. > > > > Coherent DMA buffers in Linux always have a Cacheable alias via the > > kernel linear mapping and the processor can speculatively load cache > > lines into the PL310 controller. With bit 22 cleared, Non-cacheable > > reads would unexpectedly hit such cache lines leading to buffer > > corruption. > > Is this still the case with recent kernels? I thought the dma-mapping/cma > work avoided the cacheable alias, but perhaps I'm mistaken. I haven't used CMA but DMA mappings are still normal memory non-cacheable. -- regards Shiraz ^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] Set bit 22 in the PL310 (cache controller) AuxCtlr register 2012-11-12 6:45 ` [PATCH] Set bit 22 in the PL310 (cache controller) AuxCtlr register Shiraz Hashim @ 2012-11-12 10:56 ` Will Deacon 2012-11-16 10:46 ` Shiraz Hashim 0 siblings, 1 reply; 3+ messages in thread From: Will Deacon @ 2012-11-12 10:56 UTC (permalink / raw) To: linux-arm-kernel On Mon, Nov 12, 2012 at 06:45:47AM +0000, Shiraz Hashim wrote: > On Fri, Nov 09, 2012 at 09:54:01AM +0000, Will Deacon wrote: > > On Fri, Nov 09, 2012 at 04:01:52AM +0000, Shiraz Hashim wrote: > > > From: Catalin Marinas <catalin.marinas@arm.com> > > > > > > Clearing bit 22 in the PL310 Auxiliary Control register (shared > > > attribute override enable) has the side effect of transforming Normal > > > Shared Non-cacheable reads into Cacheable no-allocate reads. > > > > > > Coherent DMA buffers in Linux always have a Cacheable alias via the > > > kernel linear mapping and the processor can speculatively load cache > > > lines into the PL310 controller. With bit 22 cleared, Non-cacheable > > > reads would unexpectedly hit such cache lines leading to buffer > > > corruption. > > > > Is this still the case with recent kernels? I thought the dma-mapping/cma > > work avoided the cacheable alias, but perhaps I'm mistaken. > > I haven't used CMA but DMA mappings are still normal memory > non-cacheable. Ok, so trawling through the list reveals we only have this issue for normal DMA mappings and not with CMA: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-October/124276.html I wonder whether we shouldn't just fix that, rather than work around it with a PL310-specific hack? Will ^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] Set bit 22 in the PL310 (cache controller) AuxCtlr register 2012-11-12 10:56 ` Will Deacon @ 2012-11-16 10:46 ` Shiraz Hashim 0 siblings, 0 replies; 3+ messages in thread From: Shiraz Hashim @ 2012-11-16 10:46 UTC (permalink / raw) To: linux-arm-kernel Hi Catalin, On Mon, Nov 12, 2012 at 10:56:41AM +0000, Will Deacon wrote: > On Mon, Nov 12, 2012 at 06:45:47AM +0000, Shiraz Hashim wrote: > > On Fri, Nov 09, 2012 at 09:54:01AM +0000, Will Deacon wrote: > > > On Fri, Nov 09, 2012 at 04:01:52AM +0000, Shiraz Hashim wrote: > > > > From: Catalin Marinas <catalin.marinas@arm.com> > > > > > > > > Clearing bit 22 in the PL310 Auxiliary Control register (shared > > > > attribute override enable) has the side effect of transforming Normal > > > > Shared Non-cacheable reads into Cacheable no-allocate reads. > > > > > > > > Coherent DMA buffers in Linux always have a Cacheable alias via the > > > > kernel linear mapping and the processor can speculatively load cache > > > > lines into the PL310 controller. With bit 22 cleared, Non-cacheable > > > > reads would unexpectedly hit such cache lines leading to buffer > > > > corruption. > > > > > > Is this still the case with recent kernels? I thought the dma-mapping/cma > > > work avoided the cacheable alias, but perhaps I'm mistaken. > > > > I haven't used CMA but DMA mappings are still normal memory > > non-cacheable. > > Ok, so trawling through the list reveals we only have this issue for normal > DMA mappings and not with CMA: > > http://lists.infradead.org/pipermail/linux-arm-kernel/2012-October/124276.html > > I wonder whether we shouldn't just fix that, rather than work around it with > a PL310-specific hack? What do you say? -- regards Shiraz ^ permalink raw reply [flat|nested] 3+ messages in thread
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2012-11-12 6:45 ` [PATCH] Set bit 22 in the PL310 (cache controller) AuxCtlr register Shiraz Hashim
2012-11-12 10:56 ` Will Deacon
2012-11-16 10:46 ` Shiraz Hashim
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