* [PATCH 1/6] clocksource: sunxi: Add Allwinner A1X Timer Driver
2012-11-15 22:46 [PATCH 0/6] Add basic support for Allwinner A1X SoCs Maxime Ripard
@ 2012-11-15 22:46 ` Maxime Ripard
2012-11-16 13:13 ` Thomas Petazzoni
2012-11-16 13:14 ` Thomas Petazzoni
2012-11-15 22:46 ` [PATCH 2/6] irqchip: sunxi: Add irq controller driver Maxime Ripard
` (7 subsequent siblings)
8 siblings, 2 replies; 25+ messages in thread
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: John Stultz <johnstul@us.ibm.com>
---
.../bindings/timer/allwinner,sunxi-timer.txt | 15 ++
drivers/clocksource/Kconfig | 3 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/sunxi_timer.c | 160 ++++++++++++++++++++
include/linux/sunxi_timer.h | 24 +++
5 files changed, 203 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
create mode 100644 drivers/clocksource/sunxi_timer.c
create mode 100644 include/linux/sunxi_timer.h
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
new file mode 100644
index 0000000..c6041ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
@@ -0,0 +1,15 @@
+Allwinner A1X SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "allwinner,sunxi-timer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer
+
+Example:
+
+timer {
+ compatible = "allwinner,sunxi-timer";
+ reg = <0x01c20c00 0x400>;
+ interrupts = <22>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 6a78073..a098573 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -22,6 +22,9 @@ config DW_APB_TIMER_OF
config ARMADA_370_XP_TIMER
bool
+config SUNXI_TIMER
+ bool
+
config CLKSRC_DBX500_PRCMU
bool "Clocksource PRCMU Timer"
depends on UX500_SOC_DB8500
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 603be36..36f06de 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
+obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o
obj-$(CONFIG_CLKSRC_ARM_GENERIC) += arm_generic.o
diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sunxi_timer.c
new file mode 100644
index 0000000..5dd5b48
--- /dev/null
+++ b/drivers/clocksource/sunxi_timer.c
@@ -0,0 +1,160 @@
+/*
+ * Allwinner A1X SoCs timer handling.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Benn Huang <benn@allwinnertech.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sunxi_timer.h>
+
+#define TIMER_CTL_REG 0x00
+#define TIMER_CTL_ENABLE (1 << 0)
+#define TIMER_IRQ_ST_REG 0x04
+#define TIMER0_CTL_REG 0x10
+#define TIMER0_CTL_ENABLE (1 << 0)
+#define TIMER0_CTL_AUTORELOAD (1 << 1)
+#define TIMER0_CTL_ONESHOT (1 << 7)
+#define TIMER0_INTVAL_REG 0x14
+#define TIMER0_CNTVAL_REG 0x18
+
+#define TIMER_CLKSRC 24000000
+#define TIMER_SCAL 16
+#define TIMER_INTERVAL (TIMER_CLKSRC / (TIMER_SCAL * HZ))
+
+static void __iomem *timer_base;
+
+static void sunxi_clkevt_mode(enum clock_event_mode mode,
+ struct clock_event_device *clk)
+{
+ u32 u = readl(timer_base + TIMER0_CTL_REG);
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ writel(TIMER_INTERVAL, timer_base + TIMER0_INTVAL_REG);
+ u &= ~(TIMER0_CTL_ONESHOT);
+ writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG);
+ break;
+
+ case CLOCK_EVT_MODE_ONESHOT:
+ writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG);
+ break;
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ default:
+ writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG);
+ break;
+ }
+}
+
+static int sunxi_clkevt_next_event(unsigned long evt,
+ struct clock_event_device *unused)
+{
+ u32 u = readl(timer_base + TIMER0_CTL_REG);
+ writel(evt, timer_base + TIMER0_CNTVAL_REG);
+ writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD,
+ timer_base + TIMER0_CTL_REG);
+
+ return 0;
+}
+
+static struct clock_event_device sunxi_clockevent = {
+ .name = "sunxi_tick",
+ .shift = 32,
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_mode = sunxi_clkevt_mode,
+ .set_next_event = sunxi_clkevt_next_event,
+};
+
+
+static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+
+ writel(0x1, timer_base + TIMER_IRQ_ST_REG);
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction sunxi_timer_irq = {
+ .name = "sunxi_timer0",
+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ .handler = sunxi_timer_interrupt,
+ .dev_id = &sunxi_clockevent,
+};
+
+static struct of_device_id sunxi_timer_dt_ids[] = {
+ { .compatible = "allwinner,sunxi-timer" },
+};
+
+static void __init sunxi_timer_init(void)
+{
+ struct device_node *node;
+ int ret, irq;
+ u32 val;
+
+ node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
+ if (!node)
+ panic("No sunxi timer node");
+
+ timer_base = of_iomap(node, 0);
+ if (!timer_base)
+ panic("Can't map registers");
+
+ irq = irq_of_parse_and_map(node, 0);
+ if (irq <= 0)
+ panic("Can't parse IRQ");
+
+ writel(TIMER_INTERVAL, timer_base + TIMER0_INTVAL_REG);
+
+ /* set clock source to HOSC, 16 pre-division */
+ val = readl(timer_base + TIMER0_CTL_REG);
+ val &= ~(0x07 << 4);
+ val &= ~(0x03 << 2);
+ val |= (4 << 4) | (1 << 2);
+ writel(val, timer_base + TIMER0_CTL_REG);
+
+ /* set mode to auto reload */
+ val = readl(timer_base + TIMER0_CTL_REG);
+ writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
+
+ ret = setup_irq(irq, &sunxi_timer_irq);
+ if (ret)
+ pr_warn("failed to setup irq %d\n", irq);
+
+ /* Enable timer0 interrupt */
+ val = readl(timer_base + TIMER_CTL_REG);
+ writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
+
+ sunxi_clockevent.mult = div_sc(TIMER_CLKSRC / TIMER_SCAL,
+ NSEC_PER_SEC,
+ sunxi_clockevent.shift);
+ sunxi_clockevent.max_delta_ns = clockevent_delta2ns(0xff,
+ &sunxi_clockevent);
+ sunxi_clockevent.min_delta_ns = clockevent_delta2ns(0x1,
+ &sunxi_clockevent);
+ sunxi_clockevent.cpumask = cpumask_of(0);
+
+ clockevents_register_device(&sunxi_clockevent);
+}
+
+struct sys_timer sunxi_timer = {
+ .init = sunxi_timer_init,
+};
diff --git a/include/linux/sunxi_timer.h b/include/linux/sunxi_timer.h
new file mode 100644
index 0000000..b9165bb
--- /dev/null
+++ b/include/linux/sunxi_timer.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SUNXI_TIMER_H
+#define __SUNXI_TIMER_H
+
+#include <asm/mach/time.h>
+
+extern struct sys_timer sunxi_timer;
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 1/6] clocksource: sunxi: Add Allwinner A1X Timer Driver
2012-11-15 22:46 ` [PATCH 1/6] clocksource: sunxi: Add Allwinner A1X Timer Driver Maxime Ripard
@ 2012-11-16 13:13 ` Thomas Petazzoni
2012-11-16 13:14 ` Thomas Petazzoni
1 sibling, 0 replies; 25+ messages in thread
From: Thomas Petazzoni @ 2012-11-16 13:13 UTC (permalink / raw)
To: linux-arm-kernel
Dear Maxime Ripard,
On Thu, 15 Nov 2012 23:46:20 +0100, Maxime Ripard wrote:
> +#define TIMER_CLKSRC 24000000
You should rather add a DT node for this fixed rate clock, and pass a
clocks = <&fooclk> DT property to your timer DT node, and then in your
timer driver do an of_clk_get() + clk_get_rate() to get the frequency
of this.
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 1/6] clocksource: sunxi: Add Allwinner A1X Timer Driver
2012-11-15 22:46 ` [PATCH 1/6] clocksource: sunxi: Add Allwinner A1X Timer Driver Maxime Ripard
2012-11-16 13:13 ` Thomas Petazzoni
@ 2012-11-16 13:14 ` Thomas Petazzoni
1 sibling, 0 replies; 25+ messages in thread
From: Thomas Petazzoni @ 2012-11-16 13:14 UTC (permalink / raw)
To: linux-arm-kernel
Dear Maxime Ripard,
On Thu, 15 Nov 2012 23:46:20 +0100, Maxime Ripard wrote:
> + /* Enable timer0 interrupt */
> + val = readl(timer_base + TIMER_CTL_REG);
> + writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
> +
> + sunxi_clockevent.mult = div_sc(TIMER_CLKSRC / TIMER_SCAL,
> + NSEC_PER_SEC,
> + sunxi_clockevent.shift);
> + sunxi_clockevent.max_delta_ns = clockevent_delta2ns(0xff,
> + &sunxi_clockevent);
> + sunxi_clockevent.min_delta_ns = clockevent_delta2ns(0x1,
> + &sunxi_clockevent);
> + sunxi_clockevent.cpumask = cpumask_of(0);
> +
> + clockevents_register_device(&sunxi_clockevent);
I haven't looked in details, but maybe it is possible here to use
clockevents_config_and_register() instead of
clockevents_register_device(). It would simplify this code a bit if it
works.
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 2/6] irqchip: sunxi: Add irq controller driver
2012-11-15 22:46 [PATCH 0/6] Add basic support for Allwinner A1X SoCs Maxime Ripard
2012-11-15 22:46 ` [PATCH 1/6] clocksource: sunxi: Add Allwinner A1X Timer Driver Maxime Ripard
@ 2012-11-15 22:46 ` Maxime Ripard
2012-11-16 7:35 ` Stefan Roese
2012-11-15 22:46 ` [PATCH 3/6] ARM: sunxi: Add basic support for Allwinner A1x SoCs Maxime Ripard
` (6 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
CC: Thomas Gleixner <tglx@linutronix.de>
---
.../interrupt-controller/allwinner,sunxi-ic.txt | 104 ++++++++++++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-sunxi.c | 173 ++++++++++++++++++++
include/linux/irqchip/sunxi.h | 27 +++
4 files changed, 305 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
create mode 100644 drivers/irqchip/irq-sunxi.c
create mode 100644 include/linux/irqchip/sunxi.h
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
new file mode 100644
index 0000000..7f9fb85
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
@@ -0,0 +1,104 @@
+Allwinner Sunxi Interrupt Controller
+
+Required properties:
+
+- compatible : should be "allwinner,sunxi-ic"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+The interrupt sources are as follows:
+
+0: ENMI
+1: UART0
+2: UART1
+3: UART2
+4: UART3
+5: IR0
+6: IR1
+7: I2C0
+8: I2C1
+9: I2C2
+10: SPI0
+11: SPI1
+12: SPI2
+13: SPDIF
+14: AC97
+15: TS
+16: I2S
+17: UART4
+18: UART5
+19: UART6
+20: UART7
+21: KEYPAD
+22: TIMER0
+23: TIMER1
+24: TIMER2
+25: TIMER3
+26: CAN
+27: DMA
+28: PIO
+29: TOUCH_PANEL
+30: AUDIO_CODEC
+31: LRADC
+32: SDMC0
+33: SDMC1
+34: SDMC2
+35: SDMC3
+36: MEMSTICK
+37: NAND
+38: USB0
+39: USB1
+40: USB2
+41: SCR
+42: CSI0
+43: CSI1
+44: LCDCTRL0
+45: LCDCTRL1
+46: MP
+47: DEFEBE0
+48: DEFEBE1
+49: PMU
+50: SPI3
+51: TZASC
+52: PATA
+53: VE
+54: SS
+55: EMAC
+56: SATA
+57: GPS
+58: HDMI
+59: TVE
+60: ACE
+61: TVD
+62: PS2_0
+63: PS2_1
+64: USB3
+65: USB4
+66: PLE_PFM
+67: TIMER4
+68: TIMER5
+69: GPU_GP
+70: GPU_GPMMU
+71: GPU_PP0
+72: GPU_PPMMU0
+73: GPU_PMU
+74: GPU_RSV0
+75: GPU_RSV1
+76: GPU_RSV2
+77: GPU_RSV3
+78: GPU_RSV4
+79: GPU_RSV5
+80: GPU_RSV6
+82: SYNC_TIMER0
+83: SYNC_TIMER1
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "allwinner,sunxi-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 054321d..2444d07 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
+obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
diff --git a/drivers/irqchip/irq-sunxi.c b/drivers/irqchip/irq-sunxi.c
new file mode 100644
index 0000000..9dcb323
--- /dev/null
+++ b/drivers/irqchip/irq-sunxi.c
@@ -0,0 +1,173 @@
+/*
+ * Allwinner A1X SoCs IRQ chip driver.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Benn Huang <benn@allwinnertech.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <linux/irqchip/sunxi.h>
+
+#define SUNXI_IRQ_PROTECTION_REG 0x08
+#define SUNXI_IRQ_NMI_CTRL_REG 0x0c
+#define SUNXI_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
+#define SUNXI_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
+#define SUNXI_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
+#define SUNXI_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
+
+static void __iomem *sunxi_irq_base;
+static struct irq_domain *sunxi_irq_domain;
+
+void sunxi_irq_ack(struct irq_data *irqd)
+{
+ unsigned int irq = irqd_to_hwirq(irqd);
+ unsigned int irq_off = irq % 32;
+ int reg = irq / 32;
+ u32 val;
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+ writel(val & ~(1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+ writel(val | (1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
+ writel(val | (1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
+}
+
+static void sunxi_irq_mask(struct irq_data *irqd)
+{
+ unsigned int irq = irqd_to_hwirq(irqd);
+ unsigned int irq_off = irq % 32;
+ int reg = irq / 32;
+ u32 val;
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+ writel(val & ~(1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+ writel(val | (1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+}
+
+static void sunxi_irq_unmask(struct irq_data *irqd)
+{
+ unsigned int irq = irqd_to_hwirq(irqd);
+ unsigned int irq_off = irq % 32;
+ int reg = irq / 32;
+ u32 val;
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+ writel(val | (1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+ writel(val & ~(1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+
+ /* Must clear pending bit when enabled */
+ if (irq == 0)
+ writel(1, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
+}
+
+static struct irq_chip sunxi_irq_chip = {
+ .name = "sunxi_irq",
+ .irq_ack = sunxi_irq_ack,
+ .irq_mask = sunxi_irq_mask,
+ .irq_unmask = sunxi_irq_unmask,
+};
+
+static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ irq_set_chip(virq, &sunxi_irq_chip);
+ irq_set_handler(virq, handle_level_irq);
+ set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+ return 0;
+}
+
+static struct irq_domain_ops sunxi_irq_ops = {
+ .map = sunxi_irq_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init sunxi_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ sunxi_irq_base = of_iomap(node, 0);
+ if (!sunxi_irq_base)
+ panic("%s: unable to map IC registers\n",
+ node->full_name);
+
+ /* Disable all interrupts */
+ writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
+ writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
+ writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
+
+ /* Mask all the interrupts */
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
+
+ /* Clear all the pending interrupts */
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
+
+ /* Enable protection mode */
+ writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
+
+ /* Configure the external interrupt source type */
+ writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
+
+ sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
+ &sunxi_irq_ops, NULL);
+ if (!sunxi_irq_domain)
+ panic("%s: unable to create IRQ domain\n", node->full_name);
+
+ return 0;
+}
+
+static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
+ { .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init }
+};
+
+void __init sunxi_init_irq(void)
+{
+ of_irq_init(sunxi_irq_dt_ids);
+}
+
+asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
+{
+ u32 irq, reg;
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ reg = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(i));
+ if (reg == 0)
+ continue;
+ irq = ilog2(reg);
+ break;
+ }
+ irq = irq_find_mapping(sunxi_irq_domain, irq);
+ handle_IRQ(irq, regs);
+}
diff --git a/include/linux/irqchip/sunxi.h b/include/linux/irqchip/sunxi.h
new file mode 100644
index 0000000..1fe2c22
--- /dev/null
+++ b/include/linux/irqchip/sunxi.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_IRQCHIP_SUNXI_H
+#define __LINUX_IRQCHIP_SUNXI_H
+
+#include <asm/exception.h>
+
+extern void sunxi_init_irq(void);
+
+extern asmlinkage void __exception_irq_entry sunxi_handle_irq(
+ struct pt_regs *regs);
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 2/6] irqchip: sunxi: Add irq controller driver
2012-11-15 22:46 ` [PATCH 2/6] irqchip: sunxi: Add irq controller driver Maxime Ripard
@ 2012-11-16 7:35 ` Stefan Roese
2012-11-16 9:16 ` Maxime Ripard
0 siblings, 1 reply; 25+ messages in thread
From: Stefan Roese @ 2012-11-16 7:35 UTC (permalink / raw)
To: linux-arm-kernel
On 11/15/2012 11:46 PM, Maxime Ripard wrote:
<snip>
> diff --git a/drivers/irqchip/irq-sunxi.c b/drivers/irqchip/irq-sunxi.c
> new file mode 100644
> index 0000000..9dcb323
> --- /dev/null
> +++ b/drivers/irqchip/irq-sunxi.c
> @@ -0,0 +1,173 @@
> +/*
> + * Allwinner A1X SoCs IRQ chip driver.
> + *
> + * Copyright (C) 2012 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * Based on code from
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Benn Huang <benn@allwinnertech.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +#include <linux/irqchip/sunxi.h>
> +
> +#define SUNXI_IRQ_PROTECTION_REG 0x08
> +#define SUNXI_IRQ_NMI_CTRL_REG 0x0c
> +#define SUNXI_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
> +#define SUNXI_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
> +#define SUNXI_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
> +#define SUNXI_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
> +
> +static void __iomem *sunxi_irq_base;
> +static struct irq_domain *sunxi_irq_domain;
> +
> +void sunxi_irq_ack(struct irq_data *irqd)
> +{
> + unsigned int irq = irqd_to_hwirq(irqd);
> + unsigned int irq_off = irq % 32;
> + int reg = irq / 32;
> + u32 val;
> +
> + val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
> + writel(val & ~(1 << irq_off),
> + sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
> +
> + val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
> + writel(val | (1 << irq_off),
> + sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
> +
> + val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
> + writel(val | (1 << irq_off),
> + sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
Are you sure that you need to touch all those 23registers to ack the
interrupt? I know that the original code provided by Allwinner does
exactly this. My tests have shown though, that writing to the pending
reg is enough.
> +}
> +
> +static void sunxi_irq_mask(struct irq_data *irqd)
> +{
> + unsigned int irq = irqd_to_hwirq(irqd);
> + unsigned int irq_off = irq % 32;
> + int reg = irq / 32;
> + u32 val;
> +
> + val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
> + writel(val & ~(1 << irq_off),
> + sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
> +
> + val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
> + writel(val | (1 << irq_off),
> + sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
I unmasked all interrupts in the mask register in the init function.
Then only using the enable register for masking/unmasking seems to be
enough. What do you think?
> +}
> +
> +static void sunxi_irq_unmask(struct irq_data *irqd)
> +{
> + unsigned int irq = irqd_to_hwirq(irqd);
> + unsigned int irq_off = irq % 32;
> + int reg = irq / 32;
> + u32 val;
> +
> + val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
> + writel(val | (1 << irq_off),
> + sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
> +
> + val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
> + writel(val & ~(1 << irq_off),
> + sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
> +
> + /* Must clear pending bit when enabled */
> + if (irq == 0)
> + writel(1, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
Again. Might be that one register is enough here.
> +}
> +
> +static struct irq_chip sunxi_irq_chip = {
> + .name = "sunxi_irq",
> + .irq_ack = sunxi_irq_ack,
> + .irq_mask = sunxi_irq_mask,
> + .irq_unmask = sunxi_irq_unmask,
> +};
> +
> +static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
> + irq_hw_number_t hw)
> +{
> + irq_set_chip(virq, &sunxi_irq_chip);
> + irq_set_handler(virq, handle_level_irq);
irq_set_chip_and_handler()
> + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
> +
> + return 0;
> +}
> +
> +static struct irq_domain_ops sunxi_irq_ops = {
> + .map = sunxi_irq_map,
> + .xlate = irq_domain_xlate_onecell,
> +};
> +
> +static int __init sunxi_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + sunxi_irq_base = of_iomap(node, 0);
> + if (!sunxi_irq_base)
> + panic("%s: unable to map IC registers\n",
> + node->full_name);
> +
> + /* Disable all interrupts */
> + writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
> + writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
> + writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
> +
> + /* Mask all the interrupts */
> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
Here is where I wrote 0 to the mask registers.
> + /* Clear all the pending interrupts */
> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
> +
> + /* Enable protection mode */
> + writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
> +
> + /* Configure the external interrupt source type */
> + writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
> +
> + sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
> + &sunxi_irq_ops, NULL);
> + if (!sunxi_irq_domain)
> + panic("%s: unable to create IRQ domain\n", node->full_name);
> +
> + return 0;
> +}
> +
> +static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
> + { .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init }
> +};
> +
> +void __init sunxi_init_irq(void)
> +{
> + of_irq_init(sunxi_irq_dt_ids);
> +}
> +
> +asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
> +{
> + u32 irq, reg;
> + int i;
> +
> + for (i = 0; i < 3; i++) {
> + reg = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(i));
> + if (reg == 0)
> + continue;
> + irq = ilog2(reg);
> + break;
> + }
> + irq = irq_find_mapping(sunxi_irq_domain, irq);
> + handle_IRQ(irq, regs);
Why don't you use the interrupt-vector register to get the active
interrupt source? Here is my version:
asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
{
u32 irq;
irq = readl(int_base + SW_INT_VECTOR_REG) >> 2;
irq = irq_find_mapping(sunxi_vic_domain, irq);
handle_IRQ(irq, regs);
}
I suggest you give it a try.
Cheers,
Stefan
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 2/6] irqchip: sunxi: Add irq controller driver
2012-11-16 7:35 ` Stefan Roese
@ 2012-11-16 9:16 ` Maxime Ripard
2012-11-16 10:38 ` Thomas Petazzoni
0 siblings, 1 reply; 25+ messages in thread
From: Maxime Ripard @ 2012-11-16 9:16 UTC (permalink / raw)
To: linux-arm-kernel
Hi Stefan,
Le 16/11/2012 08:35, Stefan Roese a ?crit :
> On 11/15/2012 11:46 PM, Maxime Ripard wrote:
>
> <snip>
>
>> diff --git a/drivers/irqchip/irq-sunxi.c b/drivers/irqchip/irq-sunxi.c
>> new file mode 100644
>> index 0000000..9dcb323
>> --- /dev/null
>> +++ b/drivers/irqchip/irq-sunxi.c
>> @@ -0,0 +1,173 @@
>> +/*
>> + * Allwinner A1X SoCs IRQ chip driver.
>> + *
>> + * Copyright (C) 2012 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>> + *
>> + * Based on code from
>> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
>> + * Benn Huang <benn@allwinnertech.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/irq.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +
>> +#include <linux/irqchip/sunxi.h>
>> +
>> +#define SUNXI_IRQ_PROTECTION_REG 0x08
>> +#define SUNXI_IRQ_NMI_CTRL_REG 0x0c
>> +#define SUNXI_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
>> +#define SUNXI_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
>> +#define SUNXI_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
>> +#define SUNXI_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
>> +
>> +static void __iomem *sunxi_irq_base;
>> +static struct irq_domain *sunxi_irq_domain;
>> +
>> +void sunxi_irq_ack(struct irq_data *irqd)
>> +{
>> + unsigned int irq = irqd_to_hwirq(irqd);
>> + unsigned int irq_off = irq % 32;
>> + int reg = irq / 32;
>> + u32 val;
>> +
>> + val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
>> + writel(val & ~(1 << irq_off),
>> + sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
>> +
>> + val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
>> + writel(val | (1 << irq_off),
>> + sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
>> +
>> + val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
>> + writel(val | (1 << irq_off),
>> + sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
>
> Are you sure that you need to touch all those 23registers to ack the
> interrupt? I know that the original code provided by Allwinner does
> exactly this. My tests have shown though, that writing to the pending
> reg is enough.
Ok, I'll test that and remove the first two writes then.
>
>> +}
>> +
>> +static void sunxi_irq_mask(struct irq_data *irqd)
>> +{
>> + unsigned int irq = irqd_to_hwirq(irqd);
>> + unsigned int irq_off = irq % 32;
>> + int reg = irq / 32;
>> + u32 val;
>> +
>> + val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
>> + writel(val & ~(1 << irq_off),
>> + sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
>> +
>> + val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
>> + writel(val | (1 << irq_off),
>> + sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
>
> I unmasked all interrupts in the mask register in the init function.
> Then only using the enable register for masking/unmasking seems to be
> enough. What do you think?
That's reasonable I guess. It will be in the v2.
>> +}
>> +
>> +static void sunxi_irq_unmask(struct irq_data *irqd)
>> +{
>> + unsigned int irq = irqd_to_hwirq(irqd);
>> + unsigned int irq_off = irq % 32;
>> + int reg = irq / 32;
>> + u32 val;
>> +
>> + val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
>> + writel(val | (1 << irq_off),
>> + sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
>> +
>> + val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
>> + writel(val & ~(1 << irq_off),
>> + sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
>> +
>> + /* Must clear pending bit when enabled */
>> + if (irq == 0)
>> + writel(1, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
>
> Again. Might be that one register is enough here.
Ok.
>> +}
>> +
>> +static struct irq_chip sunxi_irq_chip = {
>> + .name = "sunxi_irq",
>> + .irq_ack = sunxi_irq_ack,
>> + .irq_mask = sunxi_irq_mask,
>> + .irq_unmask = sunxi_irq_unmask,
>> +};
>> +
>> +static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
>> + irq_hw_number_t hw)
>> +{
>> + irq_set_chip(virq, &sunxi_irq_chip);
>> + irq_set_handler(virq, handle_level_irq);
>
> irq_set_chip_and_handler()
Ok.
>> + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
>> +
>> + return 0;
>> +}
>> +
>> +static struct irq_domain_ops sunxi_irq_ops = {
>> + .map = sunxi_irq_map,
>> + .xlate = irq_domain_xlate_onecell,
>> +};
>> +
>> +static int __init sunxi_of_init(struct device_node *node,
>> + struct device_node *parent)
>> +{
>> + sunxi_irq_base = of_iomap(node, 0);
>> + if (!sunxi_irq_base)
>> + panic("%s: unable to map IC registers\n",
>> + node->full_name);
>> +
>> + /* Disable all interrupts */
>> + writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
>> + writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
>> + writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
>> +
>> + /* Mask all the interrupts */
>> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
>> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
>> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
>
> Here is where I wrote 0 to the mask registers.
>
>> + /* Clear all the pending interrupts */
>> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
>> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
>> + writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
>> +
>> + /* Enable protection mode */
>> + writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
>> +
>> + /* Configure the external interrupt source type */
>> + writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
>> +
>> + sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
>> + &sunxi_irq_ops, NULL);
>> + if (!sunxi_irq_domain)
>> + panic("%s: unable to create IRQ domain\n", node->full_name);
>> +
>> + return 0;
>> +}
>> +
>> +static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
>> + { .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init }
>> +};
>> +
>> +void __init sunxi_init_irq(void)
>> +{
>> + of_irq_init(sunxi_irq_dt_ids);
>> +}
>> +
>> +asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
>> +{
>> + u32 irq, reg;
>> + int i;
>> +
>> + for (i = 0; i < 3; i++) {
>> + reg = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(i));
>> + if (reg == 0)
>> + continue;
>> + irq = ilog2(reg);
>> + break;
>> + }
>> + irq = irq_find_mapping(sunxi_irq_domain, irq);
>> + handle_IRQ(irq, regs);
>
> Why don't you use the interrupt-vector register to get the active
> interrupt source? Here is my version:
>
> asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
> {
> u32 irq;
>
> irq = readl(int_base + SW_INT_VECTOR_REG) >> 2;
> irq = irq_find_mapping(sunxi_vic_domain, irq);
> handle_IRQ(irq, regs);
> }
>
> I suggest you give it a try.
It definitely looks nicer. I'll try that and update.
Maxime
--
Maxime Ripard, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 2/6] irqchip: sunxi: Add irq controller driver
2012-11-16 9:16 ` Maxime Ripard
@ 2012-11-16 10:38 ` Thomas Petazzoni
2012-11-16 10:47 ` Stefan Roese
0 siblings, 1 reply; 25+ messages in thread
From: Thomas Petazzoni @ 2012-11-16 10:38 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 16 Nov 2012 10:16:42 +0100, Maxime Ripard wrote:
> >> +asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
> >> +{
> >> + u32 irq, reg;
> >> + int i;
> >> +
> >> + for (i = 0; i < 3; i++) {
> >> + reg = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(i));
> >> + if (reg == 0)
> >> + continue;
> >> + irq = ilog2(reg);
> >> + break;
> >> + }
> >> + irq = irq_find_mapping(sunxi_irq_domain, irq);
> >> + handle_IRQ(irq, regs);
> >
> > Why don't you use the interrupt-vector register to get the active
> > interrupt source? Here is my version:
> >
> > asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
> > {
> > u32 irq;
> >
> > irq = readl(int_base + SW_INT_VECTOR_REG) >> 2;
> > irq = irq_find_mapping(sunxi_vic_domain, irq);
> > handle_IRQ(irq, regs);
> > }
> >
> > I suggest you give it a try.
>
> It definitely looks nicer. I'll try that and update.
How does this SW_INT_VECTOR_REG behave when there are multiple
interrupts pending? Shouldn't the code be something like:
do {
hwirq = readl(int_base + SW_INT_VECTOR_REG) >> 2;
irq = irq_find_mapping(sunxi_vic_domain, hwirq);
handle_IRQ(irq, regs);
} while(hwirq != 0);
Or maybe the != 0 is not the good condition, but the idea is to handle
all pending interrupts. That said, the original code from Maxime was
not doing that as well.
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 2/6] irqchip: sunxi: Add irq controller driver
2012-11-16 10:38 ` Thomas Petazzoni
@ 2012-11-16 10:47 ` Stefan Roese
0 siblings, 0 replies; 25+ messages in thread
From: Stefan Roese @ 2012-11-16 10:47 UTC (permalink / raw)
To: linux-arm-kernel
On 11/16/2012 11:38 AM, Thomas Petazzoni wrote:
>>> asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
>>> {
>>> u32 irq;
>>>
>>> irq = readl(int_base + SW_INT_VECTOR_REG) >> 2;
>>> irq = irq_find_mapping(sunxi_vic_domain, irq);
>>> handle_IRQ(irq, regs);
>>> }
>>>
>>> I suggest you give it a try.
>>
>> It definitely looks nicer. I'll try that and update.
>
> How does this SW_INT_VECTOR_REG behave when there are multiple
> interrupts pending?
Not 100% sure. Hard to guess with this sparse documentation. I would
expect that multiple interrupts would be queued here.
> Shouldn't the code be something like:
>
> do {
> hwirq = readl(int_base + SW_INT_VECTOR_REG) >> 2;
> irq = irq_find_mapping(sunxi_vic_domain, hwirq);
> handle_IRQ(irq, regs);
> } while(hwirq != 0);
>
> Or maybe the != 0 is not the good condition, but the idea is to handle
> all pending interrupts. That said, the original code from Maxime was
> not doing that as well.
Yes, that would be a good change.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 3/6] ARM: sunxi: Add basic support for Allwinner A1x SoCs
2012-11-15 22:46 [PATCH 0/6] Add basic support for Allwinner A1X SoCs Maxime Ripard
2012-11-15 22:46 ` [PATCH 1/6] clocksource: sunxi: Add Allwinner A1X Timer Driver Maxime Ripard
2012-11-15 22:46 ` [PATCH 2/6] irqchip: sunxi: Add irq controller driver Maxime Ripard
@ 2012-11-15 22:46 ` Maxime Ripard
2012-11-16 7:42 ` Stefan Roese
2012-11-15 22:46 ` [PATCH 4/6] ARM: sunxi: Add earlyprintk support Maxime Ripard
` (5 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/Kconfig | 2 ++
arch/arm/Makefile | 1 +
arch/arm/mach-sunxi/Kconfig | 9 ++++++
arch/arm/mach-sunxi/Makefile | 1 +
arch/arm/mach-sunxi/Makefile.boot | 1 +
arch/arm/mach-sunxi/sunxi.c | 60 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-sunxi/sunxi.h | 20 +++++++++++++
7 files changed, 94 insertions(+)
create mode 100644 arch/arm/mach-sunxi/Kconfig
create mode 100644 arch/arm/mach-sunxi/Makefile
create mode 100644 arch/arm/mach-sunxi/Makefile.boot
create mode 100644 arch/arm/mach-sunxi/sunxi.c
create mode 100644 arch/arm/mach-sunxi/sunxi.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ade7e92..1abb573 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1113,6 +1113,8 @@ source "arch/arm/mach-exynos/Kconfig"
source "arch/arm/mach-shmobile/Kconfig"
+source "arch/arm/mach-sunxi/Kconfig"
+
source "arch/arm/mach-prima2/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5f914fc..363320a 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -193,6 +193,7 @@ machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx
machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx
machine-$(CONFIG_MACH_SPEAR600) += spear6xx
machine-$(CONFIG_ARCH_ZYNQ) += zynq
+machine-$(CONFIG_ARCH_SUNXI) += sunxi
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
new file mode 100644
index 0000000..3fdd008
--- /dev/null
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -0,0 +1,9 @@
+config ARCH_SUNXI
+ bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
+ select CLKSRC_MMIO
+ select COMMON_CLK
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_IRQ_CHIP
+ select PINCTRL
+ select SPARSE_IRQ
+ select SUNXI_TIMER
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
new file mode 100644
index 0000000..93bebfc
--- /dev/null
+++ b/arch/arm/mach-sunxi/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
diff --git a/arch/arm/mach-sunxi/Makefile.boot b/arch/arm/mach-sunxi/Makefile.boot
new file mode 100644
index 0000000..46d4cf0
--- /dev/null
+++ b/arch/arm/mach-sunxi/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-$(CONFIG_ARCH_SUNXI) += 0x40008000
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
new file mode 100644
index 0000000..8f42df8
--- /dev/null
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -0,0 +1,60 @@
+/*
+ * Device Tree support for Allwinner A1X SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/sunxi_timer.h>
+
+#include <linux/irqchip/sunxi.h>
+
+#include <asm/hardware/vic.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "sunxi.h"
+
+static struct map_desc sunxi_io_desc[] __initdata = {
+ {
+ .virtual = (unsigned long) SUNXI_REGS_VIRT_BASE,
+ .pfn = __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
+ .length = SUNXI_REGS_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+
+void __init sunxi_map_io(void)
+{
+ iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
+}
+
+static void __init sunxi_dt_init(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const sunxi_board_dt_compat[] = {
+ "allwinner,sun5i",
+ NULL,
+};
+
+DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
+ .init_machine = sunxi_dt_init,
+ .map_io = sunxi_map_io,
+ .init_irq = sunxi_init_irq,
+ .handle_irq = sunxi_handle_irq,
+ .timer = &sunxi_timer,
+ .dt_compat = sunxi_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-sunxi/sunxi.h b/arch/arm/mach-sunxi/sunxi.h
new file mode 100644
index 0000000..33b5871
--- /dev/null
+++ b/arch/arm/mach-sunxi/sunxi.h
@@ -0,0 +1,20 @@
+/*
+ * Generic definitions for Allwinner SunXi SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SUNXI_H
+#define __MACH_SUNXI_H
+
+#define SUNXI_REGS_PHYS_BASE 0x01c00000
+#define SUNXI_REGS_VIRT_BASE IOMEM(0xf1c00000)
+#define SUNXI_REGS_SIZE (SZ_2M + SZ_1M)
+
+#endif /* __MACH_SUNXI_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 4/6] ARM: sunxi: Add earlyprintk support
2012-11-15 22:46 [PATCH 0/6] Add basic support for Allwinner A1X SoCs Maxime Ripard
` (2 preceding siblings ...)
2012-11-15 22:46 ` [PATCH 3/6] ARM: sunxi: Add basic support for Allwinner A1x SoCs Maxime Ripard
@ 2012-11-15 22:46 ` Maxime Ripard
2012-11-16 7:47 ` Stefan Roese
2012-11-16 10:41 ` Thomas Petazzoni
2012-11-15 22:46 ` [PATCH 5/6] ARM: sunxi: Add device tree for the A13 and the Olinuxino board Maxime Ripard
` (4 subsequent siblings)
8 siblings, 2 replies; 25+ messages in thread
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/Kconfig.debug | 8 ++++++++
arch/arm/include/debug/sunxi.S | 22 ++++++++++++++++++++++
2 files changed, 30 insertions(+)
create mode 100644 arch/arm/include/debug/sunxi.S
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b0f3857..6672b02 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -345,6 +345,13 @@ choice
Say Y here if you want kernel low-level debugging support
on SOCFPGA based platforms.
+ config DEBUG_SUNXI_UART
+ bool "Kernel low-level debugging messages via sunXi UART"
+ depends on ARCH_SUNXI
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Allwinner A1X based platforms.
+
config DEBUG_VEXPRESS_UART0_DETECT
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -416,6 +423,7 @@ config DEBUG_LL_INCLUDE
default "debug/mvebu.S" if DEBUG_MVEBU_UART
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
+ default "debug/sunxi.S" if DEBUG_SUNXI_UART
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
default "mach/debug-macro.S"
diff --git a/arch/arm/include/debug/sunxi.S b/arch/arm/include/debug/sunxi.S
new file mode 100644
index 0000000..ffd101f
--- /dev/null
+++ b/arch/arm/include/debug/sunxi.S
@@ -0,0 +1,22 @@
+/*
+ * Early serial output macro for Allwinner A1X SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define SUNXI_UART1_PHYS_BASE 0x01c28400
+#define SUNXI_UART1_VIRT_BASE 0xf1c28400
+
+ .macro addruart, rp, rv, tmp
+ ldr \rp, =SUNXI_UART1_PHYS_BASE
+ ldr \rv, =SUNXI_UART1_VIRT_BASE
+ .endm
+
+#define UART_SHIFT 2
+#include <asm/hardware/debug-8250.S>
--
1.7.9.5
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 4/6] ARM: sunxi: Add earlyprintk support
2012-11-15 22:46 ` [PATCH 4/6] ARM: sunxi: Add earlyprintk support Maxime Ripard
@ 2012-11-16 7:47 ` Stefan Roese
2012-11-16 9:20 ` Maxime Ripard
2012-11-16 10:41 ` Thomas Petazzoni
1 sibling, 1 reply; 25+ messages in thread
From: Stefan Roese @ 2012-11-16 7:47 UTC (permalink / raw)
To: linux-arm-kernel
On 11/15/2012 11:46 PM, Maxime Ripard wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/Kconfig.debug | 8 ++++++++
> arch/arm/include/debug/sunxi.S | 22 ++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
> create mode 100644 arch/arm/include/debug/sunxi.S
>
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index b0f3857..6672b02 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -345,6 +345,13 @@ choice
> Say Y here if you want kernel low-level debugging support
> on SOCFPGA based platforms.
>
> + config DEBUG_SUNXI_UART
> + bool "Kernel low-level debugging messages via sunXi UART"
> + depends on ARCH_SUNXI
> + help
> + Say Y here if you want kernel low-level debugging support
> + on Allwinner A1X based platforms.
>
> config DEBUG_VEXPRESS_UART0_DETECT
> bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
> depends on ARCH_VEXPRESS && CPU_CP15_MMU
> @@ -416,6 +423,7 @@ config DEBUG_LL_INCLUDE
> default "debug/mvebu.S" if DEBUG_MVEBU_UART
> default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
> default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
> + default "debug/sunxi.S" if DEBUG_SUNXI_UART
> default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
> DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
> default "mach/debug-macro.S"
> diff --git a/arch/arm/include/debug/sunxi.S b/arch/arm/include/debug/sunxi.S
> new file mode 100644
> index 0000000..ffd101f
> --- /dev/null
> +++ b/arch/arm/include/debug/sunxi.S
> @@ -0,0 +1,22 @@
> +/*
> + * Early serial output macro for Allwinner A1X SoCs
> + *
> + * Copyright (C) 2012 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#define SUNXI_UART1_PHYS_BASE 0x01c28400
> +#define SUNXI_UART1_VIRT_BASE 0xf1c28400
> +
> + .macro addruart, rp, rv, tmp
> + ldr \rp, =SUNXI_UART1_PHYS_BASE
> + ldr \rv, =SUNXI_UART1_VIRT_BASE
> + .endm
> +
> +#define UART_SHIFT 2
> +#include <asm/hardware/debug-8250.S>
A10 (cubieboard) has debug the UART on UART0 instead of UART1 as on A13.
So we need support this here as well. I suggest that I add support debug
on UART0 with my cubieboard patches.
So:
Acked-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 4/6] ARM: sunxi: Add earlyprintk support
2012-11-16 7:47 ` Stefan Roese
@ 2012-11-16 9:20 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2012-11-16 9:20 UTC (permalink / raw)
To: linux-arm-kernel
Le 16/11/2012 08:47, Stefan Roese a ?crit :
> On 11/15/2012 11:46 PM, Maxime Ripard wrote:
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>> arch/arm/Kconfig.debug | 8 ++++++++
>> arch/arm/include/debug/sunxi.S | 22 ++++++++++++++++++++++
>> 2 files changed, 30 insertions(+)
>> create mode 100644 arch/arm/include/debug/sunxi.S
>>
>> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
>> index b0f3857..6672b02 100644
>> --- a/arch/arm/Kconfig.debug
>> +++ b/arch/arm/Kconfig.debug
>> @@ -345,6 +345,13 @@ choice
>> Say Y here if you want kernel low-level debugging support
>> on SOCFPGA based platforms.
>>
>> + config DEBUG_SUNXI_UART
>> + bool "Kernel low-level debugging messages via sunXi UART"
>> + depends on ARCH_SUNXI
>> + help
>> + Say Y here if you want kernel low-level debugging support
>> + on Allwinner A1X based platforms.
>>
>> config DEBUG_VEXPRESS_UART0_DETECT
>> bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
>> depends on ARCH_VEXPRESS && CPU_CP15_MMU
>> @@ -416,6 +423,7 @@ config DEBUG_LL_INCLUDE
>> default "debug/mvebu.S" if DEBUG_MVEBU_UART
>> default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
>> default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
>> + default "debug/sunxi.S" if DEBUG_SUNXI_UART
>> default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
>> DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
>> default "mach/debug-macro.S"
>> diff --git a/arch/arm/include/debug/sunxi.S b/arch/arm/include/debug/sunxi.S
>> new file mode 100644
>> index 0000000..ffd101f
>> --- /dev/null
>> +++ b/arch/arm/include/debug/sunxi.S
>> @@ -0,0 +1,22 @@
>> +/*
>> + * Early serial output macro for Allwinner A1X SoCs
>> + *
>> + * Copyright (C) 2012 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +#define SUNXI_UART1_PHYS_BASE 0x01c28400
>> +#define SUNXI_UART1_VIRT_BASE 0xf1c28400
>> +
>> + .macro addruart, rp, rv, tmp
>> + ldr \rp, =SUNXI_UART1_PHYS_BASE
>> + ldr \rv, =SUNXI_UART1_VIRT_BASE
>> + .endm
>> +
>> +#define UART_SHIFT 2
>> +#include <asm/hardware/debug-8250.S>
>
> A10 (cubieboard) has debug the UART on UART0 instead of UART1 as on A13.
> So we need support this here as well. I suggest that I add support debug
> on UART0 with my cubieboard patches.
Ok, we'll do it that way then. Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 4/6] ARM: sunxi: Add earlyprintk support
2012-11-15 22:46 ` [PATCH 4/6] ARM: sunxi: Add earlyprintk support Maxime Ripard
2012-11-16 7:47 ` Stefan Roese
@ 2012-11-16 10:41 ` Thomas Petazzoni
1 sibling, 0 replies; 25+ messages in thread
From: Thomas Petazzoni @ 2012-11-16 10:41 UTC (permalink / raw)
To: linux-arm-kernel
Dear Maxime Ripard,
On Thu, 15 Nov 2012 23:46:23 +0100, Maxime Ripard wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/Kconfig.debug | 8 ++++++++
> arch/arm/include/debug/sunxi.S | 22 ++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
> create mode 100644 arch/arm/include/debug/sunxi.S
>
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index b0f3857..6672b02 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -345,6 +345,13 @@ choice
> Say Y here if you want kernel low-level debugging support
> on SOCFPGA based platforms.
>
> + config DEBUG_SUNXI_UART
Should be DEBUG_SUNXI_UART1
> + bool "Kernel low-level debugging messages via sunXi UART"
UART1.
> + depends on ARCH_SUNXI
> + help
> + Say Y here if you want kernel low-level debugging support
> + on Allwinner A1X based platforms.
Say a few words about UART1 here.
> +
> config DEBUG_VEXPRESS_UART0_DETECT
> bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
> depends on ARCH_VEXPRESS && CPU_CP15_MMU
> @@ -416,6 +423,7 @@ config DEBUG_LL_INCLUDE
> default "debug/mvebu.S" if DEBUG_MVEBU_UART
> default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
> default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
> + default "debug/sunxi.S" if DEBUG_SUNXI_UART
UART1
> default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
> DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
> default "mach/debug-macro.S"
> diff --git a/arch/arm/include/debug/sunxi.S b/arch/arm/include/debug/sunxi.S
> new file mode 100644
> index 0000000..ffd101f
> --- /dev/null
> +++ b/arch/arm/include/debug/sunxi.S
> @@ -0,0 +1,22 @@
> +/*
> + * Early serial output macro for Allwinner A1X SoCs
> + *
> + * Copyright (C) 2012 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#define SUNXI_UART1_PHYS_BASE 0x01c28400
> +#define SUNXI_UART1_VIRT_BASE 0xf1c28400
Maybe:
#ifdef CONFIG_DEBUG_SUNXI_UART1
#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28400
#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28400
#endif
> + .macro addruart, rp, rv, tmp
> + ldr \rp, =SUNXI_UART1_PHYS_BASE
> + ldr \rv, =SUNXI_UART1_VIRT_BASE
And use SUNXI_UART_DEBUG_{VIRT,PHYS}_BASE here.
So that people can come and add CONFIG_DEBUG_SUNXI_UART0 for the
Cubieboard a bit more easily. Or you can even provision the code for
the UART0 as well.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 5/6] ARM: sunxi: Add device tree for the A13 and the Olinuxino board
2012-11-15 22:46 [PATCH 0/6] Add basic support for Allwinner A1X SoCs Maxime Ripard
` (3 preceding siblings ...)
2012-11-15 22:46 ` [PATCH 4/6] ARM: sunxi: Add earlyprintk support Maxime Ripard
@ 2012-11-15 22:46 ` Maxime Ripard
2012-11-16 7:57 ` Stefan Roese
2012-11-15 22:46 ` [PATCH 6/6] ARM: sunxi: Add entry to MAINTAINERS Maxime Ripard
` (3 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun5i-olinuxino.dts | 30 +++++++++++++++++
arch/arm/boot/dts/sun5i.dtsi | 58 +++++++++++++++++++++++++++++++++
3 files changed, 89 insertions(+)
create mode 100644 arch/arm/boot/dts/sun5i-olinuxino.dts
create mode 100644 arch/arm/boot/dts/sun5i.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f37cf9f..9b2d3f0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear310-evb.dtb \
spear320-evb.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun5i-olinuxino.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/boot/dts/sun5i-olinuxino.dts b/arch/arm/boot/dts/sun5i-olinuxino.dts
new file mode 100644
index 0000000..add1e60
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-olinuxino.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun5i.dtsi"
+
+/ {
+ model = "Olimex A13-Olinuxino";
+ compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
+
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+
+ soc {
+ duart: uart at 01c28400 {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
new file mode 100644
index 0000000..5797323
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&intc>;
+
+ cpus {
+ cpu at 0 {
+ compatible = "arm,cortex-a8";
+ };
+ };
+
+ chosen {
+ bootargs = "earlyprintk console=ttyS0,115200";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x01c20000 0x300000>;
+ ranges;
+
+ timer at 01c20c00 {
+ compatible = "allwinner,sunxi-timer";
+ reg = <0x01c20c00 0x400>;
+ interrupts = <22>;
+ };
+
+ intc: interrupt-controller at 01c20400 {
+ compatible = "allwinner,sunxi-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart1: uart at 01c28400 {
+ compatible = "ns8250";
+ reg = <0x01c28400 0x400>;
+ interrupts = <2>;
+ reg-shift = <2>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 5/6] ARM: sunxi: Add device tree for the A13 and the Olinuxino board
2012-11-15 22:46 ` [PATCH 5/6] ARM: sunxi: Add device tree for the A13 and the Olinuxino board Maxime Ripard
@ 2012-11-16 7:57 ` Stefan Roese
2012-11-16 9:24 ` Maxime Ripard
0 siblings, 1 reply; 25+ messages in thread
From: Stefan Roese @ 2012-11-16 7:57 UTC (permalink / raw)
To: linux-arm-kernel
On 11/15/2012 11:46 PM, Maxime Ripard wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/sun5i-olinuxino.dts | 30 +++++++++++++++++
> arch/arm/boot/dts/sun5i.dtsi | 58 +++++++++++++++++++++++++++++++++
> 3 files changed, 89 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun5i-olinuxino.dts
> create mode 100644 arch/arm/boot/dts/sun5i.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f37cf9f..9b2d3f0 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
> spear310-evb.dtb \
> spear320-evb.dtb
> dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
> +dtb-$(CONFIG_ARCH_SUNXI) += sun5i-olinuxino.dtb
> dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
> tegra20-medcom-wide.dtb \
> tegra20-paz00.dtb \
> diff --git a/arch/arm/boot/dts/sun5i-olinuxino.dts b/arch/arm/boot/dts/sun5i-olinuxino.dts
> new file mode 100644
> index 0000000..add1e60
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun5i-olinuxino.dts
> @@ -0,0 +1,30 @@
> +/*
> + * Copyright 2012 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "sun5i.dtsi"
> +
> +/ {
> + model = "Olimex A13-Olinuxino";
> + compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
> +
> + memory {
> + reg = <0x40000000 0x40000000>;
> + };
Sure that the board support 1GiB of RAM? AFAIK A13 only supports 512MiB.
Please re-check.
> + soc {
> + duart: uart at 01c28400 {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
> new file mode 100644
> index 0000000..5797323
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun5i.dtsi
> @@ -0,0 +1,58 @@
> +/*
> + * Copyright 2012 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + cpus {
> + cpu at 0 {
> + compatible = "arm,cortex-a8";
> + };
> + };
> +
> + chosen {
> + bootargs = "earlyprintk console=ttyS0,115200";
> + };
No memory node here? My experience is, that the soc.dtsi file should
contain a memory node with the max possible memory size of the SoC.
Which will be overwritten by the board dts file containing the max
memory size of the board.
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x01c20000 0x300000>;
> + ranges;
> +
> + timer at 01c20c00 {
> + compatible = "allwinner,sunxi-timer";
> + reg = <0x01c20c00 0x400>;
> + interrupts = <22>;
> + };
> +
> + intc: interrupt-controller at 01c20400 {
> + compatible = "allwinner,sunxi-ic";
> + reg = <0x01c20400 0x400>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + uart1: uart at 01c28400 {
> + compatible = "ns8250";
> + reg = <0x01c28400 0x400>;
> + interrupts = <2>;
> + reg-shift = <2>;
> + clock-frequency = <24000000>;
> + status = "disabled";
> + };
> + };
> +};
Looks good so far. I suggest that with the A10/cubieboard support we
move to the following dts/dtsi organization:
sunxi.dtsi - Devices common to all Allwinner sunXi SoC's
sun4i.dtsi - sun4i Devices, will include sunxi.dtsi
sun5i.dtsi - sun5i Devices, will include sunxi.dtsi
board.dts - will include either sun4i.dtsi or sun5i.dtsi
If we agree on this, then I'll send a patch with this re-organization
with the cubieboard patches.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 5/6] ARM: sunxi: Add device tree for the A13 and the Olinuxino board
2012-11-16 7:57 ` Stefan Roese
@ 2012-11-16 9:24 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2012-11-16 9:24 UTC (permalink / raw)
To: linux-arm-kernel
Le 16/11/2012 08:57, Stefan Roese a ?crit :
> On 11/15/2012 11:46 PM, Maxime Ripard wrote:
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/sun5i-olinuxino.dts | 30 +++++++++++++++++
>> arch/arm/boot/dts/sun5i.dtsi | 58 +++++++++++++++++++++++++++++++++
>> 3 files changed, 89 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sun5i-olinuxino.dts
>> create mode 100644 arch/arm/boot/dts/sun5i.dtsi
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index f37cf9f..9b2d3f0 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
>> spear310-evb.dtb \
>> spear320-evb.dtb
>> dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
>> +dtb-$(CONFIG_ARCH_SUNXI) += sun5i-olinuxino.dtb
>> dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
>> tegra20-medcom-wide.dtb \
>> tegra20-paz00.dtb \
>> diff --git a/arch/arm/boot/dts/sun5i-olinuxino.dts b/arch/arm/boot/dts/sun5i-olinuxino.dts
>> new file mode 100644
>> index 0000000..add1e60
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun5i-olinuxino.dts
>> @@ -0,0 +1,30 @@
>> +/*
>> + * Copyright 2012 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +/dts-v1/;
>> +/include/ "sun5i.dtsi"
>> +
>> +/ {
>> + model = "Olimex A13-Olinuxino";
>> + compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
>> +
>> + memory {
>> + reg = <0x40000000 0x40000000>;
>> + };
>
> Sure that the board support 1GiB of RAM? AFAIK A13 only supports 512MiB.
> Please re-check.
Ah, you're right. Good catch.
>> + soc {
>> + duart: uart at 01c28400 {
>> + status = "okay";
>> + };
>> + };
>> +};
>> diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
>> new file mode 100644
>> index 0000000..5797323
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun5i.dtsi
>> @@ -0,0 +1,58 @@
>> +/*
>> + * Copyright 2012 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +/include/ "skeleton.dtsi"
>> +
>> +/ {
>> + interrupt-parent = <&intc>;
>> +
>> + cpus {
>> + cpu at 0 {
>> + compatible = "arm,cortex-a8";
>> + };
>> + };
>> +
>> + chosen {
>> + bootargs = "earlyprintk console=ttyS0,115200";
>> + };
>
> No memory node here? My experience is, that the soc.dtsi file should
> contain a memory node with the max possible memory size of the SoC.
> Which will be overwritten by the board dts file containing the max
> memory size of the board.
I've worked on boards that were not doing that, so I have a different
experience here, but that looks reasonable.
>
>> + soc {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + reg = <0x01c20000 0x300000>;
>> + ranges;
>> +
>> + timer at 01c20c00 {
>> + compatible = "allwinner,sunxi-timer";
>> + reg = <0x01c20c00 0x400>;
>> + interrupts = <22>;
>> + };
>> +
>> + intc: interrupt-controller at 01c20400 {
>> + compatible = "allwinner,sunxi-ic";
>> + reg = <0x01c20400 0x400>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + uart1: uart at 01c28400 {
>> + compatible = "ns8250";
>> + reg = <0x01c28400 0x400>;
>> + interrupts = <2>;
>> + reg-shift = <2>;
>> + clock-frequency = <24000000>;
>> + status = "disabled";
>> + };
>> + };
>> +};
>
> Looks good so far. I suggest that with the A10/cubieboard support we
> move to the following dts/dtsi organization:
>
> sunxi.dtsi - Devices common to all Allwinner sunXi SoC's
> sun4i.dtsi - sun4i Devices, will include sunxi.dtsi
> sun5i.dtsi - sun5i Devices, will include sunxi.dtsi
> board.dts - will include either sun4i.dtsi or sun5i.dtsi
>
> If we agree on this, then I'll send a patch with this re-organization
> with the cubieboard patches.
Yes, that would make sense.
Thanks!
--
Maxime Ripard, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 6/6] ARM: sunxi: Add entry to MAINTAINERS
2012-11-15 22:46 [PATCH 0/6] Add basic support for Allwinner A1X SoCs Maxime Ripard
` (4 preceding siblings ...)
2012-11-15 22:46 ` [PATCH 5/6] ARM: sunxi: Add device tree for the A13 and the Olinuxino board Maxime Ripard
@ 2012-11-15 22:46 ` Maxime Ripard
2012-11-16 7:16 ` [PATCH 0/6] Add basic support for Allwinner A1X SoCs Stefan Roese
` (2 subsequent siblings)
8 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 59203e7..7dbfcb7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -685,6 +685,12 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
+ARM/Allwinner A1X SoC support
+M: Maxime Ripard <maxime.ripard@free-electrons.com>
+L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: arch/arm/mach-sunxi/
+
ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
M: Andrew Victor <linux@maxim.org.za>
M: Nicolas Ferre <nicolas.ferre@atmel.com>
--
1.7.9.5
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 0/6] Add basic support for Allwinner A1X SoCs
2012-11-15 22:46 [PATCH 0/6] Add basic support for Allwinner A1X SoCs Maxime Ripard
` (5 preceding siblings ...)
2012-11-15 22:46 ` [PATCH 6/6] ARM: sunxi: Add entry to MAINTAINERS Maxime Ripard
@ 2012-11-16 7:16 ` Stefan Roese
2012-11-16 7:51 ` Arnd Bergmann
2012-11-16 13:11 ` Thomas Petazzoni
8 siblings, 0 replies; 25+ messages in thread
From: Stefan Roese @ 2012-11-16 7:16 UTC (permalink / raw)
To: linux-arm-kernel
Hi Maxime,
On 11/15/2012 11:46 PM, Maxime Ripard wrote:
> You'll find in this patchset the initial support for Allwinner A10 and A13 SoCs
> from Allwinner. Since the internal name of these SoCs are sun4i and sun5i, the
> mach- directory is named sunxi.
>
> You can find these SoCs in the Cubieboard, the A13-olinuxino or the Melee
> A1000.
>
> Both SoCs should work fine, as the A13 is a trimmed down version of the A10,
> but it has only been tested on a A13-OlinuXino from Olimex.
>
> Support is quite minimal for now, since it only includes timer and IRQ
> controller drivers, so we can only boot to userspace through initramfs. Support
> for the other peripherals on these SoCs will come eventually.
Great, thanks!
I've been working on upstreaming sunxi support as well in the last days.
You were a bit faster. :) Here is my latest port, for review on the
linux-sunxi list:
https://groups.google.com/forum/#!topic/linux-sunxi/H4ct05OmYtQ
(sorry about this google list)
I'll review your patches soon and send some comments.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 0/6] Add basic support for Allwinner A1X SoCs
2012-11-15 22:46 [PATCH 0/6] Add basic support for Allwinner A1X SoCs Maxime Ripard
` (6 preceding siblings ...)
2012-11-16 7:16 ` [PATCH 0/6] Add basic support for Allwinner A1X SoCs Stefan Roese
@ 2012-11-16 7:51 ` Arnd Bergmann
2012-11-16 9:00 ` Stefan Roese
2012-11-16 9:26 ` Maxime Ripard
2012-11-16 13:11 ` Thomas Petazzoni
8 siblings, 2 replies; 25+ messages in thread
From: Arnd Bergmann @ 2012-11-16 7:51 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 15 November 2012, Maxime Ripard wrote:
> You'll find in this patchset the initial support for Allwinner A10 and A13 SoCs
> from Allwinner. Since the internal name of these SoCs are sun4i and sun5i, the
> mach- directory is named sunxi.
>
> You can find these SoCs in the Cubieboard, the A13-olinuxino or the Melee
> A1000.
>
> Both SoCs should work fine, as the A13 is a trimmed down version of the A10,
> but it has only been tested on a A13-OlinuXino from Olimex.
>
> Support is quite minimal for now, since it only includes timer and IRQ
> controller drivers, so we can only boot to userspace through initramfs. Support
> for the other peripherals on these SoCs will come eventually.
Hi Maxime,
Thanks for sending these, I'm pretty excited we actually get this far
for 3.8. All patches look good for inclusion from my side, but I'll let
Stefan and others comment first and then take your second version. We
are getting closer to the merge window already, so I'd like to pull
it in rather soon and maybe add some fixups later.
I've also ordered a Cubieboard myself now, so hopefully I'll also find
some time to play with this.
Arnd
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH 0/6] Add basic support for Allwinner A1X SoCs
2012-11-16 7:51 ` Arnd Bergmann
@ 2012-11-16 9:00 ` Stefan Roese
2012-11-16 9:26 ` Maxime Ripard
1 sibling, 0 replies; 25+ messages in thread
From: Stefan Roese @ 2012-11-16 9:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd,
On 11/16/2012 08:51 AM, Arnd Bergmann wrote:
> On Thursday 15 November 2012, Maxime Ripard wrote:
>> You'll find in this patchset the initial support for Allwinner A10 and A13 SoCs
>> from Allwinner. Since the internal name of these SoCs are sun4i and sun5i, the
>> mach- directory is named sunxi.
>>
>> You can find these SoCs in the Cubieboard, the A13-olinuxino or the Melee
>> A1000.
>>
>> Both SoCs should work fine, as the A13 is a trimmed down version of the A10,
>> but it has only been tested on a A13-OlinuXino from Olimex.
>>
>> Support is quite minimal for now, since it only includes timer and IRQ
>> controller drivers, so we can only boot to userspace through initramfs. Support
>> for the other peripherals on these SoCs will come eventually.
>
> Hi Maxime,
>
> Thanks for sending these, I'm pretty excited we actually get this far
> for 3.8. All patches look good for inclusion from my side, but I'll let
> Stefan and others comment first and then take your second version. We
> are getting closer to the merge window already, so I'd like to pull
> it in rather soon and maybe add some fixups later.
Yes, that would be great. I can send some patches to add A10/cubieboard
support in a few days.
> I've also ordered a Cubieboard myself now, so hopefully I'll also find
> some time to play with this.
Nice.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 0/6] Add basic support for Allwinner A1X SoCs
2012-11-16 7:51 ` Arnd Bergmann
2012-11-16 9:00 ` Stefan Roese
@ 2012-11-16 9:26 ` Maxime Ripard
1 sibling, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2012-11-16 9:26 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd,
Le 16/11/2012 08:51, Arnd Bergmann a ?crit :
> On Thursday 15 November 2012, Maxime Ripard wrote:
>> You'll find in this patchset the initial support for Allwinner A10 and A13 SoCs
>> from Allwinner. Since the internal name of these SoCs are sun4i and sun5i, the
>> mach- directory is named sunxi.
>>
>> You can find these SoCs in the Cubieboard, the A13-olinuxino or the Melee
>> A1000.
>>
>> Both SoCs should work fine, as the A13 is a trimmed down version of the A10,
>> but it has only been tested on a A13-OlinuXino from Olimex.
>>
>> Support is quite minimal for now, since it only includes timer and IRQ
>> controller drivers, so we can only boot to userspace through initramfs. Support
>> for the other peripherals on these SoCs will come eventually.
>
> Hi Maxime,
>
> Thanks for sending these, I'm pretty excited we actually get this far
> for 3.8. All patches look good for inclusion from my side, but I'll let
> Stefan and others comment first and then take your second version. We
> are getting closer to the merge window already, so I'd like to pull
> it in rather soon and maybe add some fixups later.
That's great. I'll do my best to send a v2 asap.
> I've also ordered a Cubieboard myself now, so hopefully I'll also find
> some time to play with this.
Nice :)
Maxime
--
Maxime Ripard, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 0/6] Add basic support for Allwinner A1X SoCs
2012-11-15 22:46 [PATCH 0/6] Add basic support for Allwinner A1X SoCs Maxime Ripard
` (7 preceding siblings ...)
2012-11-16 7:51 ` Arnd Bergmann
@ 2012-11-16 13:11 ` Thomas Petazzoni
8 siblings, 0 replies; 25+ messages in thread
From: Thomas Petazzoni @ 2012-11-16 13:11 UTC (permalink / raw)
To: linux-arm-kernel
Dear Maxime Ripard,
On Thu, 15 Nov 2012 23:46:19 +0100, Maxime Ripard wrote:
> You'll find in this patchset the initial support for Allwinner A10 and A13 SoCs
> from Allwinner. Since the internal name of these SoCs are sun4i and sun5i, the
> mach- directory is named sunxi.
>
> You can find these SoCs in the Cubieboard, the A13-olinuxino or the Melee
> A1000.
>
> Both SoCs should work fine, as the A13 is a trimmed down version of the A10,
> but it has only been tested on a A13-OlinuXino from Olimex.
>
> Support is quite minimal for now, since it only includes timer and IRQ
> controller drivers, so we can only boot to userspace through initramfs. Support
> for the other peripherals on these SoCs will come eventually.
Would you mind adding a file Documentation/arm/sunxi/README (or another
name) that lists the SoCs that are supported and the public datasheets
that are available for those SoCs?
I think it's always great to ease the process of finding the SoC
datasheets.
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 25+ messages in thread