* [PATCH] ARM: cti: fix manipulation of debug lock registers
@ 2012-11-15 21:40 Will Deacon
2012-11-19 18:21 ` Jon Hunter
0 siblings, 1 reply; 3+ messages in thread
From: Will Deacon @ 2012-11-15 21:40 UTC (permalink / raw)
To: linux-arm-kernel
The LOCKSTATUS register for memory-mapped coresight devices indicates
whether or not the device in question implements hardware locking. If
not, locking is not present (i.e. LSR.SLI == 0) and LAR is write-ignore,
so software doesn't actually need to check the status register at all.
This patch removes the broken LSR checks.
Cc: Ming Lei <ming.lei@canonical.com>
Reported-by: Mike Williams <michael.williams@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/include/asm/cti.h | 20 ++------------------
1 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
index a0ada3e..f2e5cad 100644
--- a/arch/arm/include/asm/cti.h
+++ b/arch/arm/include/asm/cti.h
@@ -146,15 +146,7 @@ static inline void cti_irq_ack(struct cti *cti)
*/
static inline void cti_unlock(struct cti *cti)
{
- void __iomem *base = cti->base;
- unsigned long val;
-
- val = __raw_readl(base + LOCKSTATUS);
-
- if (val & 1) {
- val = LOCKCODE;
- __raw_writel(val, base + LOCKACCESS);
- }
+ __raw_writel(LOCKCODE, cti->base + LOCKACCESS);
}
/**
@@ -166,14 +158,6 @@ static inline void cti_unlock(struct cti *cti)
*/
static inline void cti_lock(struct cti *cti)
{
- void __iomem *base = cti->base;
- unsigned long val;
-
- val = __raw_readl(base + LOCKSTATUS);
-
- if (!(val & 1)) {
- val = ~LOCKCODE;
- __raw_writel(val, base + LOCKACCESS);
- }
+ __raw_writel(~LOCKCODE, cti->base + LOCKACCESS);
}
#endif
--
1.7.4.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH] ARM: cti: fix manipulation of debug lock registers
2012-11-15 21:40 [PATCH] ARM: cti: fix manipulation of debug lock registers Will Deacon
@ 2012-11-19 18:21 ` Jon Hunter
2012-11-20 13:55 ` Will Deacon
0 siblings, 1 reply; 3+ messages in thread
From: Jon Hunter @ 2012-11-19 18:21 UTC (permalink / raw)
To: linux-arm-kernel
On 11/15/2012 03:40 PM, Will Deacon wrote:
> The LOCKSTATUS register for memory-mapped coresight devices indicates
> whether or not the device in question implements hardware locking. If
> not, locking is not present (i.e. LSR.SLI == 0) and LAR is write-ignore,
> so software doesn't actually need to check the status register at all.
>
> This patch removes the broken LSR checks.
>
> Cc: Ming Lei <ming.lei@canonical.com>
> Reported-by: Mike Williams <michael.williams@arm.com>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
> arch/arm/include/asm/cti.h | 20 ++------------------
> 1 files changed, 2 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
> index a0ada3e..f2e5cad 100644
> --- a/arch/arm/include/asm/cti.h
> +++ b/arch/arm/include/asm/cti.h
> @@ -146,15 +146,7 @@ static inline void cti_irq_ack(struct cti *cti)
> */
> static inline void cti_unlock(struct cti *cti)
> {
> - void __iomem *base = cti->base;
> - unsigned long val;
> -
> - val = __raw_readl(base + LOCKSTATUS);
> -
> - if (val & 1) {
> - val = LOCKCODE;
> - __raw_writel(val, base + LOCKACCESS);
> - }
> + __raw_writel(LOCKCODE, cti->base + LOCKACCESS);
> }
>
> /**
> @@ -166,14 +158,6 @@ static inline void cti_unlock(struct cti *cti)
> */
> static inline void cti_lock(struct cti *cti)
> {
> - void __iomem *base = cti->base;
> - unsigned long val;
> -
> - val = __raw_readl(base + LOCKSTATUS);
> -
> - if (!(val & 1)) {
> - val = ~LOCKCODE;
> - __raw_writel(val, base + LOCKACCESS);
> - }
> + __raw_writel(~LOCKCODE, cti->base + LOCKACCESS);
> }
> #endif
I gave this a whirl on omap4430 and PMU is working fine with this, so ...
Tested-by: Jon Hunter <jon-hunter@ti.com>
Cheers
Jon
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH] ARM: cti: fix manipulation of debug lock registers
2012-11-19 18:21 ` Jon Hunter
@ 2012-11-20 13:55 ` Will Deacon
0 siblings, 0 replies; 3+ messages in thread
From: Will Deacon @ 2012-11-20 13:55 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Nov 19, 2012 at 06:21:34PM +0000, Jon Hunter wrote:
> On 11/15/2012 03:40 PM, Will Deacon wrote:
> > diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
> > index a0ada3e..f2e5cad 100644
> > --- a/arch/arm/include/asm/cti.h
> > +++ b/arch/arm/include/asm/cti.h
> > @@ -146,15 +146,7 @@ static inline void cti_irq_ack(struct cti *cti)
> > */
> > static inline void cti_unlock(struct cti *cti)
> > {
> > - void __iomem *base = cti->base;
> > - unsigned long val;
> > -
> > - val = __raw_readl(base + LOCKSTATUS);
> > -
> > - if (val & 1) {
> > - val = LOCKCODE;
> > - __raw_writel(val, base + LOCKACCESS);
> > - }
> > + __raw_writel(LOCKCODE, cti->base + LOCKACCESS);
> > }
> >
> > /**
> > @@ -166,14 +158,6 @@ static inline void cti_unlock(struct cti *cti)
> > */
> > static inline void cti_lock(struct cti *cti)
> > {
> > - void __iomem *base = cti->base;
> > - unsigned long val;
> > -
> > - val = __raw_readl(base + LOCKSTATUS);
> > -
> > - if (!(val & 1)) {
> > - val = ~LOCKCODE;
> > - __raw_writel(val, base + LOCKACCESS);
> > - }
> > + __raw_writel(~LOCKCODE, cti->base + LOCKACCESS);
> > }
> > #endif
>
> I gave this a whirl on omap4430 and PMU is working fine with this, so ...
>
> Tested-by: Jon Hunter <jon-hunter@ti.com>
Cheers Jon,
Will
^ permalink raw reply [flat|nested] 3+ messages in thread
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2012-11-15 21:40 [PATCH] ARM: cti: fix manipulation of debug lock registers Will Deacon
2012-11-19 18:21 ` Jon Hunter
2012-11-20 13:55 ` Will Deacon
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