From mboxrd@z Thu Jan 1 00:00:00 1970 From: s.hauer@pengutronix.de (Sascha Hauer) Date: Wed, 21 Nov 2012 15:11:24 +0100 Subject: [PATCH] ARM i.MX6: Fix ethernet PLL clocks In-Reply-To: <1353505652-28200-1-git-send-email-s.hauer@pengutronix.de> References: <1353505652-28200-1-git-send-email-s.hauer@pengutronix.de> Message-ID: <20121121141124.GS10369@pengutronix.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Nov 21, 2012 at 02:47:32PM +0100, Sascha Hauer wrote: > In current code the ethernet PLL (according to code pll8, according to datasheet > pll6) is not handled correctly. The PLL runs at 500MHz and has different outputs. > Only the enet reference clock is implemented. This patch changes the PLL so that > it outputs 500MHz and adds the additional outputs as dividers. This now matches > the datasheet which says: > > > This PLL synthesizes a low jitter clock from 24 MHz reference clock. > > The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are: > > ? Ref_PCIe = 125 MHz > > ? Ref_SATA = 100 MHz > > ? Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field. > > Signed-off-by: Sascha Hauer > --- > .../devicetree/bindings/clock/imx6q-clock.txt | 5 ++ > arch/arm/mach-imx/clk-imx6q.c | 18 +++++- > arch/arm/mach-imx/clk-pllv3.c | 59 +------------------- > 3 files changed, 24 insertions(+), 58 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt > index 492bd99..94311e2 100644 > --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt > +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt > @@ -198,6 +198,11 @@ clocks and IDs. > usbphy2 183 > ldb_di0_div_3_5 184 > ldb_di1_div_3_5 185 > + sata_ref 186 > + sata_ref_100m 187 > + pcie_ref 188 > + pcie_ref_125m 189 > + enet_ref 190 > > Examples: > > diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c > index 3ec242f..95f8ea5 100644 > --- a/arch/arm/mach-imx/clk-imx6q.c > +++ b/arch/arm/mach-imx/clk-imx6q.c > @@ -153,7 +153,7 @@ enum mx6q_clks { > usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, > pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, > ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, > - clk_max > + sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, clk_max > }; > > static struct clk *clk[clk_max]; > @@ -163,6 +163,13 @@ static enum mx6q_clks const clks_init_on[] __initconst = { > mmdc_ch0_axi, rom, > }; > > +static struct clk_div_table clk_enet_ref_table[] = { > + { .val = 0, .div = 20, }, > + { .val = 1, .div = 10, }, > + { .val = 2, .div = 5, }, > + { .val = 3, .div = 4, }, > +}; > + > int __init mx6q_clocks_init(void) > { > struct device_node *np; > @@ -202,6 +209,15 @@ int __init mx6q_clocks_init(void) > clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6); > clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6); > > + clk[sata_ref] = imx_clk_gate("sata_ref", "pll8_enet", base + 0x20, 20); > + clk[pcie_ref] = imx_clk_gate("pcie_ref", "pll8_enet", base + 0x20, 19); > + clk[sata_ref_100m] = imx_clk_fixed_factor("sata_ref_100m", "sata_ref", 1, 5); > + clk[pcie_ref_125m] = imx_clk_fixed_factor("pcie_ref_100m", "pcie_ref", 1, 4); > + > + clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll8_enet", 0, > + base + 0x20, 0, 2, 0, clk_enet_ref_table, > + &imx_ccm_lock); > + > /* name parent_name reg idx */ > clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); > clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); > diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c > index 36aac94..f5e210a 100644 > --- a/arch/arm/mach-imx/clk-pllv3.c > +++ b/arch/arm/mach-imx/clk-pllv3.c > @@ -287,66 +287,13 @@ static const struct clk_ops clk_pllv3_av_ops = { > static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, > unsigned long parent_rate) > { > - struct clk_pllv3 *pll = to_clk_pllv3(hw); > - u32 div = readl_relaxed(pll->base) & pll->div_mask; > - > - switch (div) { > - case 0: > - return 25000000; > - case 1: > - return 50000000; > - case 2: > - return 100000000; > - case 3: > - return 125000000; > - } > - > - return 0; > + return 500000000; > } > > static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate, > unsigned long *prate) > { This function should be removed completely. Will fix. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |