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From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] mmc: mmci: Support non-power-of-two block sizes for ux500v2 variant
Date: Wed, 21 Nov 2012 16:50:48 +0000	[thread overview]
Message-ID: <20121121165048.GO3290@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <CAFEEs1kzJUgsvnzgWwU4i7o1jkE=8iTq5+NJ_t1jdiHEm7b-RQ@mail.gmail.com>

On Wed, Nov 21, 2012 at 05:13:55PM +0100, Per Forlin wrote:
> On Wed, Nov 21, 2012 at 4:38 PM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> > On Fri, Oct 12, 2012 at 04:02:02PM +0200, Ulf Hansson wrote:
> >>  /*
> >> + * Validate mmc prerequisites
> >> + */
> >> +static int mmci_validate_data(struct mmci_host *host,
> >> +                           struct mmc_data *data)
> >> +{
> >> +     if (!data)
> >> +             return 0;
> >> +
> >> +     if (!host->variant->non_power_of_2_blksize &&
> >> +         !is_power_of_2(data->blksz)) {
> >> +             dev_err(mmc_dev(host->mmc),
> >> +                     "unsupported block size (%d bytes)\n", data->blksz);
> >> +             return -EINVAL;
> >> +     }
> >> +
> >> +     if (data->sg->offset & 3) {
> >> +             dev_err(mmc_dev(host->mmc),
> >> +                     "unsupported alginment (0x%x)\n", data->sg->offset);
> >> +             return -EINVAL;
> >> +     }
> >
> > Why?  What's the reasoning behind this suddenly introduced restriction?
> > readsl()/writesl() copes just fine with non-aligned pointers.  It may be
> > that your DMA engine can not, but that's no business interfering with
> > non-DMA transfers, and no reason to fail such transfers.
> >
> > If your DMA engine can't do that then its your DMA engine code which
> > should refuse to prepare the transfer.
> >
> > Yes, that means problems with the way things are ordered - or it needs a
> > proper API where DMA engine can export these kinds of properties.
> The alignment constraint is related to PIO, sg_miter and that FIFO
> access must be done with 4 bytes.

Total claptrap.  No it isn't.

- sg_miter just deals with bytes, and number of bytes transferred; there
  is no word assumptions in that code.  Indeed many ATA disks transfer
  by half-word accesses so such a restriction would be insane.

- the FIFO access itself needs to be 32-bit words, so readsl or writesl
  (or their io* equivalents must be used).

- but - and this is the killer item to your argument as I said above -
  readsl and writesl _can_ take misaligned pointers and cope with them
  fine.

The actual alignment of the buffer address is totally irrelevant here.

What isn't irrelevant is the _number_ of bytes to be transferred, but
that's something totally different and completely unrelated from
data->sg->offset.

  reply	other threads:[~2012-11-21 16:50 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-12 14:02 [PATCH] mmc: mmci: Support non-power-of-two block sizes for ux500v2 variant Ulf Hansson
2012-10-12 21:22 ` Linus Walleij
2012-10-15 10:24 ` Johan Rudholm
2012-11-21 15:38 ` Russell King - ARM Linux
2012-11-21 16:13   ` Per Forlin
2012-11-21 16:50     ` Russell King - ARM Linux [this message]
2012-11-22 13:43       ` Ulf Hansson
2012-11-22 14:50         ` Russell King - ARM Linux
2012-11-22 17:28       ` Per Forlin
2012-11-22 17:37         ` Russell King - ARM Linux
2012-11-26 10:20           ` Per Förlin
2012-11-26 10:27             ` Russell King - ARM Linux
2012-11-26 10:52               ` Per Förlin
2012-11-28 16:55                 ` Per Forlin
2012-11-28 17:12                   ` Russell King - ARM Linux
2012-11-29 11:38                     ` Ulf Hansson
2012-12-21 10:36                       ` Ulf Hansson
2012-12-21 10:39                         ` Russell King - ARM Linux
2012-12-21 10:43                           ` Ulf Hansson

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