From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations
Date: Wed, 12 Dec 2012 10:31:20 +0000 [thread overview]
Message-ID: <20121212103119.GA6195@mudshark.cambridge.arm.com> (raw)
In-Reply-To: <50C7C16B.7050106@codeaurora.org>
On Tue, Dec 11, 2012 at 11:27:39PM +0000, Stephen Boyd wrote:
> On 12/11/12 08:38, Will Deacon wrote:
> > diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> > index cd95664..f58248f 100644
> > --- a/arch/arm/mm/cache-v7.S
> > +++ b/arch/arm/mm/cache-v7.S
> > @@ -44,7 +44,8 @@ ENDPROC(v7_flush_icache_all)
> > ENTRY(v7_flush_dcache_louis)
> > dmb @ ensure ordering with previous memory accesses
> > mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
> > - ands r3, r0, #0xe00000 @ extract LoUIS from clidr
> > + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
> > + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
> > mov r3, r3, lsr #20 @ r3 = LoUIS * 2
>
> You need to fix this mov as well, right?
Ha, nice catch. So the original patch ended up with a ridiculously high
level number and would've flushed L2, hence we will need to retest with the
fix below...
Will
--->8
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index cd95664..7539ec2 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -44,8 +44,10 @@ ENDPROC(v7_flush_icache_all)
ENTRY(v7_flush_dcache_louis)
dmb @ ensure ordering with previous memory accesses
mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
- ands r3, r0, #0xe00000 @ extract LoUIS from clidr
- mov r3, r3, lsr #20 @ r3 = LoUIS * 2
+ ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
+ ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
+ ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2
+ ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2
moveq pc, lr @ return if level == 0
mov r10, #0 @ r10 (starting level) = 0
b flush_levels @ start flushing cache levels
next prev parent reply other threads:[~2012-12-12 10:31 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-18 16:35 [RFC PATCH v2 0/5] ARM: augment cache flushing API Lorenzo Pieralisi
2012-09-18 16:35 ` [RFC PATCH v2 1/5] ARM: mm: implement LoUIS API for cache maintenance ops Lorenzo Pieralisi
2012-09-18 18:12 ` Nicolas Pitre
2012-09-19 12:30 ` Lorenzo Pieralisi
2012-09-18 16:35 ` [RFC PATCH v2 2/5] ARM: mm: rename jump labels in v7_flush_dcache_all function Lorenzo Pieralisi
2012-09-18 18:13 ` Nicolas Pitre
2012-09-19 13:51 ` Dave Martin
2012-09-20 10:32 ` Lorenzo Pieralisi
2012-09-20 11:01 ` Dave Martin
2012-09-18 16:35 ` [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations Lorenzo Pieralisi
2012-09-18 18:18 ` Nicolas Pitre
2012-09-19 13:46 ` Dave Martin
2012-09-20 10:25 ` Lorenzo Pieralisi
2012-09-20 11:04 ` Dave Martin
2012-12-11 16:07 ` Guennadi Liakhovetski
2012-12-11 16:33 ` Will Deacon
2012-12-11 16:38 ` Will Deacon
2012-12-11 17:07 ` Guennadi Liakhovetski
2012-12-11 17:47 ` Will Deacon
2012-12-11 17:55 ` Guennadi Liakhovetski
2012-12-11 23:27 ` Stephen Boyd
2012-12-12 10:31 ` Will Deacon [this message]
2012-12-12 16:43 ` Guennadi Liakhovetski
2012-12-12 10:33 ` Lorenzo Pieralisi
2012-12-12 13:36 ` Will Deacon
2012-12-13 8:09 ` Guennadi Liakhovetski
2012-12-13 10:51 ` Will Deacon
2012-12-13 14:32 ` Guennadi Liakhovetski
2012-12-13 14:39 ` Santosh Shilimkar
2012-12-28 11:32 ` [PATCH v2] ARM: sh7372: fix cache clean / invalidate order Guennadi Liakhovetski
2012-12-28 21:50 ` Simon Horman
2012-12-13 14:52 ` [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations Will Deacon
2012-12-12 16:43 ` Guennadi Liakhovetski
2012-09-18 16:35 ` [RFC PATCH v2 4/5] ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API Lorenzo Pieralisi
2012-09-18 18:19 ` Nicolas Pitre
2012-09-18 16:35 ` [RFC PATCH v2 5/5] ARM: mm: update __v7_setup() to the new LoUIS cache " Lorenzo Pieralisi
2012-09-18 18:20 ` Nicolas Pitre
2012-09-20 11:27 ` [RFC PATCH v2 0/5] ARM: augment cache flushing API Lorenzo Pieralisi
2012-09-21 8:07 ` Shawn Guo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20121212103119.GA6195@mudshark.cambridge.arm.com \
--to=will.deacon@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).