From: thierry.reding@avionic-design.de (Thierry Reding)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC v1] PCIe support for the Armada 370 and Armada XP SoCs
Date: Fri, 14 Dec 2012 11:05:40 +0100 [thread overview]
Message-ID: <20121214100540.GA4586@avionic-0098.adnet.avionic-design.de> (raw)
In-Reply-To: <20121213204718.GA4882@obsidianresearch.com>
On Thu, Dec 13, 2012 at 01:47:18PM -0700, Jason Gunthorpe wrote:
> On Thu, Dec 13, 2012 at 09:42:29PM +0100, Thierry Reding wrote:
>
> > So I tried this today and it breaks horribly. There's some internal
> > abort or something. I don't have access to the hardware right now and
> > forgot to save the log output, but I can follow up in the morning. Also
> > up until the abort, bus 0000:00.0 was identified as the virtual switch
> > within the FPGA that's connected to port 0, so that would indicate that
> > it isn't in fact compliant and neither root port is reachable via the
> > regular mapping.
> >
> > I suppose that may be the reason why the downstream code implements the
> > special case for accesses to the root ports' configuration space.
>
> With the special case, what does device 0:0.0 show up as? What class?
So here's some more output:
-sh-4.2# lspci
00:00.0 PCI bridge: NVIDIA Corporation Device 0bf0 (rev a0)
01:00.0 PCI bridge: PLD APPLICATIONS Device 4711
02:00.0 PCI bridge: Avionic Design GmbH FPGA PCIe PCI-to-PCI (P2P) Bridge
02:01.0 PCI bridge: Avionic Design GmbH FPGA PCIe PCI-to-PCI (P2P) Bridge
02:02.0 PCI bridge: Avionic Design GmbH FPGA PCIe PCI-to-PCI (P2P) Bridge
02:03.0 PCI bridge: Avionic Design GmbH FPGA PCIe PCI-to-PCI (P2P) Bridge
02:04.0 PCI bridge: Avionic Design GmbH FPGA PCIe PCI-to-PCI (P2P) Bridge
02:05.0 PCI bridge: Avionic Design GmbH FPGA PCIe PCI-to-PCI (P2P) Bridge
02:06.0 PCI bridge: Avionic Design GmbH FPGA PCIe PCI-to-PCI (P2P) Bridge
02:07.0 PCI bridge: Avionic Design GmbH FPGA PCIe PCI-to-PCI (P2P) Bridge
03:00.0 Memory controller: Avionic Design GmbH FPGA PCIe Test Endpoint
04:00.0 Serial bus controller [0c80]: Avionic Design GmbH OpenCores SPI Controller
05:00.0 Serial bus controller [0c80]: Avionic Design GmbH OpenCores I2C Controller
06:00.0 Intelligent controller [0e80]: Avionic Design GmbH 64 pin GPIO Controller
07:00.0 Modem: Avionic Design GmbH OpenCores 16550 UART
08:00.0 Modem: Avionic Design GmbH OpenCores 10/100 Mbps Ethernet Controller
09:00.0 Modem: Avionic Design GmbH OpenCores CAN Protocol Controller
0a:00.0 Modem: Avionic Design GmbH OpenCores CAN Protocol Controlle
-sh-4.2# lspci -tv
-[0000:00]---00.0-[01-0a]----00.0-[02-0a]--+-00.0-[03]----00.0 Avionic Design GmbH FPGA PCIe Test Endpoint
+-01.0-[04]----00.0 Avionic Design GmbH OpenCores SPI Controller
+-02.0-[05]----00.0 Avionic Design GmbH OpenCores I2C Controller
+-03.0-[06]----00.0 Avionic Design GmbH 64 pin GPIO Controller
+-04.0-[07]----00.0 Avionic Design GmbH OpenCores 16550 UART
+-05.0-[08]----00.0 Avionic Design GmbH OpenCores 10/100 Mbps Ethernet Controller
+-06.0-[09]----00.0 Avionic Design GmbH OpenCores CAN Protocol Controller
\-07.0-[0a]----00.0 Avionic Design GmbH OpenCores CAN Protocol Controller
-sh-4.2# lspci -s 00:00.0 -v
00:00.0 PCI bridge: NVIDIA Corporation Device 0bf0 (rev a0) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0
Bus: primary=00, secondary=01, subordinate=0a, sec-latency=0
Prefetchable memory behind bridge: 00000000b0000000-00000000b0ffffff
Capabilities: [40] Subsystem: NVIDIA Corporation Device 0000
Capabilities: [48] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/2 Maskable- 64bit+
Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed-
Capabilities: [80] Express Root Port (Slot+), MSI 00
Capabilities: [100] #00
So the class is 0x0604. I unfortunately have no setup where hardware is
connected to the second port. It would be interesting to see how that
looks.
Thierry
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next prev parent reply other threads:[~2012-12-14 10:05 UTC|newest]
Thread overview: 107+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-07 22:04 [RFC v1] PCIe support for the Armada 370 and Armada XP SoCs Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 01/16] lib: devres: don't enclose pcim_*() functions in CONFIG_HAS_IOPORT Thomas Petazzoni
2012-12-11 10:43 ` Arnd Bergmann
2012-12-11 16:03 ` Thomas Petazzoni
2012-12-11 16:15 ` Arnd Bergmann
2012-12-11 16:23 ` Russell King - ARM Linux
2012-12-11 16:38 ` Thomas Petazzoni
2012-12-11 16:50 ` Russell King - ARM Linux
2012-12-11 17:29 ` Alan Cox
2012-12-11 22:20 ` Arnd Bergmann
2012-12-11 22:34 ` Arnd Bergmann
2012-12-11 16:30 ` Thomas Petazzoni
2012-12-11 16:46 ` Russell King - ARM Linux
2012-12-11 17:32 ` Alan Cox
2012-12-11 22:28 ` Arnd Bergmann
2012-12-11 16:55 ` Russell King - ARM Linux
2012-12-11 16:26 ` Russell King - ARM Linux
2012-12-11 17:16 ` Alan Cox
2012-12-11 17:34 ` Russell King - ARM Linux
2012-12-11 17:45 ` Alan Cox
2012-12-11 17:51 ` Russell King - ARM Linux
2012-12-07 22:04 ` [RFC v1 02/16] clk: mvebu: create parent-child relation for PCIe clocks on Armada 370 Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 03/16] arm: plat-orion: introduce WIN_CTRL_ENABLE in address mapping code Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 04/16] arm: plat-orion: refactor the orion_disable_wins() function Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 05/16] arm: plat-orion: introduce orion_{alloc, free}_cpu_win() functions Thomas Petazzoni
2012-12-08 11:53 ` [RFC v1 05/16] arm: plat-orion: introduce orion_{alloc,free}_cpu_win() functions Andrew Lunn
2012-12-08 12:15 ` Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 06/16] arm: mvebu: add functions to alloc/free PCIe decoding windows Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 07/16] arm: plat-orion: make common PCIe code usable on mvebu Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 08/16] arm: mvebu: the core PCIe driver Thomas Petazzoni
2012-12-10 8:28 ` Andrew Lunn
2012-12-10 8:45 ` Thomas Petazzoni
2012-12-10 19:08 ` Jason Gunthorpe
2012-12-11 10:56 ` Arnd Bergmann
2012-12-12 15:58 ` Thomas Petazzoni
2012-12-12 21:51 ` Jason Gunthorpe
2012-12-13 14:58 ` Arnd Bergmann
2012-12-13 17:40 ` Jason Gunthorpe
2012-12-13 19:09 ` Thomas Petazzoni
2012-12-14 19:34 ` Rob Herring
2012-12-13 12:19 ` Arnd Bergmann
2012-12-13 17:54 ` Jason Gunthorpe
2012-12-13 19:12 ` Thomas Petazzoni
2012-12-13 21:46 ` Arnd Bergmann
2012-12-13 22:27 ` Jason Gunthorpe
2012-12-07 22:04 ` [RFC v1 09/16] arm: mvebu: PCIe support is now available on mvebu Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 10/16] arm: mvebu: add PCIe Device Tree informations for Armada 370 Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 11/16] arm: mvebu: add PCIe Device Tree informations for Armada XP Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 12/16] arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4 Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 13/16] arm: mvebu: PCIe Device Tree informations for Armada XP DB Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 14/16] arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 15/16] arm: mvebu: PCIe Device Tree informations for Armada 370 DB Thomas Petazzoni
2012-12-07 22:04 ` [RFC v1 16/16] arm: mvebu: update defconfig with PCI and USB support Thomas Petazzoni
2012-12-07 23:33 ` [RFC v1] PCIe support for the Armada 370 and Armada XP SoCs Jason Gunthorpe
2012-12-10 17:52 ` Stephen Warren
2012-12-10 18:05 ` Thomas Petazzoni
2012-12-10 18:16 ` Stephen Warren
2012-12-10 18:59 ` Thomas Petazzoni
2012-12-10 19:07 ` Jason Gunthorpe
2012-12-10 20:08 ` Stephen Warren
2012-12-10 18:44 ` Jason Gunthorpe
2012-12-10 19:03 ` Thomas Petazzoni
2012-12-10 19:18 ` Jason Gunthorpe
2012-12-12 16:04 ` Thomas Petazzoni
2012-12-12 20:09 ` Jason Gunthorpe
2012-12-16 13:02 ` Thierry Reding
2012-12-11 7:52 ` Thierry Reding
2012-12-11 21:21 ` Stephen Warren
2012-12-12 20:34 ` Thierry Reding
2012-12-12 22:30 ` Stephen Warren
2012-12-13 7:03 ` Thierry Reding
2012-12-13 8:04 ` Jason Gunthorpe
2012-12-13 8:23 ` Thierry Reding
2012-12-13 18:12 ` Stephen Warren
2012-12-13 20:42 ` Thierry Reding
2012-12-13 20:47 ` Jason Gunthorpe
2012-12-13 21:16 ` Thierry Reding
2012-12-14 10:05 ` Thierry Reding [this message]
2012-12-14 15:10 ` Thierry Reding
2012-12-14 17:27 ` Jason Gunthorpe
2012-12-16 12:33 ` Thierry Reding
2012-12-17 18:29 ` Jason Gunthorpe
2012-12-17 19:41 ` Thierry Reding
2012-12-18 2:10 ` Stephen Warren
2012-12-18 2:51 ` Jason Gunthorpe
2012-12-18 17:03 ` Stephen Warren
2012-12-20 15:32 ` Thierry Reding
2012-12-21 13:38 ` Jay Agarwal
2012-12-21 14:03 ` Thierry Reding
2012-12-22 14:50 ` Thomas Petazzoni
2012-12-28 21:06 ` Thierry Reding
2012-12-28 21:16 ` Thomas Petazzoni
2012-12-28 23:49 ` Stephen Warren
2012-12-29 8:09 ` Thomas Petazzoni
2012-12-31 16:40 ` Stephen Warren
2012-12-29 9:33 ` Thierry Reding
2012-12-31 16:44 ` Stephen Warren
2013-01-02 20:09 ` Jason Gunthorpe
2013-01-03 14:20 ` Thierry Reding
2012-12-28 23:51 ` Stephen Warren
2012-12-18 7:32 ` Thierry Reding
2013-01-03 14:39 ` Thierry Reding
2013-01-03 15:00 ` Bjorn Helgaas
2013-01-03 15:11 ` Thierry Reding
2013-01-03 15:09 ` Thomas Petazzoni
2013-01-03 15:56 ` Arnd Bergmann
2013-01-03 16:01 ` Thierry Reding
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