common clock framwork: clk_set_rate issue

[s.hauer@pengutronix.de (Sascha Hauer)]

On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote:
> hi
> When develop the clk drivers for SOCs based on common clock framework.
> I met a issue.
> For example there is a uart device, it's function clock comes from a
> divider, and the divider's parent is a mux. It means
> 
> MUX --> DIV --> UART
> 
> As we know that UART can work at low baudrate for a terminal, while it
> can also connect to GPS module which needs a high rate. So the MUX
> will provide two clock source, a low clock rate and high clock rate.
> 
> The MUX clk driver clk-mux.c does not implement a ->round_rate callbacks.
> It means that when uart driver is used for a GPS and it want to change
> it clock, the driver will call clk_set_rate(); clk_set_rate will loop
> upward to DIV, and DIV will try to set its divider, and it need loop
> upward to MUX.
> In fact the current clk drivers have some issue.
> MUX clk driver should provide the round_rate callback, it then can
> provide a new_rate. It means that in clk_calc_subtree MUX can switch
> the clock source.

It's not that simple. The input clocks to a mux may not only differ in
their rate but can also have other different properties, like for
example one input may be always present whereas another input only runs
when the CPU is in run mode.

It may be a possibility to add a flag to the mux to explicitely
allow reparenting on a rate change.

Sascha

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