* [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC
@ 2012-12-20 12:13 Barry Song
2012-12-20 12:13 ` [PATCH 1/9] ARM: PRIMA2: add CSR SiRFmarco device tree .dts Barry Song
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Barry Song @ 2012-12-20 12:13 UTC (permalink / raw)
To: linux-arm-kernel
this patch series enables the new CSR SiRFmarco SMP SoC.
change list:
1. Marco has different OS timer hardware with Prima2, so add a new timer-marco
2. add platsmp.c, headsmp.S and hotplug.c for MPcore support
3. some hardwares have changed, like rstc, so use of_compatible to branch Prima2
and Marco
4. add initial .dtsi for Marco SoC and initial .dts for the EVB
5. use GIC for Marco instead of Prima2's IRQ controller
6. add DEBUG_LL uart ports for Prima2 and Marco debug ports
Barry Song (9):
ARM: PRIMA2: add CSR SiRFmarco device tree .dts
ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig
ARM: PRIMA2: initialize l2x0 according to mach from DT
ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco
ARM: PRIMA2: rstc: enable the support for Marco
ARM: PRIMA2: rtciobg: it is also compatible with marco
ARM: PRIMA2: irq: make prima2 irq can work even we enable GIC for
Marco
ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructures
ARM: PRIMA2: provide two DEBUG_LL ports for prima2 and marco
arch/arm/Kconfig | 1 +
arch/arm/Kconfig.debug | 14 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/marco-evb.dts | 51 ++
arch/arm/boot/dts/marco.dtsi | 749 ++++++++++++++++++++++
arch/arm/configs/prima2_defconfig | 3 +
arch/arm/mach-prima2/Kconfig | 10 +
arch/arm/mach-prima2/Makefile | 5 +-
arch/arm/mach-prima2/common.c | 46 ++-
arch/arm/mach-prima2/common.h | 14 +-
arch/arm/mach-prima2/headsmp.S | 79 +++
arch/arm/mach-prima2/hotplug.c | 41 ++
arch/arm/mach-prima2/include/mach/irqs.h | 4 +-
arch/arm/mach-prima2/include/mach/uart.h | 6 +
arch/arm/mach-prima2/include/mach/uncompress.h | 3 +
arch/arm/mach-prima2/irq.c | 16 +-
arch/arm/mach-prima2/l2x0.c | 14 +
arch/arm/mach-prima2/platsmp.c | 170 +++++
arch/arm/mach-prima2/rstc.c | 45 +-
arch/arm/mach-prima2/rtciobrg.c | 1 +
arch/arm/mach-prima2/timer-marco.c | 359 +++++++++++
arch/arm/mach-prima2/{timer.c => timer-prima2.c} | 4 +-
22 files changed, 1609 insertions(+), 27 deletions(-)
create mode 100644 arch/arm/boot/dts/marco-evb.dts
create mode 100644 arch/arm/boot/dts/marco.dtsi
create mode 100644 arch/arm/mach-prima2/headsmp.S
create mode 100644 arch/arm/mach-prima2/hotplug.c
create mode 100644 arch/arm/mach-prima2/platsmp.c
create mode 100644 arch/arm/mach-prima2/timer-marco.c
rename arch/arm/mach-prima2/{timer.c => timer-prima2.c} (98%)
--
1.7.5.4
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 1/9] ARM: PRIMA2: add CSR SiRFmarco device tree .dts 2012-12-20 12:13 [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC Barry Song @ 2012-12-20 12:13 ` Barry Song 2013-01-02 12:19 ` Mark Rutland 2012-12-20 12:13 ` [PATCH 2/9] ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig Barry Song ` (3 subsequent siblings) 4 siblings, 1 reply; 12+ messages in thread From: Barry Song @ 2012-12-20 12:13 UTC (permalink / raw) To: linux-arm-kernel From: Barry Song <Baohua.Song@csr.com> SiRFmarco is a dual-core cortex-a9 SMP SoC from CSR. this patch adds the .dtsi and a basic evb board .dts for it. Signed-off-by: Barry Song <Baohua.Song@csr.com> --- arch/arm/boot/dts/marco-evb.dts | 51 +++ arch/arm/boot/dts/marco.dtsi | 749 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 800 insertions(+), 0 deletions(-) create mode 100644 arch/arm/boot/dts/marco-evb.dts create mode 100644 arch/arm/boot/dts/marco.dtsi diff --git a/arch/arm/boot/dts/marco-evb.dts b/arch/arm/boot/dts/marco-evb.dts new file mode 100644 index 0000000..4e68d3c --- /dev/null +++ b/arch/arm/boot/dts/marco-evb.dts @@ -0,0 +1,51 @@ +/* + * DTS file for CSR SiRFmarco Evaluation Board + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +/include/ "marco.dtsi" + +/ { + model = "CSR SiRFmarco Evaluation Board"; + compatible = "sirf,marco", "sirf,marco-cb"; + + memory { + reg = <0x40000000 0x60000000>; + }; + + axi { + peri-iobg { + uart1: uart at cc060000 { + status = "okay"; + }; + i2c0: i2c at cc0e0000 { + status = "okay"; + fpga-cpld at 4d { + compatible = "sirf,fpga-cpld"; + reg = <0x4d>; + }; + }; + spi1: spi at cc170000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + spi at 0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + pci-iobg { + sd0: sdhci at cd000000 { + bus-width = <8>; + status = "okay"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi new file mode 100644 index 0000000..00b5eb7 --- /dev/null +++ b/arch/arm/boot/dts/marco.dtsi @@ -0,0 +1,749 @@ +/* + * DTS file for CSR SiRFmarco SoC + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" +/ { + compatible = "sirf,marco"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + cpu at 0 { + compatible = "arm,cortex-a9"; + }; + cpu at 1 { + compatible = "arm,cortex-a9"; + }; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x40000000 0xa0000000>; + + l2-cache-controller at c0030000 { + compatible = "arm,pl310-cache", "sirf,marco-pl310-cache"; + reg = <0xc0030000 0x1000>; + interrupts = <0 59 0>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 1>; + arm,filter-ranges = <0x40000000 0x80000000>; + }; + + gic: interrupt-controller at c0011000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xc0011000 0x1000>, + <0xc0010100 0x0100>; + }; + + rstc-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc2000000 0xc2000000 0x1000000>; + + reset-controller at c2000000 { + compatible = "sirf,marco-rstc"; + reg = <0xc2000000 0x10000>; + }; + }; + + sys-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc3000000 0xc3000000 0x1000000>; + + clock-controller at c3000000 { + compatible = "sirf,marco-clkc"; + reg = <0xc3000000 0x1000>; + interrupts = <0 3 0>; + }; + + rsc-controller at c3010000 { + compatible = "sirf,marco-rsc"; + reg = <0xc3010000 0x1000>; + }; + }; + + mem-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc4000000 0xc4000000 0x1000000>; + + memory-controller at c4000000 { + compatible = "sirf,marco-memc"; + reg = <0xc4000000 0x10000>; + interrupts = <0 27 0>; + }; + }; + + disp-iobg0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc5000000 0xc5000000 0x1000000>; + + display0 at c5000000 { + compatible = "sirf,marco-lcd"; + reg = <0xc5000000 0x10000>; + interrupts = <0 30 0>; + }; + + vpp0 at c5010000 { + compatible = "sirf,marco-vpp"; + reg = <0xc5010000 0x10000>; + interrupts = <0 31 0>; + }; + }; + + disp-iobg1 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc6000000 0xc6000000 0x1000000>; + + display1 at c6000000 { + compatible = "sirf,marco-lcd"; + reg = <0xc6000000 0x10000>; + interrupts = <0 62 0>; + }; + + vpp1 at c6010000 { + compatible = "sirf,marco-vpp"; + reg = <0xc6010000 0x10000>; + interrupts = <0 63 0>; + }; + }; + + graphics-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc8000000 0xc8000000 0x1000000>; + + graphics at c8000000 { + compatible = "powervr,sgx540"; + reg = <0xc8000000 0x1000000>; + interrupts = <0 6 0>; + }; + }; + + multimedia-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc9000000 0xc9000000 0x1000000>; + + multimedia at a0000000 { + compatible = "sirf,marco-video-codec"; + reg = <0xc9000000 0x1000000>; + interrupts = <0 5 0>; + }; + }; + + dsp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xca000000 0xca000000 0x2000000>; + + dspif at ca000000 { + compatible = "sirf,marco-dspif"; + reg = <0xca000000 0x10000>; + interrupts = <0 9 0>; + }; + + gps at ca010000 { + compatible = "sirf,marco-gps"; + reg = <0xca010000 0x10000>; + interrupts = <0 7 0>; + }; + + dsp at cb000000 { + compatible = "sirf,marco-dsp"; + reg = <0xcb000000 0x1000000>; + interrupts = <0 8 0>; + }; + }; + + peri-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xcc000000 0xcc000000 0x2000000>; + + timer at cc020000 { + compatible = "sirf,marco-tick"; + reg = <0xcc020000 0x1000>; + interrupts = <0 0 0 + 0 1 0 + 0 2 0 + 0 49 0 + 0 50 0 + 0 51 0>; + }; + + nand at cc030000 { + compatible = "sirf,marco-nand"; + reg = <0xcc030000 0x10000>; + interrupts = <0 41 0>; + }; + + audio at cc040000 { + compatible = "sirf,marco-audio"; + reg = <0xcc040000 0x10000>; + interrupts = <0 35 0>; + }; + + uart0: uart at cc050000 { + cell-index = <0>; + compatible = "sirf,marco-uart"; + reg = <0xcc050000 0x1000>; + interrupts = <0 17 0>; + fifosize = <128>; + status = "disabled"; + }; + + uart1: uart at cc060000 { + cell-index = <1>; + compatible = "sirf,marco-uart"; + reg = <0xcc060000 0x1000>; + interrupts = <0 18 0>; + fifosize = <32>; + status = "disabled"; + }; + + uart2: uart at cc070000 { + cell-index = <2>; + compatible = "sirf,marco-uart"; + reg = <0xcc070000 0x1000>; + interrupts = <0 19 0>; + fifosize = <128>; + status = "disabled"; + }; + + uart3: uart at cc190000 { + cell-index = <3>; + compatible = "sirf,marco-uart"; + reg = <0xcc190000 0x1000>; + interrupts = <0 66 0>; + fifosize = <128>; + status = "disabled"; + }; + + uart4: uart at cc1a0000 { + cell-index = <4>; + compatible = "sirf,marco-uart"; + reg = <0xcc1a0000 0x1000>; + interrupts = <0 69 0>; + fifosize = <128>; + status = "disabled"; + }; + + usp0: usp at cc080000 { + cell-index = <0>; + compatible = "sirf,marco-usp"; + reg = <0xcc080000 0x10000>; + interrupts = <0 20 0>; + status = "disabled"; + }; + + usp1: usp at cc090000 { + cell-index = <1>; + compatible = "sirf,marco-usp"; + reg = <0xcc090000 0x10000>; + interrupts = <0 21 0>; + status = "disabled"; + }; + + usp2: usp at cc0a0000 { + cell-index = <2>; + compatible = "sirf,marco-usp"; + reg = <0xcc0a0000 0x10000>; + interrupts = <0 22 0>; + status = "disabled"; + }; + + dmac0: dma-controller at cc0b0000 { + cell-index = <0>; + compatible = "sirf,marco-dmac"; + reg = <0xcc0b0000 0x10000>; + interrupts = <0 12 0>; + }; + + dmac1: dma-controller at cc160000 { + cell-index = <1>; + compatible = "sirf,marco-dmac"; + reg = <0xcc160000 0x10000>; + interrupts = <0 13 0>; + }; + + vip at cc0c0000 { + compatible = "sirf,marco-vip"; + reg = <0xcc0c0000 0x10000>; + }; + + spi0: spi at cc0d0000 { + cell-index = <0>; + compatible = "sirf,marco-spi"; + reg = <0xcc0d0000 0x10000>; + interrupts = <0 15 0>; + sirf,spi-num-chipselects = <1>; + cs-gpios = <&gpio 0 0>; + sirf,spi-dma-rx-channel = <25>; + sirf,spi-dma-tx-channel = <20>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi at cc170000 { + cell-index = <1>; + compatible = "sirf,marco-spi"; + reg = <0xcc170000 0x10000>; + interrupts = <0 16 0>; + sirf,spi-num-chipselects = <1>; + cs-gpios = <&gpio 0 0>; + sirf,spi-dma-rx-channel = <12>; + sirf,spi-dma-tx-channel = <13>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c at cc0e0000 { + cell-index = <0>; + compatible = "sirf,marco-i2c"; + reg = <0xcc0e0000 0x10000>; + interrupts = <0 24 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c at cc0f0000 { + cell-index = <1>; + compatible = "sirf,marco-i2c"; + reg = <0xcc0f0000 0x10000>; + interrupts = <0 25 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + tsc at cc110000 { + compatible = "sirf,marco-tsc"; + reg = <0xcc110000 0x10000>; + interrupts = <0 33 0>; + }; + + gpio: pinctrl at cc120000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sirf,marco-pinctrl"; + reg = <0xcc120000 0x10000>; + interrupts = <0 43 0>, + <0 44 0>, + <0 45 0>, + <0 46 0>, + <0 47 0>; + gpio-controller; + interrupt-controller; + + lcd_16pins_a: lcd0 at 0 { + lcd { + sirf,pins = "lcd_16bitsgrp"; + sirf,function = "lcd_16bits"; + }; + }; + lcd_18pins_a: lcd0 at 1 { + lcd { + sirf,pins = "lcd_18bitsgrp"; + sirf,function = "lcd_18bits"; + }; + }; + lcd_24pins_a: lcd0 at 2 { + lcd { + sirf,pins = "lcd_24bitsgrp"; + sirf,function = "lcd_24bits"; + }; + }; + lcdrom_pins_a: lcdrom0 at 0 { + lcd { + sirf,pins = "lcdromgrp"; + sirf,function = "lcdrom"; + }; + }; + uart0_pins_a: uart0 at 0 { + uart { + sirf,pins = "uart0grp"; + sirf,function = "uart0"; + }; + }; + uart1_pins_a: uart1 at 0 { + uart { + sirf,pins = "uart1grp"; + sirf,function = "uart1"; + }; + }; + uart2_pins_a: uart2 at 0 { + uart { + sirf,pins = "uart2grp"; + sirf,function = "uart2"; + }; + }; + uart2_noflow_pins_a: uart2 at 1 { + uart { + sirf,pins = "uart2_nostreamctrlgrp"; + sirf,function = "uart2_nostreamctrl"; + }; + }; + spi0_pins_a: spi0 at 0 { + spi { + sirf,pins = "spi0grp"; + sirf,function = "spi0"; + }; + }; + spi1_pins_a: spi1 at 0 { + spi { + sirf,pins = "spi1grp"; + sirf,function = "spi1"; + }; + }; + i2c0_pins_a: i2c0 at 0 { + i2c { + sirf,pins = "i2c0grp"; + sirf,function = "i2c0"; + }; + }; + i2c1_pins_a: i2c1 at 0 { + i2c { + sirf,pins = "i2c1grp"; + sirf,function = "i2c1"; + }; + }; + pwm0_pins_a: pwm0 at 0 { + pwm { + sirf,pins = "pwm0grp"; + sirf,function = "pwm0"; + }; + }; + pwm1_pins_a: pwm1 at 0 { + pwm { + sirf,pins = "pwm1grp"; + sirf,function = "pwm1"; + }; + }; + pwm2_pins_a: pwm2 at 0 { + pwm { + sirf,pins = "pwm2grp"; + sirf,function = "pwm2"; + }; + }; + pwm3_pins_a: pwm3 at 0 { + pwm { + sirf,pins = "pwm3grp"; + sirf,function = "pwm3"; + }; + }; + gps_pins_a: gps at 0 { + gps { + sirf,pins = "gpsgrp"; + sirf,function = "gps"; + }; + }; + vip_pins_a: vip at 0 { + vip { + sirf,pins = "vipgrp"; + sirf,function = "vip"; + }; + }; + sdmmc0_pins_a: sdmmc0 at 0 { + sdmmc0 { + sirf,pins = "sdmmc0grp"; + sirf,function = "sdmmc0"; + }; + }; + sdmmc1_pins_a: sdmmc1 at 0 { + sdmmc1 { + sirf,pins = "sdmmc1grp"; + sirf,function = "sdmmc1"; + }; + }; + sdmmc2_pins_a: sdmmc2 at 0 { + sdmmc2 { + sirf,pins = "sdmmc2grp"; + sirf,function = "sdmmc2"; + }; + }; + sdmmc3_pins_a: sdmmc3 at 0 { + sdmmc3 { + sirf,pins = "sdmmc3grp"; + sirf,function = "sdmmc3"; + }; + }; + sdmmc4_pins_a: sdmmc4 at 0 { + sdmmc4 { + sirf,pins = "sdmmc4grp"; + sirf,function = "sdmmc4"; + }; + }; + sdmmc5_pins_a: sdmmc5 at 0 { + sdmmc5 { + sirf,pins = "sdmmc5grp"; + sirf,function = "sdmmc5"; + }; + }; + i2s_pins_a: i2s at 0 { + i2s { + sirf,pins = "i2sgrp"; + sirf,function = "i2s"; + }; + }; + ac97_pins_a: ac97 at 0 { + ac97 { + sirf,pins = "ac97grp"; + sirf,function = "ac97"; + }; + }; + nand_pins_a: nand at 0 { + nand { + sirf,pins = "nandgrp"; + sirf,function = "nand"; + }; + }; + usp0_pins_a: usp0 at 0 { + usp0 { + sirf,pins = "usp0grp"; + sirf,function = "usp0"; + }; + }; + usp1_pins_a: usp1 at 0 { + usp1 { + sirf,pins = "usp1grp"; + sirf,function = "usp1"; + }; + }; + usp2_pins_a: usp2 at 0 { + usp2 { + sirf,pins = "usp2grp"; + sirf,function = "usp2"; + }; + }; + usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus at 0 { + usb0_utmi_drvbus { + sirf,pins = "usb0_utmi_drvbusgrp"; + sirf,function = "usb0_utmi_drvbus"; + }; + }; + usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus at 0 { + usb1_utmi_drvbus { + sirf,pins = "usb1_utmi_drvbusgrp"; + sirf,function = "usb1_utmi_drvbus"; + }; + }; + warm_rst_pins_a: warm_rst at 0 { + warm_rst { + sirf,pins = "warm_rstgrp"; + sirf,function = "warm_rst"; + }; + }; + pulse_count_pins_a: pulse_count at 0 { + pulse_count { + sirf,pins = "pulse_countgrp"; + sirf,function = "pulse_count"; + }; + }; + cko0_rst_pins_a: cko0_rst at 0 { + cko0_rst { + sirf,pins = "cko0_rstgrp"; + sirf,function = "cko0_rst"; + }; + }; + cko1_rst_pins_a: cko1_rst at 0 { + cko1_rst { + sirf,pins = "cko1_rstgrp"; + sirf,function = "cko1_rst"; + }; + }; + }; + + pwm at cc130000 { + compatible = "sirf,marco-pwm"; + reg = <0xcc130000 0x10000>; + }; + + efusesys at cc140000 { + compatible = "sirf,marco-efuse"; + reg = <0xcc140000 0x10000>; + }; + + pulsec at cc150000 { + compatible = "sirf,marco-pulsec"; + reg = <0xcc150000 0x10000>; + interrupts = <0 48 0>; + }; + + pci-iobg { + compatible = "sirf,marco-pciiobg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xcd000000 0xcd000000 0x1000000>; + + sd0: sdhci at cd000000 { + cell-index = <0>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd000000 0x100000>; + interrupts = <0 38 0>; + status = "disabled"; + }; + + sd1: sdhci at cd100000 { + cell-index = <1>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd100000 0x100000>; + interrupts = <0 38 0>; + status = "disabled"; + }; + + sd2: sdhci at cd200000 { + cell-index = <2>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd200000 0x100000>; + interrupts = <0 23 0>; + status = "disabled"; + }; + + sd3: sdhci at cd300000 { + cell-index = <3>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd300000 0x100000>; + interrupts = <0 23 0>; + status = "disabled"; + }; + + sd4: sdhci at cd400000 { + cell-index = <4>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd400000 0x100000>; + interrupts = <0 39 0>; + status = "disabled"; + }; + + sd5: sdhci at cd500000 { + cell-index = <5>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd500000 0x100000>; + interrupts = <0 39 0>; + status = "disabled"; + }; + + pci-copy at cd900000 { + compatible = "sirf,marco-pcicp"; + reg = <0xcd900000 0x100000>; + interrupts = <0 40 0>; + }; + + rom-interface at cda00000 { + compatible = "sirf,marco-romif"; + reg = <0xcda00000 0x100000>; + }; + }; + }; + + rtc-iobg { + compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xc1000000 0x10000>; + + gpsrtc at 1000 { + compatible = "sirf,marco-gpsrtc"; + reg = <0x1000 0x1000>; + interrupts = <0 55 0>, + <0 56 0>, + <0 57 0>; + }; + + sysrtc at 2000 { + compatible = "sirf,marco-sysrtc"; + reg = <0x2000 0x1000>; + interrupts = <0 52 0>, + <0 53 0>, + <0 54 0>; + }; + + pwrc at 3000 { + compatible = "sirf,marco-pwrc"; + reg = <0x3000 0x1000>; + interrupts = <0 32 0>; + }; + }; + + uus-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xce000000 0xce000000 0x1000000>; + + usb0: usb at ce000000 { + compatible = "chipidea,ci13611a-marco"; + reg = <0xce000000 0x10000>; + interrupts = <0 10 0>; + }; + + usb1: usb at ce010000 { + compatible = "chipidea,ci13611a-marco"; + reg = <0xce010000 0x10000>; + interrupts = <0 11 0>; + }; + + security at ce020000 { + compatible = "sirf,marco-security"; + reg = <0xce020000 0x10000>; + interrupts = <0 42 0>; + }; + }; + + can-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xd0000000 0xd0000000 0x1000000>; + + can0: can at d0000000 { + compatible = "sirf,marco-can"; + reg = <0xd0000000 0x10000>; + }; + + can1: can at d0010000 { + compatible = "sirf,marco-can"; + reg = <0xd0010000 0x10000>; + }; + }; + + lvds-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xd1000000 0xd1000000 0x1000000>; + + lvds at d1000000 { + compatible = "sirf,marco-lvds"; + reg = <0xd1000000 0x10000>; + interrupts = <0 64 0>; + }; + }; + }; +}; -- 1.7.5.4 Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/9] ARM: PRIMA2: add CSR SiRFmarco device tree .dts 2012-12-20 12:13 ` [PATCH 1/9] ARM: PRIMA2: add CSR SiRFmarco device tree .dts Barry Song @ 2013-01-02 12:19 ` Mark Rutland 2013-01-03 10:28 ` Barry Song 0 siblings, 1 reply; 12+ messages in thread From: Mark Rutland @ 2013-01-02 12:19 UTC (permalink / raw) To: linux-arm-kernel On Thu, Dec 20, 2012 at 12:13:51PM +0000, Barry Song wrote: > From: Barry Song <Baohua.Song@csr.com> > > SiRFmarco is a dual-core cortex-a9 SMP SoC from CSR. this patch > adds the .dtsi and a basic evb board .dts for it. > > Signed-off-by: Barry Song <Baohua.Song@csr.com> > --- > arch/arm/boot/dts/marco-evb.dts | 51 +++ > arch/arm/boot/dts/marco.dtsi | 749 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 800 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/boot/dts/marco-evb.dts > create mode 100644 arch/arm/boot/dts/marco.dtsi [...] > diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi > new file mode 100644 > index 0000000..00b5eb7 > --- /dev/null > +++ b/arch/arm/boot/dts/marco.dtsi > @@ -0,0 +1,749 @@ > +/* > + * DTS file for CSR SiRFmarco SoC > + * > + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. > + * > + * Licensed under GPLv2 or later. > + */ > + > +/include/ "skeleton.dtsi" > +/ { > + compatible = "sirf,marco"; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&gic>; > + > + cpus { > + cpu at 0 { > + compatible = "arm,cortex-a9"; > + }; > + cpu at 1 { > + compatible = "arm,cortex-a9"; > + }; > + }; It would be good if the cpu nodes had their reg property set, so the logical map can be populated. They should also have their device_type set to "cpu". > + > + axi { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x40000000 0x40000000 0xa0000000>; > + > + l2-cache-controller at c0030000 { > + compatible = "arm,pl310-cache", "sirf,marco-pl310-cache"; I believe the order of these should be swapped such that the most specific match comes first. > + reg = <0xc0030000 0x1000>; > + interrupts = <0 59 0>; > + arm,tag-latency = <1 1 1>; > + arm,data-latency = <1 1 1>; > + arm,filter-ranges = <0x40000000 0x80000000>; > + }; [...] > + peri-iobg { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0xcc000000 0xcc000000 0x2000000>; > + > + timer at cc020000 { > + compatible = "sirf,marco-tick"; > + reg = <0xcc020000 0x1000>; > + interrupts = <0 0 0 > + 0 1 0 > + 0 2 0 > + 0 49 0 > + 0 50 0 > + 0 51 0>; Small nit: could we have these individually bracketed as below? We're doing this fairly consistently across platforms now. [...] > + gpio: pinctrl at cc120000 { > + #gpio-cells = <2>; > + #interrupt-cells = <2>; > + compatible = "sirf,marco-pinctrl"; > + reg = <0xcc120000 0x10000>; > + interrupts = <0 43 0>, > + <0 44 0>, > + <0 45 0>, > + <0 46 0>, > + <0 47 0>; >From this point on you seem to bracket interrupts individually consistently. Thanks, Mark. ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/9] ARM: PRIMA2: add CSR SiRFmarco device tree .dts 2013-01-02 12:19 ` Mark Rutland @ 2013-01-03 10:28 ` Barry Song 0 siblings, 0 replies; 12+ messages in thread From: Barry Song @ 2013-01-03 10:28 UTC (permalink / raw) To: linux-arm-kernel Hi Mark, Thanks very much for reviewing. 2013/1/2, Mark Rutland <mark.rutland@arm.com>: > On Thu, Dec 20, 2012 at 12:13:51PM +0000, Barry Song wrote: >> From: Barry Song <Baohua.Song@csr.com> >> >> SiRFmarco is a dual-core cortex-a9 SMP SoC from CSR. this patch >> adds the .dtsi and a basic evb board .dts for it. >> >> Signed-off-by: Barry Song <Baohua.Song@csr.com> >> --- >> arch/arm/boot/dts/marco-evb.dts | 51 +++ >> arch/arm/boot/dts/marco.dtsi | 749 >> +++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 800 insertions(+), 0 deletions(-) >> create mode 100644 arch/arm/boot/dts/marco-evb.dts >> create mode 100644 arch/arm/boot/dts/marco.dtsi > > [...] > >> diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi >> new file mode 100644 >> index 0000000..00b5eb7 >> --- /dev/null >> +++ b/arch/arm/boot/dts/marco.dtsi >> @@ -0,0 +1,749 @@ >> +/* >> + * DTS file for CSR SiRFmarco SoC >> + * >> + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group >> company. >> + * >> + * Licensed under GPLv2 or later. >> + */ >> + >> +/include/ "skeleton.dtsi" >> +/ { >> + compatible = "sirf,marco"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + interrupt-parent = <&gic>; >> + >> + cpus { >> + cpu at 0 { >> + compatible = "arm,cortex-a9"; >> + }; >> + cpu at 1 { >> + compatible = "arm,cortex-a9"; >> + }; >> + }; > > It would be good if the cpu nodes had their reg property set, so the > logical > map can be populated. They should also have their device_type set to "cpu". > agree. >> + >> + axi { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0x40000000 0x40000000 0xa0000000>; >> + >> + l2-cache-controller at c0030000 { >> + compatible = "arm,pl310-cache", >> "sirf,marco-pl310-cache"; > > I believe the order of these should be swapped such that the most specific > match comes first. agree since that compatible is a list of strings. The first string in the list specifies the exact device that the node represents in the form "<manufacturer>,<model>". The following strings represent other devices that the device is compatible with. > >> + reg = <0xc0030000 0x1000>; >> + interrupts = <0 59 0>; >> + arm,tag-latency = <1 1 1>; >> + arm,data-latency = <1 1 1>; >> + arm,filter-ranges = <0x40000000 0x80000000>; >> + }; > > [...] > >> + peri-iobg { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0xcc000000 0xcc000000 0x2000000>; >> + >> + timer at cc020000 { >> + compatible = "sirf,marco-tick"; >> + reg = <0xcc020000 0x1000>; >> + interrupts = <0 0 0 >> + 0 1 0 >> + 0 2 0 >> + 0 49 0 >> + 0 50 0 >> + 0 51 0>; > > Small nit: could we have these individually bracketed as below? We're doing > this fairly consistently across platforms now. agree. > > [...] > >> + gpio: pinctrl at cc120000 { >> + #gpio-cells = <2>; >> + #interrupt-cells = <2>; >> + compatible = "sirf,marco-pinctrl"; >> + reg = <0xcc120000 0x10000>; >> + interrupts = <0 43 0>, >> + <0 44 0>, >> + <0 45 0>, >> + <0 46 0>, >> + <0 47 0>; > > From this point on you seem to bracket interrupts individually > consistently. > > Thanks, > Mark. -barry ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/9] ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig 2012-12-20 12:13 [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC Barry Song 2012-12-20 12:13 ` [PATCH 1/9] ARM: PRIMA2: add CSR SiRFmarco device tree .dts Barry Song @ 2012-12-20 12:13 ` Barry Song 2012-12-20 12:13 ` [PATCH 3/9] ARM: PRIMA2: initialize l2x0 according to mach from DT Barry Song ` (2 subsequent siblings) 4 siblings, 0 replies; 12+ messages in thread From: Barry Song @ 2012-12-20 12:13 UTC (permalink / raw) To: linux-arm-kernel From: Barry Song <Baohua.Song@csr.com> prima2 and marco have different memory base address. prima2 begins from 0 and marco begins from Signed-off-by: Barry Song <Baohua.Song@csr.com> --- arch/arm/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8c83d98..aa8ea1a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -396,6 +396,7 @@ config ARCH_GEMINI config ARCH_SIRF bool "CSR SiRF" select ARCH_REQUIRE_GPIOLIB + select AUTO_ZRELADDR select COMMON_CLK select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP -- 1.7.5.4 Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/9] ARM: PRIMA2: initialize l2x0 according to mach from DT 2012-12-20 12:13 [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC Barry Song 2012-12-20 12:13 ` [PATCH 1/9] ARM: PRIMA2: add CSR SiRFmarco device tree .dts Barry Song 2012-12-20 12:13 ` [PATCH 2/9] ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig Barry Song @ 2012-12-20 12:13 ` Barry Song 2013-01-02 13:43 ` Mark Rutland 2012-12-20 12:13 ` [PATCH 4/9] ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco Barry Song 2013-01-06 2:52 ` [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC Barry Song 4 siblings, 1 reply; 12+ messages in thread From: Barry Song @ 2012-12-20 12:13 UTC (permalink / raw) To: linux-arm-kernel From: Barry Song <Baohua.Song@csr.com> prima2 and marco have diffetent l2 cache configuration, so we initialize l2x0 cache based on dtb given to kernel. Signed-off-by: Barry Song <Baohua.Song@csr.com> --- arch/arm/mach-prima2/l2x0.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c index c998377..909cc6f 100644 --- a/arch/arm/mach-prima2/l2x0.c +++ b/arch/arm/mach-prima2/l2x0.c @@ -16,6 +16,11 @@ static struct of_device_id prima2_l2x0_ids[] = { {}, }; +static struct of_device_id marco_l2x0_ids[] = { + { .compatible = "sirf,marco-pl310-cache" }, + {}, +}; + static int __init sirfsoc_l2x0_init(void) { struct device_node *np; @@ -26,6 +31,15 @@ static int __init sirfsoc_l2x0_init(void) return l2x0_of_init(0x40000, 0); } + np = of_find_matching_node(NULL, marco_l2x0_ids); + if (np) { + pr_info("Initializing marco L2 cache\n"); + /* Way size: 32KB Associativity: 16-way */ + return l2x0_of_init((2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | + (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT), + L2X0_AUX_CTRL_MASK); + } + return 0; } early_initcall(sirfsoc_l2x0_init); -- 1.7.5.4 Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog@www.csr.com/blog ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/9] ARM: PRIMA2: initialize l2x0 according to mach from DT 2012-12-20 12:13 ` [PATCH 3/9] ARM: PRIMA2: initialize l2x0 according to mach from DT Barry Song @ 2013-01-02 13:43 ` Mark Rutland 2013-01-03 10:20 ` Barry Song 0 siblings, 1 reply; 12+ messages in thread From: Mark Rutland @ 2013-01-02 13:43 UTC (permalink / raw) To: linux-arm-kernel On Thu, Dec 20, 2012 at 12:13:53PM +0000, Barry Song wrote: > From: Barry Song <Baohua.Song@csr.com> > > prima2 and marco have diffetent l2 cache configuration, so > we initialize l2x0 cache based on dtb given to kernel. > > Signed-off-by: Barry Song <Baohua.Song@csr.com> > --- > arch/arm/mach-prima2/l2x0.c | 14 ++++++++++++++ > 1 files changed, 14 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c > index c998377..909cc6f 100644 > --- a/arch/arm/mach-prima2/l2x0.c > +++ b/arch/arm/mach-prima2/l2x0.c > @@ -16,6 +16,11 @@ static struct of_device_id prima2_l2x0_ids[] = { > {}, > }; > > +static struct of_device_id marco_l2x0_ids[] = { > + { .compatible = "sirf,marco-pl310-cache" }, > + {}, > +}; > + > static int __init sirfsoc_l2x0_init(void) > { > struct device_node *np; > @@ -26,6 +31,15 @@ static int __init sirfsoc_l2x0_init(void) > return l2x0_of_init(0x40000, 0); > } > > + np = of_find_matching_node(NULL, marco_l2x0_ids); > + if (np) { > + pr_info("Initializing marco L2 cache\n"); > + /* Way size: 32KB Associativity: 16-way */ > + return l2x0_of_init((2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | > + (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT), > + L2X0_AUX_CTRL_MASK); > + } > + > return 0; > } > early_initcall(sirfsoc_l2x0_init); Rather than individually testing each match against the table, could you not place the configuration values in a struct, and map to this with of_device_id::data? Thanks, Mark. ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/9] ARM: PRIMA2: initialize l2x0 according to mach from DT 2013-01-02 13:43 ` Mark Rutland @ 2013-01-03 10:20 ` Barry Song 0 siblings, 0 replies; 12+ messages in thread From: Barry Song @ 2013-01-03 10:20 UTC (permalink / raw) To: linux-arm-kernel 2013/1/2, Mark Rutland <mark.rutland@arm.com>: > On Thu, Dec 20, 2012 at 12:13:53PM +0000, Barry Song wrote: >> From: Barry Song <Baohua.Song@csr.com> >> >> prima2 and marco have diffetent l2 cache configuration, so >> we initialize l2x0 cache based on dtb given to kernel. >> >> Signed-off-by: Barry Song <Baohua.Song@csr.com> >> --- >> arch/arm/mach-prima2/l2x0.c | 14 ++++++++++++++ >> 1 files changed, 14 insertions(+), 0 deletions(-) >> >> diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c >> index c998377..909cc6f 100644 >> --- a/arch/arm/mach-prima2/l2x0.c >> +++ b/arch/arm/mach-prima2/l2x0.c >> @@ -16,6 +16,11 @@ static struct of_device_id prima2_l2x0_ids[] = { >> {}, >> }; >> >> +static struct of_device_id marco_l2x0_ids[] = { >> + { .compatible = "sirf,marco-pl310-cache" }, >> + {}, >> +}; >> + >> static int __init sirfsoc_l2x0_init(void) >> { >> struct device_node *np; >> @@ -26,6 +31,15 @@ static int __init sirfsoc_l2x0_init(void) >> return l2x0_of_init(0x40000, 0); >> } >> >> + np = of_find_matching_node(NULL, marco_l2x0_ids); >> + if (np) { >> + pr_info("Initializing marco L2 cache\n"); >> + /* Way size: 32KB Associativity: 16-way */ >> + return l2x0_of_init((2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | >> + (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT), >> + L2X0_AUX_CTRL_MASK); >> + } >> + >> return 0; >> } >> early_initcall(sirfsoc_l2x0_init); > > Rather than individually testing each match against the table, could you > not > place the configuration values in a struct, and map to this with > of_device_id::data? ok. good idea. > > Thanks, > Mark. > -barry ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/9] ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco 2012-12-20 12:13 [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC Barry Song ` (2 preceding siblings ...) 2012-12-20 12:13 ` [PATCH 3/9] ARM: PRIMA2: initialize l2x0 according to mach from DT Barry Song @ 2012-12-20 12:13 ` Barry Song 2013-01-06 2:52 ` [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC Barry Song 4 siblings, 0 replies; 12+ messages in thread From: Barry Song @ 2012-12-20 12:13 UTC (permalink / raw) To: linux-arm-kernel From: Barry Song <Baohua.Song@csr.com> Marco timer has different timer IP with prima2, so rename the current timer to timer-prima2 so that we can add timer-marco. at the same time, if we don't find prima2 timer node in dt, don't panic the system as we will make prima2 and marco use same kernel image. Signed-off-by: Barry Song <Baohua.Song@csr.com> --- arch/arm/mach-prima2/Makefile | 2 +- arch/arm/mach-prima2/common.c | 2 +- arch/arm/mach-prima2/common.h | 2 +- arch/arm/mach-prima2/{timer.c => timer-prima2.c} | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) rename arch/arm/mach-prima2/{timer.c => timer-prima2.c} (98%) diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index fc9ce22..0007a6e 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -1,4 +1,3 @@ -obj-y := timer.o obj-y += rstc.o obj-y += common.o obj-y += rtciobrg.o @@ -6,3 +5,4 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_CACHE_L2X0) += l2x0.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o obj-$(CONFIG_SIRF_IRQ) += irq.o +obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index f25a541..0f30227 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -40,7 +40,7 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ .map_io = sirfsoc_map_lluart, .init_irq = sirfsoc_of_irq_init, - .timer = &sirfsoc_timer, + .timer = &sirfsoc_prima2_timer, .dma_zone_size = SZ_256M, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index 60d826f..b3b63d6 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h @@ -12,7 +12,7 @@ #include <linux/init.h> #include <asm/mach/time.h> -extern struct sys_timer sirfsoc_timer; +extern struct sys_timer sirfsoc_prima2_timer; extern void __init sirfsoc_of_irq_init(void); extern void __init sirfsoc_of_clk_init(void); diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer-prima2.c similarity index 98% rename from arch/arm/mach-prima2/timer.c rename to arch/arm/mach-prima2/timer-prima2.c index d95bf25..305cbcc 100644 --- a/arch/arm/mach-prima2/timer.c +++ b/arch/arm/mach-prima2/timer-prima2.c @@ -233,7 +233,7 @@ static void __init sirfsoc_of_timer_map(void) np = of_find_matching_node(NULL, timer_ids); if (!np) - panic("unable to find compatible timer node in dtb\n"); + return; sirfsoc_timer_base = of_iomap(np, 0); if (!sirfsoc_timer_base) panic("unable to map timer cpu registers\n"); @@ -246,6 +246,6 @@ static void __init sirfsoc_of_timer_map(void) of_node_put(np); } -struct sys_timer sirfsoc_timer = { +struct sys_timer sirfsoc_prima2_timer = { .init = sirfsoc_timer_init, }; -- 1.7.5.4 Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC 2012-12-20 12:13 [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC Barry Song ` (3 preceding siblings ...) 2012-12-20 12:13 ` [PATCH 4/9] ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco Barry Song @ 2013-01-06 2:52 ` Barry Song 2013-01-14 11:07 ` Arnd Bergmann 4 siblings, 1 reply; 12+ messages in thread From: Barry Song @ 2013-01-06 2:52 UTC (permalink / raw) To: linux-arm-kernel Hi Arnd, happy new year. 2012/12/20, Barry Song <Barry.Song@csr.com>: > this patch series enables the new CSR SiRFmarco SMP SoC. > > change list: > 1. Marco has different OS timer hardware with Prima2, so add a new > timer-marco > 2. add platsmp.c, headsmp.S and hotplug.c for MPcore support > 3. some hardwares have changed, like rstc, so use of_compatible to branch > Prima2 > and Marco > 4. add initial .dtsi for Marco SoC and initial .dts for the EVB > 5. use GIC for Marco instead of Prima2's IRQ controller > 6. add DEBUG_LL uart ports for Prima2 and Marco debug ports > > Barry Song (9): > ARM: PRIMA2: add CSR SiRFmarco device tree .dts > ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig > ARM: PRIMA2: initialize l2x0 according to mach from DT > ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco > ARM: PRIMA2: rstc: enable the support for Marco > ARM: PRIMA2: rtciobg: it is also compatible with marco > ARM: PRIMA2: irq: make prima2 irq can work even we enable GIC for > Marco > ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructures > ARM: PRIMA2: provide two DEBUG_LL ports for prima2 and marco > except those from Mark, would you kindly give more feedbacks about this series? after this, i'd like to send out a series about SiRF firmware based on trustzone. -barry ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC 2013-01-06 2:52 ` [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC Barry Song @ 2013-01-14 11:07 ` Arnd Bergmann 2013-01-14 14:30 ` Barry Song 0 siblings, 1 reply; 12+ messages in thread From: Arnd Bergmann @ 2013-01-14 11:07 UTC (permalink / raw) To: linux-arm-kernel On Sunday 06 January 2013, Barry Song wrote: > except those from Mark, would you kindly give more feedbacks about > this series? after this, i'd like to send out a series about SiRF > firmware based on trustzone. Hi Barry, Sorry for the late reply. I have looked at the patches and have no further comments besides what Mark already mentioned. Patch 4/9 will unfortunately conflict with the removal of struct sys_timer, but we can probably handle that, or you base your patches on top of the timer/cleanup branch in arm-soc. Arnd ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC 2013-01-14 11:07 ` Arnd Bergmann @ 2013-01-14 14:30 ` Barry Song 0 siblings, 0 replies; 12+ messages in thread From: Barry Song @ 2013-01-14 14:30 UTC (permalink / raw) To: linux-arm-kernel Hi Arnd, Thanks a lot! 2013/1/14 Arnd Bergmann <arnd@arndb.de>: > On Sunday 06 January 2013, Barry Song wrote: >> except those from Mark, would you kindly give more feedbacks about >> this series? after this, i'd like to send out a series about SiRF >> firmware based on trustzone. > > Hi Barry, > > Sorry for the late reply. I have looked at the patches and have no > further comments besides what Mark already mentioned. > > Patch 4/9 will unfortunately conflict with the removal of struct sys_timer, > but we can probably handle that, or you base your patches on top of > the timer/cleanup branch in arm-soc. yes. i have read that sys_timer removing patchset recently. i'll handle the move directly in v2. > > Arnd -barry ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2013-01-14 14:30 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2012-12-20 12:13 [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC Barry Song 2012-12-20 12:13 ` [PATCH 1/9] ARM: PRIMA2: add CSR SiRFmarco device tree .dts Barry Song 2013-01-02 12:19 ` Mark Rutland 2013-01-03 10:28 ` Barry Song 2012-12-20 12:13 ` [PATCH 2/9] ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig Barry Song 2012-12-20 12:13 ` [PATCH 3/9] ARM: PRIMA2: initialize l2x0 according to mach from DT Barry Song 2013-01-02 13:43 ` Mark Rutland 2013-01-03 10:20 ` Barry Song 2012-12-20 12:13 ` [PATCH 4/9] ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco Barry Song 2013-01-06 2:52 ` [PATCH 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC Barry Song 2013-01-14 11:07 ` Arnd Bergmann 2013-01-14 14:30 ` Barry Song
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).