[PATCH 0/2] arm: cache-l2x0: aurora: Various bug fixes

[PATCH 0/2] arm: cache-l2x0: aurora: Various bug fixes

[Gregory CLEMENT]

Hi,

Now that we have more devices and more boards supported, bugs shows
up. Here are a couple of fixes that have been tested on Aramda XP
based boards such as DB-78460-BP and DB-MV784MP-GP, and on Armada 370
based boards such as DB-88F6710-BP-DDR3 and Mirabox. They are 3.8
materials.

Thanks,

Gregory CLEMENT (2):
  arm: cache-l2x0: aurora: Invalidate during clean operation with WT
    enable
  arm: cache-l2x0: aurora: Use writel_relaxed instead of writel

 arch/arm/mm/cache-l2x0.c |   31 +++++++++++++++++++------------
 1 file changed, 19 insertions(+), 12 deletions(-)

-- 
1.7.9.5

[PATCH 1/2] arm: cache-l2x0: aurora: Invalidate during clean operation with WT enable

[Gregory CLEMENT]

This patch fixes a bug for Aurora L2 cache controller when the
write-through mode is enable. For the clean operation even if we don't
have to flush the lines we still need to invalidate them.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mm/cache-l2x0.c |   22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 6911b8b..7ffe943 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -505,15 +505,21 @@ static void aurora_clean_range(unsigned long start, unsigned long end)
 
 static void aurora_flush_range(unsigned long start, unsigned long end)
 {
-	if (!l2_wt_override) {
-		start &= ~(CACHE_LINE_SIZE - 1);
-		end = ALIGN(end, CACHE_LINE_SIZE);
-		while (start != end) {
-			unsigned long range_end = calc_range_end(start, end);
+	start &= ~(CACHE_LINE_SIZE - 1);
+	end = ALIGN(end, CACHE_LINE_SIZE);
+	while (start != end) {
+		unsigned long range_end = calc_range_end(start, end);
+		/*
+		 * If L2 is forced to WT, the L2 will always be clean and we
+		 * just need to invalidate.
+		 */
+		if (l2_wt_override)
 			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
-					AURORA_FLUSH_RANGE_REG);
-			start = range_end;
-		}
+							AURORA_INVAL_RANGE_REG);
+		else
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+							AURORA_FLUSH_RANGE_REG);
+		start = range_end;
 	}
 }
 
-- 
1.7.9.5

[PATCH 2/2] arm: cache-l2x0: aurora: Use writel_relaxed instead of writel

[Gregory CLEMENT]

The use of writel instead of writel_relaxed lead to deadlock in some
situation (SMP on Armada 370 for instance). The use of writel_relaxed
as it was done in the rest of this driver fixes this bug.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mm/cache-l2x0.c |    9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 7ffe943..96a1ae4 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -459,8 +459,8 @@ static void aurora_pa_range(unsigned long start, unsigned long end,
 	unsigned long flags;
 
 	raw_spin_lock_irqsave(&l2x0_lock, flags);
-	writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
-	writel(end, l2x0_base + offset);
+	writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+	writel_relaxed(end, l2x0_base + offset);
 	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 
 	cache_sync();
@@ -674,8 +674,9 @@ static void pl310_resume(void)
 static void aurora_resume(void)
 {
 	if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
-		writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
-		writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+		writel_relaxed(l2x0_saved_regs.aux_ctrl,
+				l2x0_base + L2X0_AUX_CTRL);
+		writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
 	}
 }
 
-- 
1.7.9.5

[PATCH 0/2] arm: cache-l2x0: aurora: Various bug fixes

[Jason Cooper]

On Wed, Dec 19, 2012 at 02:56:25PM +0100, Gregory CLEMENT wrote:
> Hi,
> 
> Now that we have more devices and more boards supported, bugs shows
> up. Here are a couple of fixes that have been tested on Aramda XP
> based boards such as DB-78460-BP and DB-MV784MP-GP, and on Armada 370
> based boards such as DB-88F6710-BP-DDR3 and Mirabox. They are 3.8
> materials.
> 
> Thanks,
> 
> Gregory CLEMENT (2):
>   arm: cache-l2x0: aurora: Invalidate during clean operation with WT
>     enable
>   arm: cache-l2x0: aurora: Use writel_relaxed instead of writel
> 
>  arch/arm/mm/cache-l2x0.c |   31 +++++++++++++++++++------------
>  1 file changed, 19 insertions(+), 12 deletions(-)

Series:

Acked-by: Jason Cooper <jason@lakedaemon.net>

thx,

Jason.

[PATCH 0/2] arm: cache-l2x0: aurora: Various bug fixes

[Gregory CLEMENT]

On 01/06/2013 05:56 PM, Jason Cooper wrote:
> On Wed, Dec 19, 2012 at 02:56:25PM +0100, Gregory CLEMENT wrote:
>> Hi,
>>
>> Now that we have more devices and more boards supported, bugs shows
>> up. Here are a couple of fixes that have been tested on Aramda XP
>> based boards such as DB-78460-BP and DB-MV784MP-GP, and on Armada 370
>> based boards such as DB-88F6710-BP-DDR3 and Mirabox. They are 3.8
>> materials.
>>
>> Thanks,
>>
>> Gregory CLEMENT (2):
>>   arm: cache-l2x0: aurora: Invalidate during clean operation with WT
>>     enable
>>   arm: cache-l2x0: aurora: Use writel_relaxed instead of writel
>>
>>  arch/arm/mm/cache-l2x0.c |   31 +++++++++++++++++++------------
>>  1 file changed, 19 insertions(+), 12 deletions(-)
> 
> Series:
> 
> Acked-by: Jason Cooper <jason@lakedaemon.net>
> 

Thanks I will add them to Russell patch system

> thx,
> 
> Jason.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com