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From: u.kleine-koenig@pengutronix.de (Uwe Kleine-König)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 3/3] Cortex-M3: Add support for exception handling
Date: Fri, 11 Jan 2013 12:14:56 +0100	[thread overview]
Message-ID: <20130111111456.GH14860@pengutronix.de> (raw)
In-Reply-To: <20130111110926.GD30875@n2100.arm.linux.org.uk>

Hello Russell,

On Fri, Jan 11, 2013 at 11:09:26AM +0000, Russell King - ARM Linux wrote:
> On Fri, Jan 11, 2013 at 12:05:44PM +0100, Uwe Kleine-K?nig wrote:
> > Hello,
> > 
> > On Wed, Oct 17, 2012 at 10:34:32AM +0200, Uwe Kleine-K?nig wrote:
> > > +/*
> > > + * Register switch for ARMv7-M processors.
> > > + * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
> > > + * previous and next are guaranteed not to be the same.
> > > + */
> > > +ENTRY(__switch_to)
> > > +	.fnstart
> > > +	.cantunwind
> > > +	add	ip, r1, #TI_CPU_SAVE
> > > +	stmia	ip!, {r4 - r11}		@ Store most regs on stack
> > > +	str	sp, [ip], #4
> > > +	str	lr, [ip], #4
> > > +	mov	r5, r0
> > > +	add	r4, r2, #TI_CPU_SAVE
> > > +	ldr	r0, =thread_notify_head
> > > +	mov	r1, #THREAD_NOTIFY_SWITCH
> > > +	bl	atomic_notifier_call_chain
> > > +	mov	ip, r4
> > > +	mov	r0, r5
> > > +	ldmia	ip!, {r4 - r11}		@ Load all regs saved previously
> > > +	ldr	sp, [ip], #4
> > > +	ldr	pc, [ip]
> > > +	.fnend
> > > +ENDPROC(__switch_to)
> > this code triggers a warning
> > 
> > 	This instruction may be unpredictable if executed on M-profile
> > 	cores with interrupts enabled.
> > 
> > with newer toolchains (seen with gcc 4.7.2) because of errata 752419
> > (Interrupted loads to SP can cause erroneous behaviour) which badly
> > affects the following instructions:
> > 
> > 	ldr	sp,[Rn],#imm
> > 	ldr	sp,[Rn,#imm]!
> 
> Wonder if that means we need to fix it in entry-armv.S too, as it uses
> the same sequence for Thumb:
> 
>  THUMB( ldr     sp, [ip], #4               )
>  THUMB( ldr     pc, [ip]                   )
> 
> and, of course, M-profile stuff is also Thumb.
entry-armv.S is not affected as this code snipplet is for switching from
ARM to THUMB mode on kernel entry. The M-profile CPUs don't have a ARM
mode, so this code isn't active for them anyhow. (I have a patch in my
queue to allow entry in Thumb mode for thumb-only CPUs.)

Best regards and thanks for your heedfulness,
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

  reply	other threads:[~2013-01-11 11:14 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-17  8:34 [PATCH v7 0/3] Yet another update for the Cortex-M3 series Uwe Kleine-König
2012-10-17  8:34 ` [PATCH v7 1/3] ARM: make cr_alignment read-only #ifndef CONFIG_CPU_CP15 Uwe Kleine-König
2013-01-15 13:08   ` Jonathan Austin
2013-01-16 12:03     ` Uwe Kleine-König
2012-10-17  8:34 ` [PATCH v7 2/3] Cortex-M3: Add base support for Cortex-M3 Uwe Kleine-König
2012-10-17  8:34 ` [PATCH v7 3/3] Cortex-M3: Add support for exception handling Uwe Kleine-König
2013-01-11 11:05   ` Uwe Kleine-König
2013-01-11 11:09     ` Russell King - ARM Linux
2013-01-11 11:14       ` Uwe Kleine-König [this message]
2013-01-11 11:26         ` Uwe Kleine-König
2013-01-11  9:47 ` [PATCH v7 0/3] Yet another update for the Cortex-M3 series Uwe Kleine-König

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