From: dave.martin@linaro.org (Dave Martin)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 03/16] ARM: b.L: introduce helpers for platform coherency exit/setup
Date: Mon, 14 Jan 2013 17:08:51 +0000 [thread overview]
Message-ID: <20130114170851.GA1967@linaro.org> (raw)
In-Reply-To: <1357777251-13541-4-git-send-email-nicolas.pitre@linaro.org>
On Wed, Jan 09, 2013 at 07:20:38PM -0500, Nicolas Pitre wrote:
> From: Dave Martin <dave.martin@linaro.org>
>
> This provides helper methods to coordinate between CPUs coming down
> and CPUs going up, as well as documentation on the used algorithms,
> so that cluster teardown and setup
> operations are not done for a cluster simultaneously.
[...]
In response to the incorrectness of the outer cache handling,
here's a supplementary patch:
>From b64f305c90e7ea585992df2d710f62ec6a7b5395 Mon Sep 17 00:00:00 2001
From: Dave Martin <dave.martin@linaro.org>
Date: Mon, 14 Jan 2013 16:25:47 +0000
Subject: [PATCH] ARM: b.L: Fix outer cache handling for coherency setup/exit helpers
This patch addresses the following issues:
* When invalidating stale data from the cache before a read,
outer caches must be invalidated _before_ inner caches, not
after, otherwise stale data may be re-filled from outer to
inner after the inner cache is flushed.
We still retain an inner clean before touching the outer cache,
to avoid stale data being rewritten from there into the outer
cache after the outer cache is flushed.
* All the sync_mem() calls synchronise either reads or writes,
but not both. This patch splits sync_mem() into separate
functions for reads and writes, to avoid excessive inner
flushes in the write case.
The two functions are different from the original sync_mem(),
to fix the above issues.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
NOTE: This patch is build-tested only.
arch/arm/common/bL_entry.c | 57 ++++++++++++++++++++++++++++++++++----------
1 files changed, 44 insertions(+), 13 deletions(-)
diff --git a/arch/arm/common/bL_entry.c b/arch/arm/common/bL_entry.c
index 1ea4ec9..3e1a404 100644
--- a/arch/arm/common/bL_entry.c
+++ b/arch/arm/common/bL_entry.c
@@ -119,16 +119,47 @@ int bL_cpu_powered_up(void)
struct bL_sync_struct bL_sync;
-static void __sync_range(volatile void *p, size_t size)
+/*
+ * Ensure preceding writes to *p by this CPU are visible to
+ * subsequent reads by other CPUs:
+ */
+static void __sync_range_w(volatile void *p, size_t size)
{
char *_p = (char *)p;
__cpuc_flush_dcache_area(_p, size);
- outer_flush_range(__pa(_p), __pa(_p + size));
+ outer_clean_range(__pa(_p), __pa(_p + size));
outer_sync();
}
-#define sync_mem(ptr) __sync_range(ptr, sizeof *(ptr))
+/*
+ * Ensure preceding writes to *p by other CPUs are visible to
+ * subsequent reads by this CPU:
+ */
+static void __sync_range_r(volatile void *p, size_t size)
+{
+ char *_p = (char *)p;
+
+#ifdef CONFIG_OUTER_CACHE
+ if (outer_cache.flush_range) {
+ /*
+ * Ensure ditry data migrated from other CPUs into our cache
+ * are cleaned out safely before the outer cache is cleaned:
+ */
+ __cpuc_flush_dcache_area(_p, size);
+
+ /* Clean and invalidate stale data for *p from outer ... */
+ outer_flush_range(__pa(_p), __pa(_p + size));
+ outer_sync();
+ }
+#endif
+
+ /* ... and inner cache: */
+ __cpuc_flush_dcache_area(_p, size);
+}
+
+#define sync_w(ptr) __sync_range_w(ptr, sizeof *(ptr))
+#define sync_r(ptr) __sync_range_r(ptr, sizeof *(ptr))
/*
* __bL_cpu_going_down: Indicates that the cpu is being torn down.
@@ -138,7 +169,7 @@ static void __sync_range(volatile void *p, size_t size)
void __bL_cpu_going_down(unsigned int cpu, unsigned int cluster)
{
bL_sync.clusters[cluster].cpus[cpu].cpu = CPU_GOING_DOWN;
- sync_mem(&bL_sync.clusters[cluster].cpus[cpu].cpu);
+ sync_w(&bL_sync.clusters[cluster].cpus[cpu].cpu);
}
/*
@@ -151,7 +182,7 @@ void __bL_cpu_down(unsigned int cpu, unsigned int cluster)
{
dsb();
bL_sync.clusters[cluster].cpus[cpu].cpu = CPU_DOWN;
- sync_mem(&bL_sync.clusters[cluster].cpus[cpu].cpu);
+ sync_w(&bL_sync.clusters[cluster].cpus[cpu].cpu);
sev();
}
@@ -167,7 +198,7 @@ void __bL_outbound_leave_critical(unsigned int cluster, int state)
{
dsb();
bL_sync.clusters[cluster].cluster = state;
- sync_mem(&bL_sync.clusters[cluster].cluster);
+ sync_w(&bL_sync.clusters[cluster].cluster);
sev();
}
@@ -189,10 +220,10 @@ bool __bL_outbound_enter_critical(unsigned int cpu, unsigned int cluster)
/* Warn inbound CPUs that the cluster is being torn down: */
c->cluster = CLUSTER_GOING_DOWN;
- sync_mem(&c->cluster);
+ sync_w(&c->cluster);
/* Back out if the inbound cluster is already in the critical region: */
- sync_mem(&c->inbound);
+ sync_r(&c->inbound);
if (c->inbound == INBOUND_COMING_UP)
goto abort;
@@ -203,7 +234,7 @@ bool __bL_outbound_enter_critical(unsigned int cpu, unsigned int cluster)
* If any CPU has been woken up again from the DOWN state, then we
* shouldn't be taking the cluster down at all: abort in that case.
*/
- sync_mem(&c->cpus);
+ sync_r(&c->cpus);
for (i = 0; i < BL_CPUS_PER_CLUSTER; i++) {
int cpustate;
@@ -216,7 +247,7 @@ bool __bL_outbound_enter_critical(unsigned int cpu, unsigned int cluster)
break;
wfe();
- sync_mem(&c->cpus[i].cpu);
+ sync_r(&c->cpus[i].cpu);
}
switch (cpustate) {
@@ -239,7 +270,7 @@ abort:
int __bL_cluster_state(unsigned int cluster)
{
- sync_mem(&bL_sync.clusters[cluster].cluster);
+ sync_r(&bL_sync.clusters[cluster].cluster);
return bL_sync.clusters[cluster].cluster;
}
@@ -267,11 +298,11 @@ int __init bL_cluster_sync_init(void (*power_up_setup)(void))
for_each_online_cpu(i)
bL_sync.clusters[this_cluster].cpus[i].cpu = CPU_UP;
bL_sync.clusters[this_cluster].cluster = CLUSTER_UP;
- sync_mem(&bL_sync);
+ sync_w(&bL_sync);
if (power_up_setup) {
bL_power_up_setup_phys = virt_to_phys(power_up_setup);
- sync_mem(&bL_power_up_setup_phys);
+ sync_w(&bL_power_up_setup_phys);
}
return 0;
--
1.7.4.1
next prev parent reply other threads:[~2013-01-14 17:08 UTC|newest]
Thread overview: 132+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-10 0:20 [PATCH 00/16] big.LITTLE low-level CPU and cluster power management Nicolas Pitre
2013-01-10 0:20 ` [PATCH 01/16] ARM: b.L: secondary kernel entry code Nicolas Pitre
2013-01-10 7:12 ` Stephen Boyd
2013-01-10 15:30 ` Nicolas Pitre
2013-01-10 15:34 ` Catalin Marinas
2013-01-10 16:47 ` Nicolas Pitre
2013-01-11 11:45 ` Catalin Marinas
2013-01-11 12:05 ` Lorenzo Pieralisi
2013-01-11 12:19 ` Dave Martin
2013-01-10 23:05 ` Will Deacon
2013-01-11 1:26 ` Nicolas Pitre
2013-01-11 10:55 ` Will Deacon
2013-01-11 11:35 ` Dave Martin
2013-01-11 17:16 ` Santosh Shilimkar
2013-01-11 18:10 ` Nicolas Pitre
2013-01-11 18:30 ` Santosh Shilimkar
2013-03-07 7:37 ` Pavel Machek
2013-03-07 8:57 ` Nicolas Pitre
2013-01-10 0:20 ` [PATCH 02/16] ARM: b.L: introduce the CPU/cluster power API Nicolas Pitre
2013-01-10 23:08 ` Will Deacon
2013-01-11 2:30 ` Nicolas Pitre
2013-01-11 10:58 ` Will Deacon
2013-01-11 11:29 ` Dave Martin
2013-01-11 17:26 ` Santosh Shilimkar
2013-01-11 18:33 ` Nicolas Pitre
2013-01-11 18:41 ` Santosh Shilimkar
2013-01-11 19:54 ` Nicolas Pitre
2013-01-10 0:20 ` [PATCH 03/16] ARM: b.L: introduce helpers for platform coherency exit/setup Nicolas Pitre
2013-01-10 12:01 ` Dave Martin
2013-01-10 19:04 ` Nicolas Pitre
2013-01-11 11:30 ` Dave Martin
2013-01-10 16:53 ` Catalin Marinas
2013-01-10 17:59 ` Nicolas Pitre
2013-01-10 21:50 ` Catalin Marinas
2013-01-10 22:31 ` Nicolas Pitre
2013-01-11 10:36 ` Dave Martin
2013-01-10 22:32 ` Nicolas Pitre
2013-01-10 23:13 ` Will Deacon
2013-01-11 1:50 ` Nicolas Pitre
2013-01-11 11:09 ` Dave Martin
2013-01-11 17:46 ` Santosh Shilimkar
2013-01-11 18:07 ` Dave Martin
2013-01-11 18:34 ` Santosh Shilimkar
2013-01-14 17:08 ` Dave Martin [this message]
2013-01-14 17:15 ` Catalin Marinas
2013-01-14 18:10 ` Dave Martin
2013-01-14 21:34 ` Catalin Marinas
2013-01-10 0:20 ` [PATCH 04/16] ARM: b.L: Add baremetal voting mutexes Nicolas Pitre
2013-01-10 23:18 ` Will Deacon
2013-01-11 3:15 ` Nicolas Pitre
2013-01-11 11:03 ` Will Deacon
2013-01-11 16:57 ` Dave Martin
2013-01-10 0:20 ` [PATCH 05/16] ARM: bL_head: vlock-based first man election Nicolas Pitre
2013-01-10 0:20 ` [PATCH 06/16] ARM: b.L: generic SMP secondary bringup and hotplug support Nicolas Pitre
2013-01-11 18:02 ` Santosh Shilimkar
2013-01-14 18:05 ` Achin Gupta
2013-01-15 6:32 ` Santosh Shilimkar
2013-01-15 11:18 ` Achin Gupta
2013-01-15 11:26 ` Santosh Shilimkar
2013-01-15 18:53 ` Dave Martin
2013-01-14 16:35 ` Will Deacon
2013-01-14 16:51 ` Nicolas Pitre
2013-01-15 19:09 ` Dave Martin
2013-01-10 0:20 ` [PATCH 07/16] ARM: bL_platsmp.c: close the kernel entry gate before hot-unplugging a CPU Nicolas Pitre
2013-01-14 16:37 ` Will Deacon
2013-01-14 16:53 ` Nicolas Pitre
2013-01-14 17:00 ` Will Deacon
2013-01-14 17:11 ` Catalin Marinas
2013-01-14 17:15 ` Nicolas Pitre
2013-01-14 17:23 ` Will Deacon
2013-01-14 18:26 ` Russell King - ARM Linux
2013-01-14 18:49 ` Nicolas Pitre
2013-01-15 18:40 ` Dave Martin
2013-01-16 16:06 ` Catalin Marinas
2013-01-10 0:20 ` [PATCH 08/16] ARM: bL_platsmp.c: make sure the GIC interface of a dying CPU is disabled Nicolas Pitre
2013-01-11 18:07 ` Santosh Shilimkar
2013-01-11 19:07 ` Nicolas Pitre
2013-01-12 6:50 ` Santosh Shilimkar
2013-01-12 16:47 ` Nicolas Pitre
2013-01-13 4:37 ` Santosh Shilimkar
2013-01-14 17:53 ` Lorenzo Pieralisi
2013-01-14 16:39 ` Will Deacon
2013-01-14 16:54 ` Nicolas Pitre
2013-01-14 17:02 ` Will Deacon
2013-01-14 17:18 ` Nicolas Pitre
2013-01-14 17:24 ` Will Deacon
2013-01-14 17:56 ` Lorenzo Pieralisi
2013-01-10 0:20 ` [PATCH 09/16] ARM: vexpress: Select the correct SMP operations at run-time Nicolas Pitre
2013-01-10 0:20 ` [PATCH 10/16] ARM: vexpress: introduce DCSCB support Nicolas Pitre
2013-01-11 18:12 ` Santosh Shilimkar
2013-01-11 19:13 ` Nicolas Pitre
2013-01-12 6:52 ` Santosh Shilimkar
2013-01-10 0:20 ` [PATCH 11/16] ARM: vexpress/dcscb: add CPU use counts to the power up/down API implementation Nicolas Pitre
2013-01-10 0:20 ` [PATCH 12/16] ARM: vexpress/dcscb: do not hardcode number of CPUs per cluster Nicolas Pitre
2013-01-10 0:20 ` [PATCH 13/16] drivers: misc: add ARM CCI support Nicolas Pitre
2013-01-11 18:20 ` Santosh Shilimkar
2013-01-11 19:22 ` Nicolas Pitre
2013-01-12 6:53 ` Santosh Shilimkar
2013-01-15 18:34 ` Dave Martin
2013-01-10 0:20 ` [PATCH 14/16] ARM: TC2: ensure powerdown-time data is flushed from cache Nicolas Pitre
2013-01-10 18:50 ` Dave Martin
2013-01-10 19:13 ` Nicolas Pitre
2013-01-11 11:38 ` Dave Martin
2013-01-10 0:20 ` [PATCH 15/16] ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI Nicolas Pitre
2013-01-10 12:05 ` Dave Martin
2013-01-11 18:27 ` Santosh Shilimkar
2013-01-11 19:28 ` Nicolas Pitre
2013-01-12 7:21 ` Santosh Shilimkar
2013-01-14 12:25 ` Lorenzo Pieralisi
2013-01-15 6:23 ` Santosh Shilimkar
2013-01-15 18:20 ` Dave Martin
2013-01-16 6:33 ` Santosh Shilimkar
2013-01-16 10:03 ` Lorenzo Pieralisi
2013-01-16 10:12 ` Santosh Shilimkar
2013-01-10 0:20 ` [PATCH 16/16] ARM: vexpress/dcscb: probe via device tree Nicolas Pitre
2013-01-10 0:46 ` [PATCH 00/16] big.LITTLE low-level CPU and cluster power management Rob Herring
2013-01-10 5:04 ` Nicolas Pitre
2013-01-10 23:01 ` Will Deacon
2013-01-14 9:56 ` Joseph Lo
2013-01-14 14:05 ` Nicolas Pitre
2013-01-15 2:44 ` Joseph Lo
2013-01-15 16:44 ` Nicolas Pitre
2013-01-16 16:02 ` Catalin Marinas
2013-01-16 21:18 ` Nicolas Pitre
2013-01-17 17:55 ` Catalin Marinas
2013-01-15 18:31 ` Dave Martin
2013-03-07 8:27 ` Pavel Machek
2013-03-07 9:12 ` Nicolas Pitre
2013-03-07 9:40 ` Pavel Machek
2013-03-07 9:56 ` Nicolas Pitre
2013-03-07 14:51 ` Pavel Machek
2013-03-07 15:42 ` Nicolas Pitre
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