[PATCH v2 0/3] at91: PMECC: enable PMECC in dt for at91sam9x5ek, at91sam9n12ek

[PATCH v2 0/3] at91: PMECC: enable PMECC in dt for at91sam9x5ek, at91sam9n12ek

[Josh Wu]

Those patches will enable PMECC in dt parameters for at91sam9x5ek, at91sam9n12ek.
The driver will check minimum required ecc on ONFI parameter from NAND flash. 
If pmecc-cap in dts doesn't meet the requirement then driver reports a error.

v2: rebase to v3.8-rc3. And wrapped the commit message.

Josh Wu (3):
  MTD: at91: atmel_nand: for PMECC, add code to choose the ecc bits and
    sector size according to the ONFI parameter ECC requirement.
  at91: 9x5: add DT parameters to enable PMECC
  at91: at91sam9n12: add DT parameters to enable PMECC

 arch/arm/boot/dts/at91sam9n12.dtsi  |    1 +
 arch/arm/boot/dts/at91sam9n12ek.dts |    5 +-
 arch/arm/boot/dts/at91sam9x5.dtsi   |    4 ++
 arch/arm/boot/dts/at91sam9x5cm.dtsi |    5 +-
 drivers/mtd/nand/atmel_nand.c       |   89 +++++++++++++++++++++++++++++++++++
 5 files changed, 102 insertions(+), 2 deletions(-)

-- 
1.7.9.5

[PATCH v2 1/3] MTD: at91: atmel_nand: for PMECC, add code to choose the ecc bits and sector size according to the ONFI parameter ECC requirement.

[Josh Wu]

This patch will check NAND flash's ecc minimum requirement in ONFI parameter.

If ecc minimum requirement is equal or smaller than pmecc-cap in dtsi, then 
use ecc_bits in ONFI. otherwise, return an error since pmecc-cap in dtsi 
doesn't meet the ecc minimum reqirement.

This patch also check sector size (codeword) requirement in ONFI. If it is 
equal or bigger than sector_size in dtsi, then use the one of ONFI. 
otherwise return error.

Currently we don't support to read the ECC parameter in ONFI extended 
parameter page. So in that case we just use the value specified in dts.

For non-ONFI support nand flash, we assume the minimum ecc requirement is 
2bits in 512 bytes.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
---
change log:
  v2: wrap the commit message. 

 drivers/mtd/nand/atmel_nand.c |   89 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index c516a94..b50283a 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -908,6 +908,84 @@ static void atmel_pmecc_core_init(struct mtd_info *mtd)
 	pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
 }
 
+/*
+ * Get ECC requirement in ONFI parameters, returns -1 if ONFI
+ * parameters is not supported.
+ * return 0 if success to get the ECC requirement.
+ */
+static int get_onfi_ecc_param(struct nand_chip *chip,
+		int *ecc_bits, int *sector_size)
+{
+	*ecc_bits = *sector_size = 0;
+
+	if (chip->onfi_params.ecc_bits == 0xff)
+		/* TODO: the sector_size and ecc_bits need to be find in
+		 * extended ecc parameter, currently we don't support it.
+		 */
+		return -1;
+
+	*ecc_bits = chip->onfi_params.ecc_bits;
+
+	/* The default sector size (ecc codeword size) is 512 */
+	*sector_size = 512;
+
+	return 0;
+}
+
+/*
+ * Choose ecc cap and sector size in atmel_nand_host according to ONFI
+ * parameters ecc requirement.
+ * return 0 if success. otherwise return error code.
+ */
+static int pmecc_choose_ecc_bits(struct atmel_nand_host *host,
+		struct nand_chip *chip)
+{
+	int ecc_bits, sector_size;
+
+	if (!get_onfi_ecc_param(chip, &ecc_bits, &sector_size)) {
+		dev_info(host->dev, "ONFI params, minimum required ECC: %dbits in %d bytes\n",
+				ecc_bits, sector_size);
+
+		if (ecc_bits > host->pmecc_corr_cap) {
+			dev_err(host->dev, "Error: Need to set a bigger pmecc-cap in dts. Current is: %d\n",
+				host->pmecc_corr_cap);
+			return -EINVAL;
+		}
+		if (sector_size < host->pmecc_sector_size) {
+			dev_err(host->dev, "Error: Need to set a smaller pmecc-sector-size in dts. Current is: %d\n",
+					host->pmecc_sector_size);
+			return -EINVAL;
+		}
+
+		/* use the most fitable ecc bits (the near bigger one ) */
+		if (ecc_bits <= 2)
+			host->pmecc_corr_cap = 2;
+		else if (ecc_bits <= 4)
+			host->pmecc_corr_cap = 4;
+		else if (ecc_bits < 8)
+			host->pmecc_corr_cap = 8;
+		else if (ecc_bits < 12)
+			host->pmecc_corr_cap = 12;
+		else if (ecc_bits < 24)
+			host->pmecc_corr_cap = 24;
+		else
+			return -EINVAL;
+
+		/* use the most fitable sector size (the near smaller one ) */
+		if (sector_size >= 1024)
+			host->pmecc_sector_size = 1024;
+		else if (sector_size >= 512)
+			host->pmecc_sector_size = 512;
+		else
+			return -EINVAL;
+	} else {
+		dev_info(host->dev,
+		"NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet. So use default setting in dts\n");
+	}
+
+	return 0;
+}
+
 static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
 					 struct atmel_nand_host *host)
 {
@@ -916,8 +994,19 @@ static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
 	struct resource *regs, *regs_pmerr, *regs_rom;
 	int cap, sector_size, err_no;
 
+	if (nand_chip->onfi_version) {
+		/* Choose ecc cap and sector size base on ONFI parameters */
+		err_no = pmecc_choose_ecc_bits(host, nand_chip);
+		if (err_no)
+			return err_no;
+	} else {
+		dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2");
+		host->pmecc_corr_cap = 2;
+	}
+
 	cap = host->pmecc_corr_cap;
 	sector_size = host->pmecc_sector_size;
+
 	dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
 		 cap, sector_size);
 
-- 
1.7.9.5

[PATCH v2 2/3] at91: 9x5: add DT parameters to enable PMECC

[Josh Wu]

Default ecc correctable setting is 2bits in 512 bytes.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
---
change log:
   v2: rebase to v3.8-rc3

 arch/arm/boot/dts/at91sam9x5.dtsi   |    4 ++++
 arch/arm/boot/dts/at91sam9x5cm.dtsi |    5 ++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 40ac3a4..eedc191 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -480,7 +480,11 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			reg = <0x40000000 0x10000000
+			       0xffffe000 0x600		/* PMECC Registers */
+			       0xffffe600 0x200		/* PMECC Error Location Registers */
+			       0x00100000 0x100000	/* ROM code */
 			      >;
+			atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
 			atmel,nand-addr-offset = <21>;
 			atmel,nand-cmd-offset = <22>;
 			pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 31e7be2..4027ac7 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -26,7 +26,10 @@
 	ahb {
 		nand0: nand at 40000000 {
 			nand-bus-width = <8>;
-			nand-ecc-mode = "soft";
+			nand-ecc-mode = "hw";
+			atmel,has-pmecc;	/* Enable PMECC */
+			atmel,pmecc-cap = <2>;
+			atmel,pmecc-sector-size = <512>;
 			nand-on-flash-bbt;
 			status = "okay";
 
-- 
1.7.9.5

[PATCH v2 3/3] at91: at91sam9n12: add DT parameters to enable PMECC

[Josh Wu]

Default ecc correctable setting is 2bits in 512 bytes.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
---
change log:
   v2: rebase to v3.8-rc3

 arch/arm/boot/dts/at91sam9n12.dtsi  |    1 +
 arch/arm/boot/dts/at91sam9n12ek.dts |    5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index e9efb34..eb9f12e 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -366,6 +366,7 @@
 				0xffffe600 0x00000200
 				0x00100000 0x00100000
 			       >;
+			atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
 			atmel,nand-addr-offset = <21>;
 			atmel,nand-cmd-offset = <22>;
 			pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 0376bf4..d400f8d 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -71,7 +71,10 @@
 
 		nand0: nand at 40000000 {
 			nand-bus-width = <8>;
-			nand-ecc-mode = "soft";
+			nand-ecc-mode = "hw";
+			atmel,has-pmecc;
+			atmel,pmecc-cap = <2>;
+			atmel,pmecc-sector-size = <512>;
 			nand-on-flash-bbt;
 			status = "okay";
 		};
-- 
1.7.9.5

[PATCH v2 0/3] at91: PMECC: enable PMECC in dt for at91sam9x5ek, at91sam9n12ek

[Artem Bityutskiy]

On Thu, 2013-01-17 at 11:24 +0800, Josh Wu wrote:
> Those patches will enable PMECC in dt parameters for at91sam9x5ek, at91sam9n12ek.
> The driver will check minimum required ecc on ONFI parameter from NAND flash. 
> If pmecc-cap in dts doesn't meet the requirement then driver reports a error.
> 
> v2: rebase to v3.8-rc3. And wrapped the commit message.

Please, whenever you know your patch-set depends on something which is
not yet in Linuse's tree, _always_ explicitly say about this.

-- 
Best Regards,
Artem Bityutskiy
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[PATCH v2 3/3] at91: at91sam9n12: add DT parameters to enable PMECC

[Jean-Christophe PLAGNIOL-VILLARD]

On 11:24 Thu 17 Jan     , Josh Wu wrote:
> Default ecc correctable setting is 2bits in 512 bytes.
> 
> Signed-off-by: Josh Wu <josh.wu@atmel.com>
this must go via at91 tree

so we can manage other mergie issue on dts

Best Regards,
J.
> ---
> change log:
>    v2: rebase to v3.8-rc3
> 
>  arch/arm/boot/dts/at91sam9n12.dtsi  |    1 +
>  arch/arm/boot/dts/at91sam9n12ek.dts |    5 ++++-
>  2 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
> index e9efb34..eb9f12e 100644
> --- a/arch/arm/boot/dts/at91sam9n12.dtsi
> +++ b/arch/arm/boot/dts/at91sam9n12.dtsi
> @@ -366,6 +366,7 @@
>  				0xffffe600 0x00000200
>  				0x00100000 0x00100000
>  			       >;
> +			atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
>  			atmel,nand-addr-offset = <21>;
>  			atmel,nand-cmd-offset = <22>;
>  			pinctrl-names = "default";
> diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
> index 0376bf4..d400f8d 100644
> --- a/arch/arm/boot/dts/at91sam9n12ek.dts
> +++ b/arch/arm/boot/dts/at91sam9n12ek.dts
> @@ -71,7 +71,10 @@
>  
>  		nand0: nand at 40000000 {
>  			nand-bus-width = <8>;
> -			nand-ecc-mode = "soft";
> +			nand-ecc-mode = "hw";
> +			atmel,has-pmecc;
> +			atmel,pmecc-cap = <2>;
> +			atmel,pmecc-sector-size = <512>;
>  			nand-on-flash-bbt;
>  			status = "okay";
>  		};
> -- 
> 1.7.9.5
> 

[PATCH v2 2/3] at91: 9x5: add DT parameters to enable PMECC

[Jean-Christophe PLAGNIOL-VILLARD]

On 11:24 Thu 17 Jan     , Josh Wu wrote:
> Default ecc correctable setting is 2bits in 512 bytes.
full name sam the soc
> 
> Signed-off-by: Josh Wu <josh.wu@atmel.com>
> ---
> change log:
>    v2: rebase to v3.8-rc3
> 
>  arch/arm/boot/dts/at91sam9x5.dtsi   |    4 ++++
>  arch/arm/boot/dts/at91sam9x5cm.dtsi |    5 ++++-
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> index 40ac3a4..eedc191 100644
> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> @@ -480,7 +480,11 @@
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			reg = <0x40000000 0x10000000
> +			       0xffffe000 0x600		/* PMECC Registers */
> +			       0xffffe600 0x200		/* PMECC Error Location Registers */
> +			       0x00100000 0x100000	/* ROM code */
I do not like this at all we request 1M of memory where we jsut need a few for
the tables

Best Regards,
J.
>  			      >;
> +			atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
>  			atmel,nand-addr-offset = <21>;
>  			atmel,nand-cmd-offset = <22>;
>  			pinctrl-names = "default";
> diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
> index 31e7be2..4027ac7 100644
> --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
> @@ -26,7 +26,10 @@
>  	ahb {
>  		nand0: nand at 40000000 {
>  			nand-bus-width = <8>;
> -			nand-ecc-mode = "soft";
> +			nand-ecc-mode = "hw";
> +			atmel,has-pmecc;	/* Enable PMECC */
> +			atmel,pmecc-cap = <2>;
> +			atmel,pmecc-sector-size = <512>;
>  			nand-on-flash-bbt;
>  			status = "okay";
>  
> -- 
> 1.7.9.5
>