* [PATCH v2 0/4] Preparatory GIC patches for arm64 support
@ 2013-01-29 16:18 Catalin Marinas
2013-01-29 16:18 ` [PATCH v2 1/4] arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h Catalin Marinas
` (4 more replies)
0 siblings, 5 replies; 19+ messages in thread
From: Catalin Marinas @ 2013-01-29 16:18 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
That's the second version of the GIC clean-up patches to support arm64.
The only change from v1 is that the second patch (chained_irq.h) also
covers drivers/gpio and drivers/pinctrl (#include change).
Catalin
Catalin Marinas (4):
arm: Move the set_handle_irq and handle_arch_irq declarations to
asm/irq.h
arm: Move chained_irq_(enter|exit) to a generic file
irqchip: gic: Call handle_bad_irq() directly
irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
arch/arm/include/asm/irq.h | 5 +++
arch/arm/include/asm/mach/irq.h | 36 --------------------
arch/arm/mach-at91/gpio.c | 3 +-
arch/arm/mach-exynos/common.c | 1 +
arch/arm/mach-exynos/platsmp.c | 8 -----
arch/arm/mach-highbank/platsmp.c | 7 ----
arch/arm/mach-imx/platsmp.c | 12 -------
arch/arm/mach-msm/platsmp.c | 8 -----
arch/arm/mach-omap2/omap-smp.c | 7 ----
arch/arm/mach-shmobile/smp-emev2.c | 7 ----
arch/arm/mach-shmobile/smp-r8a7779.c | 7 ----
arch/arm/mach-shmobile/smp-sh73a0.c | 7 ----
arch/arm/mach-socfpga/platsmp.c | 12 -------
arch/arm/mach-spear13xx/platsmp.c | 8 -----
arch/arm/mach-tegra/platsmp.c | 8 -----
arch/arm/mach-ux500/platsmp.c | 8 -----
arch/arm/plat-samsung/irq-vic-timer.c | 3 +-
arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +-
arch/arm/plat-versatile/platsmp.c | 8 -----
drivers/gpio/gpio-msm-v2.c | 3 +-
drivers/gpio/gpio-mxc.c | 2 +-
drivers/gpio/gpio-omap.c | 3 +-
drivers/gpio/gpio-pl061.c | 2 +-
drivers/gpio/gpio-pxa.c | 3 +-
drivers/gpio/gpio-tegra.c | 3 +-
drivers/irqchip/irq-gic.c | 32 +++++++++++++-----
drivers/irqchip/irq-vic.c | 2 +-
drivers/pinctrl/pinctrl-at91.c | 3 +-
drivers/pinctrl/pinctrl-exynos.c | 3 +-
drivers/pinctrl/pinctrl-nomadik.c | 2 +-
drivers/pinctrl/pinctrl-sirf.c | 2 +-
drivers/pinctrl/spear/pinctrl-plgpio.c | 2 +-
drivers/staging/imx-drm/ipu-v3/ipu-common.c | 2 +-
include/linux/irqchip/arm-gic.h | 1 -
include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++
35 files changed, 97 insertions(+), 178 deletions(-)
create mode 100644 include/linux/irqchip/chained_irq.h
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v2 1/4] arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h 2013-01-29 16:18 [PATCH v2 0/4] Preparatory GIC patches for arm64 support Catalin Marinas @ 2013-01-29 16:18 ` Catalin Marinas 2013-01-29 16:18 ` [PATCH v2 2/4] arm: Move chained_irq_(enter|exit) to a generic file Catalin Marinas ` (3 subsequent siblings) 4 siblings, 0 replies; 19+ messages in thread From: Catalin Marinas @ 2013-01-29 16:18 UTC (permalink / raw) To: linux-arm-kernel This patch prepares the removal of <asm/mach/irq.h> include in the GIC and VIC irqchip drivers. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com> --- arch/arm/include/asm/irq.h | 5 +++++ arch/arm/include/asm/mach/irq.h | 5 ----- drivers/irqchip/irq-vic.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index 35c21c3..53c15de 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *); void handle_IRQ(unsigned int, struct pt_regs *); void init_IRQ(void); +#ifdef CONFIG_MULTI_IRQ_HANDLER +extern void (*handle_arch_irq)(struct pt_regs *); +extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); +#endif + #endif #endif diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h index 18c8830..749d505 100644 --- a/arch/arm/include/asm/mach/irq.h +++ b/arch/arm/include/asm/mach/irq.h @@ -20,11 +20,6 @@ struct seq_file; extern void init_FIQ(int); extern int show_fiq_list(struct seq_file *, int); -#ifdef CONFIG_MULTI_IRQ_HANDLER -extern void (*handle_arch_irq)(struct pt_regs *); -extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); -#endif - /* * This is for easy migration, but should be changed in the source */ diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c index 3cf97aa..e38cb00 100644 --- a/drivers/irqchip/irq-vic.c +++ b/drivers/irqchip/irq-vic.c @@ -33,7 +33,7 @@ #include <linux/irqchip/arm-vic.h> #include <asm/exception.h> -#include <asm/mach/irq.h> +#include <asm/irq.h> #include "irqchip.h" ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 2/4] arm: Move chained_irq_(enter|exit) to a generic file 2013-01-29 16:18 [PATCH v2 0/4] Preparatory GIC patches for arm64 support Catalin Marinas 2013-01-29 16:18 ` [PATCH v2 1/4] arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h Catalin Marinas @ 2013-01-29 16:18 ` Catalin Marinas 2013-01-29 16:18 ` [PATCH v2 3/4] irqchip: gic: Call handle_bad_irq() directly Catalin Marinas ` (2 subsequent siblings) 4 siblings, 0 replies; 19+ messages in thread From: Catalin Marinas @ 2013-01-29 16:18 UTC (permalink / raw) To: linux-arm-kernel These functions have been introduced by commit 10a8c383 (irq: introduce entry and exit functions for chained handlers) in asm/mach/irq.h. This patch moves them to linux/irqchip/chained_irq.h so that generic irqchip drivers do not rely on architecture specific header files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com> --- arch/arm/include/asm/mach/irq.h | 31 ----------------- arch/arm/mach-at91/gpio.c | 3 +- arch/arm/mach-exynos/common.c | 1 + arch/arm/plat-samsung/irq-vic-timer.c | 3 +- arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +- drivers/gpio/gpio-msm-v2.c | 3 +- drivers/gpio/gpio-mxc.c | 2 +- drivers/gpio/gpio-omap.c | 3 +- drivers/gpio/gpio-pl061.c | 2 +- drivers/gpio/gpio-pxa.c | 3 +- drivers/gpio/gpio-tegra.c | 3 +- drivers/irqchip/irq-gic.c | 1 + drivers/pinctrl/pinctrl-at91.c | 3 +- drivers/pinctrl/pinctrl-exynos.c | 3 +- drivers/pinctrl/pinctrl-nomadik.c | 2 +- drivers/pinctrl/pinctrl-sirf.c | 2 +- drivers/pinctrl/spear/pinctrl-plgpio.c | 2 +- drivers/staging/imx-drm/ipu-v3/ipu-common.c | 2 +- include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++ 19 files changed, 69 insertions(+), 55 deletions(-) create mode 100644 include/linux/irqchip/chained_irq.h diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h index 749d505..2092ee1 100644 --- a/arch/arm/include/asm/mach/irq.h +++ b/arch/arm/include/asm/mach/irq.h @@ -30,35 +30,4 @@ do { \ raw_spin_unlock(&desc->lock); \ } while(0) -#ifndef __ASSEMBLY__ -/* - * Entry/exit functions for chained handlers where the primary IRQ chip - * may implement either fasteoi or level-trigger flow control. - */ -static inline void chained_irq_enter(struct irq_chip *chip, - struct irq_desc *desc) -{ - /* FastEOI controllers require no action on entry. */ - if (chip->irq_eoi) - return; - - if (chip->irq_mask_ack) { - chip->irq_mask_ack(&desc->irq_data); - } else { - chip->irq_mask(&desc->irq_data); - if (chip->irq_ack) - chip->irq_ack(&desc->irq_data); - } -} - -static inline void chained_irq_exit(struct irq_chip *chip, - struct irq_desc *desc) -{ - if (chip->irq_eoi) - chip->irq_eoi(&desc->irq_data); - else - chip->irq_unmask(&desc->irq_data); -} -#endif - #endif diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index c5d7e1e..a5afcf7 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c @@ -22,10 +22,9 @@ #include <linux/module.h> #include <linux/io.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/of_address.h> -#include <asm/mach/irq.h> - #include <mach/hardware.h> #include <mach/at91_pio.h> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 7f01a92..60dad95 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -25,6 +25,7 @@ #include <linux/irqchip.h> #include <linux/of_address.h> #include <linux/irqchip/arm-gic.h> +#include <linux/irqchip/chained_irq.h> #include <asm/proc-fns.h> #include <asm/exception.h> diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index f980cf3..5d205e7 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c @@ -16,6 +16,7 @@ #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/io.h> #include <mach/map.h> @@ -23,8 +24,6 @@ #include <plat/irq-vic-timer.h> #include <plat/regs-timer.h> -#include <asm/mach/irq.h> - static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) { struct irq_chip *chip = irq_get_chip(irq); diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c index bae5613..fafdb05 100644 --- a/arch/arm/plat-samsung/s5p-irq-gpioint.c +++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c @@ -14,6 +14,7 @@ #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/io.h> #include <linux/gpio.h> #include <linux/slab.h> @@ -22,8 +23,6 @@ #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> -#include <asm/mach/irq.h> - #define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u)) #define CON_OFFSET 0x700 diff --git a/drivers/gpio/gpio-msm-v2.c b/drivers/gpio/gpio-msm-v2.c index 55a7e77..dd2edde 100644 --- a/drivers/gpio/gpio-msm-v2.c +++ b/drivers/gpio/gpio-msm-v2.c @@ -23,13 +23,12 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/irqchip/chained_irq.h> #include <linux/irq.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/spinlock.h> -#include <asm/mach/irq.h> - #include <mach/msm_gpiomux.h> #include <mach/msm_iomap.h> diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 7877335..7176743 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -24,6 +24,7 @@ #include <linux/io.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/slab.h> @@ -32,7 +33,6 @@ #include <linux/of_device.h> #include <linux/module.h> #include <asm-generic/bug.h> -#include <asm/mach/irq.h> enum mxc_gpio_hwtype { IMX1_GPIO, /* runs on i.mx1 */ diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index f1fbedb2..6996da9 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -25,11 +25,10 @@ #include <linux/of.h> #include <linux/of_device.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/gpio.h> #include <linux/platform_data/gpio-omap.h> -#include <asm/mach/irq.h> - #define OFF_MODE 1 static LIST_HEAD(omap_gpio_list); diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index b820869..2976336 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -15,6 +15,7 @@ #include <linux/io.h> #include <linux/ioport.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/bitops.h> #include <linux/workqueue.h> #include <linux/gpio.h> @@ -23,7 +24,6 @@ #include <linux/amba/pl061.h> #include <linux/slab.h> #include <linux/pm.h> -#include <asm/mach/irq.h> #define GPIODIR 0x400 #define GPIOIS 0x404 diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index 8325f58..2d3af98 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -19,6 +19,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_device.h> @@ -26,8 +27,6 @@ #include <linux/syscore_ops.h> #include <linux/slab.h> -#include <asm/mach/irq.h> - #include <mach/irqs.h> /* diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c index 414ad91..8e21555 100644 --- a/drivers/gpio/gpio-tegra.c +++ b/drivers/gpio/gpio-tegra.c @@ -27,11 +27,10 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/pinctrl/consumer.h> #include <linux/pm.h> -#include <asm/mach/irq.h> - #define GPIO_BANK(x) ((x) >> 5) #define GPIO_PORT(x) (((x) >> 3) & 0x3) #define GPIO_BIT(x) ((x) & 0x7) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 69d9a39..688b977 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -38,6 +38,7 @@ #include <linux/interrupt.h> #include <linux/percpu.h> #include <linux/slab.h> +#include <linux/irqchip/chained_irq.h> #include <linux/irqchip/arm-gic.h> #include <asm/irq.h> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 75933a6..5cbadc9 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -18,6 +18,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/io.h> #include <linux/gpio.h> #include <linux/pinctrl/machine.h> @@ -27,8 +28,6 @@ /* Since we request GPIOs from ourself */ #include <linux/pinctrl/consumer.h> -#include <asm/mach/irq.h> - #include <mach/hardware.h> #include <mach/at91_pio.h> diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c index 8738933..911c5e7 100644 --- a/drivers/pinctrl/pinctrl-exynos.c +++ b/drivers/pinctrl/pinctrl-exynos.c @@ -23,13 +23,12 @@ #include <linux/interrupt.h> #include <linux/irqdomain.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/of_irq.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/err.h> -#include <asm/mach/irq.h> - #include "pinctrl-samsung.h" #include "pinctrl-exynos.h" diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 39c1651..d30d3c1 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -23,6 +23,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/slab.h> #include <linux/of_device.h> #include <linux/of_address.h> @@ -33,7 +34,6 @@ /* Since we request GPIOs from ourself */ #include <linux/pinctrl/consumer.h> #include <linux/platform_data/pinctrl-nomadik.h> -#include <asm/mach/irq.h> #include "pinctrl-nomadik.h" #include "core.h" diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c index 498b2ba..35e8cea 100644 --- a/drivers/pinctrl/pinctrl-sirf.c +++ b/drivers/pinctrl/pinctrl-sirf.c @@ -14,6 +14,7 @@ #include <linux/slab.h> #include <linux/err.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include <linux/pinctrl/consumer.h> @@ -25,7 +26,6 @@ #include <linux/bitops.h> #include <linux/gpio.h> #include <linux/of_gpio.h> -#include <asm/mach/irq.h> #define DRIVER_NAME "pinmux-sirf" diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index 295b349..a4908ec 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -15,12 +15,12 @@ #include <linux/io.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/module.h> #include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/pm.h> #include <linux/spinlock.h> -#include <asm/mach/irq.h> #define MAX_GPIO_PER_REG 32 #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG) diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-common.c b/drivers/staging/imx-drm/ipu-v3/ipu-common.c index 366f259..6efe4e1 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-common.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-common.c @@ -25,8 +25,8 @@ #include <linux/clk.h> #include <linux/list.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/of_device.h> -#include <asm/mach/irq.h> #include "imx-ipu-v3.h" #include "ipu-prv.h" diff --git a/include/linux/irqchip/chained_irq.h b/include/linux/irqchip/chained_irq.h new file mode 100644 index 0000000..adf4c30 --- /dev/null +++ b/include/linux/irqchip/chained_irq.h @@ -0,0 +1,52 @@ +/* + * Chained IRQ handlers support. + * + * Copyright (C) 2011 ARM Ltd. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __IRQCHIP_CHAINED_IRQ_H +#define __IRQCHIP_CHAINED_IRQ_H + +#include <linux/irq.h> + +/* + * Entry/exit functions for chained handlers where the primary IRQ chip + * may implement either fasteoi or level-trigger flow control. + */ +static inline void chained_irq_enter(struct irq_chip *chip, + struct irq_desc *desc) +{ + /* FastEOI controllers require no action on entry. */ + if (chip->irq_eoi) + return; + + if (chip->irq_mask_ack) { + chip->irq_mask_ack(&desc->irq_data); + } else { + chip->irq_mask(&desc->irq_data); + if (chip->irq_ack) + chip->irq_ack(&desc->irq_data); + } +} + +static inline void chained_irq_exit(struct irq_chip *chip, + struct irq_desc *desc) +{ + if (chip->irq_eoi) + chip->irq_eoi(&desc->irq_data); + else + chip->irq_unmask(&desc->irq_data); +} + +#endif /* __IRQCHIP_CHAINED_IRQ_H */ ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 3/4] irqchip: gic: Call handle_bad_irq() directly 2013-01-29 16:18 [PATCH v2 0/4] Preparatory GIC patches for arm64 support Catalin Marinas 2013-01-29 16:18 ` [PATCH v2 1/4] arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h Catalin Marinas 2013-01-29 16:18 ` [PATCH v2 2/4] arm: Move chained_irq_(enter|exit) to a generic file Catalin Marinas @ 2013-01-29 16:18 ` Catalin Marinas 2013-01-29 16:18 ` [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas 2013-01-31 10:30 ` [PATCH v2 0/4] Preparatory GIC patches for arm64 support Catalin Marinas 4 siblings, 0 replies; 19+ messages in thread From: Catalin Marinas @ 2013-01-29 16:18 UTC (permalink / raw) To: linux-arm-kernel Previously, the gic_handle_cascade_irq() function was calling the ARM-specific do_bad_IRQ() function which calls handle_bad_irq() after acquiring the desk->lock. Locking the cascaded IRQ desc is not needed for error reporting, so just call handle_bad_irq() directly. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com> --- drivers/irqchip/irq-gic.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 688b977..ef1429a 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -44,7 +44,6 @@ #include <asm/irq.h> #include <asm/exception.h> #include <asm/smp_plat.h> -#include <asm/mach/irq.h> #include "irqchip.h" @@ -324,7 +323,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); if (unlikely(gic_irq < 32 || gic_irq > 1020)) - do_bad_IRQ(cascade_irq, desc); + handle_bad_irq(cascade_irq, desc); else generic_handle_irq(cascade_irq); ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-01-29 16:18 [PATCH v2 0/4] Preparatory GIC patches for arm64 support Catalin Marinas ` (2 preceding siblings ...) 2013-01-29 16:18 ` [PATCH v2 3/4] irqchip: gic: Call handle_bad_irq() directly Catalin Marinas @ 2013-01-29 16:18 ` Catalin Marinas 2013-01-29 22:35 ` Nicolas Pitre 2013-01-30 0:31 ` Dinh Nguyen 2013-01-31 10:30 ` [PATCH v2 0/4] Preparatory GIC patches for arm64 support Catalin Marinas 4 siblings, 2 replies; 19+ messages in thread From: Catalin Marinas @ 2013-01-29 16:18 UTC (permalink / raw) To: linux-arm-kernel All the calls to gic_secondary_init() pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> --- arch/arm/mach-exynos/platsmp.c | 8 -------- arch/arm/mach-highbank/platsmp.c | 7 ------- arch/arm/mach-imx/platsmp.c | 12 ------------ arch/arm/mach-msm/platsmp.c | 8 -------- arch/arm/mach-omap2/omap-smp.c | 7 ------- arch/arm/mach-shmobile/smp-emev2.c | 7 ------- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ------- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ------- arch/arm/mach-socfpga/platsmp.c | 12 ------------ arch/arm/mach-spear13xx/platsmp.c | 8 -------- arch/arm/mach-tegra/platsmp.c | 8 -------- arch/arm/mach-ux500/platsmp.c | 8 -------- arch/arm/plat-versatile/platsmp.c | 8 -------- drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++------- include/linux/irqchip/arm-gic.h | 1 - 15 files changed, 21 insertions(+), 115 deletions(-) diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index a083e05..a0e8ff7 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -20,7 +20,6 @@ #include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock); static void __cpuinit exynos_secondary_init(unsigned int cpu) { /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* * let the primary processor know we're out of the * pen, then head off into the C entry point */ diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c index 8797a70..a984573 100644 --- a/arch/arm/mach-highbank/platsmp.c +++ b/arch/arm/mach-highbank/platsmp.c @@ -17,7 +17,6 @@ #include <linux/init.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/smp_scu.h> @@ -25,11 +24,6 @@ extern void secondary_startup(void); -static void __cpuinit highbank_secondary_init(unsigned int cpu) -{ - gic_secondary_init(0); -} - static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) { highbank_set_cpu_jump(cpu, secondary_startup); @@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus) struct smp_operations highbank_smp_ops __initdata = { .smp_init_cpus = highbank_smp_init_cpus, .smp_prepare_cpus = highbank_smp_prepare_cpus, - .smp_secondary_init = highbank_secondary_init, .smp_boot_secondary = highbank_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = highbank_cpu_die, diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index b2872ec..7f63dda 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -12,7 +12,6 @@ #include <linux/init.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/page.h> #include <asm/smp_scu.h> #include <asm/mach/map.h> @@ -42,16 +41,6 @@ void __init imx_scu_map_io(void) scu_base = IMX_IO_ADDRESS(base); } -static void __cpuinit imx_secondary_init(unsigned int cpu) -{ - /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); -} - static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle) { imx_set_cpu_jump(cpu, v7_secondary_startup); @@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus) struct smp_operations imx_smp_ops __initdata = { .smp_init_cpus = imx_smp_init_cpus, .smp_prepare_cpus = imx_smp_prepare_cpus, - .smp_secondary_init = imx_secondary_init, .smp_boot_secondary = imx_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = imx_cpu_die, diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 42932865..00cdb0a 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -15,7 +15,6 @@ #include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> @@ -42,13 +41,6 @@ static inline int get_core_count(void) static void __cpuinit msm_secondary_init(unsigned int cpu) { /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* * let the primary processor know we're out of the * pen, then head off into the C entry point */ diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 3616779..c6ce880 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) 4, 0, 0, 0, 0, 0); /* - * If any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* * Synchronise with the boot thread. */ spin_lock(&boot_lock); diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 953eb1f..384e27d 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -23,7 +23,6 @@ #include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/emev2.h> #include <asm/smp_plat.h> @@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu) } -static void __cpuinit emev2_secondary_init(unsigned int cpu) -{ - gic_secondary_init(0); -} - static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) { cpu = cpu_logical_map(cpu); @@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void) struct smp_operations emev2_smp_ops __initdata = { .smp_init_cpus = emev2_smp_init_cpus, .smp_prepare_cpus = emev2_smp_prepare_cpus, - .smp_secondary_init = emev2_secondary_init, .smp_boot_secondary = emev2_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = emev2_cpu_kill, diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 3a4acf2..9949065 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -23,7 +23,6 @@ #include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/r8a7779.h> #include <asm/smp_plat.h> @@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) } -static void __cpuinit r8a7779_secondary_init(unsigned int cpu) -{ - gic_secondary_init(0); -} - static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) { struct r8a7779_pm_ch *ch = NULL; @@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void) struct smp_operations r8a7779_smp_ops __initdata = { .smp_init_cpus = r8a7779_smp_init_cpus, .smp_prepare_cpus = r8a7779_smp_prepare_cpus, - .smp_secondary_init = r8a7779_secondary_init, .smp_boot_secondary = r8a7779_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = r8a7779_cpu_kill, diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 9812ea3..f3b4912 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -23,7 +23,6 @@ #include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void) return scu_get_core_count(scu_base); } -static void __cpuinit sh73a0_secondary_init(unsigned int cpu) -{ - gic_secondary_init(0); -} - static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) { cpu = cpu_logical_map(cpu); @@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu) struct smp_operations sh73a0_smp_ops __initdata = { .smp_init_cpus = sh73a0_smp_init_cpus, .smp_prepare_cpus = sh73a0_smp_prepare_cpus, - .smp_secondary_init = sh73a0_secondary_init, .smp_boot_secondary = sh73a0_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = sh73a0_cpu_kill, diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index 4e9e69d..4b468ef 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -22,7 +22,6 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h> @@ -33,16 +32,6 @@ extern void __iomem *sys_manager_base_addr; extern void __iomem *rst_manager_base_addr; -static void __cpuinit socfpga_secondary_init(unsigned int cpu) -{ - /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); -} - static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) { int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; @@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu) struct smp_operations socfpga_smp_ops __initdata = { .smp_init_cpus = socfpga_smp_init_cpus, .smp_prepare_cpus = socfpga_smp_prepare_cpus, - .smp_secondary_init = socfpga_secondary_init, .smp_boot_secondary = socfpga_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = socfpga_cpu_die, diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c index af4ade6..551c69c 100644 --- a/arch/arm/mach-spear13xx/platsmp.c +++ b/arch/arm/mach-spear13xx/platsmp.c @@ -15,7 +15,6 @@ #include <linux/jiffies.h> #include <linux/io.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h> #include <mach/spear.h> @@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE); static void __cpuinit spear13xx_secondary_init(unsigned int cpu) { /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* * let the primary processor know we're out of the * pen, then head off into the C entry point */ diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index c72e249..dea94d2 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -18,7 +18,6 @@ #include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <linux/clk/tegra.h> #include <asm/cacheflush.h> @@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); static void __cpuinit tegra_secondary_init(unsigned int cpu) { - /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - cpumask_set_cpu(cpu, &tegra_cpu_init_mask); } diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index b8adac9..b4d0735 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -16,7 +16,6 @@ #include <linux/device.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock); static void __cpuinit ux500_secondary_init(unsigned int cpu) { /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* * let the primary processor know we're out of the * pen, then head off into the C entry point */ diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c index f2ac155..1e1b2d7 100644 --- a/arch/arm/plat-versatile/platsmp.c +++ b/arch/arm/plat-versatile/platsmp.c @@ -14,7 +14,6 @@ #include <linux/device.h> #include <linux/jiffies.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock); void __cpuinit versatile_secondary_init(unsigned int cpu) { /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* * let the primary processor know we're out of the * pen, then head off into the C entry point */ diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index ef1429a..f103cb8 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -28,6 +28,7 @@ #include <linux/module.h> #include <linux/list.h> #include <linux/smp.h> +#include <linux/cpu.h> #include <linux/cpu_pm.h> #include <linux/cpumask.h> #include <linux/io.h> @@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d, return 0; } +#ifdef CONFIG_SMP +static int __cpuinit gic_secondary_init(struct notifier_block *nfb, + unsigned long action, void *hcpu) +{ + if (action == CPU_STARTING) + gic_cpu_init(&gic_data[0]); + return NOTIFY_OK; +} + +/* + * Notifier for enabling the GIC CPU interface. Set an arbitrarily high + * priority because the GIC needs to be up before the ARM generic timers. + */ +static struct notifier_block __cpuinitdata gic_cpu_notifier = { + .notifier_call = gic_secondary_init, + .priority = 100, +}; +#endif + const struct irq_domain_ops gic_irq_domain_ops = { .map = gic_irq_domain_map, .xlate = gic_irq_domain_xlate, @@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, #ifdef CONFIG_SMP set_smp_cross_call(gic_raise_softirq); + register_cpu_notifier(&gic_cpu_notifier); #endif set_handle_irq(gic_handle_irq); @@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, gic_pm_init(gic); } -void __cpuinit gic_secondary_init(unsigned int gic_nr) -{ - BUG_ON(gic_nr >= MAX_GIC_NR); - - gic_cpu_init(&gic_data[gic_nr]); -} - #ifdef CONFIG_OF static int gic_cnt __initdata = 0; diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index a67ca55..59e59b3 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn; void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, u32 offset, struct device_node *); -void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); static inline void gic_init(unsigned int nr, int start, ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-01-29 16:18 ` [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas @ 2013-01-29 22:35 ` Nicolas Pitre 2013-01-29 23:12 ` Catalin Marinas 2013-01-30 0:31 ` Dinh Nguyen 1 sibling, 1 reply; 19+ messages in thread From: Nicolas Pitre @ 2013-01-29 22:35 UTC (permalink / raw) To: linux-arm-kernel On Tue, 29 Jan 2013, Catalin Marinas wrote: > All the calls to gic_secondary_init() pass 0 as the first argument. > Since this function is called on each CPU when starting, it can be done > in a platform-independent way via a CPU notifier registered by the GIC > code. > > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> > Acked-by: Stephen Warren <swarren@nvidia.com> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org> > Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > Acked-by: Rob Herring <rob.herring@calxeda.com> > Acked-by: Simon Horman <horms+renesas@verge.net.au> > Tested-by: Simon Horman <horms+renesas@verge.net.au> > Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> > Cc: Russell King <linux@arm.linux.org.uk> > Cc: Thomas Gleixner <tglx@linutronix.de> > Cc: Kukjin Kim <kgene.kim@samsung.com> > Cc: Sascha Hauer <kernel@pengutronix.de> > Cc: David Brown <davidb@codeaurora.org> > Cc: Bryan Huntsman <bryanh@codeaurora.org> > Cc: Tony Lindgren <tony@atomide.com> > Cc: Magnus Damm <magnus.damm@gmail.com> > Cc: Dinh Nguyen <dinguyen@altera.com> > Cc: Shiraz Hashim <shiraz.hashim@st.com> > Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> What is your plan in terms of merge path and schedule? My mcpm series would depend on this. > --- > arch/arm/mach-exynos/platsmp.c | 8 -------- > arch/arm/mach-highbank/platsmp.c | 7 ------- > arch/arm/mach-imx/platsmp.c | 12 ------------ > arch/arm/mach-msm/platsmp.c | 8 -------- > arch/arm/mach-omap2/omap-smp.c | 7 ------- > arch/arm/mach-shmobile/smp-emev2.c | 7 ------- > arch/arm/mach-shmobile/smp-r8a7779.c | 7 ------- > arch/arm/mach-shmobile/smp-sh73a0.c | 7 ------- > arch/arm/mach-socfpga/platsmp.c | 12 ------------ > arch/arm/mach-spear13xx/platsmp.c | 8 -------- > arch/arm/mach-tegra/platsmp.c | 8 -------- > arch/arm/mach-ux500/platsmp.c | 8 -------- > arch/arm/plat-versatile/platsmp.c | 8 -------- > drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++------- > include/linux/irqchip/arm-gic.h | 1 - > 15 files changed, 21 insertions(+), 115 deletions(-) > > diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c > index a083e05..a0e8ff7 100644 > --- a/arch/arm/mach-exynos/platsmp.c > +++ b/arch/arm/mach-exynos/platsmp.c > @@ -20,7 +20,6 @@ > #include <linux/jiffies.h> > #include <linux/smp.h> > #include <linux/io.h> > -#include <linux/irqchip/arm-gic.h> > > #include <asm/cacheflush.h> > #include <asm/smp_plat.h> > @@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock); > static void __cpuinit exynos_secondary_init(unsigned int cpu) > { > /* > - * if any interrupts are already enabled for the primary > - * core (e.g. timer irq), then they will not have been enabled > - * for us: do so > - */ > - gic_secondary_init(0); > - > - /* > * let the primary processor know we're out of the > * pen, then head off into the C entry point > */ > diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c > index 8797a70..a984573 100644 > --- a/arch/arm/mach-highbank/platsmp.c > +++ b/arch/arm/mach-highbank/platsmp.c > @@ -17,7 +17,6 @@ > #include <linux/init.h> > #include <linux/smp.h> > #include <linux/io.h> > -#include <linux/irqchip/arm-gic.h> > > #include <asm/smp_scu.h> > > @@ -25,11 +24,6 @@ > > extern void secondary_startup(void); > > -static void __cpuinit highbank_secondary_init(unsigned int cpu) > -{ > - gic_secondary_init(0); > -} > - > static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) > { > highbank_set_cpu_jump(cpu, secondary_startup); > @@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus) > struct smp_operations highbank_smp_ops __initdata = { > .smp_init_cpus = highbank_smp_init_cpus, > .smp_prepare_cpus = highbank_smp_prepare_cpus, > - .smp_secondary_init = highbank_secondary_init, > .smp_boot_secondary = highbank_boot_secondary, > #ifdef CONFIG_HOTPLUG_CPU > .cpu_die = highbank_cpu_die, > diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c > index b2872ec..7f63dda 100644 > --- a/arch/arm/mach-imx/platsmp.c > +++ b/arch/arm/mach-imx/platsmp.c > @@ -12,7 +12,6 @@ > > #include <linux/init.h> > #include <linux/smp.h> > -#include <linux/irqchip/arm-gic.h> > #include <asm/page.h> > #include <asm/smp_scu.h> > #include <asm/mach/map.h> > @@ -42,16 +41,6 @@ void __init imx_scu_map_io(void) > scu_base = IMX_IO_ADDRESS(base); > } > > -static void __cpuinit imx_secondary_init(unsigned int cpu) > -{ > - /* > - * if any interrupts are already enabled for the primary > - * core (e.g. timer irq), then they will not have been enabled > - * for us: do so > - */ > - gic_secondary_init(0); > -} > - > static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle) > { > imx_set_cpu_jump(cpu, v7_secondary_startup); > @@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus) > struct smp_operations imx_smp_ops __initdata = { > .smp_init_cpus = imx_smp_init_cpus, > .smp_prepare_cpus = imx_smp_prepare_cpus, > - .smp_secondary_init = imx_secondary_init, > .smp_boot_secondary = imx_boot_secondary, > #ifdef CONFIG_HOTPLUG_CPU > .cpu_die = imx_cpu_die, > diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c > index 42932865..00cdb0a 100644 > --- a/arch/arm/mach-msm/platsmp.c > +++ b/arch/arm/mach-msm/platsmp.c > @@ -15,7 +15,6 @@ > #include <linux/jiffies.h> > #include <linux/smp.h> > #include <linux/io.h> > -#include <linux/irqchip/arm-gic.h> > > #include <asm/cacheflush.h> > #include <asm/cputype.h> > @@ -42,13 +41,6 @@ static inline int get_core_count(void) > static void __cpuinit msm_secondary_init(unsigned int cpu) > { > /* > - * if any interrupts are already enabled for the primary > - * core (e.g. timer irq), then they will not have been enabled > - * for us: do so > - */ > - gic_secondary_init(0); > - > - /* > * let the primary processor know we're out of the > * pen, then head off into the C entry point > */ > diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c > index 3616779..c6ce880 100644 > --- a/arch/arm/mach-omap2/omap-smp.c > +++ b/arch/arm/mach-omap2/omap-smp.c > @@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) > 4, 0, 0, 0, 0, 0); > > /* > - * If any interrupts are already enabled for the primary > - * core (e.g. timer irq), then they will not have been enabled > - * for us: do so > - */ > - gic_secondary_init(0); > - > - /* > * Synchronise with the boot thread. > */ > spin_lock(&boot_lock); > diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c > index 953eb1f..384e27d 100644 > --- a/arch/arm/mach-shmobile/smp-emev2.c > +++ b/arch/arm/mach-shmobile/smp-emev2.c > @@ -23,7 +23,6 @@ > #include <linux/spinlock.h> > #include <linux/io.h> > #include <linux/delay.h> > -#include <linux/irqchip/arm-gic.h> > #include <mach/common.h> > #include <mach/emev2.h> > #include <asm/smp_plat.h> > @@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu) > } > > > -static void __cpuinit emev2_secondary_init(unsigned int cpu) > -{ > - gic_secondary_init(0); > -} > - > static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) > { > cpu = cpu_logical_map(cpu); > @@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void) > struct smp_operations emev2_smp_ops __initdata = { > .smp_init_cpus = emev2_smp_init_cpus, > .smp_prepare_cpus = emev2_smp_prepare_cpus, > - .smp_secondary_init = emev2_secondary_init, > .smp_boot_secondary = emev2_boot_secondary, > #ifdef CONFIG_HOTPLUG_CPU > .cpu_kill = emev2_cpu_kill, > diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c > index 3a4acf2..9949065 100644 > --- a/arch/arm/mach-shmobile/smp-r8a7779.c > +++ b/arch/arm/mach-shmobile/smp-r8a7779.c > @@ -23,7 +23,6 @@ > #include <linux/spinlock.h> > #include <linux/io.h> > #include <linux/delay.h> > -#include <linux/irqchip/arm-gic.h> > #include <mach/common.h> > #include <mach/r8a7779.h> > #include <asm/smp_plat.h> > @@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) > } > > > -static void __cpuinit r8a7779_secondary_init(unsigned int cpu) > -{ > - gic_secondary_init(0); > -} > - > static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) > { > struct r8a7779_pm_ch *ch = NULL; > @@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void) > struct smp_operations r8a7779_smp_ops __initdata = { > .smp_init_cpus = r8a7779_smp_init_cpus, > .smp_prepare_cpus = r8a7779_smp_prepare_cpus, > - .smp_secondary_init = r8a7779_secondary_init, > .smp_boot_secondary = r8a7779_boot_secondary, > #ifdef CONFIG_HOTPLUG_CPU > .cpu_kill = r8a7779_cpu_kill, > diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c > index 9812ea3..f3b4912 100644 > --- a/arch/arm/mach-shmobile/smp-sh73a0.c > +++ b/arch/arm/mach-shmobile/smp-sh73a0.c > @@ -23,7 +23,6 @@ > #include <linux/spinlock.h> > #include <linux/io.h> > #include <linux/delay.h> > -#include <linux/irqchip/arm-gic.h> > #include <mach/common.h> > #include <asm/cacheflush.h> > #include <asm/smp_plat.h> > @@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void) > return scu_get_core_count(scu_base); > } > > -static void __cpuinit sh73a0_secondary_init(unsigned int cpu) > -{ > - gic_secondary_init(0); > -} > - > static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) > { > cpu = cpu_logical_map(cpu); > @@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu) > struct smp_operations sh73a0_smp_ops __initdata = { > .smp_init_cpus = sh73a0_smp_init_cpus, > .smp_prepare_cpus = sh73a0_smp_prepare_cpus, > - .smp_secondary_init = sh73a0_secondary_init, > .smp_boot_secondary = sh73a0_boot_secondary, > #ifdef CONFIG_HOTPLUG_CPU > .cpu_kill = sh73a0_cpu_kill, > diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c > index 4e9e69d..4b468ef 100644 > --- a/arch/arm/mach-socfpga/platsmp.c > +++ b/arch/arm/mach-socfpga/platsmp.c > @@ -22,7 +22,6 @@ > #include <linux/io.h> > #include <linux/of.h> > #include <linux/of_address.h> > -#include <linux/irqchip/arm-gic.h> > > #include <asm/cacheflush.h> > #include <asm/smp_scu.h> > @@ -33,16 +32,6 @@ > extern void __iomem *sys_manager_base_addr; > extern void __iomem *rst_manager_base_addr; > > -static void __cpuinit socfpga_secondary_init(unsigned int cpu) > -{ > - /* > - * if any interrupts are already enabled for the primary > - * core (e.g. timer irq), then they will not have been enabled > - * for us: do so > - */ > - gic_secondary_init(0); > -} > - > static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) > { > int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; > @@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu) > struct smp_operations socfpga_smp_ops __initdata = { > .smp_init_cpus = socfpga_smp_init_cpus, > .smp_prepare_cpus = socfpga_smp_prepare_cpus, > - .smp_secondary_init = socfpga_secondary_init, > .smp_boot_secondary = socfpga_boot_secondary, > #ifdef CONFIG_HOTPLUG_CPU > .cpu_die = socfpga_cpu_die, > diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c > index af4ade6..551c69c 100644 > --- a/arch/arm/mach-spear13xx/platsmp.c > +++ b/arch/arm/mach-spear13xx/platsmp.c > @@ -15,7 +15,6 @@ > #include <linux/jiffies.h> > #include <linux/io.h> > #include <linux/smp.h> > -#include <linux/irqchip/arm-gic.h> > #include <asm/cacheflush.h> > #include <asm/smp_scu.h> > #include <mach/spear.h> > @@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE); > static void __cpuinit spear13xx_secondary_init(unsigned int cpu) > { > /* > - * if any interrupts are already enabled for the primary > - * core (e.g. timer irq), then they will not have been enabled > - * for us: do so > - */ > - gic_secondary_init(0); > - > - /* > * let the primary processor know we're out of the > * pen, then head off into the C entry point > */ > diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c > index c72e249..dea94d2 100644 > --- a/arch/arm/mach-tegra/platsmp.c > +++ b/arch/arm/mach-tegra/platsmp.c > @@ -18,7 +18,6 @@ > #include <linux/jiffies.h> > #include <linux/smp.h> > #include <linux/io.h> > -#include <linux/irqchip/arm-gic.h> > #include <linux/clk/tegra.h> > > #include <asm/cacheflush.h> > @@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); > > static void __cpuinit tegra_secondary_init(unsigned int cpu) > { > - /* > - * if any interrupts are already enabled for the primary > - * core (e.g. timer irq), then they will not have been enabled > - * for us: do so > - */ > - gic_secondary_init(0); > - > cpumask_set_cpu(cpu, &tegra_cpu_init_mask); > } > > diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c > index b8adac9..b4d0735 100644 > --- a/arch/arm/mach-ux500/platsmp.c > +++ b/arch/arm/mach-ux500/platsmp.c > @@ -16,7 +16,6 @@ > #include <linux/device.h> > #include <linux/smp.h> > #include <linux/io.h> > -#include <linux/irqchip/arm-gic.h> > > #include <asm/cacheflush.h> > #include <asm/smp_plat.h> > @@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock); > static void __cpuinit ux500_secondary_init(unsigned int cpu) > { > /* > - * if any interrupts are already enabled for the primary > - * core (e.g. timer irq), then they will not have been enabled > - * for us: do so > - */ > - gic_secondary_init(0); > - > - /* > * let the primary processor know we're out of the > * pen, then head off into the C entry point > */ > diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c > index f2ac155..1e1b2d7 100644 > --- a/arch/arm/plat-versatile/platsmp.c > +++ b/arch/arm/plat-versatile/platsmp.c > @@ -14,7 +14,6 @@ > #include <linux/device.h> > #include <linux/jiffies.h> > #include <linux/smp.h> > -#include <linux/irqchip/arm-gic.h> > > #include <asm/cacheflush.h> > #include <asm/smp_plat.h> > @@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock); > void __cpuinit versatile_secondary_init(unsigned int cpu) > { > /* > - * if any interrupts are already enabled for the primary > - * core (e.g. timer irq), then they will not have been enabled > - * for us: do so > - */ > - gic_secondary_init(0); > - > - /* > * let the primary processor know we're out of the > * pen, then head off into the C entry point > */ > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > index ef1429a..f103cb8 100644 > --- a/drivers/irqchip/irq-gic.c > +++ b/drivers/irqchip/irq-gic.c > @@ -28,6 +28,7 @@ > #include <linux/module.h> > #include <linux/list.h> > #include <linux/smp.h> > +#include <linux/cpu.h> > #include <linux/cpu_pm.h> > #include <linux/cpumask.h> > #include <linux/io.h> > @@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d, > return 0; > } > > +#ifdef CONFIG_SMP > +static int __cpuinit gic_secondary_init(struct notifier_block *nfb, > + unsigned long action, void *hcpu) > +{ > + if (action == CPU_STARTING) > + gic_cpu_init(&gic_data[0]); > + return NOTIFY_OK; > +} > + > +/* > + * Notifier for enabling the GIC CPU interface. Set an arbitrarily high > + * priority because the GIC needs to be up before the ARM generic timers. > + */ > +static struct notifier_block __cpuinitdata gic_cpu_notifier = { > + .notifier_call = gic_secondary_init, > + .priority = 100, > +}; > +#endif > + > const struct irq_domain_ops gic_irq_domain_ops = { > .map = gic_irq_domain_map, > .xlate = gic_irq_domain_xlate, > @@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, > > #ifdef CONFIG_SMP > set_smp_cross_call(gic_raise_softirq); > + register_cpu_notifier(&gic_cpu_notifier); > #endif > > set_handle_irq(gic_handle_irq); > @@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, > gic_pm_init(gic); > } > > -void __cpuinit gic_secondary_init(unsigned int gic_nr) > -{ > - BUG_ON(gic_nr >= MAX_GIC_NR); > - > - gic_cpu_init(&gic_data[gic_nr]); > -} > - > #ifdef CONFIG_OF > static int gic_cnt __initdata = 0; > > diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h > index a67ca55..59e59b3 100644 > --- a/include/linux/irqchip/arm-gic.h > +++ b/include/linux/irqchip/arm-gic.h > @@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn; > > void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, > u32 offset, struct device_node *); > -void gic_secondary_init(unsigned int); > void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); > > static inline void gic_init(unsigned int nr, int start, > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-01-29 22:35 ` Nicolas Pitre @ 2013-01-29 23:12 ` Catalin Marinas 2013-01-30 0:11 ` Nicolas Pitre 0 siblings, 1 reply; 19+ messages in thread From: Catalin Marinas @ 2013-01-29 23:12 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jan 29, 2013 at 10:35:46PM +0000, Nicolas Pitre wrote: > On Tue, 29 Jan 2013, Catalin Marinas wrote: > > > All the calls to gic_secondary_init() pass 0 as the first argument. > > Since this function is called on each CPU when starting, it can be done > > in a platform-independent way via a CPU notifier registered by the GIC > > code. > > > > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> > > Acked-by: Stephen Warren <swarren@nvidia.com> > > Acked-by: Viresh Kumar <viresh.kumar@linaro.org> > > Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > > Acked-by: Rob Herring <rob.herring@calxeda.com> > > Acked-by: Simon Horman <horms+renesas@verge.net.au> > > Tested-by: Simon Horman <horms+renesas@verge.net.au> > > Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> > > Cc: Russell King <linux@arm.linux.org.uk> > > Cc: Thomas Gleixner <tglx@linutronix.de> > > Cc: Kukjin Kim <kgene.kim@samsung.com> > > Cc: Sascha Hauer <kernel@pengutronix.de> > > Cc: David Brown <davidb@codeaurora.org> > > Cc: Bryan Huntsman <bryanh@codeaurora.org> > > Cc: Tony Lindgren <tony@atomide.com> > > Cc: Magnus Damm <magnus.damm@gmail.com> > > Cc: Dinh Nguyen <dinguyen@altera.com> > > Cc: Shiraz Hashim <shiraz.hashim@st.com> > > Cc: Linus Walleij <linus.walleij@linaro.org> > > Acked-by: Nicolas Pitre <nico@linaro.org> Thanks. > What is your plan in terms of merge path and schedule? My mcpm series > would depend on this. I would like to get them in as soon as possible (ideally 3.9) as AArch64 needs GIC support. I can base them on Rob's branch (already in -next) and send them the same route (the arm-soc tree if Olof/Arnd are ok to take them). -- Catalin ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-01-29 23:12 ` Catalin Marinas @ 2013-01-30 0:11 ` Nicolas Pitre 2013-01-31 11:25 ` Russell King - ARM Linux 0 siblings, 1 reply; 19+ messages in thread From: Nicolas Pitre @ 2013-01-30 0:11 UTC (permalink / raw) To: linux-arm-kernel On Tue, 29 Jan 2013, Catalin Marinas wrote: > On Tue, Jan 29, 2013 at 10:35:46PM +0000, Nicolas Pitre wrote: > > On Tue, 29 Jan 2013, Catalin Marinas wrote: > > > > > All the calls to gic_secondary_init() pass 0 as the first argument. > > > Since this function is called on each CPU when starting, it can be done > > > in a platform-independent way via a CPU notifier registered by the GIC > > > code. > > > > > > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> > > > Acked-by: Stephen Warren <swarren@nvidia.com> > > > Acked-by: Viresh Kumar <viresh.kumar@linaro.org> > > > Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > > > Acked-by: Rob Herring <rob.herring@calxeda.com> > > > Acked-by: Simon Horman <horms+renesas@verge.net.au> > > > Tested-by: Simon Horman <horms+renesas@verge.net.au> > > > Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> > > > Cc: Russell King <linux@arm.linux.org.uk> > > > Cc: Thomas Gleixner <tglx@linutronix.de> > > > Cc: Kukjin Kim <kgene.kim@samsung.com> > > > Cc: Sascha Hauer <kernel@pengutronix.de> > > > Cc: David Brown <davidb@codeaurora.org> > > > Cc: Bryan Huntsman <bryanh@codeaurora.org> > > > Cc: Tony Lindgren <tony@atomide.com> > > > Cc: Magnus Damm <magnus.damm@gmail.com> > > > Cc: Dinh Nguyen <dinguyen@altera.com> > > > Cc: Shiraz Hashim <shiraz.hashim@st.com> > > > Cc: Linus Walleij <linus.walleij@linaro.org> > > > > Acked-by: Nicolas Pitre <nico@linaro.org> > > Thanks. > > > What is your plan in terms of merge path and schedule? My mcpm series > > would depend on this. > > I would like to get them in as soon as possible (ideally 3.9) as AArch64 > needs GIC support. I can base them on Rob's branch (already in -next) > and send them the same route (the arm-soc tree if Olof/Arnd are ok to > take them). Well... I'd prefer if my series was merged by RMK since this is mostly core ARM code. That is posing dependency issues. I think I'll just ignore your change for now and we'll fix things up during the v3.9-rc period. Nicolas ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-01-30 0:11 ` Nicolas Pitre @ 2013-01-31 11:25 ` Russell King - ARM Linux 2013-01-31 11:49 ` Catalin Marinas 2013-01-31 17:32 ` Nicolas Pitre 0 siblings, 2 replies; 19+ messages in thread From: Russell King - ARM Linux @ 2013-01-31 11:25 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jan 29, 2013 at 07:11:56PM -0500, Nicolas Pitre wrote: > On Tue, 29 Jan 2013, Catalin Marinas wrote: > > I would like to get them in as soon as possible (ideally 3.9) as AArch64 > > needs GIC support. I can base them on Rob's branch (already in -next) > > and send them the same route (the arm-soc tree if Olof/Arnd are ok to > > take them). > > Well... I'd prefer if my series was merged by RMK since this is mostly > core ARM code. That is posing dependency issues. > > I think I'll just ignore your change for now and we'll fix things up > during the v3.9-rc period. Given that the ARM kernel seems to be rather broken at the moment, that's not going to happen until the 32-bit kernel gets some loving attention to make it work again. Our primary responsibility is not to stuff the kernel with new features as quickly as we possibly can. It's to make sure that the kernel works, and at the moment, it doesn't. I'm not talking about ancient architectures. I'm talking about platforms using ARMv6 and above - platforms with the GIC which I'd be able to test this change on. Realview EB (MPCore) - Various failures yesterday but now works in my tree. Fixes queued for the next -rc. (But the hardware randomly locks up during kernel boot, normally around the time when the CLCD is enabled, so this can't really be used for testing.) OMAP4430SDP (Cortex A9) - Fails to boot even with proper uImage addresses (no idea yet). No kernel output. OMAP3430LDP (Cortex A8 iirc) - Ditto. No kernel output. I haven't tried Versatile Express yet as it has the TC2 tile on, and I don't yet a boot loader on it which is capable of TFTP (which makes it rather useless to me - I've been saying this for a time now but this is probably the first time publically.) I'm thinking about putting the CA9x4 tile back on because that's a lot more functionally useful to me than TC2. ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-01-31 11:25 ` Russell King - ARM Linux @ 2013-01-31 11:49 ` Catalin Marinas 2013-01-31 17:32 ` Nicolas Pitre 1 sibling, 0 replies; 19+ messages in thread From: Catalin Marinas @ 2013-01-31 11:49 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 31, 2013 at 11:25:38AM +0000, Russell King - ARM Linux wrote: > On Tue, Jan 29, 2013 at 07:11:56PM -0500, Nicolas Pitre wrote: > > On Tue, 29 Jan 2013, Catalin Marinas wrote: > > > I would like to get them in as soon as possible (ideally 3.9) as AArch64 > > > needs GIC support. I can base them on Rob's branch (already in -next) > > > and send them the same route (the arm-soc tree if Olof/Arnd are ok to > > > take them). > > > > Well... I'd prefer if my series was merged by RMK since this is mostly > > core ARM code. That is posing dependency issues. > > > > I think I'll just ignore your change for now and we'll fix things up > > during the v3.9-rc period. > > Given that the ARM kernel seems to be rather broken at the moment, that's > not going to happen until the 32-bit kernel gets some loving attention to > make it work again. > > Our primary responsibility is not to stuff the kernel with new features > as quickly as we possibly can. It's to make sure that the kernel works, > and at the moment, it doesn't. I'm not talking about ancient architectures. > I'm talking about platforms using ARMv6 and above - platforms with the GIC > which I'd be able to test this change on. FWIW, I tested this on vexpress with CA9x4 tile with both 3.8-rc3 (Rob's branch) and latest linux-next. If you want to test this change for longer, I'm ok to leave it for 3.10 and stick it in -next at some point (after 3.9-rc1 since there are many conflicts). I'd like however to push the other trivial code-moving patches in this series. -- Catalin ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-01-31 11:25 ` Russell King - ARM Linux 2013-01-31 11:49 ` Catalin Marinas @ 2013-01-31 17:32 ` Nicolas Pitre 2013-01-31 17:55 ` Russell King - ARM Linux 1 sibling, 1 reply; 19+ messages in thread From: Nicolas Pitre @ 2013-01-31 17:32 UTC (permalink / raw) To: linux-arm-kernel On Thu, 31 Jan 2013, Russell King - ARM Linux wrote: > I haven't tried Versatile Express yet as it has the TC2 tile on, and I > don't yet a boot loader on it which is capable of TFTP (which makes it > rather useless to me - I've been saying this for a time now but this is > probably the first time publically.) I'm thinking about putting the > CA9x4 tile back on because that's a lot more functionally useful to me > than TC2. You might be interested by this then: http://lists.linaro.org/pipermail/linaro-dev/2012-October/014136.html Nicolas ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-01-31 17:32 ` Nicolas Pitre @ 2013-01-31 17:55 ` Russell King - ARM Linux 2013-01-31 20:31 ` Nicolas Pitre 0 siblings, 1 reply; 19+ messages in thread From: Russell King - ARM Linux @ 2013-01-31 17:55 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 31, 2013 at 12:32:11PM -0500, Nicolas Pitre wrote: > On Thu, 31 Jan 2013, Russell King - ARM Linux wrote: > > > I haven't tried Versatile Express yet as it has the TC2 tile on, and I > > don't yet a boot loader on it which is capable of TFTP (which makes it > > rather useless to me - I've been saying this for a time now but this is > > probably the first time publically.) I'm thinking about putting the > > CA9x4 tile back on because that's a lot more functionally useful to me > > than TC2. > > You might be interested by this then: > > http://lists.linaro.org/pipermail/linaro-dev/2012-October/014136.html Great news. Everyone has been telling me that there's no uboot for TC2, or "we think Linaro might have something but we don't really know". ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-01-31 17:55 ` Russell King - ARM Linux @ 2013-01-31 20:31 ` Nicolas Pitre 2013-02-01 14:38 ` Jon Medhurst (Tixy) 0 siblings, 1 reply; 19+ messages in thread From: Nicolas Pitre @ 2013-01-31 20:31 UTC (permalink / raw) To: linux-arm-kernel On Thu, 31 Jan 2013, Russell King - ARM Linux wrote: > On Thu, Jan 31, 2013 at 12:32:11PM -0500, Nicolas Pitre wrote: > > On Thu, 31 Jan 2013, Russell King - ARM Linux wrote: > > > > > I haven't tried Versatile Express yet as it has the TC2 tile on, and I > > > don't yet a boot loader on it which is capable of TFTP (which makes it > > > rather useless to me - I've been saying this for a time now but this is > > > probably the first time publically.) I'm thinking about putting the > > > CA9x4 tile back on because that's a lot more functionally useful to me > > > than TC2. > > > > You might be interested by this then: > > > > http://lists.linaro.org/pipermail/linaro-dev/2012-October/014136.html > > Great news. Everyone has been telling me that there's no uboot for TC2, > or "we think Linaro might have something but we don't really know". Note that I cobbled those instructions on my own and the result is not officially supported by Linaro. This is obviously not suitable for setting up products or demo systems, but for a kernel developer I think such a setup is invaluable. Nicolas ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-01-31 20:31 ` Nicolas Pitre @ 2013-02-01 14:38 ` Jon Medhurst (Tixy) 2013-02-01 17:39 ` Nicolas Pitre 0 siblings, 1 reply; 19+ messages in thread From: Jon Medhurst (Tixy) @ 2013-02-01 14:38 UTC (permalink / raw) To: linux-arm-kernel On Thu, 2013-01-31 at 15:31 -0500, Nicolas Pitre wrote: > On Thu, 31 Jan 2013, Russell King - ARM Linux wrote: > > > On Thu, Jan 31, 2013 at 12:32:11PM -0500, Nicolas Pitre wrote: > > > On Thu, 31 Jan 2013, Russell King - ARM Linux wrote: > > > > > > > I haven't tried Versatile Express yet as it has the TC2 tile on, and I > > > > don't yet a boot loader on it which is capable of TFTP (which makes it > > > > rather useless to me - I've been saying this for a time now but this is > > > > probably the first time publically.) I'm thinking about putting the > > > > CA9x4 tile back on because that's a lot more functionally useful to me > > > > than TC2. > > > > > > You might be interested by this then: > > > > > > http://lists.linaro.org/pipermail/linaro-dev/2012-October/014136.html > > > > Great news. Everyone has been telling me that there's no uboot for TC2, > > or "we think Linaro might have something but we don't really know". > > Note that I cobbled those instructions on my own and the result is not > officially supported by Linaro. This is obviously not suitable for > setting up products or demo systems, but for a kernel developer I think > such a setup is invaluable. If I remember correctly, you will also only get 1GB of RAM available not the 2GB most TC2 boards have. (I did take a quick look at hacking U-Boot to get around that but couldn't get anything to work.) -- Tixy ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-02-01 14:38 ` Jon Medhurst (Tixy) @ 2013-02-01 17:39 ` Nicolas Pitre 0 siblings, 0 replies; 19+ messages in thread From: Nicolas Pitre @ 2013-02-01 17:39 UTC (permalink / raw) To: linux-arm-kernel On Fri, 1 Feb 2013, Jon Medhurst (Tixy) wrote: > On Thu, 2013-01-31 at 15:31 -0500, Nicolas Pitre wrote: > > On Thu, 31 Jan 2013, Russell King - ARM Linux wrote: > > > > > On Thu, Jan 31, 2013 at 12:32:11PM -0500, Nicolas Pitre wrote: > > > > On Thu, 31 Jan 2013, Russell King - ARM Linux wrote: > > > > > > > > > I haven't tried Versatile Express yet as it has the TC2 tile on, and I > > > > > don't yet a boot loader on it which is capable of TFTP (which makes it > > > > > rather useless to me - I've been saying this for a time now but this is > > > > > probably the first time publically.) I'm thinking about putting the > > > > > CA9x4 tile back on because that's a lot more functionally useful to me > > > > > than TC2. > > > > > > > > You might be interested by this then: > > > > > > > > http://lists.linaro.org/pipermail/linaro-dev/2012-October/014136.html > > > > > > Great news. Everyone has been telling me that there's no uboot for TC2, > > > or "we think Linaro might have something but we don't really know". > > > > Note that I cobbled those instructions on my own and the result is not > > officially supported by Linaro. This is obviously not suitable for > > setting up products or demo systems, but for a kernel developer I think > > such a setup is invaluable. > > If I remember correctly, you will also only get 1GB of RAM available not > the 2GB most TC2 boards have. (I did take a quick look at hacking U-Boot > to get around that but couldn't get anything to work.) I simply added "mem=2048m at 0x80000000" to my kernel cmdline. Nicolas ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 2013-01-29 16:18 ` [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas 2013-01-29 22:35 ` Nicolas Pitre @ 2013-01-30 0:31 ` Dinh Nguyen 1 sibling, 0 replies; 19+ messages in thread From: Dinh Nguyen @ 2013-01-30 0:31 UTC (permalink / raw) To: linux-arm-kernel Hi Catalina, On Tue, 2013-01-29 at 16:18 +0000, Catalin Marinas wrote: > All the calls to gic_secondary_init() pass 0 as the first argument. > Since this function is called on each CPU when starting, it can be done > in a platform-independent way via a CPU notifier registered by the GIC > code. > > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> > Acked-by: Stephen Warren <swarren@nvidia.com> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org> > Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > Acked-by: Rob Herring <rob.herring@calxeda.com> > Acked-by: Simon Horman <horms+renesas@verge.net.au> > Tested-by: Simon Horman <horms+renesas@verge.net.au> > Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> > Cc: Russell King <linux@arm.linux.org.uk> > Cc: Thomas Gleixner <tglx@linutronix.de> > Cc: Kukjin Kim <kgene.kim@samsung.com> > Cc: Sascha Hauer <kernel@pengutronix.de> > Cc: David Brown <davidb@codeaurora.org> > Cc: Bryan Huntsman <bryanh@codeaurora.org> > Cc: Tony Lindgren <tony@atomide.com> > Cc: Magnus Damm <magnus.damm@gmail.com> > Cc: Dinh Nguyen <dinguyen@altera.com> > Cc: Shiraz Hashim <shiraz.hashim@st.com> > Cc: Linus Walleij <linus.walleij@linaro.org> > --- > arch/arm/mach-exynos/platsmp.c | 8 -------- > arch/arm/mach-highbank/platsmp.c | 7 ------- > arch/arm/mach-imx/platsmp.c | 12 ------------ > arch/arm/mach-msm/platsmp.c | 8 -------- > arch/arm/mach-omap2/omap-smp.c | 7 ------- > arch/arm/mach-shmobile/smp-emev2.c | 7 ------- > arch/arm/mach-shmobile/smp-r8a7779.c | 7 ------- > arch/arm/mach-shmobile/smp-sh73a0.c | 7 ------- > arch/arm/mach-socfpga/platsmp.c | 12 ------------ > arch/arm/mach-spear13xx/platsmp.c | 8 -------- > arch/arm/mach-tegra/platsmp.c | 8 -------- > arch/arm/mach-ux500/platsmp.c | 8 -------- > arch/arm/plat-versatile/platsmp.c | 8 -------- > drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++------- > include/linux/irqchip/arm-gic.h | 1 - > 15 files changed, 21 insertions(+), 115 deletions(-) > > diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c > index a083e05..a0e8ff7 100644 > --- a/arch/arm/mach-exynos/platsmp.c > +++ b/arch/arm/mach-exynos/platsmp.c > @@ -20,7 +20,6 @@ > #include <linux/jiffies.h> > #include <linux/smp.h> > For mach-socfpga: Tested-by: Dinh Nguyen <dinguyen@altera.com> Thanks, Dinh ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 0/4] Preparatory GIC patches for arm64 support 2013-01-29 16:18 [PATCH v2 0/4] Preparatory GIC patches for arm64 support Catalin Marinas ` (3 preceding siblings ...) 2013-01-29 16:18 ` [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas @ 2013-01-31 10:30 ` Catalin Marinas 2013-01-31 11:47 ` Russell King - ARM Linux 4 siblings, 1 reply; 19+ messages in thread From: Catalin Marinas @ 2013-01-31 10:30 UTC (permalink / raw) To: linux-arm-kernel Olof, Arnd, On Tue, Jan 29, 2013 at 04:18:35PM +0000, Catalin Marinas wrote: > That's the second version of the GIC clean-up patches to support arm64. > The only change from v1 is that the second patch (chained_irq.h) also > covers drivers/gpio and drivers/pinctrl (#include change). Are you ok to merge this series via the arm-soc tree for 3.9-rc1? There are no complaints so far (only acks ;). This would allow me to push GIC support for arm64. Thanks, Catalin Stats below for reference: > Catalin Marinas (4): > arm: Move the set_handle_irq and handle_arch_irq declarations to > asm/irq.h > arm: Move chained_irq_(enter|exit) to a generic file > irqchip: gic: Call handle_bad_irq() directly > irqchip: gic: Perform the gic_secondary_init() call via CPU notifier > > arch/arm/include/asm/irq.h | 5 +++ > arch/arm/include/asm/mach/irq.h | 36 -------------------- > arch/arm/mach-at91/gpio.c | 3 +- > arch/arm/mach-exynos/common.c | 1 + > arch/arm/mach-exynos/platsmp.c | 8 ----- > arch/arm/mach-highbank/platsmp.c | 7 ---- > arch/arm/mach-imx/platsmp.c | 12 ------- > arch/arm/mach-msm/platsmp.c | 8 ----- > arch/arm/mach-omap2/omap-smp.c | 7 ---- > arch/arm/mach-shmobile/smp-emev2.c | 7 ---- > arch/arm/mach-shmobile/smp-r8a7779.c | 7 ---- > arch/arm/mach-shmobile/smp-sh73a0.c | 7 ---- > arch/arm/mach-socfpga/platsmp.c | 12 ------- > arch/arm/mach-spear13xx/platsmp.c | 8 ----- > arch/arm/mach-tegra/platsmp.c | 8 ----- > arch/arm/mach-ux500/platsmp.c | 8 ----- > arch/arm/plat-samsung/irq-vic-timer.c | 3 +- > arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +- > arch/arm/plat-versatile/platsmp.c | 8 ----- > drivers/gpio/gpio-msm-v2.c | 3 +- > drivers/gpio/gpio-mxc.c | 2 +- > drivers/gpio/gpio-omap.c | 3 +- > drivers/gpio/gpio-pl061.c | 2 +- > drivers/gpio/gpio-pxa.c | 3 +- > drivers/gpio/gpio-tegra.c | 3 +- > drivers/irqchip/irq-gic.c | 32 +++++++++++++----- > drivers/irqchip/irq-vic.c | 2 +- > drivers/pinctrl/pinctrl-at91.c | 3 +- > drivers/pinctrl/pinctrl-exynos.c | 3 +- > drivers/pinctrl/pinctrl-nomadik.c | 2 +- > drivers/pinctrl/pinctrl-sirf.c | 2 +- > drivers/pinctrl/spear/pinctrl-plgpio.c | 2 +- > drivers/staging/imx-drm/ipu-v3/ipu-common.c | 2 +- > include/linux/irqchip/arm-gic.h | 1 - > include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++ > 35 files changed, 97 insertions(+), 178 deletions(-) > create mode 100644 include/linux/irqchip/chained_irq.h ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 0/4] Preparatory GIC patches for arm64 support 2013-01-31 10:30 ` [PATCH v2 0/4] Preparatory GIC patches for arm64 support Catalin Marinas @ 2013-01-31 11:47 ` Russell King - ARM Linux 2013-01-31 12:32 ` Catalin Marinas 0 siblings, 1 reply; 19+ messages in thread From: Russell King - ARM Linux @ 2013-01-31 11:47 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 31, 2013 at 10:30:44AM +0000, Catalin Marinas wrote: > Olof, Arnd, > > On Tue, Jan 29, 2013 at 04:18:35PM +0000, Catalin Marinas wrote: > > That's the second version of the GIC clean-up patches to support arm64. > > The only change from v1 is that the second patch (chained_irq.h) also > > covers drivers/gpio and drivers/pinctrl (#include change). > > Are you ok to merge this series via the arm-soc tree for 3.9-rc1? There > are no complaints so far (only acks ;). This would allow me to push GIC > support for arm64. So I don't exist anymore to you? Catalin, it's already been suggested to you that this series is more core ARM stuff than SoC stuff, and it's also been suggested that you merge this through my tree. No, I guess this figures after all your excessively negative replies on all of my comments during the review of ARM64. ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 0/4] Preparatory GIC patches for arm64 support 2013-01-31 11:47 ` Russell King - ARM Linux @ 2013-01-31 12:32 ` Catalin Marinas 0 siblings, 0 replies; 19+ messages in thread From: Catalin Marinas @ 2013-01-31 12:32 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 31, 2013 at 11:47:04AM +0000, Russell King - ARM Linux wrote: > On Thu, Jan 31, 2013 at 10:30:44AM +0000, Catalin Marinas wrote: > > On Tue, Jan 29, 2013 at 04:18:35PM +0000, Catalin Marinas wrote: > > > That's the second version of the GIC clean-up patches to support arm64. > > > The only change from v1 is that the second patch (chained_irq.h) also > > > covers drivers/gpio and drivers/pinctrl (#include change). > > > > Are you ok to merge this series via the arm-soc tree for 3.9-rc1? There > > are no complaints so far (only acks ;). This would allow me to push GIC > > support for arm64. > > So I don't exist anymore to you? You do ;) and you've been cc'ed on these patches. Just wasn't sure you care about patches that have 'arm64' in the cover email ;). Since Rob's series went through the arm-soc, I consider that further changes should go the same route as there is a dependency and I'd like to get them merged sooner. These patches touch primarily SoC code, apart from some trivial code moving and the CPU notifier in irq-gic.c (you are the original author of this driver) and I'm ok if you want to merge it. I really don't mind if you or Olof merge the whole series as long as it gets upstream at some point. As you expressed an opinion on these patches and you want to merge them, they'll have to wait until after 3.9-rc1 for Rob's patches to get in. > Catalin, it's already been suggested to you that this series is more > core ARM stuff than SoC stuff, and it's also been suggested that you > merge this through my tree. No, it hasn't. Just Nico saying that he'd prefer *his* series was merged by RMK (and I agree). A way to sort the dependency issue for Nico is to at least push some of this series in 3.9-rc1. Otherwise we just postpone the dependency issue. > No, I guess this figures after all your excessively negative replies > on all of my comments during the review of ARM64. It's all relative - negative reply to negative reply would make it positive ;). -- Catalin ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2013-02-01 17:39 UTC | newest] Thread overview: 19+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-01-29 16:18 [PATCH v2 0/4] Preparatory GIC patches for arm64 support Catalin Marinas 2013-01-29 16:18 ` [PATCH v2 1/4] arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h Catalin Marinas 2013-01-29 16:18 ` [PATCH v2 2/4] arm: Move chained_irq_(enter|exit) to a generic file Catalin Marinas 2013-01-29 16:18 ` [PATCH v2 3/4] irqchip: gic: Call handle_bad_irq() directly Catalin Marinas 2013-01-29 16:18 ` [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier Catalin Marinas 2013-01-29 22:35 ` Nicolas Pitre 2013-01-29 23:12 ` Catalin Marinas 2013-01-30 0:11 ` Nicolas Pitre 2013-01-31 11:25 ` Russell King - ARM Linux 2013-01-31 11:49 ` Catalin Marinas 2013-01-31 17:32 ` Nicolas Pitre 2013-01-31 17:55 ` Russell King - ARM Linux 2013-01-31 20:31 ` Nicolas Pitre 2013-02-01 14:38 ` Jon Medhurst (Tixy) 2013-02-01 17:39 ` Nicolas Pitre 2013-01-30 0:31 ` Dinh Nguyen 2013-01-31 10:30 ` [PATCH v2 0/4] Preparatory GIC patches for arm64 support Catalin Marinas 2013-01-31 11:47 ` Russell King - ARM Linux 2013-01-31 12:32 ` Catalin Marinas
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