* [PATCH 01/04] ARM: shmobile: Initial r8a73a4 SoC support V2
2013-03-18 14:32 [PATCH 00/04] ARM: shmobile: r8a73a4 SoC support V2 Magnus Damm
@ 2013-03-18 14:32 ` Magnus Damm
2013-03-18 14:32 ` [PATCH 02/04] ARM: shmobile: r8a73a4 SCIF " Magnus Damm
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Magnus Damm @ 2013-03-18 14:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Add initial support for the r8a73a4 SoC including:
- Single Cortex-A15 CPU Core
- GIC
- Architecture timer
No static virtual mappings are used, all the components
make use of ioremap(). DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
Changes since V1:
- Best-effort sort of headers
- Removed r8a73a4_devices[] and platform_add_devices()
- Let r8a73a4_clock_init() be called directly by board code
arch/arm/boot/dts/r8a73a4.dtsi | 55 +++++++++++++++
arch/arm/mach-shmobile/Kconfig | 7 +
arch/arm/mach-shmobile/Makefile | 1
arch/arm/mach-shmobile/clock-r8a73a4.c | 89 +++++++++++++++++++++++++
arch/arm/mach-shmobile/include/mach/r8a73a4.h | 7 +
arch/arm/mach-shmobile/setup-r8a73a4.c | 50 ++++++++++++++
6 files changed, 209 insertions(+)
--- /dev/null
+++ work/arch/arm/boot/dts/r8a73a4.dtsi 2013-03-18 18:34:16.000000000 +0900
@@ -0,0 +1,55 @@
+/*
+ * Device Tree Source for the r8a73a4 SoC
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Magnus Damm
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "renesas,r8a73a4";
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1500000000>;
+ };
+ };
+
+ gic: interrupt-controller at f1001000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xf1001000 0x1000>,
+ <0xf1002000 0x1000>,
+ <0xf1004000 0x2000>,
+ <0xf1006000 0x2000>;
+ interrupts = <1 9 0xf04>;
+
+ gic-cpuif at 4 {
+ compatible = "arm,gic-cpuif";
+ cpuif-id = <4>;
+ cpu = <&cpu0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+};
--- 0001/arch/arm/mach-shmobile/Kconfig
+++ work/arch/arm/mach-shmobile/Kconfig 2013-03-18 18:34:15.000000000 +0900
@@ -18,6 +18,13 @@ config ARCH_SH73A0
select SH_CLK_CPG
select RENESAS_INTC_IRQPIN
+config ARCH_R8A73A4
+ bool "R-Mobile APE6 (R8A73A40)"
+ select ARM_GIC
+ select CPU_V7
+ select ARM_ARCH_TIMER
+ select SH_CLK_CPG
+
config ARCH_R8A7740
bool "R-Mobile A1 (R8A77400)"
select ARCH_WANT_OPTIONAL_GPIOLIB
--- 0001/arch/arm/mach-shmobile/Makefile
+++ work/arch/arm/mach-shmobile/Makefile 2013-03-18 18:34:15.000000000 +0900
@@ -8,6 +8,7 @@ obj-y := timer.o console.o clock.o
# CPU objects
obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
+obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o
obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
--- /dev/null
+++ work/arch/arm/mach-shmobile/clock-r8a73a4.c 2013-03-18 18:34:16.000000000 +0900
@@ -0,0 +1,89 @@
+/*
+ * r8a73a4 clock framework support
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+
+#define CPG_BASE 0xe6150000
+#define CPG_LEN 0x270
+
+#define MPCKCR 0xe6150080
+
+static struct clk_mapping cpg_mapping = {
+ .phys = CPG_BASE,
+ .len = CPG_LEN,
+};
+
+static struct clk extalr_clk = {
+ .rate = 32768,
+};
+
+static struct clk extal1_clk = {
+ .rate = 26000000,
+};
+
+static struct clk extal2_clk = {
+ .rate = 48000000,
+ .mapping = &cpg_mapping,
+};
+
+static struct clk *main_clks[] = {
+ &extalr_clk,
+ &extal1_clk,
+ &extal2_clk,
+};
+
+enum { MSTP_NR };
+static struct clk mstp_clks[MSTP_NR] = {
+};
+
+static struct clk_lookup lookups[] = {
+};
+
+void __init r8a73a4_clock_init(void)
+{
+ void __iomem *cpg_base, *reg;
+ int k, ret = 0;
+
+ /* fix MPCLK to EXTAL2 for now.
+ * this is needed until more detailed clock topology is supported
+ */
+ cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
+ BUG_ON(!cpg_base);
+ reg = cpg_base + (MPCKCR - CPG_BASE);
+ iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
+ iounmap(cpg_base);
+
+ for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+ ret = clk_register(main_clks[k]);
+
+ if (!ret)
+ ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
+
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+ if (!ret)
+ shmobile_clk_init();
+ else
+ panic("failed to setup r8a73a4 clocks\n");
+}
--- /dev/null
+++ work/arch/arm/mach-shmobile/include/mach/r8a73a4.h 2013-03-18 18:34:16.000000000 +0900
@@ -0,0 +1,7 @@
+#ifndef __ASM_R8A73A4_H__
+#define __ASM_R8A73A4_H__
+
+void r8a73a4_add_standard_devices(void);
+void r8a73a4_clock_init(void);
+
+#endif /* __ASM_R8A73A4_H__ */
--- /dev/null
+++ work/arch/arm/mach-shmobile/setup-r8a73a4.c 2013-03-18 21:41:35.000000000 +0900
@@ -0,0 +1,50 @@
+/*
+ * r8a73a4 processor support
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/r8a73a4.h>
+#include <asm/mach/arch.h>
+
+void __init r8a73a4_add_standard_devices(void)
+{
+}
+
+#ifdef CONFIG_USE_OF
+void __init r8a73a4_add_standard_devices_dt(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *r8a73a4_boards_compat_dt[] __initdata = {
+ "renesas,r8a73a4",
+ NULL,
+};
+
+DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
+ .init_irq = irqchip_init,
+ .init_machine = r8a73a4_add_standard_devices_dt,
+ .init_time = shmobile_timer_init,
+ .dt_compat = r8a73a4_boards_compat_dt,
+MACHINE_END
+#endif /* CONFIG_USE_OF */
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 02/04] ARM: shmobile: r8a73a4 SCIF support V2
2013-03-18 14:32 [PATCH 00/04] ARM: shmobile: r8a73a4 SoC support V2 Magnus Damm
2013-03-18 14:32 ` [PATCH 01/04] ARM: shmobile: Initial " Magnus Damm
@ 2013-03-18 14:32 ` Magnus Damm
2013-03-18 14:32 ` [PATCH 03/04] ARM: shmobile: r8a73a4 IRQC " Magnus Damm
2013-03-18 14:32 ` [PATCH 04/04] ARM: shmobile: r8a73a4 PFC support Magnus Damm
3 siblings, 0 replies; 8+ messages in thread
From: Magnus Damm @ 2013-03-18 14:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Add SCIF serial port support to the r8a73a4 SoC by
adding platform devices for SCIFA0 -> SCIFA1 as well
as SCIFB0 -> SCIFB3 together with clock bindings. DT
device description is excluded at this point since
such bindings are still under development.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
Changes since V1:
- Replaced static platform devices with array of platform data
together with a call to platform_device_register_data()
This version is about 70 lines smaller than V1.
arch/arm/mach-shmobile/clock-r8a73a4.c | 15 ++++++++++-
arch/arm/mach-shmobile/setup-r8a73a4.c | 43 ++++++++++++++++++++++++++++++++
2 files changed, 57 insertions(+), 1 deletion(-)
--- 0003/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ work/arch/arm/mach-shmobile/clock-r8a73a4.c 2013-03-18 21:42:19.000000000 +0900
@@ -28,6 +28,7 @@
#define CPG_LEN 0x270
#define MPCKCR 0xe6150080
+#define SMSTPCR2 0xe6150138
static struct clk_mapping cpg_mapping = {
.phys = CPG_BASE,
@@ -53,11 +54,23 @@ static struct clk *main_clks[] = {
&extal2_clk,
};
-enum { MSTP_NR };
+enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
+ [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
+ [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
+ [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
+ [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
+ [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
+ [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
};
static struct clk_lookup lookups[] = {
+ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
+ CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
+ CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
+ CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
+ CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
+ CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
};
void __init r8a73a4_clock_init(void)
--- 0003/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ work/arch/arm/mach-shmobile/setup-r8a73a4.c 2013-03-18 21:43:19.000000000 +0900
@@ -21,13 +21,56 @@
#include <linux/irqchip.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
+#include <linux/serial_sci.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a73a4.h>
#include <asm/mach/arch.h>
+#define SCIF_COMMON(scif_type, baseaddr, irq) \
+ .type = PORT_SCIFA, \
+ .mapbase = baseaddr, \
+ .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
+ .scbrr_algo_id = SCBRR_ALGO_4, \
+ .irqs = SCIx_IRQ_MUXED(irq)
+
+#define SCIFA_DATA(index, baseaddr, irq) \
+[index] = { \
+ SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
+ .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
+}
+
+#define SCIFB_DATA(index, baseaddr, irq) \
+[index] = { \
+ SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
+ .scscr = SCSCR_RE | SCSCR_TE, \
+}
+
+enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
+
+static const struct plat_sci_port scif[] = {
+ SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
+ SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
+ SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
+ SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
+ SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
+ SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
+};
+
+static inline void r8a73a4_register_scif(int idx)
+{
+ platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
+ sizeof(struct plat_sci_port));
+}
+
void __init r8a73a4_add_standard_devices(void)
{
+ r8a73a4_register_scif(SCIFA0);
+ r8a73a4_register_scif(SCIFA1);
+ r8a73a4_register_scif(SCIFB0);
+ r8a73a4_register_scif(SCIFB1);
+ r8a73a4_register_scif(SCIFB2);
+ r8a73a4_register_scif(SCIFB3);
}
#ifdef CONFIG_USE_OF
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 03/04] ARM: shmobile: r8a73a4 IRQC support V2
2013-03-18 14:32 [PATCH 00/04] ARM: shmobile: r8a73a4 SoC support V2 Magnus Damm
2013-03-18 14:32 ` [PATCH 01/04] ARM: shmobile: Initial " Magnus Damm
2013-03-18 14:32 ` [PATCH 02/04] ARM: shmobile: r8a73a4 SCIF " Magnus Damm
@ 2013-03-18 14:32 ` Magnus Damm
2013-03-18 14:32 ` Arnd Bergmann
2013-03-18 14:32 ` [PATCH 04/04] ARM: shmobile: r8a73a4 PFC support Magnus Damm
3 siblings, 1 reply; 8+ messages in thread
From: Magnus Damm @ 2013-03-18 14:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Add IRQC interrupt controller support to r8a73a4 by
hooking up two IRQC instances to handle 58 external
IRQ signals. There IRQC controllers are tied to SPIs
of the GIC. On r8a73a4 exact IRQ pin routing is handled
by the PFC which is excluded from this patch.
Both platform devices and DT devices are added in this
patch. The platform device versions are used to provide
a static interrupt map configuration for board code
written in C.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
Change since V1:
- Use platform_device_register_resndata() instead of static platform device
Depends on:
[PATCH] irqchip: Renesas IRQC driver
[PATCH] irqchip: irqc: Add DT support
arch/arm/boot/dts/r8a73a4.dtsi | 32 ++++++++++++
arch/arm/mach-shmobile/Kconfig | 1
arch/arm/mach-shmobile/setup-r8a73a4.c | 84 ++++++++++++++++++++++++++++++++
3 files changed, 117 insertions(+)
--- 0003/arch/arm/boot/dts/r8a73a4.dtsi
+++ work/arch/arm/boot/dts/r8a73a4.dtsi 2013-03-18 21:28:49.000000000 +0900
@@ -52,4 +52,36 @@
<1 11 0xf08>,
<1 10 0xf08>;
};
+
+ irqc0: interrupt-controller at e61c0000 {
+ compatible = "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xe61c0000 0x200>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>,
+ <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>,
+ <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>,
+ <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>,
+ <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>,
+ <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>,
+ <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>,
+ <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>;
+ };
+
+ irqc1: interrupt-controller at e61c0200 {
+ compatible = "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xe61c0200 0x200>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>,
+ <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>,
+ <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>,
+ <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>,
+ <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>,
+ <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>,
+ <0 56 4>, <0 57 4>;
+ };
+
};
--- 0003/arch/arm/mach-shmobile/Kconfig
+++ work/arch/arm/mach-shmobile/Kconfig 2013-03-18 21:28:49.000000000 +0900
@@ -24,6 +24,7 @@ config ARCH_R8A73A4
select CPU_V7
select ARM_ARCH_TIMER
select SH_CLK_CPG
+ select RENESAS_IRQC
config ARCH_R8A7740
bool "R-Mobile A1 (R8A77400)"
--- 0004/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ work/arch/arm/mach-shmobile/setup-r8a73a4.c 2013-03-18 21:29:11.000000000 +0900
@@ -21,6 +21,7 @@
#include <linux/irqchip.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
+#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
#include <mach/common.h>
#include <mach/irqs.h>
@@ -63,6 +64,87 @@ static inline void r8a73a4_register_scif
sizeof(struct plat_sci_port));
}
+static const struct renesas_irqc_config irqc0_data = {
+ .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
+};
+
+static const struct resource irqc0_resources[] = {
+ DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
+ DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
+ DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
+ DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
+ DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
+ DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
+ DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
+ DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
+ DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
+ DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
+ DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
+ DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
+ DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
+ DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
+ DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
+ DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
+ DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
+ DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
+ DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
+ DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
+ DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
+ DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
+ DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
+ DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
+ DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
+ DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
+ DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
+ DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
+ DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
+ DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
+ DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
+ DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
+ DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
+};
+
+static const struct renesas_irqc_config irqc1_data = {
+ .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
+};
+
+static const struct resource irqc1_resources[] = {
+ DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
+ DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
+ DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
+ DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
+ DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
+ DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
+ DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
+ DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
+ DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
+ DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
+ DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
+ DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
+ DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
+ DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
+ DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
+ DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
+ DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
+ DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
+ DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
+ DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
+ DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
+ DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
+ DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
+ DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
+ DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
+ DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
+ DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
+};
+
+#define r8a73a4_register_irqc(idx) \
+ platform_device_register_resndata(&platform_bus, "renesas_irqc", \
+ idx, irqc##idx##_resources, \
+ ARRAY_SIZE(irqc##idx##_resources), \
+ &irqc##idx##_data, \
+ sizeof(struct renesas_irqc_config))
+
void __init r8a73a4_add_standard_devices(void)
{
r8a73a4_clock_init();
@@ -73,6 +155,8 @@ void __init r8a73a4_add_standard_devices
r8a73a4_register_scif(SCIFB1);
r8a73a4_register_scif(SCIFB2);
r8a73a4_register_scif(SCIFB3);
+ r8a73a4_register_irqc(0);
+ r8a73a4_register_irqc(1);
}
#ifdef CONFIG_USE_OF
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 03/04] ARM: shmobile: r8a73a4 IRQC support V2
2013-03-18 14:32 ` [PATCH 03/04] ARM: shmobile: r8a73a4 IRQC " Magnus Damm
@ 2013-03-18 14:32 ` Arnd Bergmann
2013-03-19 3:00 ` Magnus Damm
0 siblings, 1 reply; 8+ messages in thread
From: Arnd Bergmann @ 2013-03-18 14:32 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 18 March 2013, Magnus Damm wrote:
> Both platform devices and DT devices are added in this
> patch. The platform device versions are used to provide
> a static interrupt map configuration for board code
> written in C.
I had not noticed this part with the first version. Why is this required?
I thought you would always have the DTS in there, so that can be used to
provide the resources even for static platform devices.
Arnd
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 03/04] ARM: shmobile: r8a73a4 IRQC support V2
2013-03-18 14:32 ` Arnd Bergmann
@ 2013-03-19 3:00 ` Magnus Damm
0 siblings, 0 replies; 8+ messages in thread
From: Magnus Damm @ 2013-03-19 3:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd,
On Mon, Mar 18, 2013 at 11:32 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Monday 18 March 2013, Magnus Damm wrote:
>> Both platform devices and DT devices are added in this
>> patch. The platform device versions are used to provide
>> a static interrupt map configuration for board code
>> written in C.
>
> I had not noticed this part with the first version. Why is this required?
> I thought you would always have the DTS in there, so that can be used to
> provide the resources even for static platform devices.
Right now there is an intentional difference between the "C" version
of the board code and the DT-only version:
The "C" version of board code relies on DTS for architected timer and
GIC. Besides that, platform devices are used. Other devices in DTS are
not used at this point.
The DT version (DT_MACHINE_START in setup-r8a73a4.c) is using DTS only.
Would you like me to change to "C" version of the code to use DTS to
describe more devices?
Thanks,
/ magnus
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 04/04] ARM: shmobile: r8a73a4 PFC support
2013-03-18 14:32 [PATCH 00/04] ARM: shmobile: r8a73a4 SoC support V2 Magnus Damm
` (2 preceding siblings ...)
2013-03-18 14:32 ` [PATCH 03/04] ARM: shmobile: r8a73a4 IRQC " Magnus Damm
@ 2013-03-18 14:32 ` Magnus Damm
3 siblings, 0 replies; 8+ messages in thread
From: Magnus Damm @ 2013-03-18 14:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Add a platform device for the r8a73a4 PFC.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
No build time dependency, but requires PFC tables
in separate patch series to actually do something.
arch/arm/mach-shmobile/Kconfig | 1 +
arch/arm/mach-shmobile/include/mach/r8a73a4.h | 1 +
arch/arm/mach-shmobile/setup-r8a73a4.c | 10 ++++++++++
3 files changed, 12 insertions(+)
--- 0005/arch/arm/mach-shmobile/Kconfig
+++ work/arch/arm/mach-shmobile/Kconfig 2013-03-18 18:51:13.000000000 +0900
@@ -20,6 +20,7 @@ config ARCH_SH73A0
config ARCH_R8A73A4
bool "R-Mobile APE6 (R8A73A40)"
+ select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select CPU_V7
select ARM_ARCH_TIMER
--- 0003/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ work/arch/arm/mach-shmobile/include/mach/r8a73a4.h 2013-03-18 18:51:13.000000000 +0900
@@ -3,5 +3,6 @@
void r8a73a4_add_standard_devices(void);
void r8a73a4_clock_init(void);
+void r8a73a4_pinmux_init(void);
#endif /* __ASM_R8A73A4_H__ */
--- 0005/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ work/arch/arm/mach-shmobile/setup-r8a73a4.c 2013-03-18 18:53:50.000000000 +0900
@@ -28,6 +28,16 @@
#include <mach/r8a73a4.h>
#include <asm/mach/arch.h>
+static const struct resource pfc_resources[] = {
+ DEFINE_RES_MEM(0xe6050000, 0x9000),
+};
+
+void __init r8a73a4_pinmux_init(void)
+{
+ platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
+ ARRAY_SIZE(pfc_resources));
+}
+
#define SCIF_COMMON(scif_type, baseaddr, irq) \
.type = PORT_SCIFA, \
.mapbase = baseaddr, \
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 03/04] ARM: shmobile: r8a73a4 IRQC support V2
2013-03-26 1:34 [PATCH 00/04] ARM: shmobile: r8a73a4 SoC support V3 Magnus Damm
@ 2013-03-26 1:34 ` Magnus Damm
0 siblings, 0 replies; 8+ messages in thread
From: Magnus Damm @ 2013-03-26 1:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
Add IRQC interrupt controller support to r8a73a4 by
hooking up two IRQC instances to handle 58 external
IRQ signals. There IRQC controllers are tied to SPIs
of the GIC. On r8a73a4 exact IRQ pin routing is handled
by the PFC which is excluded from this patch.
Both platform devices and DT devices are added in this
patch. The platform device versions are used to provide
a static interrupt map configuration for board code
written in C.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
Change since V1:
- Use platform_device_register_resndata() instead of static platform device
Depends on:
[PATCH] irqchip: Renesas IRQC driver
[PATCH] irqchip: irqc: Add DT support
arch/arm/boot/dts/r8a73a4.dtsi | 32 ++++++++++++
arch/arm/mach-shmobile/Kconfig | 1
arch/arm/mach-shmobile/setup-r8a73a4.c | 84 ++++++++++++++++++++++++++++++++
3 files changed, 117 insertions(+)
--- 0003/arch/arm/boot/dts/r8a73a4.dtsi
+++ work/arch/arm/boot/dts/r8a73a4.dtsi 2013-03-18 21:28:49.000000000 +0900
@@ -52,4 +52,36 @@
<1 11 0xf08>,
<1 10 0xf08>;
};
+
+ irqc0: interrupt-controller at e61c0000 {
+ compatible = "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xe61c0000 0x200>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>,
+ <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>,
+ <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>,
+ <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>,
+ <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>,
+ <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>,
+ <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>,
+ <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>;
+ };
+
+ irqc1: interrupt-controller at e61c0200 {
+ compatible = "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xe61c0200 0x200>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>,
+ <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>,
+ <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>,
+ <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>,
+ <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>,
+ <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>,
+ <0 56 4>, <0 57 4>;
+ };
+
};
--- 0003/arch/arm/mach-shmobile/Kconfig
+++ work/arch/arm/mach-shmobile/Kconfig 2013-03-18 21:28:49.000000000 +0900
@@ -24,6 +24,7 @@ config ARCH_R8A73A4
select CPU_V7
select ARM_ARCH_TIMER
select SH_CLK_CPG
+ select RENESAS_IRQC
config ARCH_R8A7740
bool "R-Mobile A1 (R8A77400)"
--- 0004/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ work/arch/arm/mach-shmobile/setup-r8a73a4.c 2013-03-18 21:29:11.000000000 +0900
@@ -21,6 +21,7 @@
#include <linux/irqchip.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
+#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
#include <mach/common.h>
#include <mach/irqs.h>
@@ -63,6 +64,87 @@ static inline void r8a73a4_register_scif
sizeof(struct plat_sci_port));
}
+static const struct renesas_irqc_config irqc0_data = {
+ .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
+};
+
+static const struct resource irqc0_resources[] = {
+ DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
+ DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
+ DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
+ DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
+ DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
+ DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
+ DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
+ DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
+ DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
+ DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
+ DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
+ DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
+ DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
+ DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
+ DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
+ DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
+ DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
+ DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
+ DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
+ DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
+ DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
+ DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
+ DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
+ DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
+ DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
+ DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
+ DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
+ DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
+ DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
+ DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
+ DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
+ DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
+ DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
+};
+
+static const struct renesas_irqc_config irqc1_data = {
+ .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
+};
+
+static const struct resource irqc1_resources[] = {
+ DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
+ DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
+ DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
+ DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
+ DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
+ DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
+ DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
+ DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
+ DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
+ DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
+ DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
+ DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
+ DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
+ DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
+ DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
+ DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
+ DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
+ DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
+ DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
+ DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
+ DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
+ DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
+ DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
+ DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
+ DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
+ DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
+ DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
+};
+
+#define r8a73a4_register_irqc(idx) \
+ platform_device_register_resndata(&platform_bus, "renesas_irqc", \
+ idx, irqc##idx##_resources, \
+ ARRAY_SIZE(irqc##idx##_resources), \
+ &irqc##idx##_data, \
+ sizeof(struct renesas_irqc_config))
+
void __init r8a73a4_add_standard_devices(void)
{
r8a73a4_clock_init();
@@ -73,6 +155,8 @@ void __init r8a73a4_add_standard_devices
r8a73a4_register_scif(SCIFB1);
r8a73a4_register_scif(SCIFB2);
r8a73a4_register_scif(SCIFB3);
+ r8a73a4_register_irqc(0);
+ r8a73a4_register_irqc(1);
}
#ifdef CONFIG_USE_OF
^ permalink raw reply [flat|nested] 8+ messages in thread