* [PATCH 001/142] sh-pfc: Declare operation structures as const
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
@ 2013-03-18 11:04 ` Simon Horman
2013-03-18 11:04 ` [PATCH 002/142] sh-pfc: Don't define the per-device pinctrl struct instances as global Simon Horman
` (140 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:04 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The pinconf, pinctrl and pinmux operation structures hold function
pointers that are never modified. Declare them as const.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 11e0e13..887930e 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -70,7 +70,7 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
seq_printf(s, "%s", DRV_NAME);
}
-static struct pinctrl_ops sh_pfc_pinctrl_ops = {
+static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
.get_groups_count = sh_pfc_get_groups_count,
.get_group_name = sh_pfc_get_group_name,
.get_group_pins = sh_pfc_get_group_pins,
@@ -252,7 +252,7 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
}
-static struct pinmux_ops sh_pfc_pinmux_ops = {
+static const struct pinmux_ops sh_pfc_pinmux_ops = {
.get_functions_count = sh_pfc_get_functions_count,
.get_function_name = sh_pfc_get_function_name,
.get_function_groups = sh_pfc_get_function_groups,
@@ -308,7 +308,7 @@ static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
seq_printf(s, " %s", pinmux_type_str[config]);
}
-static struct pinconf_ops sh_pfc_pinconf_ops = {
+static const struct pinconf_ops sh_pfc_pinconf_ops = {
.pin_config_get = sh_pfc_pinconf_get,
.pin_config_set = sh_pfc_pinconf_set,
.pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 002/142] sh-pfc: Don't define the per-device pinctrl struct instances as global
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
2013-03-18 11:04 ` [PATCH 001/142] sh-pfc: Declare operation structures as const Simon Horman
@ 2013-03-18 11:04 ` Simon Horman
2013-03-18 11:04 ` [PATCH 003/142] sh-pfc: Fix a typo and simplify a definition on sh73a0 Simon Horman
` (139 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:04 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The pinctrl_desc and pinctrl_gpio_range structures registered with the
pinctrl core are per-device instances. Move them to the dynamically
allocated sh_pfc_pinctrl structure and initialize them at runtime.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 40 +++++++++++++++++---------------------
1 file changed, 18 insertions(+), 22 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 887930e..d113746 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -27,6 +27,9 @@
struct sh_pfc_pinctrl {
struct pinctrl_dev *pctl;
+ struct pinctrl_desc pctl_desc;
+ struct pinctrl_gpio_range range;
+
struct sh_pfc *pfc;
struct pinmux_gpio **functions;
@@ -314,19 +317,6 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = {
.pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
};
-static struct pinctrl_gpio_range sh_pfc_gpio_range = {
- .name = DRV_NAME,
- .id = 0,
-};
-
-static struct pinctrl_desc sh_pfc_pinctrl_desc = {
- .name = DRV_NAME,
- .owner = THIS_MODULE,
- .pctlops = &sh_pfc_pinctrl_ops,
- .pmxops = &sh_pfc_pinmux_ops,
- .confops = &sh_pfc_pinconf_ops,
-};
-
static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx,
struct pinmux_gpio *gpio, unsigned offset)
{
@@ -386,9 +376,6 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
spin_unlock_irqrestore(&pfc->lock, flags);
- sh_pfc_pinctrl_desc.pins = pmx->pads;
- sh_pfc_pinctrl_desc.npins = pmx->nr_pads;
-
return 0;
}
@@ -438,16 +425,25 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
if (unlikely(ret != 0))
return ret;
- pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, pfc->dev, pmx);
+ pmx->pctl_desc.name = DRV_NAME;
+ pmx->pctl_desc.owner = THIS_MODULE;
+ pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
+ pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
+ pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
+ pmx->pctl_desc.pins = pmx->pads;
+ pmx->pctl_desc.npins = pmx->nr_pads;
+
+ pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
if (IS_ERR(pmx->pctl))
return PTR_ERR(pmx->pctl);
- sh_pfc_gpio_range.npins = pfc->info->last_gpio
- - pfc->info->first_gpio + 1;
- sh_pfc_gpio_range.base = pfc->info->first_gpio;
- sh_pfc_gpio_range.pin_base = pfc->info->first_gpio;
+ pmx->range.name = DRV_NAME,
+ pmx->range.id = 0;
+ pmx->range.npins = pfc->info->last_gpio - pfc->info->first_gpio + 1;
+ pmx->range.base = pfc->info->first_gpio;
+ pmx->range.pin_base = pfc->info->first_gpio;
- pinctrl_add_gpio_range(pmx->pctl, &sh_pfc_gpio_range);
+ pinctrl_add_gpio_range(pmx->pctl, &pmx->range);
return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 003/142] sh-pfc: Fix a typo and simplify a definition on sh73a0
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
2013-03-18 11:04 ` [PATCH 001/142] sh-pfc: Declare operation structures as const Simon Horman
2013-03-18 11:04 ` [PATCH 002/142] sh-pfc: Don't define the per-device pinctrl struct instances as global Simon Horman
@ 2013-03-18 11:04 ` Simon Horman
2013-03-18 11:05 ` [PATCH 004/142] sh-pfc: Drop the sh_pfc_pinctrl spinlock Simon Horman
` (138 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:04 UTC (permalink / raw)
To: linux-arm-kernel
From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Fix definition of the SDHIWP0 function and simplify the CPU_ALL_PORT
definition on sh73a0.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 709008e..232731b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -25,11 +25,7 @@
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \
- PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \
- PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \
- PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \
+ PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), \
PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
@@ -1502,7 +1498,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU),
PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU),
PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU),
- PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU),
+ PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT257_IN_PU),
PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU),
PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU),
PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 004/142] sh-pfc: Drop the sh_pfc_pinctrl spinlock
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (2 preceding siblings ...)
2013-03-18 11:04 ` [PATCH 003/142] sh-pfc: Fix a typo and simplify a definition on sh73a0 Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 005/142] sh-pfc: Don't take the sh_pfc spinlock in sh_pfc_map_gpios() Simon Horman
` (137 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The spinlock is used to protect data that is only accessed sequentially
during initialization. Remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index d113746..9bd0a83 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -37,8 +37,6 @@ struct sh_pfc_pinctrl {
struct pinctrl_pin_desc *pads;
unsigned int nr_pads;
-
- spinlock_t lock;
};
static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
@@ -321,7 +319,6 @@ static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx,
struct pinmux_gpio *gpio, unsigned offset)
{
struct pinmux_data_reg *dummy;
- unsigned long flags;
int bit;
gpio->flags &= ~PINMUX_FLAG_TYPE;
@@ -330,10 +327,7 @@ static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx,
gpio->flags |= PINMUX_TYPE_GPIO;
else {
gpio->flags |= PINMUX_TYPE_FUNCTION;
-
- spin_lock_irqsave(&pmx->lock, flags);
pmx->nr_functions++;
- spin_unlock_irqrestore(&pmx->lock, flags);
}
}
@@ -381,7 +375,6 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
- unsigned long flags;
int i, fn;
pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions *
@@ -389,8 +382,6 @@ static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
if (unlikely(!pmx->functions))
return -ENOMEM;
- spin_lock_irqsave(&pmx->lock, flags);
-
for (i = fn = 0; i < pmx->nr_pads; i++) {
struct pinmux_gpio *gpio = pfc->info->gpios + i;
@@ -398,8 +389,6 @@ static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
pmx->functions[fn++] = gpio;
}
- spin_unlock_irqrestore(&pmx->lock, flags);
-
return 0;
}
@@ -412,8 +401,6 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
if (unlikely(!pmx))
return -ENOMEM;
- spin_lock_init(&pmx->lock);
-
pmx->pfc = pfc;
pfc->pinctrl = pmx;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 005/142] sh-pfc: Don't take the sh_pfc spinlock in sh_pfc_map_gpios()
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (3 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 004/142] sh-pfc: Drop the sh_pfc_pinctrl spinlock Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 007/142] sh-pfc: Replace first_gpio and last_gpio with nr_gpios Simon Horman
` (136 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The sh_pfc_map_gpios() function is only called at initialization time
when no other task can access the sh_pfc fields. Don't protect the
operation with a spinlock.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 9bd0a83..4ce2753 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -334,7 +334,6 @@ static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx,
/* pinmux ranges -> pinctrl pin descs */
static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
- unsigned long flags;
int i;
pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1;
@@ -346,8 +345,6 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
return -ENOMEM;
}
- spin_lock_irqsave(&pfc->lock, flags);
-
/*
* We don't necessarily have a 1:1 mapping between pin and linux
* GPIO number, as the latter maps to the associated enum_id.
@@ -368,8 +365,6 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
}
- spin_unlock_irqrestore(&pfc->lock, flags);
-
return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 007/142] sh-pfc: Replace first_gpio and last_gpio with nr_gpios
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (4 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 005/142] sh-pfc: Don't take the sh_pfc spinlock in sh_pfc_map_gpios() Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 008/142] sh-pfc: Replace SoC info data and mark ranges with a number of pins Simon Horman
` (135 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The SoC information first_gpio field is always equal to 0, and the
last_gpio field is the index of the last entry in the pinmux_gpios
array. Replace the first_gpio and last_gpio fields by a nr_gpios field,
and initialize it to ARRAY_SIZE(pinmux_gpios).
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 2 +-
drivers/pinctrl/sh-pfc/gpio.c | 11 ++++-------
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7203.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7264.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7269.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7372.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7720.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7722.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7723.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7724.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7734.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7757.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7785.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-sh7786.c | 5 ++---
drivers/pinctrl/sh-pfc/pfc-shx3.c | 3 +--
drivers/pinctrl/sh-pfc/pinctrl.c | 16 +++++-----------
drivers/pinctrl/sh-pfc/sh_pfc.h | 4 ++--
20 files changed, 43 insertions(+), 68 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 970ddff..1b86a90 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -260,7 +260,7 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
struct pinmux_data_reg *drp;
int k;
- for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++)
+ for (k = 0; k < pfc->info->nr_gpios; k++)
sh_pfc_setup_data_reg(pfc, k);
k = 0;
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index a535075..f46f069 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -130,12 +130,10 @@ static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip)
gc->set = sh_gpio_set;
gc->to_irq = sh_gpio_to_irq;
- WARN_ON(pfc->info->first_gpio != 0); /* needs testing */
-
gc->label = pfc->info->name;
gc->owner = THIS_MODULE;
- gc->base = pfc->info->first_gpio;
- gc->ngpio = (pfc->info->last_gpio - pfc->info->first_gpio) + 1;
+ gc->base = 0;
+ gc->ngpio = pfc->info->nr_gpios;
}
int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
@@ -157,9 +155,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
pfc->gpio = chip;
- pr_info("%s handling gpio %d -> %d\n",
- pfc->info->name, pfc->info->first_gpio,
- pfc->info->last_gpio);
+ pr_info("%s handling gpio 0 -> %u\n",
+ pfc->info->name, pfc->info->nr_gpios - 1);
return 0;
}
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 214788c..c189a86 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2597,10 +2597,9 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = {
.function = { PINMUX_FUNCTION_BEGIN,
PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PORT0,
- .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 13feaa0..16ec97a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2612,10 +2612,9 @@ struct sh_pfc_soc_info r8a7779_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_SCK4_B,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index 22be49b..6cc6701 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -1580,10 +1580,9 @@ struct sh_pfc_soc_info sh7203_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PA7,
- .last_gpio = GPIO_FN_LCD_DATA0,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index ebe9c7c..c2ecc65 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -2119,10 +2119,9 @@ struct sh_pfc_soc_info sh7264_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PA3,
- .last_gpio = GPIO_FN_LCD_M_DISP,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index 87cb693..2013f4f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -2822,10 +2822,9 @@ struct sh_pfc_soc_info sh7269_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PA1,
- .last_gpio = GPIO_FN_LCD_M_DISP,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index d44e7f0..332cf34 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1643,10 +1643,9 @@ struct sh_pfc_soc_info sh7372_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PORT0,
- .last_gpio = GPIO_FN_SDENC_DV_CLKI,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 232731b..d5ee0f7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2779,10 +2779,9 @@ struct sh_pfc_soc_info sh73a0_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PORT0,
- .last_gpio = GPIO_FN_FSIAISLD_PU,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index e2e4520..8646237 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -1223,10 +1223,9 @@ struct sh_pfc_soc_info sh7720_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PTA7,
- .last_gpio = GPIO_FN_STATUS1,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index 225fa96..194ae3d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -1767,10 +1767,9 @@ struct sh_pfc_soc_info sh7722_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PTA7,
- .last_gpio = GPIO_FN_KEYOUT5_IN5,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index 49fd5c8..f31aa4f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -1891,10 +1891,9 @@ struct sh_pfc_soc_info sh7723_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PTA7,
- .last_gpio = GPIO_FN_IDEA0,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 054b700..64b69b7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -2213,10 +2213,9 @@ struct sh_pfc_soc_info sh7724_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PTA7,
- .last_gpio = GPIO_FN_INTC_IRQ0,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index 23d76d2..d67a572 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -2463,10 +2463,9 @@ struct sh_pfc_soc_info sh7734_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_ST_CLKOUT,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index ffbd8b7..7fc1310 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -2270,10 +2270,9 @@ struct sh_pfc_soc_info sh7757_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PTA0,
- .last_gpio = GPIO_FN_ON_DQ0,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index 2e9d7cb..4bde4b5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -1292,10 +1292,9 @@ struct sh_pfc_soc_info sh7785_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PA7,
- .last_gpio = GPIO_FN_IRQOUT,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index c9d8f50..9a42d25 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -825,10 +825,9 @@ struct sh_pfc_soc_info sh7786_pinmux_info = {
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PA7,
- .last_gpio = GPIO_FN_IRL4,
-
.gpios = pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index 04e8940..b23f5f9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -572,9 +572,8 @@ struct sh_pfc_soc_info shx3_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PA7,
- .last_gpio = GPIO_FN_STATUS0,
.gpios = shx3_pinmux_gpios,
+ .nr_gpios = ARRAY_SIZE(shx3_pinmux_gpios),
.gpio_data = shx3_pinmux_data,
.gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
.cfg_regs = shx3_pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 4ce2753..908b536 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -336,7 +336,7 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
int i;
- pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1;
+ pmx->nr_pads = pfc->info->nr_gpios;
pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads,
GFP_KERNEL);
@@ -345,17 +345,11 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
return -ENOMEM;
}
- /*
- * We don't necessarily have a 1:1 mapping between pin and linux
- * GPIO number, as the latter maps to the associated enum_id.
- * Care needs to be taken to translate back to pin space when
- * dealing with any pin configurations.
- */
for (i = 0; i < pmx->nr_pads; i++) {
struct pinctrl_pin_desc *pin = pmx->pads + i;
struct pinmux_gpio *gpio = pfc->info->gpios + i;
- pin->number = pfc->info->first_gpio + i;
+ pin->number = i;
pin->name = gpio->name;
/* XXX */
@@ -421,9 +415,9 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
pmx->range.name = DRV_NAME,
pmx->range.id = 0;
- pmx->range.npins = pfc->info->last_gpio - pfc->info->first_gpio + 1;
- pmx->range.base = pfc->info->first_gpio;
- pmx->range.pin_base = pfc->info->first_gpio;
+ pmx->range.npins = pfc->info->nr_gpios;
+ pmx->range.base = 0;
+ pmx->range.pin_base = 0;
pinctrl_add_gpio_range(pmx->pctl, &pmx->range);
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 13049c4..67fe91b 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -99,9 +99,9 @@ struct sh_pfc_soc_info {
struct pinmux_range mark;
struct pinmux_range function;
- unsigned first_gpio, last_gpio;
-
struct pinmux_gpio *gpios;
+ unsigned int nr_gpios;
+
struct pinmux_cfg_reg *cfg_regs;
struct pinmux_data_reg *data_regs;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 008/142] sh-pfc: Replace SoC info data and mark ranges with a number of pins
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (5 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 007/142] sh-pfc: Replace first_gpio and last_gpio with nr_gpios Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 009/142] sh-pfc: Remove unused sh_pfc_soc_info reserved_id field Simon Horman
` (134 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The data and mark ranges are only used to check whether a GPIO
corresponds to a real pin or a function. As pins come first in the list
of GPIOs and in the platform-specific GPIO enumerations, we can replace
the data and mark ranges by a number of pins.
Add an nr_pins field to struct sh_pfc_soc_info to store the number of
pins implemented by the SoC, remove the data and mark range fields and
introduce sh_pfc_gpio_is_pin() and sh_pfc_gpio_is_function() functions
to replace range-based checks.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 27 +++++++++++++++++++--------
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 5 +----
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7203.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7264.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7269.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7372.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7720.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7722.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7723.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7724.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7734.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7757.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7785.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-sh7786.c | 3 +--
drivers/pinctrl/sh-pfc/pfc-shx3.c | 3 +--
drivers/pinctrl/sh-pfc/sh_pfc.h | 3 +--
18 files changed, 36 insertions(+), 44 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 1b86a90..e7ad0d9 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -89,6 +89,18 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
return 1;
}
+static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio)
+{
+ return (gpio < pfc->info->nr_pins) &&
+ (pfc->info->gpios[gpio].enum_id != 0);
+}
+
+static bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio)
+{
+ return (gpio >= pfc->info->nr_pins) && (gpio < pfc->info->nr_gpios) &&
+ (pfc->info->gpios[gpio].enum_id != 0);
+}
+
static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
unsigned long reg_width)
{
@@ -226,7 +238,7 @@ static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
struct pinmux_data_reg *data_reg;
int k, n;
- if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
+ if (!sh_pfc_gpio_is_pin(pfc, gpio))
return -1;
k = 0;
@@ -260,7 +272,7 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
struct pinmux_data_reg *drp;
int k;
- for (k = 0; k < pfc->info->nr_gpios; k++)
+ for (k = 0; k < pfc->info->nr_pins; k++)
sh_pfc_setup_data_reg(pfc, k);
k = 0;
@@ -282,7 +294,7 @@ int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
int k, n;
- if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
+ if (!sh_pfc_gpio_is_pin(pfc, gpio))
return -1;
k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
@@ -344,11 +356,10 @@ int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
pinmux_enum_t *data = pfc->info->gpio_data;
int k;
- if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) {
- if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) {
- pr_err("non data/mark enum_id for gpio %d\n", gpio);
- return -1;
- }
+ if (!sh_pfc_gpio_is_pin(pfc, gpio) &&
+ !sh_pfc_gpio_is_function(pfc, gpio)) {
+ pr_err("non data/mark enum_id for gpio %d\n", gpio);
+ return -1;
}
if (pos) {
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index c189a86..f1ef9f7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2582,8 +2582,6 @@ static struct pinmux_irq pinmux_irqs[] = {
struct sh_pfc_soc_info r8a7740_pinmux_info = {
.name = "r8a7740_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN,
- PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN,
PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
@@ -2592,12 +2590,11 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = {
PINMUX_INPUT_PULLDOWN_END },
.output = { PINMUX_OUTPUT_BEGIN,
PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN,
- PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN,
PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PORT211 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 16ec97a..c8018ce 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2606,13 +2606,12 @@ struct sh_pfc_soc_info r8a7779_pinmux_info = {
.unlock_reg = 0xfffc0000, /* PMMR */
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_GP_6_8 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index 6cc6701..07377e4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -1574,13 +1574,12 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7203_pinmux_info = {
.name = "sh7203_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PF0 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index c2ecc65..21b5899 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -2113,13 +2113,12 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7264_pinmux_info = {
.name = "sh7264_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PK0 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index 2013f4f..b722de1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -2816,13 +2816,12 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7269_pinmux_info = {
.name = "sh7269_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PJ0 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 332cf34..0c56f57 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1635,15 +1635,14 @@ static struct pinmux_irq pinmux_irqs[] = {
struct sh_pfc_soc_info sh7372_pinmux_info = {
.name = "sh7372_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PORT190 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index d5ee0f7..6573dba 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2771,15 +2771,14 @@ static struct pinmux_irq pinmux_irqs[] = {
struct sh_pfc_soc_info sh73a0_pinmux_info = {
.name = "sh73a0_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PORT309 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index 8646237..4877177 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -1216,14 +1216,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7720_pinmux_info = {
.name = "sh7720_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PTV0 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index 194ae3d..7cedac6 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -1759,15 +1759,14 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7722_pinmux_info = {
.name = "sh7722_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PTZ1 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index f31aa4f..160edf0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -1884,14 +1884,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7723_pinmux_info = {
.name = "sh7723_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PTZ0 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 64b69b7..269f33d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -2206,14 +2206,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7724_pinmux_info = {
.name = "sh7724_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PTZ0 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index d67a572..be5cca6 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -2457,13 +2457,12 @@ struct sh_pfc_soc_info sh7734_pinmux_info = {
.unlock_reg = 0xFFFC0000,
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_GP_5_11 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index 7fc1310..d95f5b8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -2263,14 +2263,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7757_pinmux_info = {
.name = "sh7757_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PTZ7 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index 4bde4b5..0d4c6de 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -1285,14 +1285,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7785_pinmux_info = {
.name = "sh7785_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PR0 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index 9a42d25..2981d0b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -818,14 +818,13 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7786_pinmux_info = {
.name = "sh7786_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = pinmux_gpios,
+ .nr_pins = GPIO_PJ0 + 1,
.nr_gpios = ARRAY_SIZE(pinmux_gpios),
.cfg_regs = pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index b23f5f9..e985099 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -565,14 +565,13 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
struct sh_pfc_soc_info shx3_pinmux_info = {
.name = "shx3_pfc",
.reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.gpios = shx3_pinmux_gpios,
+ .nr_pins = GPIO_PH0 + 1,
.nr_gpios = ARRAY_SIZE(shx3_pinmux_gpios),
.gpio_data = shx3_pinmux_data,
.gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 67fe91b..c50fb51 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -91,15 +91,14 @@ struct pinmux_range {
struct sh_pfc_soc_info {
char *name;
pinmux_enum_t reserved_id;
- struct pinmux_range data;
struct pinmux_range input;
struct pinmux_range input_pd;
struct pinmux_range input_pu;
struct pinmux_range output;
- struct pinmux_range mark;
struct pinmux_range function;
struct pinmux_gpio *gpios;
+ unsigned int nr_pins;
unsigned int nr_gpios;
struct pinmux_cfg_reg *cfg_regs;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 009/142] sh-pfc: Remove unused sh_pfc_soc_info reserved_id field
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (6 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 008/142] sh-pfc: Replace SoC info data and mark ranges with a number of pins Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 010/142] sh-pfc: Initialize pinmux_gpio flags statically Simon Horman
` (133 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The field is unused, remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 1 -
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7203.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7264.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7269.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7372.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7720.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7722.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7723.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7724.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7734.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7757.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7785.c | 1 -
drivers/pinctrl/sh-pfc/pfc-sh7786.c | 1 -
drivers/pinctrl/sh-pfc/pfc-shx3.c | 1 -
drivers/pinctrl/sh-pfc/sh_pfc.h | 1 -
17 files changed, 17 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index f1ef9f7..957502e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2581,7 +2581,6 @@ static struct pinmux_irq pinmux_irqs[] = {
struct sh_pfc_soc_info r8a7740_pinmux_info = {
.name = "r8a7740_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN,
PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index c8018ce..bd5a70d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2605,7 +2605,6 @@ struct sh_pfc_soc_info r8a7779_pinmux_info = {
.unlock_reg = 0xfffc0000, /* PMMR */
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index 07377e4..ee972f0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -1573,7 +1573,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7203_pinmux_info = {
.name = "sh7203_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index 21b5899..44066de 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -2112,7 +2112,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7264_pinmux_info = {
.name = "sh7264_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index b722de1..072c7d5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -2815,7 +2815,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7269_pinmux_info = {
.name = "sh7269_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 0c56f57..c112074 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1634,7 +1634,6 @@ static struct pinmux_irq pinmux_irqs[] = {
struct sh_pfc_soc_info sh7372_pinmux_info = {
.name = "sh7372_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 6573dba..e41aa21 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2770,7 +2770,6 @@ static struct pinmux_irq pinmux_irqs[] = {
struct sh_pfc_soc_info sh73a0_pinmux_info = {
.name = "sh73a0_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index 4877177..294b758 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -1215,7 +1215,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7720_pinmux_info = {
.name = "sh7720_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index 7cedac6..e7eadaf 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -1758,7 +1758,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7722_pinmux_info = {
.name = "sh7722_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index 160edf0..06b1d73 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -1883,7 +1883,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7723_pinmux_info = {
.name = "sh7723_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 269f33d..41160a3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -2205,7 +2205,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7724_pinmux_info = {
.name = "sh7724_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index be5cca6..df32e71 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -2456,7 +2456,6 @@ struct sh_pfc_soc_info sh7734_pinmux_info = {
.unlock_reg = 0xFFFC0000,
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index d95f5b8..dd32f34 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -2262,7 +2262,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7757_pinmux_info = {
.name = "sh7757_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index 0d4c6de..447bd92 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -1284,7 +1284,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7785_pinmux_info = {
.name = "sh7785_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index 2981d0b..dee3cfb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -817,7 +817,6 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
struct sh_pfc_soc_info sh7786_pinmux_info = {
.name = "sh7786_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index e985099..e59da79 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -564,7 +564,6 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
struct sh_pfc_soc_info shx3_pinmux_info = {
.name = "shx3_pfc",
- .reserved_id = PINMUX_RESERVED,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
PINMUX_INPUT_PULLUP_END },
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index c50fb51..2627a89 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -90,7 +90,6 @@ struct pinmux_range {
struct sh_pfc_soc_info {
char *name;
- pinmux_enum_t reserved_id;
struct pinmux_range input;
struct pinmux_range input_pd;
struct pinmux_range input_pu;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 010/142] sh-pfc: Initialize pinmux_gpio flags statically
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (7 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 009/142] sh-pfc: Remove unused sh_pfc_soc_info reserved_id field Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 011/142] sh-pfc: Make struct pinmux_gpio enum_id field const Simon Horman
` (132 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All function GPIO entries are initialized with the GPIO_FN macro that
expands to the PINMUX_GPIO macro, used to initialize real GPIOs. Create
a PINMUX_GPIO_FN macro that duplicates PINMUX_GPIO and sets flags to
PINMUX_TYPE_FUNCTION and use it in GPIO_FN, and make PINMUX_GPIO set
flags to PINMUX_TYPE_GPIO.
This removes the need to initialize GPIO flags at runtime and thus
simplifies the code, preparing for the GPIO and functions split.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 19 ++-----------------
drivers/pinctrl/sh-pfc/sh_pfc.h | 16 +++++++++++++---
2 files changed, 15 insertions(+), 20 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 908b536..682b3a6 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -315,22 +315,6 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = {
.pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
};
-static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx,
- struct pinmux_gpio *gpio, unsigned offset)
-{
- struct pinmux_data_reg *dummy;
- int bit;
-
- gpio->flags &= ~PINMUX_FLAG_TYPE;
-
- if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0)
- gpio->flags |= PINMUX_TYPE_GPIO;
- else {
- gpio->flags |= PINMUX_TYPE_FUNCTION;
- pmx->nr_functions++;
- }
-}
-
/* pinmux ranges -> pinctrl pin descs */
static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
@@ -356,7 +340,8 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
if (unlikely(!gpio->enum_id))
continue;
- sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
+ if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
+ pmx->nr_functions++;
}
return 0;
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 2627a89..e150395 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -41,8 +41,18 @@ struct pinmux_gpio {
const char *name;
};
-#define PINMUX_GPIO(gpio, data_or_mark) \
- [gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE }
+#define PINMUX_GPIO(gpio, data_or_mark) \
+ [gpio] = { \
+ .name = __stringify(gpio), \
+ .enum_id = data_or_mark, \
+ .flags = PINMUX_TYPE_GPIO \
+ }
+#define PINMUX_GPIO_FN(gpio, data_or_mark) \
+ [gpio] = { \
+ .name = __stringify(gpio), \
+ .enum_id = data_or_mark, \
+ .flags = PINMUX_TYPE_FUNCTION \
+ }
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
@@ -135,7 +145,7 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
-#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
+#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, str##_MARK)
/* helper macro for pinmux_enum_t */
#define PORT_DATA_I(nr) \
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 011/142] sh-pfc: Make struct pinmux_gpio enum_id field const
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (8 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 010/142] sh-pfc: Initialize pinmux_gpio flags statically Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 012/142] sh-pfc: Shrink the pinctrl GPIO range to include real GPIOs only Simon Horman
` (131 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This ensures that the field is not modified, which is a prerequisite for
the rest of the PFC refactoring work.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/sh_pfc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index e150395..6ed7ab9 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -36,7 +36,7 @@ enum {
#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
struct pinmux_gpio {
- pinmux_enum_t enum_id;
+ const pinmux_enum_t enum_id;
pinmux_flag_t flags;
const char *name;
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 012/142] sh-pfc: Shrink the pinctrl GPIO range to include real GPIOs only
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (9 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 011/142] sh-pfc: Make struct pinmux_gpio enum_id field const Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 013/142] sh-pfc: Don't needlessly check GPIO type in sh_gpio_free() Simon Horman
` (130 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
As a step towards GPIO function removal, shorten the GPIO range
registered with the pinctrl core. Function GPIOs are now handled in the
GPIO handlers directly instead of going through the pinctrl API.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 2 +-
drivers/pinctrl/sh-pfc/core.h | 1 +
drivers/pinctrl/sh-pfc/gpio.c | 57 ++++++++++++++++++++++++++++++++++++--
drivers/pinctrl/sh-pfc/pinctrl.c | 27 ++----------------
4 files changed, 59 insertions(+), 28 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index e7ad0d9..bed2d23 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -95,7 +95,7 @@ static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio)
(pfc->info->gpios[gpio].enum_id != 0);
}
-static bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio)
+bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio)
{
return (gpio >= pfc->info->nr_pins) && (gpio < pfc->info->nr_gpios) &&
(pfc->info->gpios[gpio].enum_id != 0);
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index ba7c33c..dceaec0 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -47,6 +47,7 @@ void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
unsigned long value);
int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
struct pinmux_data_reg **drp, int *bitp);
+bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio);
int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
pinmux_enum_t *enum_idp);
int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index f46f069..80a50d8 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -38,12 +38,51 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
static int sh_gpio_request(struct gpio_chip *gc, unsigned offset)
{
- return pinctrl_request_gpio(offset);
+ struct sh_pfc *pfc = gpio_to_pfc(gc);
+ unsigned long flags;
+ int ret = -EINVAL;
+
+ if (offset < pfc->info->nr_pins)
+ return pinctrl_request_gpio(offset);
+
+ pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
+
+ spin_lock_irqsave(&pfc->lock, flags);
+
+ if (!sh_pfc_gpio_is_function(pfc, offset))
+ goto done;
+
+ if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION,
+ GPIO_CFG_DRYRUN))
+ goto done;
+
+ if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION,
+ GPIO_CFG_REQ))
+ goto done;
+
+ ret = 0;
+
+done:
+ spin_unlock_irqrestore(&pfc->lock, flags);
+ return ret;
}
static void sh_gpio_free(struct gpio_chip *gc, unsigned offset)
{
- pinctrl_free_gpio(offset);
+ struct sh_pfc *pfc = gpio_to_pfc(gc);
+ unsigned long flags;
+ int pinmux_type;
+
+ if (offset < pfc->info->nr_pins)
+ return pinctrl_free_gpio(offset);
+
+ spin_lock_irqsave(&pfc->lock, flags);
+
+ pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
+
+ sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
+
+ spin_unlock_irqrestore(&pfc->lock, flags);
}
static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value)
@@ -70,12 +109,26 @@ static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio)
static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
+ struct sh_pfc *pfc = gpio_to_pfc(gc);
+
+ if (offset >= pfc->info->nr_pins) {
+ /* Function GPIOs can only be requested, never configured. */
+ return -EINVAL;
+ }
+
return pinctrl_gpio_direction_input(offset);
}
static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
+ struct sh_pfc *pfc = gpio_to_pfc(gc);
+
+ if (offset >= pfc->info->nr_pins) {
+ /* Function GPIOs can only be requested, never configured. */
+ return -EINVAL;
+ }
+
sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
return pinctrl_gpio_direction_output(offset);
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 682b3a6..747ee64 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -116,21 +116,6 @@ static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
{
}
-static int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset)
-{
- if (sh_pfc_config_gpio(pfc, offset,
- PINMUX_TYPE_FUNCTION,
- GPIO_CFG_DRYRUN) != 0)
- return -EINVAL;
-
- if (sh_pfc_config_gpio(pfc, offset,
- PINMUX_TYPE_FUNCTION,
- GPIO_CFG_REQ) != 0)
- return -EINVAL;
-
- return 0;
-}
-
static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
int new_type)
{
@@ -198,19 +183,11 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
switch (pinmux_type) {
- case PINMUX_TYPE_FUNCTION:
- pr_notice_once("Use of GPIO API for function requests is "
- "deprecated, convert to pinctrl\n");
- /* handle for now */
- ret = sh_pfc_config_function(pfc, offset);
- if (unlikely(ret < 0))
- goto err;
-
- break;
case PINMUX_TYPE_GPIO:
case PINMUX_TYPE_INPUT:
case PINMUX_TYPE_OUTPUT:
break;
+ case PINMUX_TYPE_FUNCTION:
default:
pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
ret = -ENOTSUPP;
@@ -400,7 +377,7 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
pmx->range.name = DRV_NAME,
pmx->range.id = 0;
- pmx->range.npins = pfc->info->nr_gpios;
+ pmx->range.npins = pfc->info->nr_pins;
pmx->range.base = 0;
pmx->range.pin_base = 0;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 013/142] sh-pfc: Don't needlessly check GPIO type in sh_gpio_free()
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (10 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 012/142] sh-pfc: Shrink the pinctrl GPIO range to include real GPIOs only Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 014/142] sh-pfc: Split pins and functions definition tables Simon Horman
` (129 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The GPIO type is always PINMUX_TYPE_FUNCTION when freeing a function
GPIO. Hardcode the type value.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/gpio.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 80a50d8..8f01113 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -71,16 +71,13 @@ static void sh_gpio_free(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
unsigned long flags;
- int pinmux_type;
if (offset < pfc->info->nr_pins)
return pinctrl_free_gpio(offset);
spin_lock_irqsave(&pfc->lock, flags);
- pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
-
- sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
+ sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE);
spin_unlock_irqrestore(&pfc->lock, flags);
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 014/142] sh-pfc: Split pins and functions definition tables
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (11 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 013/142] sh-pfc: Don't needlessly check GPIO type in sh_gpio_free() Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 015/142] sh-pfc: Split pins and functions into separate gpio_chip instances Simon Horman
` (128 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Split the GPIOs table into a pins table for real GPIOs and a functions
table for function GPIOs.
Only register pins with the pinctrl core. The function GPIOs remain
accessible as GPIOs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 21 ++++++++++-------
drivers/pinctrl/sh-pfc/gpio.c | 5 +++--
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 15 ++++++++-----
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 14 ++++++++----
drivers/pinctrl/sh-pfc/pfc-sh7203.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-sh7264.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-sh7269.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-sh7372.c | 15 ++++++++-----
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-sh7720.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-sh7722.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-sh7723.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-sh7724.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-sh7734.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-sh7757.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-sh7785.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-sh7786.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pfc-shx3.c | 13 +++++++----
drivers/pinctrl/sh-pfc/pinctrl.c | 41 +++++++++++++++++-----------------
drivers/pinctrl/sh-pfc/sh_pfc.h | 19 ++++++++++------
20 files changed, 193 insertions(+), 106 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index bed2d23..9dee3b9 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -92,13 +92,14 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio)
{
return (gpio < pfc->info->nr_pins) &&
- (pfc->info->gpios[gpio].enum_id != 0);
+ (pfc->info->pins[gpio].enum_id != 0);
}
bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio)
{
- return (gpio >= pfc->info->nr_pins) && (gpio < pfc->info->nr_gpios) &&
- (pfc->info->gpios[gpio].enum_id != 0);
+ return (gpio >= pfc->info->nr_pins) &&
+ (gpio < pfc->info->nr_pins + pfc->info->nr_func_gpios) &&
+ (pfc->info->func_gpios[gpio - pfc->info->nr_pins].enum_id != 0);
}
static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
@@ -234,7 +235,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
{
- struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
+ struct pinmux_pin *gpiop = &pfc->info->pins[gpio];
struct pinmux_data_reg *data_reg;
int k, n;
@@ -291,7 +292,7 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
struct pinmux_data_reg **drp, int *bitp)
{
- struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
+ struct pinmux_pin *gpiop = &pfc->info->pins[gpio];
int k, n;
if (!sh_pfc_gpio_is_pin(pfc, gpio))
@@ -352,12 +353,16 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
pinmux_enum_t *enum_idp)
{
- pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id;
pinmux_enum_t *data = pfc->info->gpio_data;
+ pinmux_enum_t enum_id;
int k;
- if (!sh_pfc_gpio_is_pin(pfc, gpio) &&
- !sh_pfc_gpio_is_function(pfc, gpio)) {
+ if (sh_pfc_gpio_is_pin(pfc, gpio)) {
+ enum_id = pfc->info->pins[gpio].enum_id;
+ } else if (sh_pfc_gpio_is_function(pfc, gpio)) {
+ unsigned int offset = gpio - pfc->info->nr_pins;
+ enum_id = pfc->info->func_gpios[offset].enum_id;
+ } else {
pr_err("non data/mark enum_id for gpio %d\n", gpio);
return -1;
}
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 8f01113..2a99bef 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -183,7 +183,7 @@ static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip)
gc->label = pfc->info->name;
gc->owner = THIS_MODULE;
gc->base = 0;
- gc->ngpio = pfc->info->nr_gpios;
+ gc->ngpio = pfc->info->nr_pins + pfc->info->nr_func_gpios;
}
int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
@@ -206,7 +206,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
pfc->gpio = chip;
pr_info("%s handling gpio 0 -> %u\n",
- pfc->info->name, pfc->info->nr_gpios - 1);
+ pfc->info->name,
+ pfc->info->nr_pins + pfc->info->nr_func_gpios - 1);
return 0;
}
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 957502e..a22763e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1654,11 +1654,13 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
};
-static struct pinmux_gpio pinmux_gpios[] = {
-
- /* PORT */
+static struct pinmux_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* IRQ */
GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
GPIO_FN(IRQ1),
@@ -2592,9 +2594,10 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = {
.function = { PINMUX_FUNCTION_BEGIN,
PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PORT211 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index bd5a70d..f771239 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1450,8 +1450,13 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+
+static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
GPIO_FN(A19),
@@ -2609,9 +2614,10 @@ struct sh_pfc_soc_info r8a7779_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_GP_6_8 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index ee972f0..17e2d06 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -703,7 +703,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
@@ -815,7 +815,11 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
GPIO_FN(PINT7_PB),
GPIO_FN(PINT6_PB),
@@ -1577,9 +1581,10 @@ struct sh_pfc_soc_info sh7203_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PF0 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index 44066de..b927440 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -1072,7 +1072,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SD_D2_MARK, PK0MD_10),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
@@ -1216,7 +1216,11 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PK2, PK2_DATA),
PINMUX_GPIO(GPIO_PK1, PK1_DATA),
PINMUX_GPIO(GPIO_PK0, PK0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
GPIO_FN(PINT7_PG),
GPIO_FN(PINT6_PG),
@@ -2116,9 +2120,10 @@ struct sh_pfc_soc_info sh7264_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PK0 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index 072c7d5..8f9b975 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -1452,7 +1452,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(PWM1A_MARK, PJ0MD_100),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
@@ -1613,7 +1613,11 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
GPIO_FN(IRQ7_PG),
GPIO_FN(IRQ6_PG),
@@ -2819,9 +2823,10 @@ struct sh_pfc_soc_info sh7269_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PJ0 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index c112074..3a1961b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -929,11 +929,13 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
};
-static struct pinmux_gpio pinmux_gpios[] = {
-
- /* PORT */
+static struct pinmux_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* IRQ */
GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1),
GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8),
@@ -1640,9 +1642,10 @@ struct sh_pfc_soc_info sh7372_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PORT190 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index e41aa21..02cb1dc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -1539,9 +1539,13 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* Table 25-1 (Functions 0-7) */
GPIO_FN(VBUS_0),
GPIO_FN(GPI0),
@@ -2776,9 +2780,10 @@ struct sh_pfc_soc_info sh73a0_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PORT309 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index 294b758..9952a7c2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -606,7 +606,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -759,7 +759,11 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* BSC */
GPIO_FN(D31),
GPIO_FN(D30),
@@ -1220,9 +1224,10 @@ struct sh_pfc_soc_info sh7720_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PTV0 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index e7eadaf..d561737 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -787,7 +787,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -982,7 +982,11 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* SCIF0 */
GPIO_FN(SCIF0_TXD),
GPIO_FN(SCIF0_RXD),
@@ -1764,9 +1768,10 @@ struct sh_pfc_soc_info sh7722_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PTZ1 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index 06b1d73..60831bf 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -923,7 +923,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1139,7 +1139,11 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* SCIF0 */
GPIO_FN(SCIF0_PTT_TXD),
GPIO_FN(SCIF0_PTT_RXD),
@@ -1888,9 +1892,10 @@ struct sh_pfc_soc_info sh7723_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PTZ0 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 41160a3..0b9d16e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -1192,7 +1192,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1418,7 +1418,11 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* BSC */
GPIO_FN(D31),
GPIO_FN(D30),
@@ -2210,9 +2214,10 @@ struct sh_pfc_soc_info sh7724_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PTZ0 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index df32e71..e3bfeff 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -1384,9 +1384,13 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
@@ -2460,9 +2464,10 @@ struct sh_pfc_soc_info sh7734_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_GP_5_11 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index dd32f34..6e78358 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -1114,7 +1114,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1370,7 +1370,11 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* PTA (mobule: LBSC, RGMII) */
GPIO_FN(BS),
GPIO_FN(RDWR),
@@ -2267,9 +2271,10 @@ struct sh_pfc_soc_info sh7757_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PTZ7 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index 447bd92..cce232d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -702,7 +702,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -845,7 +845,11 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PR2, PR2_DATA),
PINMUX_GPIO(GPIO_PR1, PR1_DATA),
PINMUX_GPIO(GPIO_PR0, PR0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* FN */
GPIO_FN(D63_AD31),
GPIO_FN(D62_AD30),
@@ -1289,9 +1293,10 @@ struct sh_pfc_soc_info sh7785_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PR0 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index dee3cfb..74a0e11 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -427,7 +427,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct pinmux_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -505,7 +505,11 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_func pinmux_func_gpios[] = {
/* FN */
GPIO_FN(CDE),
GPIO_FN(ETH_MAGIC),
@@ -822,9 +826,10 @@ struct sh_pfc_soc_info sh7786_pinmux_info = {
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = pinmux_gpios,
- .nr_pins = GPIO_PJ0 + 1,
- .nr_gpios = ARRAY_SIZE(pinmux_gpios),
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index e59da79..eeecffc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -306,7 +306,7 @@ static pinmux_enum_t shx3_pinmux_data[] = {
PINMUX_DATA(IRQOUT_MARK, PH0_FN),
};
-static struct pinmux_gpio shx3_pinmux_gpios[] = {
+static struct pinmux_pin shx3_pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -384,7 +384,11 @@ static struct pinmux_gpio shx3_pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PH2, PH2_DATA),
PINMUX_GPIO(GPIO_PH1, PH1_DATA),
PINMUX_GPIO(GPIO_PH0, PH0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(shx3_pinmux_pins)
+static struct pinmux_func shx3_pinmux_func_gpios[] = {
/* FN */
GPIO_FN(D31),
GPIO_FN(D30),
@@ -569,9 +573,10 @@ struct sh_pfc_soc_info shx3_pinmux_info = {
PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .gpios = shx3_pinmux_gpios,
- .nr_pins = GPIO_PH0 + 1,
- .nr_gpios = ARRAY_SIZE(shx3_pinmux_gpios),
+ .pins = shx3_pinmux_pins,
+ .nr_pins = ARRAY_SIZE(shx3_pinmux_pins),
+ .func_gpios = shx3_pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(shx3_pinmux_func_gpios),
.gpio_data = shx3_pinmux_data,
.gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
.cfg_regs = shx3_pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 747ee64..7759290 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -32,7 +32,7 @@ struct sh_pfc_pinctrl {
struct sh_pfc *pfc;
- struct pinmux_gpio **functions;
+ struct pinmux_func **functions;
unsigned int nr_functions;
struct pinctrl_pin_desc *pads;
@@ -125,7 +125,7 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
spin_lock_irqsave(&pfc->lock, flags);
- pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
+ pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE;
/*
* See if the present config needs to first be de-configured.
@@ -157,8 +157,8 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
GPIO_CFG_REQ) != 0)
goto err;
- pfc->info->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
- pfc->info->gpios[offset].flags |= new_type;
+ pfc->info->pins[offset].flags &= ~PINMUX_FLAG_TYPE;
+ pfc->info->pins[offset].flags |= new_type;
ret = 0;
@@ -168,7 +168,6 @@ err:
return ret;
}
-
static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
@@ -180,7 +179,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
spin_lock_irqsave(&pfc->lock, flags);
- pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
+ pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE;
switch (pinmux_type) {
case PINMUX_TYPE_GPIO:
@@ -213,7 +212,7 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
spin_lock_irqsave(&pfc->lock, flags);
- pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
+ pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE;
sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
@@ -247,7 +246,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
- *config = pfc->info->gpios[pin].flags & PINMUX_FLAG_TYPE;
+ *config = pfc->info->pins[pin].flags & PINMUX_FLAG_TYPE;
return 0;
}
@@ -297,7 +296,7 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
int i;
- pmx->nr_pads = pfc->info->nr_gpios;
+ pmx->nr_pads = pfc->info->nr_pins;
pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads,
GFP_KERNEL);
@@ -308,17 +307,10 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
for (i = 0; i < pmx->nr_pads; i++) {
struct pinctrl_pin_desc *pin = pmx->pads + i;
- struct pinmux_gpio *gpio = pfc->info->gpios + i;
+ struct pinmux_pin *gpio = pfc->info->pins + i;
pin->number = i;
pin->name = gpio->name;
-
- /* XXX */
- if (unlikely(!gpio->enum_id))
- continue;
-
- if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
- pmx->nr_functions++;
}
return 0;
@@ -328,16 +320,23 @@ static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
int i, fn;
+ for (i = 0; i < pfc->info->nr_func_gpios; i++) {
+ struct pinmux_func *func = pfc->info->func_gpios + i;
+
+ if (func->enum_id)
+ pmx->nr_functions++;
+ }
+
pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions *
sizeof(*pmx->functions), GFP_KERNEL);
if (unlikely(!pmx->functions))
return -ENOMEM;
- for (i = fn = 0; i < pmx->nr_pads; i++) {
- struct pinmux_gpio *gpio = pfc->info->gpios + i;
+ for (i = fn = 0; i < pfc->info->nr_func_gpios; i++) {
+ struct pinmux_func *func = pfc->info->func_gpios + i;
- if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
- pmx->functions[fn++] = gpio;
+ if (func->enum_id)
+ pmx->functions[fn++] = func;
}
return 0;
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 6ed7ab9..940170a 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -35,23 +35,27 @@ enum {
#define PINMUX_FLAG_DREG_SHIFT 10
#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
-struct pinmux_gpio {
+struct pinmux_pin {
const pinmux_enum_t enum_id;
pinmux_flag_t flags;
const char *name;
};
+struct pinmux_func {
+ const pinmux_enum_t enum_id;
+ const char *name;
+};
+
#define PINMUX_GPIO(gpio, data_or_mark) \
[gpio] = { \
.name = __stringify(gpio), \
.enum_id = data_or_mark, \
.flags = PINMUX_TYPE_GPIO \
}
-#define PINMUX_GPIO_FN(gpio, data_or_mark) \
- [gpio] = { \
+#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
+ [gpio - (base)] = { \
.name = __stringify(gpio), \
.enum_id = data_or_mark, \
- .flags = PINMUX_TYPE_FUNCTION \
}
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
@@ -106,9 +110,10 @@ struct sh_pfc_soc_info {
struct pinmux_range output;
struct pinmux_range function;
- struct pinmux_gpio *gpios;
+ struct pinmux_pin *pins;
unsigned int nr_pins;
- unsigned int nr_gpios;
+ struct pinmux_func *func_gpios;
+ unsigned int nr_func_gpios;
struct pinmux_cfg_reg *cfg_regs;
struct pinmux_data_reg *data_regs;
@@ -145,7 +150,7 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
-#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, str##_MARK)
+#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
/* helper macro for pinmux_enum_t */
#define PORT_DATA_I(nr) \
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 015/142] sh-pfc: Split pins and functions into separate gpio_chip instances
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (12 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 014/142] sh-pfc: Split pins and functions definition tables Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 016/142] sh-pfc: Rename struct pinmux_pin to struct sh_pfc_pin Simon Horman
` (127 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Register two GPIO chips, one for the real GPIOs and one for the function
GPIOs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 2 +-
drivers/pinctrl/sh-pfc/core.h | 3 +-
drivers/pinctrl/sh-pfc/gpio.c | 227 +++++++++++++++++++++++------------------
3 files changed, 132 insertions(+), 100 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 9dee3b9..6cf3943 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -95,7 +95,7 @@ static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio)
(pfc->info->pins[gpio].enum_id != 0);
}
-bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio)
+static bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio)
{
return (gpio >= pfc->info->nr_pins) &&
(gpio < pfc->info->nr_pins + pfc->info->nr_func_gpios) &&
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index dceaec0..5a0143b 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -33,6 +33,8 @@ struct sh_pfc {
struct sh_pfc_window *window;
struct sh_pfc_chip *gpio;
+ struct sh_pfc_chip *func;
+
struct sh_pfc_pinctrl *pinctrl;
};
@@ -47,7 +49,6 @@ void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
unsigned long value);
int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
struct pinmux_data_reg **drp, int *bitp);
-bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio);
int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
pinmux_enum_t *enum_idp);
int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 2a99bef..82fcb5f 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -36,112 +36,62 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
return gpio_to_pfc_chip(gc)->pfc;
}
-static int sh_gpio_request(struct gpio_chip *gc, unsigned offset)
-{
- struct sh_pfc *pfc = gpio_to_pfc(gc);
- unsigned long flags;
- int ret = -EINVAL;
-
- if (offset < pfc->info->nr_pins)
- return pinctrl_request_gpio(offset);
-
- pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
-
- spin_lock_irqsave(&pfc->lock, flags);
-
- if (!sh_pfc_gpio_is_function(pfc, offset))
- goto done;
-
- if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION,
- GPIO_CFG_DRYRUN))
- goto done;
-
- if (sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION,
- GPIO_CFG_REQ))
- goto done;
-
- ret = 0;
-
-done:
- spin_unlock_irqrestore(&pfc->lock, flags);
- return ret;
-}
+/* -----------------------------------------------------------------------------
+ * Pin GPIOs
+ */
-static void sh_gpio_free(struct gpio_chip *gc, unsigned offset)
+static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
{
- struct sh_pfc *pfc = gpio_to_pfc(gc);
- unsigned long flags;
-
- if (offset < pfc->info->nr_pins)
- return pinctrl_free_gpio(offset);
-
- spin_lock_irqsave(&pfc->lock, flags);
-
- sh_pfc_config_gpio(pfc, offset, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE);
-
- spin_unlock_irqrestore(&pfc->lock, flags);
+ return pinctrl_request_gpio(offset);
}
-static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value)
+static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
{
- struct pinmux_data_reg *dr = NULL;
- int bit = 0;
-
- if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
- BUG();
- else
- sh_pfc_write_bit(dr, bit, value);
+ return pinctrl_free_gpio(offset);
}
-static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio)
+static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value)
{
struct pinmux_data_reg *dr = NULL;
int bit = 0;
- if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
- return -EINVAL;
+ if (sh_pfc_get_data_reg(pfc, offset, &dr, &bit) != 0)
+ BUG();
- return sh_pfc_read_bit(dr, bit);
+ sh_pfc_write_bit(dr, bit, value);
}
-static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
+static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
{
- struct sh_pfc *pfc = gpio_to_pfc(gc);
-
- if (offset >= pfc->info->nr_pins) {
- /* Function GPIOs can only be requested, never configured. */
- return -EINVAL;
- }
-
return pinctrl_gpio_direction_input(offset);
}
-static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
+static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
- struct sh_pfc *pfc = gpio_to_pfc(gc);
-
- if (offset >= pfc->info->nr_pins) {
- /* Function GPIOs can only be requested, never configured. */
- return -EINVAL;
- }
-
- sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
+ gpio_pin_set_value(gpio_to_pfc(gc), offset, value);
return pinctrl_gpio_direction_output(offset);
}
-static int sh_gpio_get(struct gpio_chip *gc, unsigned offset)
+static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
{
- return sh_gpio_get_value(gpio_to_pfc(gc), offset);
+ struct sh_pfc *pfc = gpio_to_pfc(gc);
+ struct pinmux_data_reg *dr = NULL;
+ int bit = 0;
+
+ if (sh_pfc_get_data_reg(pfc, offset, &dr, &bit) != 0)
+ return -EINVAL;
+
+ return sh_pfc_read_bit(dr, bit);
}
-static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
+static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
{
- sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
+ gpio_pin_set_value(gpio_to_pfc(gc), offset, value);
}
-static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
pinmux_enum_t enum_id;
@@ -167,60 +117,141 @@ static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
return -ENOSYS;
}
-static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip)
+static void gpio_pin_setup(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
struct gpio_chip *gc = &chip->gpio_chip;
- gc->request = sh_gpio_request;
- gc->free = sh_gpio_free;
- gc->direction_input = sh_gpio_direction_input;
- gc->get = sh_gpio_get;
- gc->direction_output = sh_gpio_direction_output;
- gc->set = sh_gpio_set;
- gc->to_irq = sh_gpio_to_irq;
+ gc->request = gpio_pin_request;
+ gc->free = gpio_pin_free;
+ gc->direction_input = gpio_pin_direction_input;
+ gc->get = gpio_pin_get;
+ gc->direction_output = gpio_pin_direction_output;
+ gc->set = gpio_pin_set;
+ gc->to_irq = gpio_pin_to_irq;
gc->label = pfc->info->name;
+ gc->dev = pfc->dev;
gc->owner = THIS_MODULE;
gc->base = 0;
- gc->ngpio = pfc->info->nr_pins + pfc->info->nr_func_gpios;
+ gc->ngpio = pfc->info->nr_pins;
}
-int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
+/* -----------------------------------------------------------------------------
+ * Function GPIOs
+ */
+
+static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
+{
+ struct sh_pfc *pfc = gpio_to_pfc(gc);
+ unsigned int gpio = gc->base + offset;
+ unsigned long flags;
+ int ret = -EINVAL;
+
+ pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
+
+ if (pfc->info->func_gpios[offset].enum_id == 0)
+ return ret;
+
+ spin_lock_irqsave(&pfc->lock, flags);
+
+ if (sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION,
+ GPIO_CFG_DRYRUN))
+ goto done;
+
+ if (sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION,
+ GPIO_CFG_REQ))
+ goto done;
+
+ ret = 0;
+
+done:
+ spin_unlock_irqrestore(&pfc->lock, flags);
+ return ret;
+}
+
+static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
+{
+ struct sh_pfc *pfc = gpio_to_pfc(gc);
+ unsigned int gpio = gc->base + offset;
+ unsigned long flags;
+
+ spin_lock_irqsave(&pfc->lock, flags);
+
+ sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE);
+
+ spin_unlock_irqrestore(&pfc->lock, flags);
+}
+
+static void gpio_function_setup(struct sh_pfc_chip *chip)
+{
+ struct sh_pfc *pfc = chip->pfc;
+ struct gpio_chip *gc = &chip->gpio_chip;
+
+ gc->request = gpio_function_request;
+ gc->free = gpio_function_free;
+
+ gc->label = pfc->info->name;
+ gc->owner = THIS_MODULE;
+ gc->base = pfc->info->nr_pins;
+ gc->ngpio = pfc->info->nr_func_gpios;
+}
+
+/* -----------------------------------------------------------------------------
+ * Register/unregister
+ */
+
+static struct sh_pfc_chip *
+sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *))
{
struct sh_pfc_chip *chip;
int ret;
chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
if (unlikely(!chip))
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
chip->pfc = pfc;
- sh_pfc_gpio_setup(chip);
+ setup(chip);
ret = gpiochip_add(&chip->gpio_chip);
if (unlikely(ret < 0))
- return ret;
+ return ERR_PTR(ret);
+
+ pr_info("%s handling gpio %u -> %u\n",
+ chip->gpio_chip.label, chip->gpio_chip.base,
+ chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
+
+ return chip;
+}
+
+int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
+{
+ struct sh_pfc_chip *chip;
+
+ chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
pfc->gpio = chip;
- pr_info("%s handling gpio 0 -> %u\n",
- pfc->info->name,
- pfc->info->nr_pins + pfc->info->nr_func_gpios - 1);
+ chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup);
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
+
+ pfc->func = chip;
return 0;
}
int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
{
- struct sh_pfc_chip *chip = pfc->gpio;
+ int err;
int ret;
- ret = gpiochip_remove(&chip->gpio_chip);
- if (unlikely(ret < 0))
- return ret;
+ ret = gpiochip_remove(&pfc->gpio->gpio_chip);
+ err = gpiochip_remove(&pfc->func->gpio_chip);
- pfc->gpio = NULL;
- return 0;
+ return ret < 0 ? ret : err;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 016/142] sh-pfc: Rename struct pinmux_pin to struct sh_pfc_pin
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (13 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 015/142] sh-pfc: Split pins and functions into separate gpio_chip instances Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 017/142] sh-pfc: Look up IRQ table entries by GPIO number Simon Horman
` (126 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
And drop the pinmux_flag_t typedef.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 4 ++--
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7203.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7264.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7269.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7372.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7720.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7722.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7723.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7724.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7734.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7757.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7785.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh7786.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-shx3.c | 2 +-
drivers/pinctrl/sh-pfc/pinctrl.c | 2 +-
drivers/pinctrl/sh-pfc/sh_pfc.h | 7 +++----
19 files changed, 22 insertions(+), 23 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 6cf3943..f94d80c 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -235,7 +235,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
{
- struct pinmux_pin *gpiop = &pfc->info->pins[gpio];
+ struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
struct pinmux_data_reg *data_reg;
int k, n;
@@ -292,7 +292,7 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
struct pinmux_data_reg **drp, int *bitp)
{
- struct pinmux_pin *gpiop = &pfc->info->pins[gpio];
+ struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
int k, n;
if (!sh_pfc_gpio_is_pin(pfc, gpio))
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index a22763e..ccf9161 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1654,7 +1654,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index f771239..0e53674 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1450,7 +1450,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index 17e2d06..fc4a128 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -703,7 +703,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index b927440..c03365c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -1072,7 +1072,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SD_D2_MARK, PK0MD_10),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index 8f9b975..1fa0950 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -1452,7 +1452,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(PWM1A_MARK, PJ0MD_100),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 3a1961b..b15a16a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -929,7 +929,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 02cb1dc..ca1e97a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -1539,7 +1539,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index 9952a7c2..0b3078b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -606,7 +606,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index d561737..3a8d95f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -787,7 +787,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index 60831bf..d8797ff 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -923,7 +923,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 0b9d16e..40f430b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -1192,7 +1192,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index e3bfeff..20c44dd 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -1384,7 +1384,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index 6e78358..e81ab0e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -1114,7 +1114,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index cce232d..6049f59 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -702,7 +702,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index 74a0e11..526e784 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -427,7 +427,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
};
-static struct pinmux_pin pinmux_pins[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index eeecffc..93d60cd 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -306,7 +306,7 @@ static pinmux_enum_t shx3_pinmux_data[] = {
PINMUX_DATA(IRQOUT_MARK, PH0_FN),
};
-static struct pinmux_pin shx3_pinmux_pins[] = {
+static struct sh_pfc_pin shx3_pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 7759290..d420d99 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -307,7 +307,7 @@ static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
for (i = 0; i < pmx->nr_pads; i++) {
struct pinctrl_pin_desc *pin = pmx->pads + i;
- struct pinmux_pin *gpio = pfc->info->pins + i;
+ struct sh_pfc_pin *gpio = pfc->info->pins + i;
pin->number = i;
pin->name = gpio->name;
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 940170a..dae9e15 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -15,7 +15,6 @@
#include <asm-generic/gpio.h>
typedef unsigned short pinmux_enum_t;
-typedef unsigned short pinmux_flag_t;
enum {
PINMUX_TYPE_NONE,
@@ -35,9 +34,9 @@ enum {
#define PINMUX_FLAG_DREG_SHIFT 10
#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
-struct pinmux_pin {
+struct sh_pfc_pin {
const pinmux_enum_t enum_id;
- pinmux_flag_t flags;
+ unsigned short flags;
const char *name;
};
@@ -110,7 +109,7 @@ struct sh_pfc_soc_info {
struct pinmux_range output;
struct pinmux_range function;
- struct pinmux_pin *pins;
+ struct sh_pfc_pin *pins;
unsigned int nr_pins;
struct pinmux_func *func_gpios;
unsigned int nr_func_gpios;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 017/142] sh-pfc: Look up IRQ table entries by GPIO number
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (14 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 016/142] sh-pfc: Rename struct pinmux_pin to struct sh_pfc_pin Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 018/142] sh-pfc: Share the PORT_10_REV, PORT_32 and PORT_32_REV definitions Simon Horman
` (125 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Instead of converting the GPIO number to an enum_id and looking up IRQ
table entries by enum_id, replace the pinmux_irq enum_ids field with a
gpios field and lookup entries using the GPIO number.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 4 +--
drivers/pinctrl/sh-pfc/core.h | 2 --
drivers/pinctrl/sh-pfc/gpio.c | 25 +++++--------
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 64 +++++++++++++++++-----------------
drivers/pinctrl/sh-pfc/pfc-sh7372.c | 64 +++++++++++++++++-----------------
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 64 +++++++++++++++++-----------------
drivers/pinctrl/sh-pfc/sh_pfc.h | 4 +--
7 files changed, 108 insertions(+), 119 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index f94d80c..22f2999 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -350,8 +350,8 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
return -1;
}
-int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
- pinmux_enum_t *enum_idp)
+static int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
+ pinmux_enum_t *enum_idp)
{
pinmux_enum_t *data = pfc->info->gpio_data;
pinmux_enum_t enum_id;
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 5a0143b..f22d03f 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -49,8 +49,6 @@ void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
unsigned long value);
int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
struct pinmux_data_reg **drp, int *bitp);
-int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
- pinmux_enum_t *enum_idp);
int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
int cfg_mode);
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 82fcb5f..454c965 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -94,23 +94,14 @@ static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
- pinmux_enum_t enum_id;
- pinmux_enum_t *enum_ids;
- int i, k, pos;
-
- pos = 0;
- enum_id = 0;
- while (1) {
- pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id);
- if (pos <= 0 || !enum_id)
- break;
-
- for (i = 0; i < pfc->info->gpio_irq_size; i++) {
- enum_ids = pfc->info->gpio_irq[i].enum_ids;
- for (k = 0; enum_ids[k]; k++) {
- if (enum_ids[k] == enum_id)
- return pfc->info->gpio_irq[i].irq;
- }
+ int i, k;
+
+ for (i = 0; i < pfc->info->gpio_irq_size; i++) {
+ unsigned short *gpios = pfc->info->gpio_irq[i].gpios;
+
+ for (k = 0; gpios[k]; k++) {
+ if (gpios[k] == offset)
+ return pfc->info->gpio_irq[i].irq;
}
}
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index ccf9161..fd91381 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2547,38 +2547,38 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
};
static struct pinmux_irq pinmux_irqs[] = {
- PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */
- PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */
- PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */
- PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */
- PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */
- PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */
- PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */
- PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */
- PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */
- PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */
- PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */
- PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */
- PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */
- PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */
- PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */
- PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */
- PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */
- PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */
- PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */
- PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */
- PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */
- PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */
- PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */
- PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */
- PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */
- PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */
- PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */
- PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */
- PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */
- PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */
- PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */
- PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */
+ PINMUX_IRQ(evt2irq(0x0200), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */
+ PINMUX_IRQ(evt2irq(0x0220), GPIO_PORT20), /* IRQ1A */
+ PINMUX_IRQ(evt2irq(0x0240), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */
+ PINMUX_IRQ(evt2irq(0x0260), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */
+ PINMUX_IRQ(evt2irq(0x0280), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */
+ PINMUX_IRQ(evt2irq(0x02A0), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */
+ PINMUX_IRQ(evt2irq(0x02C0), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
+ PINMUX_IRQ(evt2irq(0x02E0), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
+ PINMUX_IRQ(evt2irq(0x0300), GPIO_PORT119), /* IRQ8A */
+ PINMUX_IRQ(evt2irq(0x0320), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
+ PINMUX_IRQ(evt2irq(0x0340), GPIO_PORT19), /* IRQ10A */
+ PINMUX_IRQ(evt2irq(0x0360), GPIO_PORT104), /* IRQ11A */
+ PINMUX_IRQ(evt2irq(0x0380), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */
+ PINMUX_IRQ(evt2irq(0x03A0), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */
+ PINMUX_IRQ(evt2irq(0x03C0), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */
+ PINMUX_IRQ(evt2irq(0x03E0), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */
+ PINMUX_IRQ(evt2irq(0x3200), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */
+ PINMUX_IRQ(evt2irq(0x3220), GPIO_PORT69), /* IRQ17A */
+ PINMUX_IRQ(evt2irq(0x3240), GPIO_PORT70), /* IRQ18A */
+ PINMUX_IRQ(evt2irq(0x3260), GPIO_PORT71), /* IRQ19A */
+ PINMUX_IRQ(evt2irq(0x3280), GPIO_PORT67), /* IRQ20A */
+ PINMUX_IRQ(evt2irq(0x32A0), GPIO_PORT202), /* IRQ21A */
+ PINMUX_IRQ(evt2irq(0x32C0), GPIO_PORT95), /* IRQ22A */
+ PINMUX_IRQ(evt2irq(0x32E0), GPIO_PORT96), /* IRQ23A */
+ PINMUX_IRQ(evt2irq(0x3300), GPIO_PORT180), /* IRQ24A */
+ PINMUX_IRQ(evt2irq(0x3320), GPIO_PORT38), /* IRQ25A */
+ PINMUX_IRQ(evt2irq(0x3340), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */
+ PINMUX_IRQ(evt2irq(0x3360), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */
+ PINMUX_IRQ(evt2irq(0x3380), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */
+ PINMUX_IRQ(evt2irq(0x33A0), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */
+ PINMUX_IRQ(evt2irq(0x33C0), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */
+ PINMUX_IRQ(evt2irq(0x33E0), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */
};
struct sh_pfc_soc_info r8a7740_pinmux_info = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index b15a16a..847e0cd 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1600,38 +1600,38 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
static struct pinmux_irq pinmux_irqs[] = {
- PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0),
- PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0),
- PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0),
- PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0),
- PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0),
- PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0),
- PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0),
- PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0),
- PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0),
- PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0),
- PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0),
- PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0),
- PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0),
- PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0),
- PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0),
- PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0),
- PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0),
- PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0),
- PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0),
- PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0),
- PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0),
- PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0),
- PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0),
- PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0),
- PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0),
- PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0),
- PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0),
- PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0),
- PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0),
- PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0),
- PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0),
- PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
+ PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
+ PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
+ PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16),
+ PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163),
+ PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18),
+ PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164),
+ PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167),
+ PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168),
+ PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169),
+ PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65),
+ PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67),
+ PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137),
+ PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145),
+ PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146),
+ PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147),
+ PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170),
+ PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85),
+ PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86),
+ PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87),
+ PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92),
+ PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93),
+ PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94),
+ PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95),
+ PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112),
+ PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119),
+ PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172),
+ PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180),
+ PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181),
+ PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182),
+ PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183),
+ PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
};
struct sh_pfc_soc_info sh7372_pinmux_info = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index ca1e97a..639b5e2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2738,38 +2738,38 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
static struct pinmux_irq pinmux_irqs[] = {
- PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
- PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
- PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
- PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
- PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
- PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
- PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
- PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
- PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
- PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
- PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
- PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
- PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
- PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
- PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
- PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
- PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
- PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
- PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
- PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
- PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
- PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
- PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
- PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
- PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
- PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
- PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
- PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
- PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
- PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
- PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
- PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT9),
+ PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT10),
+ PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT11),
+ PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT13),
+ PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT14),
+ PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT15),
+ PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT26),
+ PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT27),
+ PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT28),
+ PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT40),
+ PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT53),
+ PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT54),
+ PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT56),
+ PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT115),
+ PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT116),
+ PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT117),
+ PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT118),
+ PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT147),
+ PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT149),
+ PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT150),
+ PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT156),
+ PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT159),
+ PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT164),
+ PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT223),
+ PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT224),
+ PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT227),
+ PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT234),
+ PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT238),
+ PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT239),
+ PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT249),
+ PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT251),
+ PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT308),
};
struct sh_pfc_soc_info sh73a0_pinmux_info = {
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index dae9e15..f9d4480 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -89,11 +89,11 @@ struct pinmux_data_reg {
struct pinmux_irq {
int irq;
- pinmux_enum_t *enum_ids;
+ unsigned short *gpios;
};
#define PINMUX_IRQ(irq_nr, ids...) \
- { .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \
+ { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \
struct pinmux_range {
pinmux_enum_t begin;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 018/142] sh-pfc: Share the PORT_10_REV, PORT_32 and PORT_32_REV definitions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (15 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 017/142] sh-pfc: Look up IRQ table entries by GPIO number Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 019/142] sh-pfc: Use pinmux identifiers in the pin muxing API Simon Horman
` (124 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The macros are defined identically and used in two SoC-specific files,
share them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 34 ++++++++--------------------------
drivers/pinctrl/sh-pfc/pfc-sh7734.c | 31 +++++++------------------------
drivers/pinctrl/sh-pfc/sh_pfc.h | 17 +++++++++++++++++
3 files changed, 32 insertions(+), 50 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 0e53674..e9a7ead 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -23,11 +23,6 @@
#include "sh_pfc.h"
-#define CPU_32_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_1(fn, pfx##31, sfx)
-
#define CPU_32_PORT6(fn, pfx, sfx) \
PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
@@ -36,12 +31,12 @@
PORT_1(fn, pfx##8, sfx)
#define CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT(fn, pfx##_0_, sfx), \
- CPU_32_PORT(fn, pfx##_1_, sfx), \
- CPU_32_PORT(fn, pfx##_2_, sfx), \
- CPU_32_PORT(fn, pfx##_3_, sfx), \
- CPU_32_PORT(fn, pfx##_4_, sfx), \
- CPU_32_PORT(fn, pfx##_5_, sfx), \
+ PORT_32(fn, pfx##_0_, sfx), \
+ PORT_32(fn, pfx##_1_, sfx), \
+ PORT_32(fn, pfx##_2_, sfx), \
+ PORT_32(fn, pfx##_3_, sfx), \
+ PORT_32(fn, pfx##_4_, sfx), \
+ PORT_32(fn, pfx##_5_, sfx), \
CPU_32_PORT6(fn, pfx##_6_, sfx)
#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
@@ -55,21 +50,8 @@
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
-
-#define PORT_10_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
- PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index 20c44dd..99ea220 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -14,11 +14,6 @@
#include "sh_pfc.h"
-#define CPU_32_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_1(fn, pfx##31, sfx)
-
#define CPU_32_PORT5(fn, pfx, sfx) \
PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
@@ -29,11 +24,11 @@
/* GPSR0 - GPSR5 */
#define CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT(fn, pfx##_0_, sfx), \
- CPU_32_PORT(fn, pfx##_1_, sfx), \
- CPU_32_PORT(fn, pfx##_2_, sfx), \
- CPU_32_PORT(fn, pfx##_3_, sfx), \
- CPU_32_PORT(fn, pfx##_4_, sfx), \
+ PORT_32(fn, pfx##_0_, sfx), \
+ PORT_32(fn, pfx##_1_, sfx), \
+ PORT_32(fn, pfx##_2_, sfx), \
+ PORT_32(fn, pfx##_3_, sfx), \
+ PORT_32(fn, pfx##_4_, sfx), \
CPU_32_PORT5(fn, pfx##_5_, sfx)
#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
@@ -47,20 +42,8 @@
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
-#define PORT_10_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
- PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index f9d4480..43c858d 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -138,6 +138,23 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
+#define PORT_10_REV(fn, pfx, sfx) \
+ PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
+ PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
+ PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
+ PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
+ PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
+
+#define PORT_32(fn, pfx, sfx) \
+ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
+ PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
+ PORT_1(fn, pfx##31, sfx)
+
+#define PORT_32_REV(fn, pfx, sfx) \
+ PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
+ PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
+ PORT_10_REV(fn, pfx, sfx)
+
#define PORT_90(fn, pfx, sfx) \
PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 019/142] sh-pfc: Use pinmux identifiers in the pin muxing API
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (16 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 018/142] sh-pfc: Share the PORT_10_REV, PORT_32 and PORT_32_REV definitions Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 020/142] sh-pfc: Simplify the sh_pfc_gpio_is_pin() logic Simon Horman
` (123 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC core exposes a sh_pfc_config_gpio() function that configures
pinmuxing for a given GPIO (either a real GPIO or a function GPIO).
Handling of real and function GPIOs belong to the GPIO layer, move the
GPIO number to mark translation to the caller and rename the function to
sh_pfc_config_mux().
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 32 +++++++-------------------------
drivers/pinctrl/sh-pfc/core.h | 4 ++--
drivers/pinctrl/sh-pfc/gpio.c | 14 ++++++--------
drivers/pinctrl/sh-pfc/pinctrl.c | 12 ++++++------
4 files changed, 21 insertions(+), 41 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 22f2999..3387f82 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -95,13 +95,6 @@ static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio)
(pfc->info->pins[gpio].enum_id != 0);
}
-static bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio)
-{
- return (gpio >= pfc->info->nr_pins) &&
- (gpio < pfc->info->nr_pins + pfc->info->nr_func_gpios) &&
- (pfc->info->func_gpios[gpio - pfc->info->nr_pins].enum_id != 0);
-}
-
static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
unsigned long reg_width)
{
@@ -350,41 +343,30 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
return -1;
}
-static int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
- pinmux_enum_t *enum_idp)
+static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
+ pinmux_enum_t *enum_idp)
{
pinmux_enum_t *data = pfc->info->gpio_data;
- pinmux_enum_t enum_id;
int k;
- if (sh_pfc_gpio_is_pin(pfc, gpio)) {
- enum_id = pfc->info->pins[gpio].enum_id;
- } else if (sh_pfc_gpio_is_function(pfc, gpio)) {
- unsigned int offset = gpio - pfc->info->nr_pins;
- enum_id = pfc->info->func_gpios[offset].enum_id;
- } else {
- pr_err("non data/mark enum_id for gpio %d\n", gpio);
- return -1;
- }
-
if (pos) {
*enum_idp = data[pos + 1];
return pos + 1;
}
for (k = 0; k < pfc->info->gpio_data_size; k++) {
- if (data[k] == enum_id) {
+ if (data[k] == mark) {
*enum_idp = data[k + 1];
return k + 1;
}
}
- pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
+ pr_err("cannot locate data/mark enum_id for mark %d\n", mark);
return -1;
}
-int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
- int cfg_mode)
+int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
+ int cfg_mode)
{
struct pinmux_cfg_reg *cr = NULL;
pinmux_enum_t enum_id;
@@ -423,7 +405,7 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
field = 0;
value = 0;
while (1) {
- pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
+ pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
if (pos <= 0)
goto out_err;
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index f22d03f..ab816b7 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -49,8 +49,8 @@ void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
unsigned long value);
int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
struct pinmux_data_reg **drp, int *bitp);
-int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
- int cfg_mode);
+int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
+ int cfg_mode);
extern struct sh_pfc_soc_info r8a7740_pinmux_info;
extern struct sh_pfc_soc_info r8a7779_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 454c965..3ad938f 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -135,23 +135,21 @@ static void gpio_pin_setup(struct sh_pfc_chip *chip)
static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
- unsigned int gpio = gc->base + offset;
+ unsigned int mark = pfc->info->func_gpios[offset].enum_id;
unsigned long flags;
int ret = -EINVAL;
pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
- if (pfc->info->func_gpios[offset].enum_id == 0)
+ if (mark == 0)
return ret;
spin_lock_irqsave(&pfc->lock, flags);
- if (sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION,
- GPIO_CFG_DRYRUN))
+ if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_DRYRUN))
goto done;
- if (sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION,
- GPIO_CFG_REQ))
+ if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_REQ))
goto done;
ret = 0;
@@ -164,12 +162,12 @@ done:
static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
- unsigned int gpio = gc->base + offset;
+ unsigned int mark = pfc->info->func_gpios[offset].enum_id;
unsigned long flags;
spin_lock_irqsave(&pfc->lock, flags);
- sh_pfc_config_gpio(pfc, gpio, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE);
+ sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE);
spin_unlock_irqrestore(&pfc->lock, flags);
}
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index d420d99..a83f400 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -119,6 +119,7 @@ static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
int new_type)
{
+ unsigned int mark = pfc->info->pins[offset].enum_id;
unsigned long flags;
int pinmux_type;
int ret = -EINVAL;
@@ -137,7 +138,7 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
case PINMUX_TYPE_INPUT:
case PINMUX_TYPE_INPUT_PULLUP:
case PINMUX_TYPE_INPUT_PULLDOWN:
- sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
+ sh_pfc_config_mux(pfc, mark, pinmux_type, GPIO_CFG_FREE);
break;
default:
goto err;
@@ -146,15 +147,13 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
/*
* Dry run
*/
- if (sh_pfc_config_gpio(pfc, offset, new_type,
- GPIO_CFG_DRYRUN) != 0)
+ if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_DRYRUN) != 0)
goto err;
/*
* Request
*/
- if (sh_pfc_config_gpio(pfc, offset, new_type,
- GPIO_CFG_REQ) != 0)
+ if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_REQ) != 0)
goto err;
pfc->info->pins[offset].flags &= ~PINMUX_FLAG_TYPE;
@@ -214,7 +213,8 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE;
- sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
+ sh_pfc_config_mux(pfc, pfc->info->pins[offset].enum_id, pinmux_type,
+ GPIO_CFG_FREE);
spin_unlock_irqrestore(&pfc->lock, flags);
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 020/142] sh-pfc: Simplify the sh_pfc_gpio_is_pin() logic
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (17 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 019/142] sh-pfc: Use pinmux identifiers in the pin muxing API Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 021/142] sh-pfc: Add function to retrieve a pin instance from its pin number Simon Horman
` (122 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The function is guaranteed to be called with a gpio number smaller than
nr_pins. The condition can the be simplified, and the function inlined.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 29 +++++++++--------------------
drivers/pinctrl/sh-pfc/core.h | 4 ++--
drivers/pinctrl/sh-pfc/gpio.c | 21 +++++++++++----------
3 files changed, 22 insertions(+), 32 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 3387f82..9b5c031 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -89,12 +89,6 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
return 1;
}
-static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio)
-{
- return (gpio < pfc->info->nr_pins) &&
- (pfc->info->pins[gpio].enum_id != 0);
-}
-
static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
unsigned long reg_width)
{
@@ -226,15 +220,12 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
-static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
+static void sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
{
struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
struct pinmux_data_reg *data_reg;
int k, n;
- if (!sh_pfc_gpio_is_pin(pfc, gpio))
- return -1;
-
k = 0;
while (1) {
data_reg = pfc->info->data_regs + k;
@@ -250,15 +241,13 @@ static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
gpiop->flags &= ~PINMUX_FLAG_DBIT;
gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
- return 0;
+ return;
}
}
k++;
}
BUG();
-
- return -1;
}
static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
@@ -266,8 +255,12 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
struct pinmux_data_reg *drp;
int k;
- for (k = 0; k < pfc->info->nr_pins; k++)
+ for (k = 0; k < pfc->info->nr_pins; k++) {
+ if (pfc->info->pins[k].enum_id == 0)
+ continue;
+
sh_pfc_setup_data_reg(pfc, k);
+ }
k = 0;
while (1) {
@@ -282,20 +275,16 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
}
}
-int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
- struct pinmux_data_reg **drp, int *bitp)
+void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
+ struct pinmux_data_reg **drp, int *bitp)
{
struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
int k, n;
- if (!sh_pfc_gpio_is_pin(pfc, gpio))
- return -1;
-
k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
*drp = pfc->info->data_regs + k;
*bitp = n;
- return 0;
}
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index ab816b7..a3111b7 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -47,8 +47,8 @@ int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);
int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos);
void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
unsigned long value);
-int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
- struct pinmux_data_reg **drp, int *bitp);
+void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
+ struct pinmux_data_reg **drp, int *bitp);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
int cfg_mode);
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 3ad938f..db9af4e 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -42,6 +42,11 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
{
+ struct sh_pfc *pfc = gpio_to_pfc(gc);
+
+ if (pfc->info->pins[offset].enum_id == 0)
+ return -EINVAL;
+
return pinctrl_request_gpio(offset);
}
@@ -52,12 +57,10 @@ static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value)
{
- struct pinmux_data_reg *dr = NULL;
- int bit = 0;
-
- if (sh_pfc_get_data_reg(pfc, offset, &dr, &bit) != 0)
- BUG();
+ struct pinmux_data_reg *dr;
+ int bit;
+ sh_pfc_get_data_reg(pfc, offset, &dr, &bit);
sh_pfc_write_bit(dr, bit, value);
}
@@ -77,12 +80,10 @@ static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
- struct pinmux_data_reg *dr = NULL;
- int bit = 0;
-
- if (sh_pfc_get_data_reg(pfc, offset, &dr, &bit) != 0)
- return -EINVAL;
+ struct pinmux_data_reg *dr;
+ int bit;
+ sh_pfc_get_data_reg(pfc, offset, &dr, &bit);
return sh_pfc_read_bit(dr, bit);
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 021/142] sh-pfc: Add function to retrieve a pin instance from its pin number
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (18 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 020/142] sh-pfc: Simplify the sh_pfc_gpio_is_pin() logic Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 022/142] sh-pfc: Replace pinctrl_add_gpio_range() with gpiochip_add_pin_range() Simon Horman
` (121 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This prepares support for sparse pin numbering. The function currently
just performs and indexed lookup in the pins array.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 7 ++++++-
drivers/pinctrl/sh-pfc/core.h | 1 +
drivers/pinctrl/sh-pfc/gpio.c | 3 ++-
drivers/pinctrl/sh-pfc/pinctrl.c | 23 +++++++++++++----------
4 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 9b5c031..667db99 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -78,6 +78,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
return (void __iomem *)address;
}
+struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin)
+{
+ return &pfc->info->pins[pin];
+}
+
static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
{
if (enum_id < r->begin)
@@ -278,7 +283,7 @@ static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
struct pinmux_data_reg **drp, int *bitp)
{
- struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
+ struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio);
int k, n;
k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index a3111b7..6ea3d4f 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -49,6 +49,7 @@ void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
unsigned long value);
void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
struct pinmux_data_reg **drp, int *bitp);
+struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
int cfg_mode);
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index db9af4e..45090d8 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -43,8 +43,9 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
+ struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
- if (pfc->info->pins[offset].enum_id == 0)
+ if (pin->enum_id == 0)
return -EINVAL;
return pinctrl_request_gpio(offset);
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index a83f400..78bd277 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -119,14 +119,15 @@ static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
int new_type)
{
- unsigned int mark = pfc->info->pins[offset].enum_id;
+ struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
+ unsigned int mark = pin->enum_id;
unsigned long flags;
int pinmux_type;
int ret = -EINVAL;
spin_lock_irqsave(&pfc->lock, flags);
- pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE;
+ pinmux_type = pin->flags & PINMUX_FLAG_TYPE;
/*
* See if the present config needs to first be de-configured.
@@ -156,8 +157,8 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_REQ) != 0)
goto err;
- pfc->info->pins[offset].flags &= ~PINMUX_FLAG_TYPE;
- pfc->info->pins[offset].flags |= new_type;
+ pin->flags &= ~PINMUX_FLAG_TYPE;
+ pin->flags |= new_type;
ret = 0;
@@ -173,12 +174,13 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
+ struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
unsigned long flags;
int ret, pinmux_type;
spin_lock_irqsave(&pfc->lock, flags);
- pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE;
+ pinmux_type = pin->flags & PINMUX_FLAG_TYPE;
switch (pinmux_type) {
case PINMUX_TYPE_GPIO:
@@ -206,15 +208,15 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
+ struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
unsigned long flags;
int pinmux_type;
spin_lock_irqsave(&pfc->lock, flags);
- pinmux_type = pfc->info->pins[offset].flags & PINMUX_FLAG_TYPE;
+ pinmux_type = pin->flags & PINMUX_FLAG_TYPE;
- sh_pfc_config_mux(pfc, pfc->info->pins[offset].enum_id, pinmux_type,
- GPIO_CFG_FREE);
+ sh_pfc_config_mux(pfc, pin->enum_id, pinmux_type, GPIO_CFG_FREE);
spin_unlock_irqrestore(&pfc->lock, flags);
}
@@ -240,13 +242,14 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = {
.gpio_set_direction = sh_pfc_gpio_set_direction,
};
-static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
+static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
unsigned long *config)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
+ struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, _pin);
- *config = pfc->info->pins[pin].flags & PINMUX_FLAG_TYPE;
+ *config = pin->flags & PINMUX_FLAG_TYPE;
return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 022/142] sh-pfc: Replace pinctrl_add_gpio_range() with gpiochip_add_pin_range()
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (19 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 021/142] sh-pfc: Add function to retrieve a pin instance from its pin number Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 023/142] sh-pfc: Add support for sparse pin numbers Simon Horman
` (120 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Adding a GPIO range to a pinctrl device logically belongs to the GPIO
driver. Switch to the right API.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/gpio.c | 6 ++++++
drivers/pinctrl/sh-pfc/pinctrl.c | 9 ---------
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 45090d8..32a9c78 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -220,6 +220,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *))
int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
{
struct sh_pfc_chip *chip;
+ int ret;
chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
if (IS_ERR(chip))
@@ -227,6 +228,11 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
pfc->gpio = chip;
+ ret = gpiochip_add_pin_range(&chip->gpio_chip, dev_name(pfc->dev), 0, 0,
+ chip->gpio_chip.ngpio);
+ if (ret < 0)
+ return ret;
+
chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup);
if (IS_ERR(chip))
return PTR_ERR(chip);
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 78bd277..a60c317 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -28,7 +28,6 @@
struct sh_pfc_pinctrl {
struct pinctrl_dev *pctl;
struct pinctrl_desc pctl_desc;
- struct pinctrl_gpio_range range;
struct sh_pfc *pfc;
@@ -377,14 +376,6 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
if (IS_ERR(pmx->pctl))
return PTR_ERR(pmx->pctl);
- pmx->range.name = DRV_NAME,
- pmx->range.id = 0;
- pmx->range.npins = pfc->info->nr_pins;
- pmx->range.base = 0;
- pmx->range.pin_base = 0;
-
- pinctrl_add_gpio_range(pmx->pctl, &pmx->range);
-
return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 023/142] sh-pfc: Add support for sparse pin numbers
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (20 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 022/142] sh-pfc: Replace pinctrl_add_gpio_range() with gpiochip_add_pin_range() Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 024/142] ARM: shmobile: sh73a0: Support sparse GPIO numbers Simon Horman
` (119 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC driver assumes that the value of the GPIO_PORTxxx enumeration
names are equal to the port number. This isn't true when the port number
space is sparse, as with the SH73A0.
Fix the issue by adding support for pin numbers ranges specified through
SoC data. When no range is specified the driver considers that the PFC
implements a single contiguous range for all pins.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 19 ++++++++++++-
drivers/pinctrl/sh-pfc/core.h | 2 ++
drivers/pinctrl/sh-pfc/gpio.c | 37 +++++++++++++++++++-----
drivers/pinctrl/sh-pfc/pinctrl.c | 58 +++++++++++++++++++++++++-------------
drivers/pinctrl/sh-pfc/sh_pfc.h | 2 ++
5 files changed, 91 insertions(+), 27 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 667db99..79824826 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -80,7 +80,24 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin)
{
- return &pfc->info->pins[pin];
+ unsigned int offset;
+ unsigned int i;
+
+ if (pfc->info->ranges == NULL)
+ return &pfc->info->pins[pin];
+
+ for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
+ const struct pinmux_range *range = &pfc->info->ranges[i];
+
+ if (pin <= range->end)
+ return pin >= range->begin
+ ? &pfc->info->pins[offset + pin - range->begin]
+ : NULL;
+
+ offset += range->end - range->begin + 1;
+ }
+
+ return NULL;
}
static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 6ea3d4f..b8b3e87 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -32,6 +32,8 @@ struct sh_pfc {
unsigned int num_windows;
struct sh_pfc_window *window;
+ unsigned int nr_pins;
+
struct sh_pfc_chip *gpio;
struct sh_pfc_chip *func;
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 32a9c78..806e2dd 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -45,7 +45,7 @@ static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
struct sh_pfc *pfc = gpio_to_pfc(gc);
struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
- if (pin->enum_id == 0)
+ if (pin == NULL || pin->enum_id == 0)
return -EINVAL;
return pinctrl_request_gpio(offset);
@@ -127,7 +127,7 @@ static void gpio_pin_setup(struct sh_pfc_chip *chip)
gc->dev = pfc->dev;
gc->owner = THIS_MODULE;
gc->base = 0;
- gc->ngpio = pfc->info->nr_pins;
+ gc->ngpio = pfc->nr_pins;
}
/* -----------------------------------------------------------------------------
@@ -184,7 +184,7 @@ static void gpio_function_setup(struct sh_pfc_chip *chip)
gc->label = pfc->info->name;
gc->owner = THIS_MODULE;
- gc->base = pfc->info->nr_pins;
+ gc->base = pfc->nr_pins;
gc->ngpio = pfc->info->nr_func_gpios;
}
@@ -219,20 +219,43 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *))
int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
{
+ const struct pinmux_range *ranges;
+ struct pinmux_range def_range;
struct sh_pfc_chip *chip;
+ unsigned int nr_ranges;
+ unsigned int i;
int ret;
+ /* Register the real GPIOs chip. */
chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
if (IS_ERR(chip))
return PTR_ERR(chip);
pfc->gpio = chip;
- ret = gpiochip_add_pin_range(&chip->gpio_chip, dev_name(pfc->dev), 0, 0,
- chip->gpio_chip.ngpio);
- if (ret < 0)
- return ret;
+ /* Register the GPIO to pin mappings. */
+ if (pfc->info->ranges == NULL) {
+ def_range.begin = 0;
+ def_range.end = pfc->info->nr_pins - 1;
+ ranges = &def_range;
+ nr_ranges = 1;
+ } else {
+ ranges = pfc->info->ranges;
+ nr_ranges = pfc->info->nr_ranges;
+ }
+
+ for (i = 0; i < nr_ranges; ++i) {
+ const struct pinmux_range *range = &ranges[i];
+
+ ret = gpiochip_add_pin_range(&chip->gpio_chip,
+ dev_name(pfc->dev),
+ range->begin, range->begin,
+ range->end - range->begin + 1);
+ if (ret < 0)
+ return ret;
+ }
+ /* Register the function GPIOs chip. */
chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup);
if (IS_ERR(chip))
return PTR_ERR(chip);
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index a60c317..c9e9a1d 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -293,29 +293,48 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = {
.pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
};
-/* pinmux ranges -> pinctrl pin descs */
-static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
+/* PFC ranges -> pinctrl pin descs */
+static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
- int i;
-
- pmx->nr_pads = pfc->info->nr_pins;
+ const struct pinmux_range *ranges;
+ struct pinmux_range def_range;
+ unsigned int nr_ranges;
+ unsigned int nr_pins;
+ unsigned int i;
+
+ if (pfc->info->ranges == NULL) {
+ def_range.begin = 0;
+ def_range.end = pfc->info->nr_pins - 1;
+ ranges = &def_range;
+ nr_ranges = 1;
+ } else {
+ ranges = pfc->info->ranges;
+ nr_ranges = pfc->info->nr_ranges;
+ }
- pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads,
+ pmx->pads = devm_kzalloc(pfc->dev,
+ sizeof(*pmx->pads) * pfc->info->nr_pins,
GFP_KERNEL);
- if (unlikely(!pmx->pads)) {
- pmx->nr_pads = 0;
+ if (unlikely(!pmx->pads))
return -ENOMEM;
- }
- for (i = 0; i < pmx->nr_pads; i++) {
- struct pinctrl_pin_desc *pin = pmx->pads + i;
- struct sh_pfc_pin *gpio = pfc->info->pins + i;
+ for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
+ const struct pinmux_range *range = &ranges[i];
+ unsigned int number;
+
+ for (number = range->begin; number <= range->end;
+ number++, nr_pins++) {
+ struct pinctrl_pin_desc *pin = &pmx->pads[nr_pins];
+ struct sh_pfc_pin *info = &pfc->info->pins[nr_pins];
- pin->number = i;
- pin->name = gpio->name;
+ pin->number = number;
+ pin->name = info->name;
+ }
}
- return 0;
+ pfc->nr_pins = ranges[nr_ranges-1].end + 1;
+
+ return nr_ranges;
}
static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
@@ -347,6 +366,7 @@ static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
struct sh_pfc_pinctrl *pmx;
+ int nr_ranges;
int ret;
pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
@@ -356,9 +376,9 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
pmx->pfc = pfc;
pfc->pinctrl = pmx;
- ret = sh_pfc_map_gpios(pfc, pmx);
- if (unlikely(ret != 0))
- return ret;
+ nr_ranges = sh_pfc_map_pins(pfc, pmx);
+ if (unlikely(nr_ranges < 0))
+ return nr_ranges;
ret = sh_pfc_map_functions(pfc, pmx);
if (unlikely(ret != 0))
@@ -370,7 +390,7 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
pmx->pctl_desc.pins = pmx->pads;
- pmx->pctl_desc.npins = pmx->nr_pads;
+ pmx->pctl_desc.npins = pfc->info->nr_pins;
pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
if (IS_ERR(pmx->pctl))
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 43c858d..dbcaa60 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -111,6 +111,8 @@ struct sh_pfc_soc_info {
struct sh_pfc_pin *pins;
unsigned int nr_pins;
+ const struct pinmux_range *ranges;
+ unsigned int nr_ranges;
struct pinmux_func *func_gpios;
unsigned int nr_func_gpios;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 024/142] ARM: shmobile: sh73a0: Support sparse GPIO numbers
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (21 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 023/142] sh-pfc: Add support for sparse pin numbers Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 025/142] ARM: shmobile: ap4-evb: Replace GPIO_PORTx enum with GPIO port numbers Simon Horman
` (118 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
The SH73A0 SoC has sparse GPIO numbers. Declare the pin numbers ranges
in the PFC SoC data and use the pin numbers in the GPIO API.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-shmobile/board-ag5evm.c | 26 ++++-----
arch/arm/mach-shmobile/board-kota2.c | 42 +++++++--------
arch/arm/mach-shmobile/board-kzm9g.c | 14 ++---
arch/arm/mach-shmobile/include/mach/sh73a0.h | 2 +-
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 75 ++++++++++++++------------
5 files changed, 84 insertions(+), 75 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 8ff53a1..a4ac46a 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -304,9 +304,9 @@ static int lcd_backlight_set_brightness(int brightness)
if (brightness == 0) {
/* Reset the chip */
- gpio_set_value(GPIO_PORT235, 0);
+ gpio_set_value(235, 0);
mdelay(24);
- gpio_set_value(GPIO_PORT235, 1);
+ gpio_set_value(235, 1);
return 0;
}
@@ -406,7 +406,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
- .cd_gpio = GPIO_PORT251,
+ .cd_gpio = 251,
};
static struct resource sdhi0_resources[] = {
@@ -461,7 +461,7 @@ static struct regulator_init_data cn4_power_init_data = {
static struct fixed_voltage_config cn4_power_info = {
.supply_name = "CN4 SD/MMC Vdd",
.microvolts = 3300000,
- .gpio = GPIO_PORT114,
+ .gpio = 114,
.enable_high = 1,
.init_data = &cn4_power_init_data,
};
@@ -479,10 +479,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
static int power_gpio = -EINVAL;
if (power_gpio < 0) {
- int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW,
+ int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW,
"sdhi1_power");
if (!ret)
- power_gpio = GPIO_PORT114;
+ power_gpio = 114;
}
/*
@@ -493,7 +493,7 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
* regulator driver. We have to live with the race in case the driver
* gets unloaded and the GPIO freed between these two steps.
*/
- gpio_set_value(GPIO_PORT114, state);
+ gpio_set_value(114, state);
}
static struct sh_mobile_sdhi_info sh_sdhi1_info = {
@@ -603,11 +603,11 @@ static void __init ag5evm_init(void)
gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
- gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
+ gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
/* enable SMSC911X */
- gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
- gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
+ gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
+ gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
/* FSI A */
gpio_request(GPIO_FN_FSIACK, NULL);
@@ -622,13 +622,13 @@ static void __init ag5evm_init(void)
gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
/* LCD panel */
- gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
+ gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
mdelay(1);
- gpio_set_value(GPIO_PORT217, 1);
+ gpio_set_value(217, 1);
mdelay(100);
/* LCD backlight controller */
- gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
+ gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
lcd_backlight_set_brightness(0);
/* enable SDHI0 on CN15 [SD I/F] */
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 2ccc860..b6f0515 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -135,17 +135,17 @@ static struct platform_device keysc_device = {
#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
static struct gpio_keys_button gpio_buttons[] = {
- GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */
- GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */
- GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */
- GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */
- GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */
- GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */
- GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */
- GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */
- /* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */
- GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */
- /* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */
+ GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */
+ GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */
+ GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */
+ GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */
+ GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */
+ GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */
+ GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */
+ GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */
+ /* Omitted button "C3?": 223 - S10: CUST [IRQ8] */
+ GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */
+ /* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */
};
static struct gpio_keys_platform_data gpio_key_info = {
@@ -165,9 +165,9 @@ static struct platform_device gpio_keys_device = {
#define GPIO_LED(n, g) { .name = n, .gpio = g }
static struct gpio_led gpio_leds[] = {
- GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */
- GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */
- GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */
+ GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */
+ GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */
+ GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */
};
static struct gpio_led_platform_data gpio_leds_info = {
@@ -187,7 +187,7 @@ static struct platform_device gpio_leds_device = {
static struct led_renesas_tpu_config led_renesas_tpu12_pdata = {
.name = "V2513",
.pin_gpio_fn = GPIO_FN_TPU1TO2,
- .pin_gpio = GPIO_PORT153,
+ .pin_gpio = 153,
.channel_offset = 0x90,
.timer_bit = 2,
.max_brightness = 1000,
@@ -215,7 +215,7 @@ static struct platform_device leds_tpu12_device = {
static struct led_renesas_tpu_config led_renesas_tpu41_pdata = {
.name = "V2514",
.pin_gpio_fn = GPIO_FN_TPU4TO1,
- .pin_gpio = GPIO_PORT199,
+ .pin_gpio = 199,
.channel_offset = 0x50,
.timer_bit = 1,
.max_brightness = 1000,
@@ -243,7 +243,7 @@ static struct platform_device leds_tpu41_device = {
static struct led_renesas_tpu_config led_renesas_tpu21_pdata = {
.name = "V2515",
.pin_gpio_fn = GPIO_FN_TPU2TO1,
- .pin_gpio = GPIO_PORT197,
+ .pin_gpio = 197,
.channel_offset = 0x50,
.timer_bit = 1,
.max_brightness = 1000,
@@ -271,7 +271,7 @@ static struct platform_device leds_tpu21_device = {
static struct led_renesas_tpu_config led_renesas_tpu30_pdata = {
.name = "KEYLED",
.pin_gpio_fn = GPIO_FN_TPU3TO0,
- .pin_gpio = GPIO_PORT163,
+ .pin_gpio = 163,
.channel_offset = 0x10,
.timer_bit = 0,
.max_brightness = 1000,
@@ -474,8 +474,8 @@ static void __init kota2_init(void)
gpio_request(GPIO_FN_D15_NAF15, NULL);
gpio_request(GPIO_FN_CS5A_, NULL);
gpio_request(GPIO_FN_WE0__FWE, NULL);
- gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
- gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
+ gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
+ gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
/* KEYSC */
gpio_request(GPIO_FN_KEYIN0_PU, NULL);
@@ -507,7 +507,7 @@ static void __init kota2_init(void)
gpio_request(GPIO_FN_MMCD0_6, NULL);
gpio_request(GPIO_FN_MMCD0_7, NULL);
gpio_request(GPIO_FN_MMCCMD0, NULL);
- gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
+ gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
/* SDHI0 (microSD) */
gpio_request(GPIO_FN_SDHICD0_PU, NULL);
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 7f3a6b7..65a5e0b 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -433,7 +433,7 @@ static struct sh_mobile_sdhi_info sdhi2_info = {
TMIO_MMC_WRPROTECT_DISABLE,
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
- .cd_gpio = GPIO_PORT13,
+ .cd_gpio = 13,
};
static struct resource sdhi2_resources[] = {
@@ -672,7 +672,7 @@ static void __init kzm_init(void)
gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
/* SMSC */
- gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */
+ gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
/* LCDC */
gpio_request(GPIO_FN_LCDD23, NULL);
@@ -702,11 +702,11 @@ static void __init kzm_init(void)
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
- gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
- gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
+ gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
+ gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
/* Touchscreen */
- gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */
+ gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
/* enable MMCIF */
gpio_request(GPIO_FN_MMCCLK0, NULL);
@@ -730,7 +730,7 @@ static void __init kzm_init(void)
gpio_request(GPIO_FN_SDHID0_1, NULL);
gpio_request(GPIO_FN_SDHID0_0, NULL);
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
- gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
+ gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
/* enable Micro SD */
gpio_request(GPIO_FN_SDHID2_0, NULL);
@@ -739,7 +739,7 @@ static void __init kzm_init(void)
gpio_request(GPIO_FN_SDHID2_3, NULL);
gpio_request(GPIO_FN_SDHICMD2, NULL);
gpio_request(GPIO_FN_SDHICLK2, NULL);
- gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
+ gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
/* I2C 3 */
gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 606d31d..4dca135 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -94,7 +94,7 @@ enum {
GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
/* Table 25-1 (Function 0-7) */
- GPIO_FN_VBUS_0,
+ GPIO_FN_VBUS_0 = 310,
GPIO_FN_GPI0,
GPIO_FN_GPI1,
GPIO_FN_GPI2,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 639b5e2..9cef0d8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -1543,7 +1543,14 @@ static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
};
-#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static struct pinmux_range pinmux_ranges[] = {
+ {.begin = 0, .end = 118,},
+ {.begin = 128, .end = 164,},
+ {.begin = 192, .end = 282,},
+ {.begin = 288, .end = 309,},
+};
+
+#define PINMUX_FN_BASE GPIO_FN_VBUS_0
static struct pinmux_func pinmux_func_gpios[] = {
/* Table 25-1 (Functions 0-7) */
@@ -2738,38 +2745,38 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
static struct pinmux_irq pinmux_irqs[] = {
- PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT9),
- PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT10),
- PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT11),
- PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT13),
- PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT14),
- PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT15),
- PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT26),
- PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT27),
- PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT28),
- PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT40),
- PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT53),
- PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT54),
- PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT56),
- PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT115),
- PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT116),
- PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT117),
- PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT118),
- PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT147),
- PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT149),
- PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT150),
- PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT156),
- PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT159),
- PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT164),
- PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT223),
- PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT224),
- PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT227),
- PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT234),
- PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT238),
- PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT239),
- PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT249),
- PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT251),
- PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT308),
+ PINMUX_IRQ(EXT_IRQ16H(19), 9),
+ PINMUX_IRQ(EXT_IRQ16L(1), 10),
+ PINMUX_IRQ(EXT_IRQ16L(0), 11),
+ PINMUX_IRQ(EXT_IRQ16H(18), 13),
+ PINMUX_IRQ(EXT_IRQ16H(20), 14),
+ PINMUX_IRQ(EXT_IRQ16H(21), 15),
+ PINMUX_IRQ(EXT_IRQ16H(31), 26),
+ PINMUX_IRQ(EXT_IRQ16H(30), 27),
+ PINMUX_IRQ(EXT_IRQ16H(29), 28),
+ PINMUX_IRQ(EXT_IRQ16H(22), 40),
+ PINMUX_IRQ(EXT_IRQ16H(23), 53),
+ PINMUX_IRQ(EXT_IRQ16L(10), 54),
+ PINMUX_IRQ(EXT_IRQ16L(9), 56),
+ PINMUX_IRQ(EXT_IRQ16H(26), 115),
+ PINMUX_IRQ(EXT_IRQ16H(27), 116),
+ PINMUX_IRQ(EXT_IRQ16H(28), 117),
+ PINMUX_IRQ(EXT_IRQ16H(24), 118),
+ PINMUX_IRQ(EXT_IRQ16L(6), 147),
+ PINMUX_IRQ(EXT_IRQ16L(2), 149),
+ PINMUX_IRQ(EXT_IRQ16L(7), 150),
+ PINMUX_IRQ(EXT_IRQ16L(12), 156),
+ PINMUX_IRQ(EXT_IRQ16L(4), 159),
+ PINMUX_IRQ(EXT_IRQ16H(25), 164),
+ PINMUX_IRQ(EXT_IRQ16L(8), 223),
+ PINMUX_IRQ(EXT_IRQ16L(3), 224),
+ PINMUX_IRQ(EXT_IRQ16L(5), 227),
+ PINMUX_IRQ(EXT_IRQ16H(17), 234),
+ PINMUX_IRQ(EXT_IRQ16L(11), 238),
+ PINMUX_IRQ(EXT_IRQ16L(13), 239),
+ PINMUX_IRQ(EXT_IRQ16H(16), 249),
+ PINMUX_IRQ(EXT_IRQ16L(14), 251),
+ PINMUX_IRQ(EXT_IRQ16L(9), 308),
};
struct sh_pfc_soc_info sh73a0_pinmux_info = {
@@ -2782,6 +2789,8 @@ struct sh_pfc_soc_info sh73a0_pinmux_info = {
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
+ .ranges = pinmux_ranges,
+ .nr_ranges = ARRAY_SIZE(pinmux_ranges),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 025/142] ARM: shmobile: ap4-evb: Replace GPIO_PORTx enum with GPIO port numbers
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (22 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 024/142] ARM: shmobile: sh73a0: Support sparse GPIO numbers Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 026/142] ARM: shmobile: armadillo: " Simon Horman
` (117 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC GPIO API implementation moved to using port numbers. Replace all
GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx
enum values are identical to the port number on this platform.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-shmobile/board-ap4evb.c | 36 ++++++++++++++++-----------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 38f1259..0a2b6e4 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -273,11 +273,11 @@ static struct platform_device smc911x_device = {
/*
* The card detect pin of the top SD/MMC slot (CN7) is active low and is
- * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ * connected to GPIO A22 of SH7372 (GPIO 41).
*/
static int slot_cn7_get_cd(struct platform_device *pdev)
{
- return !gpio_get_value(GPIO_PORT41);
+ return !gpio_get_value(41);
}
/* MERAM */
static struct sh_mobile_meram_info meram_info = {
@@ -838,22 +838,22 @@ static struct platform_device fsi_hdmi_device = {
static struct gpio_led ap4evb_leds[] = {
{
.name = "led4",
- .gpio = GPIO_PORT185,
+ .gpio = 185,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led2",
- .gpio = GPIO_PORT186,
+ .gpio = 186,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led3",
- .gpio = GPIO_PORT187,
+ .gpio = 187,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led1",
- .gpio = GPIO_PORT188,
+ .gpio = 188,
.default_state = LEDS_GPIO_DEFSTATE_ON,
}
};
@@ -1026,10 +1026,10 @@ out:
/* TouchScreen */
#ifdef CONFIG_AP4EVB_QHD
# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
-# define GPIO_TSC_PORT GPIO_PORT123
+# define GPIO_TSC_PORT 123
#else /* WVGA */
# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
-# define GPIO_TSC_PORT GPIO_PORT40
+# define GPIO_TSC_PORT 40
#endif
#define IRQ28 evt2irq(0x3380) /* IRQ28A */
@@ -1121,10 +1121,10 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_IRQ6_39, NULL);
/* enable Debug switch (S6) */
- gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL);
- gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL);
- gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL);
- gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL);
+ gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
+ gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
+ gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
+ gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
/* SDHI0 */
gpio_request(GPIO_FN_SDHICD0, NULL);
@@ -1172,15 +1172,15 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
- gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
+ gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
- gpio_request(GPIO_PORT9, NULL);
- gpio_request(GPIO_PORT10, NULL);
+ gpio_request(9, NULL);
+ gpio_request(10, NULL);
gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
/* card detect pin for MMC slot (CN7) */
- gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
+ gpio_request_one(41, GPIOF_IN, NULL);
/* setup FSI2 port B (HDMI) */
gpio_request(GPIO_FN_FSIBCK, NULL);
@@ -1268,8 +1268,8 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
- gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
- gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+ gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
+ gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
lcdc_info.clock_source = LCDC_CLK_BUS;
lcdc_info.ch[0].interface_type = RGB18;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 026/142] ARM: shmobile: armadillo: Replace GPIO_PORTx enum with GPIO port numbers
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (23 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 025/142] ARM: shmobile: ap4-evb: Replace GPIO_PORTx enum with GPIO port numbers Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 027/142] ARM: shmobile: bonito: " Simon Horman
` (116 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC GPIO API implementation moved to using port numbers. Replace all
GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx
enum values are identical to the port number on this platform.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-shmobile/board-armadillo800eva.c | 58 ++++++++++++------------
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index f2ec077..92d7991 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -227,7 +227,7 @@ static void usbhsf_power_ctrl(struct platform_device *pdev,
static int usbhsf_get_vbus(struct platform_device *pdev)
{
- return gpio_get_value(GPIO_PORT209);
+ return gpio_get_value(209);
}
static irqreturn_t usbhsf_interrupt(int irq, void *data)
@@ -535,10 +535,10 @@ static struct platform_device hdmi_lcdc_device = {
{ .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
static struct gpio_keys_button gpio_buttons[] = {
- GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1),
- GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"),
- GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"),
- GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"),
+ GPIO_KEY(KEY_POWER, 99, "SW3", .wakeup = 1),
+ GPIO_KEY(KEY_BACK, 100, "SW4"),
+ GPIO_KEY(KEY_MENU, 97, "SW5"),
+ GPIO_KEY(KEY_HOME, 98, "SW6"),
};
static struct gpio_keys_platform_data gpio_key_info = {
@@ -708,9 +708,9 @@ static int mt9t111_power(struct device *dev, int mode)
/* video1 (= CON1 camera) expect 24MHz */
clk_set_rate(mclk, clk_round_rate(mclk, 24000000));
clk_enable(mclk);
- gpio_set_value(GPIO_PORT158, 1);
+ gpio_set_value(158, 1);
} else {
- gpio_set_value(GPIO_PORT158, 0);
+ gpio_set_value(158, 0);
clk_disable(mclk);
}
@@ -864,8 +864,8 @@ static struct platform_device fsi_hdmi_device = {
/* RTC: RTC connects i2c-gpio. */
static struct i2c_gpio_platform_data i2c_gpio_data = {
- .sda_pin = GPIO_PORT208,
- .scl_pin = GPIO_PORT91,
+ .sda_pin = 208,
+ .scl_pin = 91,
.udelay = 5, /* 100 kHz */
};
@@ -1000,12 +1000,12 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_LCD0_DISP, NULL);
gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
- gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
- gpio_request_one(GPIO_PORT202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
+ gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+ gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
/* Touchscreen */
gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */
- gpio_request_one(GPIO_PORT166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
+ gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
/* GETHER */
gpio_request(GPIO_FN_ET_CRS, NULL);
@@ -1028,12 +1028,12 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_ET_RX_DV, NULL);
gpio_request(GPIO_FN_ET_RX_CLK, NULL);
- gpio_request_one(GPIO_PORT18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
+ gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
/* USB */
- gpio_request_one(GPIO_PORT159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
+ gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
- if (gpio_get_value(GPIO_PORT159)) {
+ if (gpio_get_value(159)) {
/* USB Host */
} else {
/* USB Func */
@@ -1042,10 +1042,10 @@ static void __init eva_init(void)
* OTOH, usbhs interrupt needs its value (HI/LOW) to decide
* USB connection/disconnection (usbhsf_get_vbus()).
* This means we needs to select GPIO_FN_IRQ7_PORT209 first,
- * and select GPIO_PORT209 here
+ * and select GPIO 209 here
*/
gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
- gpio_request_one(GPIO_PORT209, GPIOF_IN, NULL);
+ gpio_request_one(209, GPIOF_IN, NULL);
platform_device_register(&usbhsf_device);
usb = &usbhsf_device;
@@ -1060,9 +1060,9 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_SDHI0_D3, NULL);
gpio_request(GPIO_FN_SDHI0_WP, NULL);
- gpio_request_one(GPIO_PORT17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */
- gpio_request_one(GPIO_PORT74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
- gpio_request_one(GPIO_PORT75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
+ gpio_request_one(17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */
+ gpio_request_one(74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
+ gpio_request_one(75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
/* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
@@ -1099,10 +1099,10 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_VIO_CKO, NULL);
/* CON1/CON15 Camera */
- gpio_request_one(GPIO_PORT173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */
- gpio_request_one(GPIO_PORT172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
+ gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */
+ gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
/* see mt9t111_power() */
- gpio_request_one(GPIO_PORT158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */
+ gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */
/* FSI-WM8978 */
gpio_request(GPIO_FN_FSIAIBT, NULL);
@@ -1111,8 +1111,8 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_FSIAOSLD, NULL);
gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL);
- gpio_request(GPIO_PORT7, NULL);
- gpio_request(GPIO_PORT8, NULL);
+ gpio_request(7, NULL);
+ gpio_request(8, NULL);
gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
@@ -1129,14 +1129,14 @@ static void __init eva_init(void)
* DBGMD/LCDC0/FSIA MUX
* DBGMD_SELECT_B should be set after setting PFC Function.
*/
- gpio_request_one(GPIO_PORT176, GPIOF_OUT_INIT_HIGH, NULL);
+ gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL);
/*
* We can switch CON8/CON14 by SW1.5,
* but it needs after DBGMD_SELECT_B
*/
- gpio_request_one(GPIO_PORT6, GPIOF_IN, NULL);
- if (gpio_get_value(GPIO_PORT6)) {
+ gpio_request_one(6, GPIOF_IN, NULL);
+ if (gpio_get_value(6)) {
/* CON14 enable */
} else {
/* CON8 (SDHI1) enable */
@@ -1150,7 +1150,7 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_SDHI1_WP, NULL);
/* SDSLOT2_PON */
- gpio_request_one(GPIO_PORT16, GPIOF_OUT_INIT_HIGH, NULL);
+ gpio_request_one(16, GPIOF_OUT_INIT_HIGH, NULL);
platform_device_register(&sdhi1_device);
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 027/142] ARM: shmobile: bonito: Replace GPIO_PORTx enum with GPIO port numbers
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (24 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 026/142] ARM: shmobile: armadillo: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 028/142] ARM: shmobile: mackerel: " Simon Horman
` (115 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC GPIO API implementation moved to using port numbers. Replace all
GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx
enum values are identical to the port number on this platform.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-shmobile/board-bonito.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index e50f866..d363526 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -392,8 +392,8 @@ static void __init bonito_init(void)
/*
* base board settings
*/
- gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL);
- if (!gpio_get_value(GPIO_PORT176)) {
+ gpio_request_one(176, GPIOF_IN, NULL);
+ if (!gpio_get_value(176)) {
u16 bsw2;
u16 bsw3;
u16 bsw4;
@@ -461,7 +461,7 @@ static void __init bonito_init(void)
gpio_request(GPIO_FN_LCD0_DISP, NULL);
gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
- gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
+ gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
NULL); /* LCDDON */
/* backlight on */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 028/142] ARM: shmobile: mackerel: Replace GPIO_PORTx enum with GPIO port numbers
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (25 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 027/142] ARM: shmobile: bonito: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 029/142] sh-pfc: Expose real groups and functions in pinctrl/pinmux operations Simon Horman
` (114 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC GPIO API implementation moved to using port numbers. Replace all
GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx
enum values are identical to the port number on this platform.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-shmobile/board-mackerel.c | 34 +++++++++++++++----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index db968a5..172d472 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -363,7 +363,7 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
static int mackerel_set_brightness(int brightness)
{
- gpio_set_value(GPIO_PORT31, brightness);
+ gpio_set_value(31, brightness);
return 0;
}
@@ -819,22 +819,22 @@ static struct platform_device usbhs1_device = {
static struct gpio_led mackerel_leds[] = {
{
.name = "led0",
- .gpio = GPIO_PORT0,
+ .gpio = 0,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led1",
- .gpio = GPIO_PORT1,
+ .gpio = 1,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led2",
- .gpio = GPIO_PORT2,
+ .gpio = 2,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led3",
- .gpio = GPIO_PORT159,
+ .gpio = 159,
.default_state = LEDS_GPIO_DEFSTATE_ON,
}
};
@@ -964,11 +964,11 @@ static struct platform_device nand_flash_device = {
/*
* The card detect pin of the top SD/MMC slot (CN7) is active low and is
- * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ * connected to GPIO A22 of SH7372 (GPIO 41).
*/
static int slot_cn7_get_cd(struct platform_device *pdev)
{
- return !gpio_get_value(GPIO_PORT41);
+ return !gpio_get_value(41);
}
/* SDHI0 */
@@ -977,7 +977,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
.tmio_flags = TMIO_MMC_USE_GPIO_CD,
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
- .cd_gpio = GPIO_PORT172,
+ .cd_gpio = 172,
};
static struct resource sdhi0_resources[] = {
@@ -1060,11 +1060,11 @@ static struct platform_device sdhi1_device = {
/*
* The card detect pin of the top SD/MMC slot (CN23) is active low and is
- * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162).
+ * connected to GPIO SCIFB_SCK of SH7372 (162).
*/
static int slot_cn23_get_cd(struct platform_device *pdev)
{
- return !gpio_get_value(GPIO_PORT162);
+ return !gpio_get_value(162);
}
/* SDHI2 */
@@ -1403,9 +1403,9 @@ static void __init mackerel_init(void)
gpio_request(GPIO_FN_LCDDCK, NULL);
/* backlight, off by default */
- gpio_request_one(GPIO_PORT31, GPIOF_OUT_INIT_LOW, NULL);
+ gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
- gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+ gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
/* USBHS0 */
gpio_request(GPIO_FN_VBUS0_0, NULL);
@@ -1421,10 +1421,10 @@ static void __init mackerel_init(void)
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
- gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
+ gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
- gpio_request(GPIO_PORT9, NULL);
- gpio_request(GPIO_PORT10, NULL);
+ gpio_request(9, NULL);
+ gpio_request(10, NULL);
gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
@@ -1475,7 +1475,7 @@ static void __init mackerel_init(void)
gpio_request(GPIO_FN_SDHID1_0, NULL);
#endif
/* card detect pin for MMC slot (CN7) */
- gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
+ gpio_request_one(41, GPIOF_IN, NULL);
/* enable SDHI2 */
gpio_request(GPIO_FN_SDHICMD2, NULL);
@@ -1486,7 +1486,7 @@ static void __init mackerel_init(void)
gpio_request(GPIO_FN_SDHID2_0, NULL);
/* card detect pin for microSD slot (CN23) */
- gpio_request_one(GPIO_PORT162, GPIOF_IN, NULL);
+ gpio_request_one(162, GPIOF_IN, NULL);
/* MMCIF */
gpio_request(GPIO_FN_MMCD0_0, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 029/142] sh-pfc: Expose real groups and functions in pinctrl/pinmux operations
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (26 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 028/142] ARM: shmobile: mackerel: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 030/142] sh: sh7203: Add pin control resources Simon Horman
` (113 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The sh-pfc driver exposes one fake group and function per GPIO pin. As
the pinctrl and pinmux APIs are not used by any SuperH and SH Mobile
board or driver, drop the fake groups and functions and replace them by
a real pinctrl and pinmux implementation.
Groups and functions must now be explicitly provided by PFC SoC-specific
data.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 114 +++++++++++++++++++-------------------
drivers/pinctrl/sh-pfc/sh_pfc.h | 35 ++++++++++++
2 files changed, 93 insertions(+), 56 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index c9e9a1d..c7f3c40 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -31,18 +31,14 @@ struct sh_pfc_pinctrl {
struct sh_pfc *pfc;
- struct pinmux_func **functions;
- unsigned int nr_functions;
-
- struct pinctrl_pin_desc *pads;
- unsigned int nr_pads;
+ struct pinctrl_pin_desc *pins;
};
static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- return pmx->nr_pads;
+ return pmx->pfc->info->nr_groups;
}
static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
@@ -50,16 +46,16 @@ static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- return pmx->pads[selector].name;
+ return pmx->pfc->info->groups[selector].name;
}
-static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
+static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
const unsigned **pins, unsigned *num_pins)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- *pins = &pmx->pads[group].number;
- *num_pins = 1;
+ *pins = pmx->pfc->info->groups[selector].pins;
+ *num_pins = pmx->pfc->info->groups[selector].nr_pins;
return 0;
}
@@ -81,7 +77,7 @@ static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- return pmx->nr_functions;
+ return pmx->pfc->info->nr_functions;
}
static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
@@ -89,30 +85,67 @@ static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- return pmx->functions[selector]->name;
+ return pmx->pfc->info->functions[selector].name;
}
-static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
+static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- *groups = &pmx->functions[func]->name;
- *num_groups = 1;
+ *groups = pmx->pfc->info->functions[selector].groups;
+ *num_groups = pmx->pfc->info->functions[selector].nr_groups;
return 0;
}
-static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
+static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
- return 0;
+ struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+ struct sh_pfc *pfc = pmx->pfc;
+ const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
+ unsigned long flags;
+ unsigned int i;
+ int ret = -EINVAL;
+
+ spin_lock_irqsave(&pfc->lock, flags);
+
+ for (i = 0; i < grp->nr_pins; ++i) {
+ if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
+ GPIO_CFG_DRYRUN))
+ goto done;
+
+ if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
+ GPIO_CFG_REQ))
+ goto done;
+ }
+
+ ret = 0;
+
+done:
+ spin_unlock_irqrestore(&pfc->lock, flags);
+ return ret;
}
-static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
+static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
+ struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+ struct sh_pfc *pfc = pmx->pfc;
+ const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
+ unsigned long flags;
+ unsigned int i;
+
+ spin_lock_irqsave(&pfc->lock, flags);
+
+ for (i = 0; i < grp->nr_pins; ++i)
+ sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
+ GPIO_CFG_FREE);
+
+ spin_unlock_irqrestore(&pfc->lock, flags);
}
static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
@@ -234,8 +267,8 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = {
.get_functions_count = sh_pfc_get_functions_count,
.get_function_name = sh_pfc_get_function_name,
.get_function_groups = sh_pfc_get_function_groups,
- .enable = sh_pfc_noop_enable,
- .disable = sh_pfc_noop_disable,
+ .enable = sh_pfc_func_enable,
+ .disable = sh_pfc_func_disable,
.gpio_request_enable = sh_pfc_gpio_request_enable,
.gpio_disable_free = sh_pfc_gpio_disable_free,
.gpio_set_direction = sh_pfc_gpio_set_direction,
@@ -312,10 +345,10 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
nr_ranges = pfc->info->nr_ranges;
}
- pmx->pads = devm_kzalloc(pfc->dev,
- sizeof(*pmx->pads) * pfc->info->nr_pins,
+ pmx->pins = devm_kzalloc(pfc->dev,
+ sizeof(*pmx->pins) * pfc->info->nr_pins,
GFP_KERNEL);
- if (unlikely(!pmx->pads))
+ if (unlikely(!pmx->pins))
return -ENOMEM;
for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
@@ -324,7 +357,7 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
for (number = range->begin; number <= range->end;
number++, nr_pins++) {
- struct pinctrl_pin_desc *pin = &pmx->pads[nr_pins];
+ struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
struct sh_pfc_pin *info = &pfc->info->pins[nr_pins];
pin->number = number;
@@ -337,37 +370,10 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
return nr_ranges;
}
-static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
-{
- int i, fn;
-
- for (i = 0; i < pfc->info->nr_func_gpios; i++) {
- struct pinmux_func *func = pfc->info->func_gpios + i;
-
- if (func->enum_id)
- pmx->nr_functions++;
- }
-
- pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions *
- sizeof(*pmx->functions), GFP_KERNEL);
- if (unlikely(!pmx->functions))
- return -ENOMEM;
-
- for (i = fn = 0; i < pfc->info->nr_func_gpios; i++) {
- struct pinmux_func *func = pfc->info->func_gpios + i;
-
- if (func->enum_id)
- pmx->functions[fn++] = func;
- }
-
- return 0;
-}
-
int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
struct sh_pfc_pinctrl *pmx;
int nr_ranges;
- int ret;
pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
if (unlikely(!pmx))
@@ -380,16 +386,12 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
if (unlikely(nr_ranges < 0))
return nr_ranges;
- ret = sh_pfc_map_functions(pfc, pmx);
- if (unlikely(ret != 0))
- return ret;
-
pmx->pctl_desc.name = DRV_NAME;
pmx->pctl_desc.owner = THIS_MODULE;
pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
- pmx->pctl_desc.pins = pmx->pads;
+ pmx->pctl_desc.pins = pmx->pins;
pmx->pctl_desc.npins = pfc->info->nr_pins;
pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index dbcaa60..028e29a 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -16,6 +16,8 @@
typedef unsigned short pinmux_enum_t;
+#define SH_PFC_MARK_INVALID ((pinmux_enum_t)-1)
+
enum {
PINMUX_TYPE_NONE,
@@ -40,6 +42,34 @@ struct sh_pfc_pin {
const char *name;
};
+#define SH_PFC_PIN_GROUP(n) \
+ { \
+ .name = #n, \
+ .pins = n##_pins, \
+ .mux = n##_mux, \
+ .nr_pins = ARRAY_SIZE(n##_pins), \
+ }
+
+struct sh_pfc_pin_group {
+ const char *name;
+ const unsigned int *pins;
+ const unsigned int *mux;
+ unsigned int nr_pins;
+};
+
+#define SH_PFC_FUNCTION(n) \
+ { \
+ .name = #n, \
+ .groups = n##_groups, \
+ .nr_groups = ARRAY_SIZE(n##_groups), \
+ }
+
+struct sh_pfc_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int nr_groups;
+};
+
struct pinmux_func {
const pinmux_enum_t enum_id;
const char *name;
@@ -113,6 +143,11 @@ struct sh_pfc_soc_info {
unsigned int nr_pins;
const struct pinmux_range *ranges;
unsigned int nr_ranges;
+ const struct sh_pfc_pin_group *groups;
+ unsigned int nr_groups;
+ const struct sh_pfc_function *functions;
+ unsigned int nr_functions;
+
struct pinmux_func *func_gpios;
unsigned int nr_func_gpios;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 030/142] sh: sh7203: Add pin control resources
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (27 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 029/142] sh-pfc: Expose real groups and functions in pinctrl/pinmux operations Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 031/142] sh: sh7264: " Simon Horman
` (112 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add memory resources for the pin control platform device to let the
sh-pfc driver ioremap() registers properly instead of evily casting
register physical addresses to virtual addresses.
The memory resource address range has been extracted from the config and
data registes lists in the sh-pfc driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
index 96c6c26..eef17dc 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
@@ -8,12 +8,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7203_pfc_resources[] = {
+ [0] = {
+ .start = 0xfffe3800,
+ .end = 0xfffe3a9f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7203", NULL, 0);
+ return sh_pfc_register("pfc-sh7203", sh7203_pfc_resources,
+ ARRAY_SIZE(sh7203_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 031/142] sh: sh7264: Add pin control resources
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (28 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 030/142] sh: sh7203: Add pin control resources Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 032/142] sh: sh7269: " Simon Horman
` (111 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add memory resources for the pin control platform device to let the
sh-pfc driver ioremap() registers properly instead of evily casting
register physical addresses to virtual addresses.
The memory resource address range has been extracted from the config and
data registes lists in the sh-pfc driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
index b1b7c1b..569decb 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
@@ -8,12 +8,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7264_pfc_resources[] = {
+ [0] = {
+ .start = 0xfffe3800,
+ .end = 0xfffe393f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7264", NULL, 0);
+ return sh_pfc_register("pfc-sh7264", sh7264_pfc_resources,
+ ARRAY_SIZE(sh7264_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 032/142] sh: sh7269: Add pin control resources
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (29 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 031/142] sh: sh7264: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 033/142] sh: sh7720: " Simon Horman
` (110 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add memory resources for the pin control platform device to let the
sh-pfc driver ioremap() registers properly instead of evily casting
register physical addresses to virtual addresses.
The memory resource address range has been extracted from the config and
data registes lists in the sh-pfc driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
index dc2a868..1825b0b 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
@@ -13,8 +13,17 @@
#include <linux/kernel.h>
#include <cpu/pfc.h>
+static struct resource sh7269_pfc_resources[] = {
+ [0] = {
+ .start = 0xfffe3800,
+ .end = 0xfffe391f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7269", NULL, 0);
+ return sh_pfc_register("pfc-sh7269", sh7269_pfc_resources,
+ ARRAY_SIZE(sh7269_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 033/142] sh: sh7720: Add pin control resources
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (30 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 032/142] sh: sh7269: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 034/142] sh: sh7722: " Simon Horman
` (109 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add memory resources for the pin control platform device to let the
sh-pfc driver ioremap() registers properly instead of evily casting
register physical addresses to virtual addresses.
The memory resource address range has been extracted from the config and
data registes lists in the sh-pfc driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/sh/kernel/cpu/sh3/pinmux-sh7720.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
index 7d3744a..26e90a6 100644
--- a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
@@ -8,13 +8,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7720_pfc_resources[] = {
+ [0] = {
+ .start = 0xa4050100,
+ .end = 0xa405016f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7720", NULL, 0);
+ return sh_pfc_register("pfc-sh7720", sh7720_pfc_resources,
+ ARRAY_SIZE(sh7720_pfc_resources));
}
-
arch_initcall(plat_pinmux_setup);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 034/142] sh: sh7722: Add pin control resources
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (31 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 033/142] sh: sh7720: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 035/142] sh: sh7723: " Simon Horman
` (108 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add memory resources for the pin control platform device to let the
sh-pfc driver ioremap() registers properly instead of evily casting
register physical addresses to virtual addresses.
The memory resource address range has been extracted from the config and
data registes lists in the sh-pfc driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
index d9bcc42..271bbc8 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -1,10 +1,20 @@
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7722_pfc_resources[] = {
+ [0] = {
+ .start = 0xa4050100,
+ .end = 0xa405018f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7722", NULL, 0);
+ return sh_pfc_register("pfc-sh7722", sh7722_pfc_resources,
+ ARRAY_SIZE(sh7722_pfc_resources));
}
-
arch_initcall(plat_pinmux_setup);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 035/142] sh: sh7723: Add pin control resources
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (32 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 034/142] sh: sh7722: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 036/142] sh: sh7724: " Simon Horman
` (107 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add memory resources for the pin control platform device to let the
sh-pfc driver ioremap() registers properly instead of evily casting
register physical addresses to virtual addresses.
The memory resource address range has been extracted from the config and
data registes lists in the sh-pfc driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
index bcec7ad..99c637d 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
@@ -8,13 +8,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7723_pfc_resources[] = {
+ [0] = {
+ .start = 0xa4050100,
+ .end = 0xa405016f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7723", NULL, 0);
+ return sh_pfc_register("pfc-sh7723", sh7723_pfc_resources,
+ ARRAY_SIZE(sh7723_pfc_resources));
}
-
arch_initcall(plat_pinmux_setup);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 036/142] sh: sh7724: Add pin control resources
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (33 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 035/142] sh: sh7723: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 037/142] sh: sh7757: " Simon Horman
` (106 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add memory resources for the pin control platform device to let the
sh-pfc driver ioremap() registers properly instead of evily casting
register physical addresses to virtual addresses.
The memory resource address range has been extracted from the config and
data registes lists in the sh-pfc driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
index 5c3541d..63be474 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
@@ -13,12 +13,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7724_pfc_resources[] = {
+ [0] = {
+ .start = 0xa4050100,
+ .end = 0xa405016f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7724", NULL, 0);
+ return sh_pfc_register("pfc-sh7724", sh7724_pfc_resources,
+ ARRAY_SIZE(sh7724_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 037/142] sh: sh7757: Add pin control resources
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (34 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 036/142] sh: sh7724: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 038/142] sh: sh7785: " Simon Horman
` (105 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add memory resources for the pin control platform device to let the
sh-pfc driver ioremap() registers properly instead of evily casting
register physical addresses to virtual addresses.
The memory resource address range has been extracted from the config and
data registes lists in the sh-pfc driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
index cda6bd1..567745d 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -13,12 +13,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7757_pfc_resources[] = {
+ [0] = {
+ .start = 0xffec0000,
+ .end = 0xffec008f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7757", NULL, 0);
+ return sh_pfc_register("pfc-sh7757", sh7757_pfc_resources,
+ ARRAY_SIZE(sh7757_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 038/142] sh: sh7785: Add pin control resources
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (35 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 037/142] sh: sh7757: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 039/142] sh: sh7786: " Simon Horman
` (104 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add memory resources for the pin control platform device to let the
sh-pfc driver ioremap() registers properly instead of evily casting
register physical addresses to virtual addresses.
The memory resource address range has been extracted from the config and
data registes lists in the sh-pfc driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
index 01055b8..e336ab8 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
@@ -8,13 +8,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7785_pfc_resources[] = {
+ [0] = {
+ .start = 0xffe70000,
+ .end = 0xffe7008f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7785", NULL, 0);
+ return sh_pfc_register("pfc-sh7785", sh7785_pfc_resources,
+ ARRAY_SIZE(sh7785_pfc_resources));
}
-
arch_initcall(plat_pinmux_setup);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 039/142] sh: sh7786: Add pin control resources
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (36 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 038/142] sh: sh7785: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 040/142] sh: shx3: " Simon Horman
` (103 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add memory resources for the pin control platform device to let the
sh-pfc driver ioremap() registers properly instead of evily casting
register physical addresses to virtual addresses.
The memory resource address range has been extracted from the config and
data registes lists in the sh-pfc driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
index 3061778..9a45955 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
@@ -13,13 +13,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7786_pfc_resources[] = {
+ [0] = {
+ .start = 0xffcc0000,
+ .end = 0xffcc008f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7786", NULL, 0);
+ return sh_pfc_register("pfc-sh7786", sh7786_pfc_resources,
+ ARRAY_SIZE(sh7786_pfc_resources));
}
-
arch_initcall(plat_pinmux_setup);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 040/142] sh: shx3: Add pin control resources
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (37 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 039/142] sh: sh7786: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 041/142] sh-pfc: Fix return value check in sh_pfc_register_pinctrl() Simon Horman
` (102 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add memory resources for the pin control platform device to let the
sh-pfc driver ioremap() registers properly instead of evily casting
register physical addresses to virtual addresses.
The memory resource address range has been extracted from the config and
data registes lists in the sh-pfc driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/sh/kernel/cpu/sh4a/pinmux-shx3.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
index ace84ac..444bf25 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
@@ -7,12 +7,23 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
-static int __init shx3_pinmux_setup(void)
+static struct resource shx3_pfc_resources[] = {
+ [0] = {
+ .start = 0xffc70000,
+ .end = 0xffc7001f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-shx3", NULL, 0);
+ return sh_pfc_register("pfc-shx3", shx3_pfc_resources,
+ ARRAY_SIZE(shx3_pfc_resources));
}
-arch_initcall(shx3_pinmux_setup);
+arch_initcall(plat_pinmux_setup);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 041/142] sh-pfc: Fix return value check in sh_pfc_register_pinctrl()
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (38 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 040/142] sh: shx3: " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 042/142] sh-pfc: Move GPIO registers access functions to gpio.c Simon Horman
` (101 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
In case of error, the function pinctrl_register() returns NULL not
ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index c7f3c40..3e49bf0 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -395,8 +395,8 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
pmx->pctl_desc.npins = pfc->info->nr_pins;
pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
- if (IS_ERR(pmx->pctl))
- return PTR_ERR(pmx->pctl);
+ if (pmx->pctl == NULL)
+ return -EINVAL;
return 0;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 042/142] sh-pfc: Move GPIO registers access functions to gpio.c
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (39 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 041/142] sh-pfc: Fix return value check in sh_pfc_register_pinctrl() Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 043/142] sh-pfc: Don't map data registers individually Simon Horman
` (100 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Move the sh_pfc_setup_data_regs(), sh_pfc_setup_data_reg(),
sh_pfc_get_data_reg(), sh_pfc_read_bit() and sh_pfc_write_bit()
function to gpio.c as they belong to the GPIO implementation. Inline
sh_pfc_read_bit() and sh_pfc_write_bit() in their only call location.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 110 ++---------------------------------------
drivers/pinctrl/sh-pfc/core.h | 11 +++--
drivers/pinctrl/sh-pfc/gpio.c | 92 +++++++++++++++++++++++++++++++---
3 files changed, 97 insertions(+), 116 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 79824826..49fde28 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -55,8 +55,7 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
return 0;
}
-static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
- unsigned long address)
+void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address)
{
struct sh_pfc_window *window;
int k;
@@ -111,8 +110,8 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
return 1;
}
-static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
- unsigned long reg_width)
+unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
+ unsigned long reg_width)
{
switch (reg_width) {
case 8:
@@ -127,8 +126,8 @@ static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
return 0;
}
-static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
- unsigned long reg_width, unsigned long data)
+void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
+ unsigned long data)
{
switch (reg_width) {
case 8:
@@ -145,37 +144,6 @@ static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
BUG();
}
-int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
-{
- unsigned long pos;
-
- pos = dr->reg_width - (in_pos + 1);
-
- pr_debug("read_bit: addr = %lx, pos = %ld, "
- "r_width = %ld\n", dr->reg, pos, dr->reg_width);
-
- return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
-}
-
-void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
- unsigned long value)
-{
- unsigned long pos;
-
- pos = dr->reg_width - (in_pos + 1);
-
- pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
- "r_width = %ld\n",
- dr->reg, !!value, pos, dr->reg_width);
-
- if (value)
- set_bit(pos, &dr->reg_shadow);
- else
- clear_bit(pos, &dr->reg_shadow);
-
- sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
-}
-
static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
struct pinmux_cfg_reg *crp,
unsigned long in_pos,
@@ -242,73 +210,6 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
-static void sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
-{
- struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
- struct pinmux_data_reg *data_reg;
- int k, n;
-
- k = 0;
- while (1) {
- data_reg = pfc->info->data_regs + k;
-
- if (!data_reg->reg_width)
- break;
-
- data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
-
- for (n = 0; n < data_reg->reg_width; n++) {
- if (data_reg->enum_ids[n] == gpiop->enum_id) {
- gpiop->flags &= ~PINMUX_FLAG_DREG;
- gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
- gpiop->flags &= ~PINMUX_FLAG_DBIT;
- gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
- return;
- }
- }
- k++;
- }
-
- BUG();
-}
-
-static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
-{
- struct pinmux_data_reg *drp;
- int k;
-
- for (k = 0; k < pfc->info->nr_pins; k++) {
- if (pfc->info->pins[k].enum_id == 0)
- continue;
-
- sh_pfc_setup_data_reg(pfc, k);
- }
-
- k = 0;
- while (1) {
- drp = pfc->info->data_regs + k;
-
- if (!drp->reg_width)
- break;
-
- drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
- drp->reg_width);
- k++;
- }
-}
-
-void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
- struct pinmux_data_reg **drp, int *bitp)
-{
- struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio);
- int k, n;
-
- k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
- n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
- *drp = pfc->info->data_regs + k;
- *bitp = n;
-}
-
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
struct pinmux_cfg_reg **crp, int *fieldp,
int *valuep, unsigned long **cntp)
@@ -518,7 +419,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
spin_lock_init(&pfc->lock);
pinctrl_provide_dummies();
- sh_pfc_setup_data_regs(pfc);
/*
* Initialize pinctrl bindings first
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index b8b3e87..434b628 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -46,11 +46,12 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);
-int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos);
-void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
- unsigned long value);
-void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
- struct pinmux_data_reg **drp, int *bitp);
+void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address);
+unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
+ unsigned long reg_width);
+void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
+ unsigned long data);
+
struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
int cfg_mode);
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 806e2dd..027c777 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -36,6 +36,71 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
return gpio_to_pfc_chip(gc)->pfc;
}
+static void gpio_get_data_reg(struct sh_pfc *pfc, unsigned int gpio,
+ struct pinmux_data_reg **dr, unsigned int *bit)
+{
+ struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio);
+
+ *dr = pfc->info->data_regs
+ + ((gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT);
+ *bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
+}
+
+static void gpio_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
+{
+ struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
+ struct pinmux_data_reg *data_reg;
+ int k, n;
+
+ k = 0;
+ while (1) {
+ data_reg = pfc->info->data_regs + k;
+
+ if (!data_reg->reg_width)
+ break;
+
+ data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
+
+ for (n = 0; n < data_reg->reg_width; n++) {
+ if (data_reg->enum_ids[n] == gpiop->enum_id) {
+ gpiop->flags &= ~PINMUX_FLAG_DREG;
+ gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
+ gpiop->flags &= ~PINMUX_FLAG_DBIT;
+ gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
+ return;
+ }
+ }
+ k++;
+ }
+
+ BUG();
+}
+
+static void gpio_setup_data_regs(struct sh_pfc *pfc)
+{
+ struct pinmux_data_reg *drp;
+ int k;
+
+ for (k = 0; k < pfc->info->nr_pins; k++) {
+ if (pfc->info->pins[k].enum_id == 0)
+ continue;
+
+ gpio_setup_data_reg(pfc, k);
+ }
+
+ k = 0;
+ while (1) {
+ drp = pfc->info->data_regs + k;
+
+ if (!drp->reg_width)
+ break;
+
+ drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
+ drp->reg_width);
+ k++;
+ }
+}
+
/* -----------------------------------------------------------------------------
* Pin GPIOs
*/
@@ -59,10 +124,19 @@ static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value)
{
struct pinmux_data_reg *dr;
- int bit;
+ unsigned long pos;
+ unsigned int bit;
- sh_pfc_get_data_reg(pfc, offset, &dr, &bit);
- sh_pfc_write_bit(dr, bit, value);
+ gpio_get_data_reg(pfc, offset, &dr, &bit);
+
+ pos = dr->reg_width - (bit + 1);
+
+ if (value)
+ set_bit(pos, &dr->reg_shadow);
+ else
+ clear_bit(pos, &dr->reg_shadow);
+
+ sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
}
static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
@@ -82,10 +156,14 @@ static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
struct pinmux_data_reg *dr;
- int bit;
+ unsigned long pos;
+ unsigned int bit;
- sh_pfc_get_data_reg(pfc, offset, &dr, &bit);
- return sh_pfc_read_bit(dr, bit);
+ gpio_get_data_reg(pfc, offset, &dr, &bit);
+
+ pos = dr->reg_width - (bit + 1);
+
+ return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
}
static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
@@ -226,6 +304,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
unsigned int i;
int ret;
+ gpio_setup_data_regs(pfc);
+
/* Register the real GPIOs chip. */
chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
if (IS_ERR(chip))
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 043/142] sh-pfc: Don't map data registers individually
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (40 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 042/142] sh-pfc: Move GPIO registers access functions to gpio.c Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 044/142] sh-pfc: Drop unused support for 1:1 physical to virtual memory mappings Simon Horman
` (99 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All data registers are located in the same memory resource. Locate the
mapped resource at initializat time and use it directly instead of
computing a mapped address for each register. This gets rid of the
mapped_reg field of the pinmux_data_reg structure.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 3 +-
drivers/pinctrl/sh-pfc/core.h | 1 -
drivers/pinctrl/sh-pfc/gpio.c | 130 ++++++++++++++++++++++++---------------
drivers/pinctrl/sh-pfc/sh_pfc.h | 1 -
4 files changed, 82 insertions(+), 53 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 49fde28..e847d16 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -55,7 +55,8 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
return 0;
}
-void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address)
+static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
+ unsigned long address)
{
struct sh_pfc_window *window;
int k;
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 434b628..1c3816d 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -46,7 +46,6 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);
-void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address);
unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
unsigned long reg_width);
void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 027c777..b370d28 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -24,6 +24,8 @@
struct sh_pfc_chip {
struct sh_pfc *pfc;
struct gpio_chip gpio_chip;
+
+ struct sh_pfc_window *mem;
};
static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
@@ -46,59 +48,77 @@ static void gpio_get_data_reg(struct sh_pfc *pfc, unsigned int gpio,
*bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
}
-static void gpio_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
+static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip,
+ const struct pinmux_data_reg *dreg)
{
- struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
- struct pinmux_data_reg *data_reg;
- int k, n;
+ void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
- k = 0;
- while (1) {
- data_reg = pfc->info->data_regs + k;
+ return sh_pfc_read_raw_reg(mem, dreg->reg_width);
+}
- if (!data_reg->reg_width)
- break;
+static void gpio_write_data_reg(struct sh_pfc_chip *chip,
+ const struct pinmux_data_reg *dreg,
+ unsigned long value)
+{
+ void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
- data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
+ sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
+}
- for (n = 0; n < data_reg->reg_width; n++) {
- if (data_reg->enum_ids[n] == gpiop->enum_id) {
+static void gpio_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
+{
+ struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
+ const struct pinmux_data_reg *dreg;
+ unsigned int bit;
+ unsigned int i;
+
+ for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) {
+ for (bit = 0; bit < dreg->reg_width; bit++) {
+ if (dreg->enum_ids[bit] == gpiop->enum_id) {
gpiop->flags &= ~PINMUX_FLAG_DREG;
- gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
+ gpiop->flags |= i << PINMUX_FLAG_DREG_SHIFT;
gpiop->flags &= ~PINMUX_FLAG_DBIT;
- gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
+ gpiop->flags |= bit << PINMUX_FLAG_DBIT_SHIFT;
return;
}
}
- k++;
}
BUG();
}
-static void gpio_setup_data_regs(struct sh_pfc *pfc)
+static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
{
- struct pinmux_data_reg *drp;
- int k;
+ struct sh_pfc *pfc = chip->pfc;
+ unsigned long addr = pfc->info->data_regs[0].reg;
+ struct pinmux_data_reg *dreg;
+ unsigned int i;
- for (k = 0; k < pfc->info->nr_pins; k++) {
- if (pfc->info->pins[k].enum_id == 0)
- continue;
+ /* Find the window that contain the GPIO registers. */
+ for (i = 0; i < pfc->num_windows; ++i) {
+ struct sh_pfc_window *window = &pfc->window[i];
- gpio_setup_data_reg(pfc, k);
+ if (addr >= window->phys && addr < window->phys + window->size)
+ break;
}
- k = 0;
- while (1) {
- drp = pfc->info->data_regs + k;
+ if (i == pfc->num_windows)
+ return -EINVAL;
- if (!drp->reg_width)
- break;
+ /* GPIO data registers must be in the first memory resource. */
+ chip->mem = &pfc->window[i];
+
+ for (dreg = pfc->info->data_regs; dreg->reg; ++dreg)
+ dreg->reg_shadow = gpio_read_data_reg(chip, dreg);
+
+ for (i = 0; i < pfc->info->nr_pins; i++) {
+ if (pfc->info->pins[i].enum_id == 0)
+ continue;
- drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
- drp->reg_width);
- k++;
+ gpio_setup_data_reg(pfc, i);
}
+
+ return 0;
}
/* -----------------------------------------------------------------------------
@@ -121,22 +141,23 @@ static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
return pinctrl_free_gpio(offset);
}
-static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value)
+static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
+ int value)
{
- struct pinmux_data_reg *dr;
+ struct pinmux_data_reg *dreg;
unsigned long pos;
unsigned int bit;
- gpio_get_data_reg(pfc, offset, &dr, &bit);
+ gpio_get_data_reg(chip->pfc, offset, &dreg, &bit);
- pos = dr->reg_width - (bit + 1);
+ pos = dreg->reg_width - (bit + 1);
if (value)
- set_bit(pos, &dr->reg_shadow);
+ set_bit(pos, &dreg->reg_shadow);
else
- clear_bit(pos, &dr->reg_shadow);
+ clear_bit(pos, &dreg->reg_shadow);
- sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
+ gpio_write_data_reg(chip, dreg, dreg->reg_shadow);
}
static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
@@ -147,28 +168,28 @@ static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
- gpio_pin_set_value(gpio_to_pfc(gc), offset, value);
+ gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
return pinctrl_gpio_direction_output(offset);
}
static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
{
- struct sh_pfc *pfc = gpio_to_pfc(gc);
- struct pinmux_data_reg *dr;
+ struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
+ struct pinmux_data_reg *dreg;
unsigned long pos;
unsigned int bit;
- gpio_get_data_reg(pfc, offset, &dr, &bit);
+ gpio_get_data_reg(chip->pfc, offset, &dreg, &bit);
- pos = dr->reg_width - (bit + 1);
+ pos = dreg->reg_width - (bit + 1);
- return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
+ return (gpio_read_data_reg(chip, dreg) >> pos) & 1;
}
static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
{
- gpio_pin_set_value(gpio_to_pfc(gc), offset, value);
+ gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
}
static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
@@ -188,10 +209,15 @@ static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
return -ENOSYS;
}
-static void gpio_pin_setup(struct sh_pfc_chip *chip)
+static int gpio_pin_setup(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
struct gpio_chip *gc = &chip->gpio_chip;
+ int ret;
+
+ ret = gpio_setup_data_regs(chip);
+ if (ret < 0)
+ return ret;
gc->request = gpio_pin_request;
gc->free = gpio_pin_free;
@@ -206,6 +232,8 @@ static void gpio_pin_setup(struct sh_pfc_chip *chip)
gc->owner = THIS_MODULE;
gc->base = 0;
gc->ngpio = pfc->nr_pins;
+
+ return 0;
}
/* -----------------------------------------------------------------------------
@@ -252,7 +280,7 @@ static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
spin_unlock_irqrestore(&pfc->lock, flags);
}
-static void gpio_function_setup(struct sh_pfc_chip *chip)
+static int gpio_function_setup(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
struct gpio_chip *gc = &chip->gpio_chip;
@@ -264,6 +292,8 @@ static void gpio_function_setup(struct sh_pfc_chip *chip)
gc->owner = THIS_MODULE;
gc->base = pfc->nr_pins;
gc->ngpio = pfc->info->nr_func_gpios;
+
+ return 0;
}
/* -----------------------------------------------------------------------------
@@ -271,7 +301,7 @@ static void gpio_function_setup(struct sh_pfc_chip *chip)
*/
static struct sh_pfc_chip *
-sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *))
+sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *))
{
struct sh_pfc_chip *chip;
int ret;
@@ -282,7 +312,9 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *))
chip->pfc = pfc;
- setup(chip);
+ ret = setup(chip);
+ if (ret < 0)
+ return ERR_PTR(ret);
ret = gpiochip_add(&chip->gpio_chip);
if (unlikely(ret < 0))
@@ -304,8 +336,6 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
unsigned int i;
int ret;
- gpio_setup_data_regs(pfc);
-
/* Register the real GPIOs chip. */
chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
if (IS_ERR(chip))
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 028e29a..ba3697d 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -110,7 +110,6 @@ struct pinmux_cfg_reg {
struct pinmux_data_reg {
unsigned long reg, reg_width, reg_shadow;
pinmux_enum_t *enum_ids;
- void __iomem *mapped_reg;
};
#define PINMUX_DATA_REG(name, r, r_width) \
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 044/142] sh-pfc: Drop unused support for 1:1 physical to virtual memory mappings
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (41 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 043/142] sh-pfc: Don't map data registers individually Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 045/142] sh-pfc: Don't modify pinmux_data_reg SoC data Simon Horman
` (98 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Now that all PFC platform devices provide memory resources support for
registers without an associated memory resource isn't used anymore. Drop
it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index e847d16..cadfb37 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -30,10 +30,8 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
struct resource *res;
int k;
- if (pdev->num_resources == 0) {
- pfc->num_windows = 0;
- return 0;
- }
+ if (pdev->num_resources == 0)
+ return -EINVAL;
pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
sizeof(*pfc->window), GFP_NOWAIT);
@@ -59,11 +57,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
unsigned long address)
{
struct sh_pfc_window *window;
- int k;
+ unsigned int i;
/* scan through physical windows and convert address */
- for (k = 0; k < pfc->num_windows; k++) {
- window = pfc->window + k;
+ for (i = 0; i < pfc->num_windows; i++) {
+ window = pfc->window + i;
if (address < window->phys)
continue;
@@ -74,8 +72,7 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
return window->virt + (address - window->phys);
}
- /* no windows defined, register must be 1:1 mapped virt:phys */
- return (void __iomem *)address;
+ BUG();
}
struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 045/142] sh-pfc: Don't modify pinmux_data_reg SoC data
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (42 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 044/142] sh-pfc: Drop unused support for 1:1 physical to virtual memory mappings Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 046/142] sh-pfc: Don't modify sh_pfc_pin " Simon Horman
` (97 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The pinmux_data_reg structure supplied in SoC data contains information
about data registers. It's abused to store per-device mapped iomem and
shadow values. Move those fields out of the pinmux_data_reg structure
into the per-device sh_pfc_chip structure.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/gpio.c | 58 +++++++++++++++++++++++++++------------
drivers/pinctrl/sh-pfc/sh_pfc.h | 2 +-
2 files changed, 41 insertions(+), 19 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index b370d28..55eaf75 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -21,11 +21,17 @@
#include "core.h"
+struct sh_pfc_gpio_data_reg {
+ const struct pinmux_data_reg *info;
+ unsigned long shadow;
+};
+
struct sh_pfc_chip {
struct sh_pfc *pfc;
struct gpio_chip gpio_chip;
struct sh_pfc_window *mem;
+ struct sh_pfc_gpio_data_reg *regs;
};
static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
@@ -38,13 +44,16 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
return gpio_to_pfc_chip(gc)->pfc;
}
-static void gpio_get_data_reg(struct sh_pfc *pfc, unsigned int gpio,
- struct pinmux_data_reg **dr, unsigned int *bit)
+static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio,
+ struct sh_pfc_gpio_data_reg **reg,
+ unsigned int *bit)
{
- struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio);
+ struct sh_pfc_pin *gpiop = sh_pfc_get_pin(chip->pfc, gpio);
+ unsigned int reg_idx;
- *dr = pfc->info->data_regs
- + ((gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT);
+ reg_idx = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
+
+ *reg = &chip->regs[reg_idx];
*bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
}
@@ -91,7 +100,7 @@ static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
unsigned long addr = pfc->info->data_regs[0].reg;
- struct pinmux_data_reg *dreg;
+ const struct pinmux_data_reg *dreg;
unsigned int i;
/* Find the window that contain the GPIO registers. */
@@ -108,8 +117,21 @@ static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
/* GPIO data registers must be in the first memory resource. */
chip->mem = &pfc->window[i];
- for (dreg = pfc->info->data_regs; dreg->reg; ++dreg)
- dreg->reg_shadow = gpio_read_data_reg(chip, dreg);
+ /* Count the number of data registers, allocate memory and initialize
+ * them.
+ */
+ for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
+ ;
+
+ chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs),
+ GFP_KERNEL);
+ if (chip->regs == NULL)
+ return -ENOMEM;
+
+ for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
+ chip->regs[i].info = dreg;
+ chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
+ }
for (i = 0; i < pfc->info->nr_pins; i++) {
if (pfc->info->pins[i].enum_id == 0)
@@ -144,20 +166,20 @@ static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
int value)
{
- struct pinmux_data_reg *dreg;
+ struct sh_pfc_gpio_data_reg *reg;
unsigned long pos;
unsigned int bit;
- gpio_get_data_reg(chip->pfc, offset, &dreg, &bit);
+ gpio_get_data_reg(chip, offset, ®, &bit);
- pos = dreg->reg_width - (bit + 1);
+ pos = reg->info->reg_width - (bit + 1);
if (value)
- set_bit(pos, &dreg->reg_shadow);
+ set_bit(pos, ®->shadow);
else
- clear_bit(pos, &dreg->reg_shadow);
+ clear_bit(pos, ®->shadow);
- gpio_write_data_reg(chip, dreg, dreg->reg_shadow);
+ gpio_write_data_reg(chip, reg->info, reg->shadow);
}
static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
@@ -176,15 +198,15 @@ static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
- struct pinmux_data_reg *dreg;
+ struct sh_pfc_gpio_data_reg *reg;
unsigned long pos;
unsigned int bit;
- gpio_get_data_reg(chip->pfc, offset, &dreg, &bit);
+ gpio_get_data_reg(chip, offset, ®, &bit);
- pos = dreg->reg_width - (bit + 1);
+ pos = reg->info->reg_width - (bit + 1);
- return (gpio_read_data_reg(chip, dreg) >> pos) & 1;
+ return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
}
static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index ba3697d..e6a51a9 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -108,7 +108,7 @@ struct pinmux_cfg_reg {
.enum_ids = (pinmux_enum_t [])
struct pinmux_data_reg {
- unsigned long reg, reg_width, reg_shadow;
+ unsigned long reg, reg_width;
pinmux_enum_t *enum_ids;
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 046/142] sh-pfc: Don't modify sh_pfc_pin SoC data
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (43 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 045/142] sh-pfc: Don't modify pinmux_data_reg SoC data Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 047/142] sh-pfc: Remove configuration dry-run and free Simon Horman
` (96 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The sh_pfc_pin structure supplied in SoC data contains information about
pin configuration and name. It's abused to store GPIO data registers
information and pin config type. Move those fields out of the
pinmux_data_reg structure into the new sh_pfc_gpio_pin and
sh_pfc_pin_config structures.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 14 +++------
drivers/pinctrl/sh-pfc/core.h | 2 +-
drivers/pinctrl/sh-pfc/gpio.c | 47 ++++++++++++++++++------------
drivers/pinctrl/sh-pfc/pinctrl.c | 59 ++++++++++++++++++++++----------------
drivers/pinctrl/sh-pfc/sh_pfc.h | 7 -----
5 files changed, 68 insertions(+), 61 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index cadfb37..1973501 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -75,26 +75,25 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
BUG();
}
-struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin)
+int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
{
unsigned int offset;
unsigned int i;
if (pfc->info->ranges == NULL)
- return &pfc->info->pins[pin];
+ return pin;
for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
const struct pinmux_range *range = &pfc->info->ranges[i];
if (pin <= range->end)
return pin >= range->begin
- ? &pfc->info->pins[offset + pin - range->begin]
- : NULL;
+ ? offset + pin - range->begin : -1;
offset += range->end - range->begin + 1;
}
- return NULL;
+ return -1;
}
static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
@@ -393,11 +392,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
struct sh_pfc *pfc;
int ret;
- /*
- * Ensure that the type encoding fits
- */
- BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
-
info = pdev->id_entry->driver_data
? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
if (info == NULL)
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 1c3816d..6db54aa 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -51,7 +51,7 @@ unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
unsigned long data);
-struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin);
+int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
int cfg_mode);
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 55eaf75..ce074b2 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -26,12 +26,18 @@ struct sh_pfc_gpio_data_reg {
unsigned long shadow;
};
+struct sh_pfc_gpio_pin {
+ u8 dbit;
+ u8 dreg;
+};
+
struct sh_pfc_chip {
- struct sh_pfc *pfc;
- struct gpio_chip gpio_chip;
+ struct sh_pfc *pfc;
+ struct gpio_chip gpio_chip;
- struct sh_pfc_window *mem;
+ struct sh_pfc_window *mem;
struct sh_pfc_gpio_data_reg *regs;
+ struct sh_pfc_gpio_pin *pins;
};
static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
@@ -48,13 +54,11 @@ static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio,
struct sh_pfc_gpio_data_reg **reg,
unsigned int *bit)
{
- struct sh_pfc_pin *gpiop = sh_pfc_get_pin(chip->pfc, gpio);
- unsigned int reg_idx;
+ int idx = sh_pfc_get_pin_index(chip->pfc, gpio);
+ struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
- reg_idx = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
-
- *reg = &chip->regs[reg_idx];
- *bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
+ *reg = &chip->regs[gpio_pin->dreg];
+ *bit = gpio_pin->dbit;
}
static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip,
@@ -74,20 +78,20 @@ static void gpio_write_data_reg(struct sh_pfc_chip *chip,
sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
}
-static void gpio_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
+static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
{
- struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
+ struct sh_pfc *pfc = chip->pfc;
+ struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio];
+ struct sh_pfc_pin *pin = &pfc->info->pins[gpio];
const struct pinmux_data_reg *dreg;
unsigned int bit;
unsigned int i;
for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) {
for (bit = 0; bit < dreg->reg_width; bit++) {
- if (dreg->enum_ids[bit] == gpiop->enum_id) {
- gpiop->flags &= ~PINMUX_FLAG_DREG;
- gpiop->flags |= i << PINMUX_FLAG_DREG_SHIFT;
- gpiop->flags &= ~PINMUX_FLAG_DBIT;
- gpiop->flags |= bit << PINMUX_FLAG_DBIT_SHIFT;
+ if (dreg->enum_ids[bit] == pin->enum_id) {
+ gpio_pin->dreg = i;
+ gpio_pin->dbit = bit;
return;
}
}
@@ -137,7 +141,7 @@ static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
if (pfc->info->pins[i].enum_id == 0)
continue;
- gpio_setup_data_reg(pfc, i);
+ gpio_setup_data_reg(chip, i);
}
return 0;
@@ -150,9 +154,9 @@ static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
- struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
+ int idx = sh_pfc_get_pin_index(pfc, offset);
- if (pin == NULL || pin->enum_id == 0)
+ if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
return -EINVAL;
return pinctrl_request_gpio(offset);
@@ -237,6 +241,11 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
struct gpio_chip *gc = &chip->gpio_chip;
int ret;
+ chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins),
+ GFP_KERNEL);
+ if (chip->pins == NULL)
+ return -ENOMEM;
+
ret = gpio_setup_data_regs(chip);
if (ret < 0)
return ret;
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 3e49bf0..ef5cf5d 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -25,6 +25,10 @@
#include "core.h"
+struct sh_pfc_pin_config {
+ u32 type;
+};
+
struct sh_pfc_pinctrl {
struct pinctrl_dev *pctl;
struct pinctrl_desc pctl_desc;
@@ -32,6 +36,7 @@ struct sh_pfc_pinctrl {
struct sh_pfc *pfc;
struct pinctrl_pin_desc *pins;
+ struct sh_pfc_pin_config *configs;
};
static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
@@ -148,30 +153,30 @@ static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
spin_unlock_irqrestore(&pfc->lock, flags);
}
-static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
+static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset,
int new_type)
{
- struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
+ struct sh_pfc *pfc = pmx->pfc;
+ int idx = sh_pfc_get_pin_index(pfc, offset);
+ struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
+ struct sh_pfc_pin *pin = &pfc->info->pins[idx];
unsigned int mark = pin->enum_id;
unsigned long flags;
- int pinmux_type;
int ret = -EINVAL;
spin_lock_irqsave(&pfc->lock, flags);
- pinmux_type = pin->flags & PINMUX_FLAG_TYPE;
-
/*
* See if the present config needs to first be de-configured.
*/
- switch (pinmux_type) {
+ switch (cfg->type) {
case PINMUX_TYPE_GPIO:
break;
case PINMUX_TYPE_OUTPUT:
case PINMUX_TYPE_INPUT:
case PINMUX_TYPE_INPUT_PULLUP:
case PINMUX_TYPE_INPUT_PULLDOWN:
- sh_pfc_config_mux(pfc, mark, pinmux_type, GPIO_CFG_FREE);
+ sh_pfc_config_mux(pfc, mark, cfg->type, GPIO_CFG_FREE);
break;
default:
goto err;
@@ -189,8 +194,7 @@ static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_REQ) != 0)
goto err;
- pin->flags &= ~PINMUX_FLAG_TYPE;
- pin->flags |= new_type;
+ cfg->type = new_type;
ret = 0;
@@ -206,22 +210,21 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
- struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
+ int idx = sh_pfc_get_pin_index(pfc, offset);
+ struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
unsigned long flags;
- int ret, pinmux_type;
+ int ret;
spin_lock_irqsave(&pfc->lock, flags);
- pinmux_type = pin->flags & PINMUX_FLAG_TYPE;
-
- switch (pinmux_type) {
+ switch (cfg->type) {
case PINMUX_TYPE_GPIO:
case PINMUX_TYPE_INPUT:
case PINMUX_TYPE_OUTPUT:
break;
case PINMUX_TYPE_FUNCTION:
default:
- pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
+ pr_err("Unsupported mux type (%d), bailing...\n", cfg->type);
ret = -ENOTSUPP;
goto err;
}
@@ -240,15 +243,14 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
- struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
+ int idx = sh_pfc_get_pin_index(pfc, offset);
+ struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
+ struct sh_pfc_pin *pin = &pfc->info->pins[idx];
unsigned long flags;
- int pinmux_type;
spin_lock_irqsave(&pfc->lock, flags);
- pinmux_type = pin->flags & PINMUX_FLAG_TYPE;
-
- sh_pfc_config_mux(pfc, pin->enum_id, pinmux_type, GPIO_CFG_FREE);
+ sh_pfc_config_mux(pfc, pin->enum_id, cfg->type, GPIO_CFG_FREE);
spin_unlock_irqrestore(&pfc->lock, flags);
}
@@ -260,7 +262,7 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
- return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
+ return sh_pfc_reconfig_pin(pmx, offset, type);
}
static const struct pinmux_ops sh_pfc_pinmux_ops = {
@@ -279,9 +281,10 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
- struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, _pin);
+ int idx = sh_pfc_get_pin_index(pfc, _pin);
+ struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
- *config = pin->flags & PINMUX_FLAG_TYPE;
+ *config = cfg->type;
return 0;
}
@@ -295,7 +298,7 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
if (config >= PINMUX_FLAG_TYPE)
return -EINVAL;
- return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
+ return sh_pfc_reconfig_pin(pmx, pin, config);
}
static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
@@ -351,17 +354,25 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
if (unlikely(!pmx->pins))
return -ENOMEM;
+ pmx->configs = devm_kzalloc(pfc->dev,
+ sizeof(*pmx->configs) * pfc->info->nr_pins,
+ GFP_KERNEL);
+ if (unlikely(!pmx->configs))
+ return -ENOMEM;
+
for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
const struct pinmux_range *range = &ranges[i];
unsigned int number;
for (number = range->begin; number <= range->end;
number++, nr_pins++) {
+ struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
struct sh_pfc_pin *info = &pfc->info->pins[nr_pins];
pin->number = number;
pin->name = info->name;
+ cfg->type = PINMUX_TYPE_GPIO;
}
}
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index e6a51a9..6a4a62f 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -31,14 +31,8 @@ enum {
PINMUX_FLAG_TYPE, /* must be last */
};
-#define PINMUX_FLAG_DBIT_SHIFT 5
-#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT)
-#define PINMUX_FLAG_DREG_SHIFT 10
-#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
-
struct sh_pfc_pin {
const pinmux_enum_t enum_id;
- unsigned short flags;
const char *name;
};
@@ -79,7 +73,6 @@ struct pinmux_func {
[gpio] = { \
.name = __stringify(gpio), \
.enum_id = data_or_mark, \
- .flags = PINMUX_TYPE_GPIO \
}
#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
[gpio - (base)] = { \
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 047/142] sh-pfc: Remove configuration dry-run and free
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (44 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 046/142] sh-pfc: Don't modify sh_pfc_pin " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 048/142] sh-pfc: Constify all SoC data Simon Horman
` (95 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The purpose of the dry-run is to ensure that a pin about to be
configured isn't in use. However, the current implementation is a no-op.
This proves that the dry-run isn't essential. Remove it.
Freeing configuration then becomes a no-op as well. Remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 50 ++++++--------------------------------
drivers/pinctrl/sh-pfc/core.h | 3 +--
drivers/pinctrl/sh-pfc/gpio.c | 14 +----------
drivers/pinctrl/sh-pfc/pinctrl.c | 48 ++----------------------------------
drivers/pinctrl/sh-pfc/sh_pfc.h | 5 +---
5 files changed, 12 insertions(+), 108 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 1973501..e2864ec 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -163,22 +163,6 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
}
}
-static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
- struct pinmux_cfg_reg *crp,
- unsigned long field)
-{
- void __iomem *mapped_reg;
- unsigned long mask, pos;
-
- sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
-
- pr_debug("read_reg: addr = %lx, field = %ld, "
- "r_width = %ld, f_width = %ld\n",
- crp->reg, field, crp->reg_width, crp->field_width);
-
- return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
-}
-
static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
struct pinmux_cfg_reg *crp,
unsigned long field, unsigned long value)
@@ -209,7 +193,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
struct pinmux_cfg_reg **crp, int *fieldp,
- int *valuep, unsigned long **cntp)
+ int *valuep)
{
struct pinmux_cfg_reg *config_reg;
unsigned long r_width, f_width, curr_width, ncomb;
@@ -239,7 +223,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
*crp = config_reg;
*fieldp = m;
*valuep = n;
- *cntp = &config_reg->cnt[m];
return 0;
}
}
@@ -274,14 +257,12 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
return -1;
}
-int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
- int cfg_mode)
+int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
struct pinmux_cfg_reg *cr = NULL;
pinmux_enum_t enum_id;
struct pinmux_range *range;
int in_range, pos, field, value;
- unsigned long *cntp;
switch (pinmux_type) {
@@ -306,7 +287,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
break;
default:
- goto out_err;
+ return -1;
}
pos = 0;
@@ -316,7 +297,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
while (1) {
pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
if (pos <= 0)
- goto out_err;
+ return -1;
if (!enum_id)
break;
@@ -360,30 +341,13 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
continue;
if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
- &field, &value, &cntp) != 0)
- goto out_err;
-
- switch (cfg_mode) {
- case GPIO_CFG_DRYRUN:
- if (!*cntp ||
- (sh_pfc_read_config_reg(pfc, cr, field) != value))
- continue;
- break;
-
- case GPIO_CFG_REQ:
- sh_pfc_write_config_reg(pfc, cr, field, value);
- *cntp = *cntp + 1;
- break;
+ &field, &value) != 0)
+ return -1;
- case GPIO_CFG_FREE:
- *cntp = *cntp - 1;
- break;
- }
+ sh_pfc_write_config_reg(pfc, cr, field, value);
}
return 0;
- out_err:
- return -1;
}
static int sh_pfc_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 6db54aa..7b2b4f0 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -52,8 +52,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
unsigned long data);
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
-int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
- int cfg_mode);
+int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
extern struct sh_pfc_soc_info r8a7740_pinmux_info;
extern struct sh_pfc_soc_info r8a7779_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index ce074b2..761a0da 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -285,10 +285,7 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
spin_lock_irqsave(&pfc->lock, flags);
- if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_DRYRUN))
- goto done;
-
- if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_REQ))
+ if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION))
goto done;
ret = 0;
@@ -300,15 +297,6 @@ done:
static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
{
- struct sh_pfc *pfc = gpio_to_pfc(gc);
- unsigned int mark = pfc->info->func_gpios[offset].enum_id;
- unsigned long flags;
-
- spin_lock_irqsave(&pfc->lock, flags);
-
- sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE);
-
- spin_unlock_irqrestore(&pfc->lock, flags);
}
static int gpio_function_setup(struct sh_pfc_chip *chip)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index ef5cf5d..9978ad1 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -119,12 +119,7 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
spin_lock_irqsave(&pfc->lock, flags);
for (i = 0; i < grp->nr_pins; ++i) {
- if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
- GPIO_CFG_DRYRUN))
- goto done;
-
- if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
- GPIO_CFG_REQ))
+ if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION))
goto done;
}
@@ -138,19 +133,6 @@ done:
static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
- struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- struct sh_pfc *pfc = pmx->pfc;
- const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
- unsigned long flags;
- unsigned int i;
-
- spin_lock_irqsave(&pfc->lock, flags);
-
- for (i = 0; i < grp->nr_pins; ++i)
- sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION,
- GPIO_CFG_FREE);
-
- spin_unlock_irqrestore(&pfc->lock, flags);
}
static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset,
@@ -166,32 +148,18 @@ static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset,
spin_lock_irqsave(&pfc->lock, flags);
- /*
- * See if the present config needs to first be de-configured.
- */
switch (cfg->type) {
case PINMUX_TYPE_GPIO:
- break;
case PINMUX_TYPE_OUTPUT:
case PINMUX_TYPE_INPUT:
case PINMUX_TYPE_INPUT_PULLUP:
case PINMUX_TYPE_INPUT_PULLDOWN:
- sh_pfc_config_mux(pfc, mark, cfg->type, GPIO_CFG_FREE);
break;
default:
goto err;
}
- /*
- * Dry run
- */
- if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_DRYRUN) != 0)
- goto err;
-
- /*
- * Request
- */
- if (sh_pfc_config_mux(pfc, mark, new_type, GPIO_CFG_REQ) != 0)
+ if (sh_pfc_config_mux(pfc, mark, new_type) != 0)
goto err;
cfg->type = new_type;
@@ -241,18 +209,6 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
- struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- struct sh_pfc *pfc = pmx->pfc;
- int idx = sh_pfc_get_pin_index(pfc, offset);
- struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
- struct sh_pfc_pin *pin = &pfc->info->pins[idx];
- unsigned long flags;
-
- spin_lock_irqsave(&pfc->lock, flags);
-
- sh_pfc_config_mux(pfc, pin->enum_id, cfg->type, GPIO_CFG_FREE);
-
- spin_unlock_irqrestore(&pfc->lock, flags);
}
static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 6a4a62f..19da3b7 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -84,19 +84,16 @@ struct pinmux_func {
struct pinmux_cfg_reg {
unsigned long reg, reg_width, field_width;
- unsigned long *cnt;
pinmux_enum_t *enum_ids;
unsigned long *var_field_width;
};
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
.reg = r, .reg_width = r_width, .field_width = f_width, \
- .cnt = (unsigned long [r_width / f_width]) {}, \
.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
.reg = r, .reg_width = r_width, \
- .cnt = (unsigned long [r_width]) {}, \
.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
.enum_ids = (pinmux_enum_t [])
@@ -155,7 +152,7 @@ struct sh_pfc_soc_info {
unsigned long unlock_reg;
};
-enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
+enum { GPIO_CFG_REQ, GPIO_CFG_FREE };
/* helper macro for port */
#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 048/142] sh-pfc: Constify all SoC data
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (45 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 047/142] sh-pfc: Remove configuration dry-run and free Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 049/142] sh-pfc: Use proper error codes Simon Horman
` (94 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
None of the SoC data need to be modified. Constify it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 19 ++++++++++---------
drivers/pinctrl/sh-pfc/core.h | 34 +++++++++++++++++-----------------
drivers/pinctrl/sh-pfc/gpio.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 12 ++++++------
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-sh7203.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-sh7264.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-sh7269.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-sh7372.c | 12 ++++++------
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 14 +++++++-------
drivers/pinctrl/sh-pfc/pfc-sh7720.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-sh7722.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-sh7723.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-sh7724.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-sh7734.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-sh7757.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-sh7785.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-sh7786.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pfc-shx3.c | 10 +++++-----
drivers/pinctrl/sh-pfc/pinctrl.c | 5 +++--
drivers/pinctrl/sh-pfc/sh_pfc.h | 20 ++++++++++----------
21 files changed, 125 insertions(+), 123 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index e2864ec..3a94946 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -96,7 +96,8 @@ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
return -1;
}
-static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
+static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,
+ const struct pinmux_range *r)
{
if (enum_id < r->begin)
return 0;
@@ -142,7 +143,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
}
static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
- struct pinmux_cfg_reg *crp,
+ const struct pinmux_cfg_reg *crp,
unsigned long in_pos,
void __iomem **mapped_regp,
unsigned long *maskp,
@@ -164,7 +165,7 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
}
static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
- struct pinmux_cfg_reg *crp,
+ const struct pinmux_cfg_reg *crp,
unsigned long field, unsigned long value)
{
void __iomem *mapped_reg;
@@ -192,10 +193,10 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
}
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
- struct pinmux_cfg_reg **crp, int *fieldp,
+ const struct pinmux_cfg_reg **crp, int *fieldp,
int *valuep)
{
- struct pinmux_cfg_reg *config_reg;
+ const struct pinmux_cfg_reg *config_reg;
unsigned long r_width, f_width, curr_width, ncomb;
int k, m, n, pos, bit_pos;
@@ -238,7 +239,7 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
pinmux_enum_t *enum_idp)
{
- pinmux_enum_t *data = pfc->info->gpio_data;
+ const pinmux_enum_t *data = pfc->info->gpio_data;
int k;
if (pos) {
@@ -259,9 +260,9 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
- struct pinmux_cfg_reg *cr = NULL;
+ const struct pinmux_cfg_reg *cr = NULL;
pinmux_enum_t enum_id;
- struct pinmux_range *range;
+ const struct pinmux_range *range;
int in_range, pos, field, value;
switch (pinmux_type) {
@@ -352,7 +353,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
static int sh_pfc_probe(struct platform_device *pdev)
{
- struct sh_pfc_soc_info *info;
+ const struct sh_pfc_soc_info *info;
struct sh_pfc *pfc;
int ret;
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 7b2b4f0..763d717 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -26,7 +26,7 @@ struct sh_pfc_pinctrl;
struct sh_pfc {
struct device *dev;
- struct sh_pfc_soc_info *info;
+ const struct sh_pfc_soc_info *info;
spinlock_t lock;
unsigned int num_windows;
@@ -54,21 +54,21 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
-extern struct sh_pfc_soc_info r8a7740_pinmux_info;
-extern struct sh_pfc_soc_info r8a7779_pinmux_info;
-extern struct sh_pfc_soc_info sh7203_pinmux_info;
-extern struct sh_pfc_soc_info sh7264_pinmux_info;
-extern struct sh_pfc_soc_info sh7269_pinmux_info;
-extern struct sh_pfc_soc_info sh7372_pinmux_info;
-extern struct sh_pfc_soc_info sh73a0_pinmux_info;
-extern struct sh_pfc_soc_info sh7720_pinmux_info;
-extern struct sh_pfc_soc_info sh7722_pinmux_info;
-extern struct sh_pfc_soc_info sh7723_pinmux_info;
-extern struct sh_pfc_soc_info sh7724_pinmux_info;
-extern struct sh_pfc_soc_info sh7734_pinmux_info;
-extern struct sh_pfc_soc_info sh7757_pinmux_info;
-extern struct sh_pfc_soc_info sh7785_pinmux_info;
-extern struct sh_pfc_soc_info sh7786_pinmux_info;
-extern struct sh_pfc_soc_info shx3_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
+extern const struct sh_pfc_soc_info sh7203_pinmux_info;
+extern const struct sh_pfc_soc_info sh7264_pinmux_info;
+extern const struct sh_pfc_soc_info sh7269_pinmux_info;
+extern const struct sh_pfc_soc_info sh7372_pinmux_info;
+extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
+extern const struct sh_pfc_soc_info sh7720_pinmux_info;
+extern const struct sh_pfc_soc_info sh7722_pinmux_info;
+extern const struct sh_pfc_soc_info sh7723_pinmux_info;
+extern const struct sh_pfc_soc_info sh7724_pinmux_info;
+extern const struct sh_pfc_soc_info sh7734_pinmux_info;
+extern const struct sh_pfc_soc_info sh7757_pinmux_info;
+extern const struct sh_pfc_soc_info sh7785_pinmux_info;
+extern const struct sh_pfc_soc_info sh7786_pinmux_info;
+extern const struct sh_pfc_soc_info shx3_pinmux_info;
#endif /* __SH_PFC_CORE_H__ */
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 761a0da..480beae 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -82,7 +82,7 @@ static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
{
struct sh_pfc *pfc = chip->pfc;
struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio];
- struct sh_pfc_pin *pin = &pfc->info->pins[gpio];
+ const struct sh_pfc_pin *pin = &pfc->info->pins[gpio];
const struct pinmux_data_reg *dreg;
unsigned int bit;
unsigned int i;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index fd91381..de13348 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -577,7 +577,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
/* I/O and Pull U/D */
@@ -1660,7 +1660,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* IRQ */
GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
GPIO_FN(IRQ1),
@@ -2128,7 +2128,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(TRACEAUD_FROM_MEMC),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
PORTCR(2, 0xe6050002), /* PORT2CR */
@@ -2442,7 +2442,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
@@ -2546,7 +2546,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-static struct pinmux_irq pinmux_irqs[] = {
+static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(evt2irq(0x0200), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */
PINMUX_IRQ(evt2irq(0x0220), GPIO_PORT20), /* IRQ1A */
PINMUX_IRQ(evt2irq(0x0240), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */
@@ -2581,7 +2581,7 @@ static struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(evt2irq(0x33E0), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */
};
-struct sh_pfc_soc_info r8a7740_pinmux_info = {
+const struct sh_pfc_soc_info r8a7740_pinmux_info = {
.name = "r8a7740_pfc",
.input = { PINMUX_INPUT_BEGIN,
PINMUX_INPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index e9a7ead..eb56858 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -631,7 +631,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(AVS1_MARK, FN_AVS1),
@@ -1438,7 +1438,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
GPIO_FN(A19),
@@ -1710,7 +1710,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
GP_0_31_FN, FN_IP3_31_29,
GP_0_30_FN, FN_IP3_26_24,
@@ -2571,7 +2571,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
{ PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
{ PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
@@ -2587,7 +2587,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info r8a7779_pinmux_info = {
+const struct sh_pfc_soc_info r8a7779_pinmux_info = {
.name = "r8a7779_pfc",
.unlock_reg = 0xfffc0000, /* PMMR */
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index fc4a128..f63d51d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -272,7 +272,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* PA */
PINMUX_DATA(PA7_DATA, PA7_IN),
@@ -819,7 +819,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
GPIO_FN(PINT7_PB),
GPIO_FN(PINT6_PB),
@@ -1077,7 +1077,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(LCD_DATA0),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) {
0, 0,
0, 0,
@@ -1529,7 +1529,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) {
0, 0, 0, 0,
0, 0, 0, 0,
@@ -1575,7 +1575,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info sh7203_pinmux_info = {
+const struct sh_pfc_soc_info sh7203_pinmux_info = {
.name = "sh7203_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index c03365c..2846752 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -604,7 +604,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* Port A */
PINMUX_DATA(PA3_DATA, PA3_IN),
@@ -1220,7 +1220,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
GPIO_FN(PINT7_PG),
GPIO_FN(PINT6_PG),
@@ -1470,7 +1470,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(LCD_M_DISP),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -2036,7 +2036,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
0, 0, 0, 0, 0, 0, 0, PA3_DATA,
0, 0, 0, 0, 0, 0, 0, PA2_DATA }
@@ -2114,7 +2114,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ }
};
-struct sh_pfc_soc_info sh7264_pinmux_info = {
+const struct sh_pfc_soc_info sh7264_pinmux_info = {
.name = "sh7264_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index 1fa0950..4c401a7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -781,7 +781,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* Port A */
PINMUX_DATA(PA1_DATA, PA1_IN),
@@ -1617,7 +1617,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
GPIO_FN(IRQ7_PG),
GPIO_FN(IRQ6_PG),
@@ -1949,7 +1949,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(LCD_M_DISP),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* "name" addr register_size Field_Width */
/* where Field_Width is 1 for single mode registers or 4 for upto 16
@@ -2738,7 +2738,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
0, 0, 0, 0, 0, 0, 0, PA1_DATA,
0, 0, 0, 0, 0, 0, 0, PA0_DATA }
@@ -2817,7 +2817,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ }
};
-struct sh_pfc_soc_info sh7269_pinmux_info = {
+const struct sh_pfc_soc_info sh7269_pinmux_info = {
.name = "sh7269_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 847e0cd..6b56344 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -368,7 +368,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
@@ -935,7 +935,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* IRQ */
GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1),
GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8),
@@ -1202,7 +1202,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SDENC_DV_CLKI),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xE6051000), /* PORT0CR */
PORTCR(1, 0xE6051001), /* PORT1CR */
PORTCR(2, 0xE6051002), /* PORT2CR */
@@ -1474,7 +1474,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
@@ -1599,7 +1599,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
-static struct pinmux_irq pinmux_irqs[] = {
+static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
@@ -1634,7 +1634,7 @@ static struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
};
-struct sh_pfc_soc_info sh7372_pinmux_info = {
+const struct sh_pfc_soc_info sh7372_pinmux_info = {
.name = "sh7372_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 9cef0d8..3200fc2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -509,7 +509,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
/* Table 25-1 (I/O and Pull U/D) */
@@ -1543,7 +1543,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
};
-static struct pinmux_range pinmux_ranges[] = {
+static const struct pinmux_range pinmux_ranges[] = {
{.begin = 0, .end = 118,},
{.begin = 128, .end = 164,},
{.begin = 192, .end = 282,},
@@ -1552,7 +1552,7 @@ static struct pinmux_range pinmux_ranges[] = {
#define PINMUX_FN_BASE GPIO_FN_VBUS_0
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* Table 25-1 (Functions 0-7) */
GPIO_FN(VBUS_0),
GPIO_FN(GPI0),
@@ -2228,7 +2228,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(FSIAISLD_PU),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
PORTCR(2, 0xe6050002), /* PORT2CR */
@@ -2636,7 +2636,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
@@ -2744,7 +2744,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
-static struct pinmux_irq pinmux_irqs[] = {
+static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(EXT_IRQ16H(19), 9),
PINMUX_IRQ(EXT_IRQ16L(1), 10),
PINMUX_IRQ(EXT_IRQ16L(0), 11),
@@ -2779,7 +2779,7 @@ static struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(EXT_IRQ16L(9), 308),
};
-struct sh_pfc_soc_info sh73a0_pinmux_info = {
+const struct sh_pfc_soc_info sh73a0_pinmux_info = {
.name = "sh73a0_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index 0b3078b..52e9f6b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -262,7 +262,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* PTA GPIO */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
@@ -763,7 +763,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* BSC */
GPIO_FN(D31),
GPIO_FN(D30),
@@ -957,7 +957,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(STATUS1),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
@@ -1141,7 +1141,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050140, 8) {
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1217,7 +1217,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info sh7720_pinmux_info = {
+const struct sh_pfc_soc_info sh7720_pinmux_info = {
.name = "sh7720_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index 3a8d95f..3203438 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -296,7 +296,7 @@ enum {
PINMUX_FUNCTION_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* PTA */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD),
@@ -986,7 +986,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* SCIF0 */
GPIO_FN(SCIF0_TXD),
GPIO_FN(SCIF0_RXD),
@@ -1268,7 +1268,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(KEYOUT5_IN5),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN,
VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN,
@@ -1664,7 +1664,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1760,7 +1760,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info sh7722_pinmux_info = {
+const struct sh_pfc_soc_info sh7722_pinmux_info = {
.name = "sh7722_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index d8797ff..07ad1d8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -350,7 +350,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* PTA GPIO */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
@@ -1143,7 +1143,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* SCIF0 */
GPIO_FN(SCIF0_PTT_TXD),
GPIO_FN(SCIF0_PTT_RXD),
@@ -1515,7 +1515,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(IDEA0),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
PTA7_FN, PTA7_OUT, 0, PTA7_IN,
PTA6_FN, PTA6_OUT, 0, PTA6_IN,
@@ -1789,7 +1789,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1885,7 +1885,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info sh7723_pinmux_info = {
+const struct sh_pfc_soc_info sh7723_pinmux_info = {
.name = "sh7723_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 40f430b..35e5516 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -572,7 +572,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* PTA GPIO */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
@@ -1422,7 +1422,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* BSC */
GPIO_FN(D31),
GPIO_FN(D30),
@@ -1787,7 +1787,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(INTC_IRQ0),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
@@ -2111,7 +2111,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -2207,7 +2207,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info sh7724_pinmux_info = {
+const struct sh_pfc_soc_info sh7724_pinmux_info = {
.name = "sh7724_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index 99ea220..2fd5b7d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -592,7 +592,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),
@@ -1373,7 +1373,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
@@ -1652,7 +1652,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) {
GP_0_31_FN, FN_IP2_2_0,
GP_0_30_FN, FN_IP1_31_29,
@@ -2421,7 +2421,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
/* GPIO 0 - 5*/
{ PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } },
{ PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } },
@@ -2438,7 +2438,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info sh7734_pinmux_info = {
+const struct sh_pfc_soc_info sh7734_pinmux_info = {
.name = "sh7734_pfc",
.unlock_reg = 0xFFFC0000,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index e81ab0e..e074230 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -526,7 +526,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* PTA GPIO */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
@@ -1374,7 +1374,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* PTA (mobule: LBSC, RGMII) */
GPIO_FN(BS),
GPIO_FN(RDWR),
@@ -1726,7 +1726,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(ON_DQ0),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
@@ -2156,7 +2156,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -2264,7 +2264,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info sh7757_pinmux_info = {
+const struct sh_pfc_soc_info sh7757_pinmux_info = {
.name = "sh7757_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index 6049f59..c176b79 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -355,7 +355,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* PA GPIO */
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -849,7 +849,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* FN */
GPIO_FN(D63_AD31),
GPIO_FN(D62_AD30),
@@ -1018,7 +1018,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(IRQOUT),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) {
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -1218,7 +1218,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xffe70020, 8) {
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
@@ -1286,7 +1286,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info sh7785_pinmux_info = {
+const struct sh_pfc_soc_info sh7785_pinmux_info = {
.name = "sh7785_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index 526e784..8ae0e32 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -191,7 +191,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* PA GPIO */
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -509,7 +509,7 @@ static struct sh_pfc_pin pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
-static struct pinmux_func pinmux_func_gpios[] = {
+static const struct pinmux_func pinmux_func_gpios[] = {
/* FN */
GPIO_FN(CDE),
GPIO_FN(ETH_MAGIC),
@@ -649,7 +649,7 @@ static struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(FSE),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -779,7 +779,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
@@ -819,7 +819,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info sh7786_pinmux_info = {
+const struct sh_pfc_soc_info sh7786_pinmux_info = {
.name = "sh7786_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index 93d60cd..6594c8c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -147,7 +147,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t shx3_pinmux_data[] = {
+static const pinmux_enum_t shx3_pinmux_data[] = {
/* PA GPIO */
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -388,7 +388,7 @@ static struct sh_pfc_pin shx3_pinmux_pins[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(shx3_pinmux_pins)
-static struct pinmux_func shx3_pinmux_func_gpios[] = {
+static const struct pinmux_func shx3_pinmux_func_gpios[] = {
/* FN */
GPIO_FN(D31),
GPIO_FN(D30),
@@ -454,7 +454,7 @@ static struct pinmux_func shx3_pinmux_func_gpios[] = {
GPIO_FN(IRQOUT),
};
-static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -530,7 +530,7 @@ static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
{ },
};
-static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
+static const struct pinmux_data_reg shx3_pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
0, 0, 0, 0, 0, 0, 0, 0,
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
@@ -566,7 +566,7 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info shx3_pinmux_info = {
+const struct sh_pfc_soc_info shx3_pinmux_info = {
.name = "shx3_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 9978ad1..b4960df 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -141,7 +141,7 @@ static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset,
struct sh_pfc *pfc = pmx->pfc;
int idx = sh_pfc_get_pin_index(pfc, offset);
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
- struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+ const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
unsigned int mark = pin->enum_id;
unsigned long flags;
int ret = -EINVAL;
@@ -324,7 +324,8 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
number++, nr_pins++) {
struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
- struct sh_pfc_pin *info = &pfc->info->pins[nr_pins];
+ const struct sh_pfc_pin *info =
+ &pfc->info->pins[nr_pins];
pin->number = number;
pin->name = info->name;
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 19da3b7..b250dac 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -84,8 +84,8 @@ struct pinmux_func {
struct pinmux_cfg_reg {
unsigned long reg, reg_width, field_width;
- pinmux_enum_t *enum_ids;
- unsigned long *var_field_width;
+ const pinmux_enum_t *enum_ids;
+ const unsigned long *var_field_width;
};
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
@@ -99,7 +99,7 @@ struct pinmux_cfg_reg {
struct pinmux_data_reg {
unsigned long reg, reg_width;
- pinmux_enum_t *enum_ids;
+ const pinmux_enum_t *enum_ids;
};
#define PINMUX_DATA_REG(name, r, r_width) \
@@ -121,14 +121,14 @@ struct pinmux_range {
};
struct sh_pfc_soc_info {
- char *name;
+ const char *name;
struct pinmux_range input;
struct pinmux_range input_pd;
struct pinmux_range input_pu;
struct pinmux_range output;
struct pinmux_range function;
- struct sh_pfc_pin *pins;
+ const struct sh_pfc_pin *pins;
unsigned int nr_pins;
const struct pinmux_range *ranges;
unsigned int nr_ranges;
@@ -137,16 +137,16 @@ struct sh_pfc_soc_info {
const struct sh_pfc_function *functions;
unsigned int nr_functions;
- struct pinmux_func *func_gpios;
+ const struct pinmux_func *func_gpios;
unsigned int nr_func_gpios;
- struct pinmux_cfg_reg *cfg_regs;
- struct pinmux_data_reg *data_regs;
+ const struct pinmux_cfg_reg *cfg_regs;
+ const struct pinmux_data_reg *data_regs;
- pinmux_enum_t *gpio_data;
+ const pinmux_enum_t *gpio_data;
unsigned int gpio_data_size;
- struct pinmux_irq *gpio_irq;
+ const struct pinmux_irq *gpio_irq;
unsigned int gpio_irq_size;
unsigned long unlock_reg;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 049/142] sh-pfc: Use proper error codes
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (46 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 048/142] sh-pfc: Constify all SoC data Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 050/142] sh-pfc: Implement generic pinconf support Simon Horman
` (93 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Return proper error codes instead of -1, and propagate the error codes.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 19 ++++++++++---------
drivers/pinctrl/sh-pfc/gpio.c | 13 ++++---------
drivers/pinctrl/sh-pfc/pinctrl.c | 24 +++++++++++-------------
3 files changed, 25 insertions(+), 31 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 3a94946..a04c497 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -93,7 +93,7 @@ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
offset += range->end - range->begin + 1;
}
- return -1;
+ return -EINVAL;
}
static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,
@@ -233,7 +233,7 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
k++;
}
- return -1;
+ return -EINVAL;
}
static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
@@ -255,7 +255,7 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
}
pr_err("cannot locate data/mark enum_id for mark %d\n", mark);
- return -1;
+ return -EINVAL;
}
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
@@ -264,6 +264,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
pinmux_enum_t enum_id;
const struct pinmux_range *range;
int in_range, pos, field, value;
+ int ret;
switch (pinmux_type) {
@@ -288,7 +289,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
break;
default:
- return -1;
+ return -EINVAL;
}
pos = 0;
@@ -297,8 +298,8 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
value = 0;
while (1) {
pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
- if (pos <= 0)
- return -1;
+ if (pos < 0)
+ return pos;
if (!enum_id)
break;
@@ -341,9 +342,9 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
if (!in_range)
continue;
- if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
- &field, &value) != 0)
- return -1;
+ ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
+ if (ret < 0)
+ return ret;
sh_pfc_write_config_reg(pfc, cr, field, value);
}
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 480beae..e299f14 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -276,22 +276,17 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
struct sh_pfc *pfc = gpio_to_pfc(gc);
unsigned int mark = pfc->info->func_gpios[offset].enum_id;
unsigned long flags;
- int ret = -EINVAL;
+ int ret;
pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
if (mark == 0)
- return ret;
+ return -EINVAL;
spin_lock_irqsave(&pfc->lock, flags);
-
- if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION))
- goto done;
-
- ret = 0;
-
-done:
+ ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
spin_unlock_irqrestore(&pfc->lock, flags);
+
return ret;
}
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index b4960df..c150910 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -114,18 +114,16 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
unsigned long flags;
unsigned int i;
- int ret = -EINVAL;
+ int ret = 0;
spin_lock_irqsave(&pfc->lock, flags);
for (i = 0; i < grp->nr_pins; ++i) {
- if (sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION))
- goto done;
+ ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
+ if (ret < 0)
+ break;
}
- ret = 0;
-
-done:
spin_unlock_irqrestore(&pfc->lock, flags);
return ret;
}
@@ -144,7 +142,7 @@ static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset,
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
unsigned int mark = pin->enum_id;
unsigned long flags;
- int ret = -EINVAL;
+ int ret;
spin_lock_irqsave(&pfc->lock, flags);
@@ -156,17 +154,17 @@ static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset,
case PINMUX_TYPE_INPUT_PULLDOWN:
break;
default:
- goto err;
+ ret = -EINVAL;
+ goto done;
}
- if (sh_pfc_config_mux(pfc, mark, new_type) != 0)
- goto err;
+ ret = sh_pfc_config_mux(pfc, mark, new_type);
+ if (ret < 0)
+ goto done;
cfg->type = new_type;
- ret = 0;
-
-err:
+done:
spin_unlock_irqrestore(&pfc->lock, flags);
return ret;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 050/142] sh-pfc: Implement generic pinconf support
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (47 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 049/142] sh-pfc: Use proper error codes Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 051/142] sh-pfc: Merge sh_pfc_reconfig_pin() into sh_pfc_gpio_set_direction() Simon Horman
` (92 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The existing PFC pinconf implementation, tied to the PFC-specific pin
types, isn't used by drivers or boards. Replace it with the generic
pinconf types to implement bias (pull-up/down) setup. Other pin
configuration options can be implemented later if needed.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/Kconfig | 1 +
drivers/pinctrl/sh-pfc/pinctrl.c | 123 ++++++++++++++++++++++++++++----------
drivers/pinctrl/sh-pfc/sh_pfc.h | 16 +++++
3 files changed, 110 insertions(+), 30 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index c3340f5..af16f8f 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -10,6 +10,7 @@ config PINCTRL_SH_PFC
select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
select PINMUX
select PINCONF
+ select GENERIC_PINCONF
def_bool y
help
This enables pin control drivers for SH and SH Mobile platforms
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index c150910..79fa170 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -24,6 +24,8 @@
#include <linux/spinlock.h>
#include "core.h"
+#include "../core.h"
+#include "../pinconf.h"
struct sh_pfc_pin_config {
u32 type;
@@ -230,57 +232,118 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = {
.gpio_set_direction = sh_pfc_gpio_set_direction,
};
+/* Check whether the requested parameter is supported for a pin. */
+static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
+ enum pin_config_param param)
+{
+ int idx = sh_pfc_get_pin_index(pfc, _pin);
+ const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ return true;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
+
+ default:
+ return false;
+ }
+}
+
static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
unsigned long *config)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
- int idx = sh_pfc_get_pin_index(pfc, _pin);
- struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ unsigned long flags;
+ unsigned int bias;
+
+ if (!sh_pfc_pinconf_validate(pfc, _pin, param))
+ return -ENOTSUPP;
- *config = cfg->type;
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (!pfc->info->ops || !pfc->info->ops->get_bias)
+ return -ENOTSUPP;
+
+ spin_lock_irqsave(&pfc->lock, flags);
+ bias = pfc->info->ops->get_bias(pfc, _pin);
+ spin_unlock_irqrestore(&pfc->lock, flags);
+
+ if (bias != param)
+ return -EINVAL;
+
+ *config = 0;
+ break;
+
+ default:
+ return -ENOTSUPP;
+ }
return 0;
}
-static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
+static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
unsigned long config)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+ struct sh_pfc *pfc = pmx->pfc;
+ enum pin_config_param param = pinconf_to_config_param(config);
+ unsigned long flags;
- /* Validate the new type */
- if (config >= PINMUX_FLAG_TYPE)
- return -EINVAL;
+ if (!sh_pfc_pinconf_validate(pfc, _pin, param))
+ return -ENOTSUPP;
- return sh_pfc_reconfig_pin(pmx, pin, config);
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (!pfc->info->ops || !pfc->info->ops->set_bias)
+ return -ENOTSUPP;
+
+ spin_lock_irqsave(&pfc->lock, flags);
+ pfc->info->ops->set_bias(pfc, _pin, param);
+ spin_unlock_irqrestore(&pfc->lock, flags);
+
+ break;
+
+ default:
+ return -ENOTSUPP;
+ }
+
+ return 0;
}
-static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned pin)
+static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
+ unsigned long config)
{
- const char *pinmux_type_str[] = {
- [PINMUX_TYPE_NONE] = "none",
- [PINMUX_TYPE_FUNCTION] = "function",
- [PINMUX_TYPE_GPIO] = "gpio",
- [PINMUX_TYPE_OUTPUT] = "output",
- [PINMUX_TYPE_INPUT] = "input",
- [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up",
- [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down",
- };
- unsigned long config;
- int rc;
-
- rc = sh_pfc_pinconf_get(pctldev, pin, &config);
- if (unlikely(rc != 0))
- return;
-
- seq_printf(s, " %s", pinmux_type_str[config]);
+ struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+ const unsigned int *pins;
+ unsigned int num_pins;
+ unsigned int i;
+
+ pins = pmx->pfc->info->groups[group].pins;
+ num_pins = pmx->pfc->info->groups[group].nr_pins;
+
+ for (i = 0; i < num_pins; ++i)
+ sh_pfc_pinconf_set(pctldev, pins[i], config);
+
+ return 0;
}
static const struct pinconf_ops sh_pfc_pinconf_ops = {
- .pin_config_get = sh_pfc_pinconf_get,
- .pin_config_set = sh_pfc_pinconf_set,
- .pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
+ .is_generic = true,
+ .pin_config_get = sh_pfc_pinconf_get,
+ .pin_config_set = sh_pfc_pinconf_set,
+ .pin_config_group_set = sh_pfc_pinconf_group_set,
+ .pin_config_config_dbg_show = pinconf_generic_dump_config,
};
/* PFC ranges -> pinctrl pin descs */
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index b250dac..3b785fc 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -31,9 +31,15 @@ enum {
PINMUX_FLAG_TYPE, /* must be last */
};
+#define SH_PFC_PIN_CFG_INPUT (1 << 0)
+#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
+#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
+#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
+
struct sh_pfc_pin {
const pinmux_enum_t enum_id;
const char *name;
+ unsigned int configs;
};
#define SH_PFC_PIN_GROUP(n) \
@@ -120,8 +126,18 @@ struct pinmux_range {
pinmux_enum_t force;
};
+struct sh_pfc;
+
+struct sh_pfc_soc_operations {
+ unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
+ void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
+ unsigned int bias);
+};
+
struct sh_pfc_soc_info {
const char *name;
+ const struct sh_pfc_soc_operations *ops;
+
struct pinmux_range input;
struct pinmux_range input_pd;
struct pinmux_range input_pu;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 051/142] sh-pfc: Merge sh_pfc_reconfig_pin() into sh_pfc_gpio_set_direction()
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (48 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 050/142] sh-pfc: Implement generic pinconf support Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 052/142] sh-pfc: Clean up pin configuration type handling Simon Horman
` (91 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The sh_pfc_reconfig_pin() is only called from a single location. Merge
it into its call site to make the code easier to follow.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 71 +++++++++++++++++---------------------
1 file changed, 32 insertions(+), 39 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 79fa170..36f08f8 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -135,43 +135,6 @@ static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
{
}
-static int sh_pfc_reconfig_pin(struct sh_pfc_pinctrl *pmx, unsigned offset,
- int new_type)
-{
- struct sh_pfc *pfc = pmx->pfc;
- int idx = sh_pfc_get_pin_index(pfc, offset);
- struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
- const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
- unsigned int mark = pin->enum_id;
- unsigned long flags;
- int ret;
-
- spin_lock_irqsave(&pfc->lock, flags);
-
- switch (cfg->type) {
- case PINMUX_TYPE_GPIO:
- case PINMUX_TYPE_OUTPUT:
- case PINMUX_TYPE_INPUT:
- case PINMUX_TYPE_INPUT_PULLUP:
- case PINMUX_TYPE_INPUT_PULLDOWN:
- break;
- default:
- ret = -EINVAL;
- goto done;
- }
-
- ret = sh_pfc_config_mux(pfc, mark, new_type);
- if (ret < 0)
- goto done;
-
- cfg->type = new_type;
-
-done:
- spin_unlock_irqrestore(&pfc->lock, flags);
-
- return ret;
-}
-
static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
@@ -216,9 +179,39 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
unsigned offset, bool input)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
+ struct sh_pfc *pfc = pmx->pfc;
+ int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
+ int idx = sh_pfc_get_pin_index(pfc, offset);
+ struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
+ const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+ unsigned int mark = pin->enum_id;
+ unsigned long flags;
+ int ret;
- return sh_pfc_reconfig_pin(pmx, offset, type);
+ spin_lock_irqsave(&pfc->lock, flags);
+
+ switch (cfg->type) {
+ case PINMUX_TYPE_GPIO:
+ case PINMUX_TYPE_OUTPUT:
+ case PINMUX_TYPE_INPUT:
+ case PINMUX_TYPE_INPUT_PULLUP:
+ case PINMUX_TYPE_INPUT_PULLDOWN:
+ break;
+ default:
+ ret = -EINVAL;
+ goto done;
+ }
+
+ ret = sh_pfc_config_mux(pfc, mark, new_type);
+ if (ret < 0)
+ goto done;
+
+ cfg->type = new_type;
+
+done:
+ spin_unlock_irqrestore(&pfc->lock, flags);
+
+ return ret;
}
static const struct pinmux_ops sh_pfc_pinmux_ops = {
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 052/142] sh-pfc: Clean up pin configuration type handling
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (49 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 051/142] sh-pfc: Merge sh_pfc_reconfig_pin() into sh_pfc_gpio_set_direction() Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 053/142] sh-pfc: Convert message printing from pr_* to dev_* Simon Horman
` (90 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Set pin configuration type to
- PINMUX_TYPE_NONE at initialization time and when disabling a function
or freeing a GPIO
- PINMUX_TYPE_FUNCTION when enabling a function
- PINMUX_TYPE_INPUT or PINMUX_TYPE_OUTPUT when setting the GPIO
direction
Verify that the type is PINMUX_TYPE_NONE when enabling a function or
requesting a GPIO and return -EBUSY if it isn't.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 74 +++++++++++++++++++++++---------------
1 file changed, 46 insertions(+), 28 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 36f08f8..82e4fb2 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -121,11 +121,22 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
spin_lock_irqsave(&pfc->lock, flags);
for (i = 0; i < grp->nr_pins; ++i) {
+ int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+ struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
+
+ if (cfg->type != PINMUX_TYPE_NONE) {
+ ret = -EBUSY;
+ goto done;
+ }
+ }
+
+ for (i = 0; i < grp->nr_pins; ++i) {
ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
if (ret < 0)
break;
}
+done:
spin_unlock_irqrestore(&pfc->lock, flags);
return ret;
}
@@ -133,6 +144,22 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
+ struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+ struct sh_pfc *pfc = pmx->pfc;
+ const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
+ unsigned long flags;
+ unsigned int i;
+
+ spin_lock_irqsave(&pfc->lock, flags);
+
+ for (i = 0; i < grp->nr_pins; ++i) {
+ int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+ struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
+
+ cfg->type = PINMUX_TYPE_NONE;
+ }
+
+ spin_unlock_irqrestore(&pfc->lock, flags);
}
static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
@@ -148,21 +175,17 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
spin_lock_irqsave(&pfc->lock, flags);
- switch (cfg->type) {
- case PINMUX_TYPE_GPIO:
- case PINMUX_TYPE_INPUT:
- case PINMUX_TYPE_OUTPUT:
- break;
- case PINMUX_TYPE_FUNCTION:
- default:
- pr_err("Unsupported mux type (%d), bailing...\n", cfg->type);
- ret = -ENOTSUPP;
- goto err;
+ if (cfg->type != PINMUX_TYPE_NONE) {
+ pr_err("Pin %u is busy, can't configure it as GPIO.\n", offset);
+ ret = -EBUSY;
+ goto done;
}
+ cfg->type = PINMUX_TYPE_GPIO;
+
ret = 0;
-err:
+done:
spin_unlock_irqrestore(&pfc->lock, flags);
return ret;
@@ -172,6 +195,15 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
+ struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+ struct sh_pfc *pfc = pmx->pfc;
+ int idx = sh_pfc_get_pin_index(pfc, offset);
+ struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
+ unsigned long flags;
+
+ spin_lock_irqsave(&pfc->lock, flags);
+ cfg->type = PINMUX_TYPE_NONE;
+ spin_unlock_irqrestore(&pfc->lock, flags);
}
static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
@@ -182,27 +214,14 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
struct sh_pfc *pfc = pmx->pfc;
int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
int idx = sh_pfc_get_pin_index(pfc, offset);
- struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
- unsigned int mark = pin->enum_id;
+ struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
unsigned long flags;
int ret;
spin_lock_irqsave(&pfc->lock, flags);
- switch (cfg->type) {
- case PINMUX_TYPE_GPIO:
- case PINMUX_TYPE_OUTPUT:
- case PINMUX_TYPE_INPUT:
- case PINMUX_TYPE_INPUT_PULLUP:
- case PINMUX_TYPE_INPUT_PULLDOWN:
- break;
- default:
- ret = -EINVAL;
- goto done;
- }
-
- ret = sh_pfc_config_mux(pfc, mark, new_type);
+ ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
if (ret < 0)
goto done;
@@ -210,7 +229,6 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
done:
spin_unlock_irqrestore(&pfc->lock, flags);
-
return ret;
}
@@ -383,7 +401,7 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
pin->number = number;
pin->name = info->name;
- cfg->type = PINMUX_TYPE_GPIO;
+ cfg->type = PINMUX_TYPE_NONE;
}
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 053/142] sh-pfc: Convert message printing from pr_* to dev_*
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (50 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 052/142] sh-pfc: Clean up pin configuration type handling Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 054/142] sh-pfc: Return an error if a pin doesn't support the requested direction Simon Horman
` (89 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/core.c | 14 +++++++-------
drivers/pinctrl/sh-pfc/gpio.c | 16 ++++++++++------
drivers/pinctrl/sh-pfc/pinctrl.c | 5 +++--
3 files changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index a04c497..feef897 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -10,7 +10,6 @@
*/
#define DRV_NAME "sh-pfc"
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bitops.h>
#include <linux/err.h>
@@ -173,9 +172,9 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
- pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
- "r_width = %ld, f_width = %ld\n",
- crp->reg, value, field, crp->reg_width, crp->field_width);
+ dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
+ "r_width = %ld, f_width = %ld\n",
+ crp->reg, value, field, crp->reg_width, crp->field_width);
mask = ~(mask << pos);
value = value << pos;
@@ -254,7 +253,8 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
}
}
- pr_err("cannot locate data/mark enum_id for mark %d\n", mark);
+ dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
+ mark);
return -EINVAL;
}
@@ -396,13 +396,13 @@ static int sh_pfc_probe(struct platform_device *pdev)
* PFC state as it is, given that there are already
* extant users of it that have succeeded by this point.
*/
- pr_notice("failed to init GPIO chip, ignoring...\n");
+ dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
}
#endif
platform_set_drvdata(pdev, pfc);
- pr_info("%s support registered\n", info->name);
+ dev_info(pfc->dev, "%s support registered\n", info->name);
return 0;
}
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index e299f14..d7acb06 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -9,8 +9,6 @@
* for more details.
*/
-#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt
-
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/init.h>
@@ -273,12 +271,18 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
{
+ static bool __print_once;
struct sh_pfc *pfc = gpio_to_pfc(gc);
unsigned int mark = pfc->info->func_gpios[offset].enum_id;
unsigned long flags;
int ret;
- pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
+ if (!__print_once) {
+ dev_notice(pfc->dev,
+ "Use of GPIO API for function requests is deprecated."
+ " Convert to pinctrl\n");
+ __print_once = true;
+ }
if (mark == 0)
return -EINVAL;
@@ -334,9 +338,9 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *))
if (unlikely(ret < 0))
return ERR_PTR(ret);
- pr_info("%s handling gpio %u -> %u\n",
- chip->gpio_chip.label, chip->gpio_chip.base,
- chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
+ dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
+ chip->gpio_chip.label, chip->gpio_chip.base,
+ chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
return chip;
}
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 82e4fb2..52179bb 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -9,7 +9,6 @@
*/
#define DRV_NAME "sh-pfc"
-#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt
#include <linux/device.h>
#include <linux/err.h>
@@ -176,7 +175,9 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
spin_lock_irqsave(&pfc->lock, flags);
if (cfg->type != PINMUX_TYPE_NONE) {
- pr_err("Pin %u is busy, can't configure it as GPIO.\n", offset);
+ dev_err(pfc->dev,
+ "Pin %u is busy, can't configure it as GPIO.\n",
+ offset);
ret = -EBUSY;
goto done;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 054/142] sh-pfc: Return an error if a pin doesn't support the requested direction
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (51 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 053/142] sh-pfc: Convert message printing from pr_* to dev_* Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 055/142] sh-pfc: sh7372: Add SDHCI and MMCIF pin groups and functions Simon Horman
` (88 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
When setting a pin direction verify that the requested direction is
supported, and return an error if it isn't.
This requires pin configuration information to be supplied by SoC data.
The check is a no-op if the information is not supplied.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 52179bb..aef268b 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -218,8 +218,18 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
unsigned long flags;
+ unsigned int dir;
int ret;
+ /* Check if the requested direction is supported by the pin. Not all SoC
+ * provide pin config data, so perform the check conditionally.
+ */
+ if (pin->configs) {
+ dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
+ if (!(pin->configs & dir))
+ return -EINVAL;
+ }
+
spin_lock_irqsave(&pfc->lock, flags);
ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 055/142] sh-pfc: sh7372: Add SDHCI and MMCIF pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (52 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 054/142] sh-pfc: Return an error if a pin doesn't support the requested direction Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 056/142] sh-pfc: sh73a0: Add bias (pull-up/down) pinconf support Simon Horman
` (87 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Add pin groups for all three SDHI interfaces and two alternative pin
groups for the MMCIF interface on the sh7372 SoC.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
drivers/pinctrl/sh-pfc/pfc-sh7372.c | 206 +++++++++++++++++++++++++++++++++++
1 file changed, 206 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 6b56344..cef4d6a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -933,6 +933,207 @@ static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_0_pins[] = {
+ /* D[0] */
+ 84,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+ MMCD0_0_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+ /* D[0:3] */
+ 84, 85, 86, 87,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+ MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+ /* D[0:7] */
+ 84, 85, 86, 87, 88, 89, 90, 91,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+ MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+ MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+ /* CMD, CLK */
+ 92, 99,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+ MMCCMD0_MARK, MMCCLK0_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+ /* D[0] */
+ 54,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+ MMCD1_0_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+ /* D[0:3] */
+ 54, 55, 56, 57,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+ MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+ /* D[0:7] */
+ 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+ MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+ MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+ /* CMD, CLK */
+ 67, 66,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+ MMCCMD1_MARK, MMCCLK1_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ 173,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SDHID0_0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ 173, 174, 175, 176,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CMD, CLK */
+ 177, 171,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SDHICMD0_MARK, SDHICLK0_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ 172,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SDHICD0_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ 178,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SDHIWP0_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ 180,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SDHID1_0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ 180, 181, 182, 183,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CMD, CLK */
+ 184, 179,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SDHICMD1_MARK, SDHICLK1_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ 186,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SDHID2_0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ 186, 187, 188, 189,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CMD, CLK */
+ 190, 185,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SDHICMD2_MARK, SDHICLK2_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(mmc0_data1_0),
+ SH_PFC_PIN_GROUP(mmc0_data4_0),
+ SH_PFC_PIN_GROUP(mmc0_data8_0),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+ SH_PFC_PIN_GROUP(mmc0_data1_1),
+ SH_PFC_PIN_GROUP(mmc0_data4_1),
+ SH_PFC_PIN_GROUP(mmc0_data8_1),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+};
+
+static const char * const mmc0_groups[] = {
+ "mmc0_data1_0",
+ "mmc0_data4_0",
+ "mmc0_data8_0",
+ "mmc0_ctrl_0",
+ "mmc0_data1_1",
+ "mmc0_data4_1",
+ "mmc0_data8_1",
+ "mmc0_ctrl_1",
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(mmc0),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+};
+
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
@@ -1644,6 +1845,11 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = {
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 056/142] sh-pfc: sh73a0: Add bias (pull-up/down) pinconf support
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (53 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 055/142] sh-pfc: sh7372: Add SDHCI and MMCIF pin groups and functions Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 057/142] sh-pfc: sh73a0: Add LCD and LCD2 pin groups and functions Simon Horman
` (86 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 351 ++++++++++++++++++++++++++++++++++-
1 file changed, 350 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 3200fc2..f31adfc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -18,10 +18,14 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
#include <mach/sh73a0.h>
#include <mach/irqs.h>
+#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -1539,8 +1543,300 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
};
+#define SH73A0_PIN(pin, cfgs) \
+ { \
+ .name = __stringify(PORT##pin), \
+ .enum_id = PORT##pin##_DATA, \
+ .configs = cfgs, \
+ }
+
+#define __I (SH_PFC_PIN_CFG_INPUT)
+#define __O (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU (SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD)
+#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU)
+#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD)
+#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO)
+#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD)
+#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU)
+#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD)
+#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O)
+
static struct sh_pfc_pin pinmux_pins[] = {
- GPIO_PORT_ALL(),
+ /* Table 25-1 (I/O and Pull U/D) */
+ SH73A0_PIN_I_PD(0),
+ SH73A0_PIN_I_PU(1),
+ SH73A0_PIN_I_PU(2),
+ SH73A0_PIN_I_PU(3),
+ SH73A0_PIN_I_PU(4),
+ SH73A0_PIN_I_PU(5),
+ SH73A0_PIN_I_PU(6),
+ SH73A0_PIN_I_PU(7),
+ SH73A0_PIN_I_PU(8),
+ SH73A0_PIN_I_PD(9),
+ SH73A0_PIN_I_PD(10),
+ SH73A0_PIN_I_PU_PD(11),
+ SH73A0_PIN_IO_PU_PD(12),
+ SH73A0_PIN_IO_PU_PD(13),
+ SH73A0_PIN_IO_PU_PD(14),
+ SH73A0_PIN_IO_PU_PD(15),
+ SH73A0_PIN_IO_PD(16),
+ SH73A0_PIN_IO_PD(17),
+ SH73A0_PIN_IO_PU(18),
+ SH73A0_PIN_IO_PU(19),
+ SH73A0_PIN_O(20),
+ SH73A0_PIN_O(21),
+ SH73A0_PIN_O(22),
+ SH73A0_PIN_O(23),
+ SH73A0_PIN_O(24),
+ SH73A0_PIN_I_PD(25),
+ SH73A0_PIN_I_PD(26),
+ SH73A0_PIN_IO_PU(27),
+ SH73A0_PIN_IO_PU(28),
+ SH73A0_PIN_IO_PD(29),
+ SH73A0_PIN_IO_PD(30),
+ SH73A0_PIN_IO_PU(31),
+ SH73A0_PIN_IO_PD(32),
+ SH73A0_PIN_I_PU_PD(33),
+ SH73A0_PIN_IO_PD(34),
+ SH73A0_PIN_I_PU_PD(35),
+ SH73A0_PIN_IO_PD(36),
+ SH73A0_PIN_IO(37),
+ SH73A0_PIN_O(38),
+ SH73A0_PIN_I_PU(39),
+ SH73A0_PIN_I_PU_PD(40),
+ SH73A0_PIN_O(41),
+ SH73A0_PIN_IO_PD(42),
+ SH73A0_PIN_IO_PU_PD(43),
+ SH73A0_PIN_IO_PU_PD(44),
+ SH73A0_PIN_IO_PD(45),
+ SH73A0_PIN_IO_PD(46),
+ SH73A0_PIN_IO_PD(47),
+ SH73A0_PIN_I_PD(48),
+ SH73A0_PIN_IO_PU_PD(49),
+ SH73A0_PIN_IO_PD(50),
+ SH73A0_PIN_IO_PD(51),
+ SH73A0_PIN_O(52),
+ SH73A0_PIN_IO_PU_PD(53),
+ SH73A0_PIN_IO_PU_PD(54),
+ SH73A0_PIN_IO_PD(55),
+ SH73A0_PIN_I_PU_PD(56),
+ SH73A0_PIN_IO(57),
+ SH73A0_PIN_IO(58),
+ SH73A0_PIN_IO(59),
+ SH73A0_PIN_IO(60),
+ SH73A0_PIN_IO(61),
+ SH73A0_PIN_IO_PD(62),
+ SH73A0_PIN_IO_PD(63),
+ SH73A0_PIN_IO_PU_PD(64),
+ SH73A0_PIN_IO_PD(65),
+ SH73A0_PIN_IO_PU_PD(66),
+ SH73A0_PIN_IO_PU_PD(67),
+ SH73A0_PIN_IO_PU_PD(68),
+ SH73A0_PIN_IO_PU_PD(69),
+ SH73A0_PIN_IO_PU_PD(70),
+ SH73A0_PIN_IO_PU_PD(71),
+ SH73A0_PIN_IO_PU_PD(72),
+ SH73A0_PIN_I_PU_PD(73),
+ SH73A0_PIN_IO_PU(74),
+ SH73A0_PIN_IO_PU(75),
+ SH73A0_PIN_IO_PU(76),
+ SH73A0_PIN_IO_PU(77),
+ SH73A0_PIN_IO_PU(78),
+ SH73A0_PIN_IO_PU(79),
+ SH73A0_PIN_IO_PU(80),
+ SH73A0_PIN_IO_PU(81),
+ SH73A0_PIN_IO_PU(82),
+ SH73A0_PIN_IO_PU(83),
+ SH73A0_PIN_IO_PU(84),
+ SH73A0_PIN_IO_PU(85),
+ SH73A0_PIN_IO_PU(86),
+ SH73A0_PIN_IO_PU(87),
+ SH73A0_PIN_IO_PU(88),
+ SH73A0_PIN_IO_PU(89),
+ SH73A0_PIN_O(90),
+ SH73A0_PIN_IO_PU(91),
+ SH73A0_PIN_O(92),
+ SH73A0_PIN_IO_PU(93),
+ SH73A0_PIN_O(94),
+ SH73A0_PIN_I_PU_PD(95),
+ SH73A0_PIN_IO(96),
+ SH73A0_PIN_IO(97),
+ SH73A0_PIN_IO(98),
+ SH73A0_PIN_I_PU(99),
+ SH73A0_PIN_O(100),
+ SH73A0_PIN_O(101),
+ SH73A0_PIN_I_PU(102),
+ SH73A0_PIN_IO_PD(103),
+ SH73A0_PIN_I_PU_PD(104),
+ SH73A0_PIN_I_PD(105),
+ SH73A0_PIN_I_PD(106),
+ SH73A0_PIN_I_PU_PD(107),
+ SH73A0_PIN_I_PU_PD(108),
+ SH73A0_PIN_IO_PD(109),
+ SH73A0_PIN_IO_PD(110),
+ SH73A0_PIN_IO_PU_PD(111),
+ SH73A0_PIN_IO_PU_PD(112),
+ SH73A0_PIN_IO_PU_PD(113),
+ SH73A0_PIN_IO_PD(114),
+ SH73A0_PIN_IO_PU(115),
+ SH73A0_PIN_IO_PU(116),
+ SH73A0_PIN_IO_PU_PD(117),
+ SH73A0_PIN_IO_PU_PD(118),
+ SH73A0_PIN_IO_PD(128),
+ SH73A0_PIN_IO_PD(129),
+ SH73A0_PIN_IO_PU_PD(130),
+ SH73A0_PIN_IO_PD(131),
+ SH73A0_PIN_IO_PD(132),
+ SH73A0_PIN_IO_PD(133),
+ SH73A0_PIN_IO_PU_PD(134),
+ SH73A0_PIN_IO_PU_PD(135),
+ SH73A0_PIN_IO_PU_PD(136),
+ SH73A0_PIN_IO_PU_PD(137),
+ SH73A0_PIN_IO_PD(138),
+ SH73A0_PIN_IO_PD(139),
+ SH73A0_PIN_IO_PD(140),
+ SH73A0_PIN_IO_PD(141),
+ SH73A0_PIN_IO_PD(142),
+ SH73A0_PIN_IO_PD(143),
+ SH73A0_PIN_IO_PU_PD(144),
+ SH73A0_PIN_IO_PD(145),
+ SH73A0_PIN_IO_PU_PD(146),
+ SH73A0_PIN_IO_PU_PD(147),
+ SH73A0_PIN_IO_PU_PD(148),
+ SH73A0_PIN_IO_PU_PD(149),
+ SH73A0_PIN_I_PU_PD(150),
+ SH73A0_PIN_IO_PU_PD(151),
+ SH73A0_PIN_IO_PU_PD(152),
+ SH73A0_PIN_IO_PD(153),
+ SH73A0_PIN_IO_PD(154),
+ SH73A0_PIN_I_PU_PD(155),
+ SH73A0_PIN_IO_PU_PD(156),
+ SH73A0_PIN_I_PD(157),
+ SH73A0_PIN_IO_PD(158),
+ SH73A0_PIN_IO_PU_PD(159),
+ SH73A0_PIN_IO_PU_PD(160),
+ SH73A0_PIN_I_PU_PD(161),
+ SH73A0_PIN_I_PU_PD(162),
+ SH73A0_PIN_IO_PU_PD(163),
+ SH73A0_PIN_I_PU_PD(164),
+ SH73A0_PIN_IO_PD(192),
+ SH73A0_PIN_IO_PU_PD(193),
+ SH73A0_PIN_IO_PD(194),
+ SH73A0_PIN_IO_PU_PD(195),
+ SH73A0_PIN_IO_PD(196),
+ SH73A0_PIN_IO_PD(197),
+ SH73A0_PIN_IO_PD(198),
+ SH73A0_PIN_IO_PD(199),
+ SH73A0_PIN_IO_PU_PD(200),
+ SH73A0_PIN_IO_PU_PD(201),
+ SH73A0_PIN_IO_PU_PD(202),
+ SH73A0_PIN_IO_PU_PD(203),
+ SH73A0_PIN_IO_PU_PD(204),
+ SH73A0_PIN_IO_PU_PD(205),
+ SH73A0_PIN_IO_PU_PD(206),
+ SH73A0_PIN_IO_PD(207),
+ SH73A0_PIN_IO_PD(208),
+ SH73A0_PIN_IO_PD(209),
+ SH73A0_PIN_IO_PD(210),
+ SH73A0_PIN_IO_PD(211),
+ SH73A0_PIN_IO_PD(212),
+ SH73A0_PIN_IO_PD(213),
+ SH73A0_PIN_IO_PU_PD(214),
+ SH73A0_PIN_IO_PU_PD(215),
+ SH73A0_PIN_IO_PD(216),
+ SH73A0_PIN_IO_PD(217),
+ SH73A0_PIN_O(218),
+ SH73A0_PIN_IO_PD(219),
+ SH73A0_PIN_IO_PD(220),
+ SH73A0_PIN_IO_PU_PD(221),
+ SH73A0_PIN_IO_PU_PD(222),
+ SH73A0_PIN_I_PU_PD(223),
+ SH73A0_PIN_I_PU_PD(224),
+ SH73A0_PIN_IO_PU_PD(225),
+ SH73A0_PIN_O(226),
+ SH73A0_PIN_IO_PU_PD(227),
+ SH73A0_PIN_I_PU_PD(228),
+ SH73A0_PIN_I_PD(229),
+ SH73A0_PIN_IO(230),
+ SH73A0_PIN_IO_PU_PD(231),
+ SH73A0_PIN_IO_PU_PD(232),
+ SH73A0_PIN_I_PU_PD(233),
+ SH73A0_PIN_IO_PU_PD(234),
+ SH73A0_PIN_IO_PU_PD(235),
+ SH73A0_PIN_IO_PU_PD(236),
+ SH73A0_PIN_IO_PD(237),
+ SH73A0_PIN_IO_PU_PD(238),
+ SH73A0_PIN_IO_PU_PD(239),
+ SH73A0_PIN_IO_PU_PD(240),
+ SH73A0_PIN_O(241),
+ SH73A0_PIN_I_PD(242),
+ SH73A0_PIN_IO_PU_PD(243),
+ SH73A0_PIN_IO_PU_PD(244),
+ SH73A0_PIN_IO_PU_PD(245),
+ SH73A0_PIN_IO_PU_PD(246),
+ SH73A0_PIN_IO_PU_PD(247),
+ SH73A0_PIN_IO_PU_PD(248),
+ SH73A0_PIN_IO_PU_PD(249),
+ SH73A0_PIN_IO_PU_PD(250),
+ SH73A0_PIN_IO_PU_PD(251),
+ SH73A0_PIN_IO_PU_PD(252),
+ SH73A0_PIN_IO_PU_PD(253),
+ SH73A0_PIN_IO_PU_PD(254),
+ SH73A0_PIN_IO_PU_PD(255),
+ SH73A0_PIN_IO_PU_PD(256),
+ SH73A0_PIN_IO_PU_PD(257),
+ SH73A0_PIN_IO_PU_PD(258),
+ SH73A0_PIN_IO_PU_PD(259),
+ SH73A0_PIN_IO_PU_PD(260),
+ SH73A0_PIN_IO_PU_PD(261),
+ SH73A0_PIN_IO_PU_PD(262),
+ SH73A0_PIN_IO_PU_PD(263),
+ SH73A0_PIN_IO_PU_PD(264),
+ SH73A0_PIN_IO_PU_PD(265),
+ SH73A0_PIN_IO_PU_PD(266),
+ SH73A0_PIN_IO_PU_PD(267),
+ SH73A0_PIN_IO_PU_PD(268),
+ SH73A0_PIN_IO_PU_PD(269),
+ SH73A0_PIN_IO_PU_PD(270),
+ SH73A0_PIN_IO_PU_PD(271),
+ SH73A0_PIN_IO_PU_PD(272),
+ SH73A0_PIN_IO_PU_PD(273),
+ SH73A0_PIN_IO_PU_PD(274),
+ SH73A0_PIN_IO_PU_PD(275),
+ SH73A0_PIN_IO_PU_PD(276),
+ SH73A0_PIN_IO_PU_PD(277),
+ SH73A0_PIN_IO_PU_PD(278),
+ SH73A0_PIN_IO_PU_PD(279),
+ SH73A0_PIN_IO_PU_PD(280),
+ SH73A0_PIN_O(281),
+ SH73A0_PIN_O(282),
+ SH73A0_PIN_I_PU(288),
+ SH73A0_PIN_IO_PU_PD(289),
+ SH73A0_PIN_IO_PU_PD(290),
+ SH73A0_PIN_IO_PU_PD(291),
+ SH73A0_PIN_IO_PU_PD(292),
+ SH73A0_PIN_IO_PU_PD(293),
+ SH73A0_PIN_IO_PU_PD(294),
+ SH73A0_PIN_IO_PU_PD(295),
+ SH73A0_PIN_IO_PU_PD(296),
+ SH73A0_PIN_IO_PU_PD(297),
+ SH73A0_PIN_IO_PU_PD(298),
+ SH73A0_PIN_IO_PU_PD(299),
+ SH73A0_PIN_IO_PU_PD(300),
+ SH73A0_PIN_IO_PU_PD(301),
+ SH73A0_PIN_IO_PU_PD(302),
+ SH73A0_PIN_IO_PU_PD(303),
+ SH73A0_PIN_IO_PU_PD(304),
+ SH73A0_PIN_IO_PU_PD(305),
+ SH73A0_PIN_O(306),
+ SH73A0_PIN_O(307),
+ SH73A0_PIN_I_PU(308),
+ SH73A0_PIN_O(309),
};
static const struct pinmux_range pinmux_ranges[] = {
@@ -2779,8 +3075,61 @@ static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(EXT_IRQ16L(9), 308),
};
+#define PORTnCR_PULMD_OFF (0 << 6)
+#define PORTnCR_PULMD_DOWN (2 << 6)
+#define PORTnCR_PULMD_UP (3 << 6)
+#define PORTnCR_PULMD_MASK (3 << 6)
+
+static const unsigned int sh73a0_portcr_offsets[] = {
+ 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
+ 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
+};
+
+static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+ void __iomem *addr = pfc->window->virt
+ + sh73a0_portcr_offsets[pin >> 5] + pin;
+ u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+ switch (value) {
+ case PORTnCR_PULMD_UP:
+ return PIN_CONFIG_BIAS_PULL_UP;
+ case PORTnCR_PULMD_DOWN:
+ return PIN_CONFIG_BIAS_PULL_DOWN;
+ case PORTnCR_PULMD_OFF:
+ default:
+ return PIN_CONFIG_BIAS_DISABLE;
+ }
+}
+
+static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ unsigned int bias)
+{
+ void __iomem *addr = pfc->window->virt
+ + sh73a0_portcr_offsets[pin >> 5] + pin;
+ u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+ switch (bias) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ value |= PORTnCR_PULMD_UP;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ value |= PORTnCR_PULMD_DOWN;
+ break;
+ }
+
+ iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
+ .get_bias = sh73a0_pinmux_get_bias,
+ .set_bias = sh73a0_pinmux_set_bias,
+};
+
const struct sh_pfc_soc_info sh73a0_pinmux_info = {
.name = "sh73a0_pfc",
+ .ops = &sh73a0_pinmux_ops,
+
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 057/142] sh-pfc: sh73a0: Add LCD and LCD2 pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (54 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 056/142] sh-pfc: sh73a0: Add bias (pull-up/down) pinconf support Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 058/142] sh-pfc: sh73a0: Add SCIFA and SCIFB " Simon Horman
` (85 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 254 +++++++++++++++++++++++++++++++++++
1 file changed, 254 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index f31adfc..c8b2604 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -1846,6 +1846,255 @@ static const struct pinmux_range pinmux_ranges[] = {
{.begin = 288, .end = 309,},
};
+/* - LCD -------------------------------------------------------------------- */
+static const unsigned int lcd_data8_pins[] = {
+ /* D[0:7] */
+ 192, 193, 194, 195, 196, 197, 198, 199,
+};
+static const unsigned int lcd_data8_mux[] = {
+ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+};
+static const unsigned int lcd_data9_pins[] = {
+ /* D[0:8] */
+ 192, 193, 194, 195, 196, 197, 198, 199,
+ 200,
+};
+static const unsigned int lcd_data9_mux[] = {
+ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+ LCDD8_MARK,
+};
+static const unsigned int lcd_data12_pins[] = {
+ /* D[0:11] */
+ 192, 193, 194, 195, 196, 197, 198, 199,
+ 200, 201, 202, 203,
+};
+static const unsigned int lcd_data12_mux[] = {
+ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+ LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+};
+static const unsigned int lcd_data16_pins[] = {
+ /* D[0:15] */
+ 192, 193, 194, 195, 196, 197, 198, 199,
+ 200, 201, 202, 203, 204, 205, 206, 207,
+};
+static const unsigned int lcd_data16_mux[] = {
+ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+ LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+ LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+};
+static const unsigned int lcd_data18_pins[] = {
+ /* D[0:17] */
+ 192, 193, 194, 195, 196, 197, 198, 199,
+ 200, 201, 202, 203, 204, 205, 206, 207,
+ 208, 209,
+};
+static const unsigned int lcd_data18_mux[] = {
+ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+ LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+ LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+ LCDD16_MARK, LCDD17_MARK,
+};
+static const unsigned int lcd_data24_pins[] = {
+ /* D[0:23] */
+ 192, 193, 194, 195, 196, 197, 198, 199,
+ 200, 201, 202, 203, 204, 205, 206, 207,
+ 208, 209, 210, 211, 212, 213, 214, 215
+};
+static const unsigned int lcd_data24_mux[] = {
+ LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+ LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+ LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+ LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+ LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
+ LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
+};
+static const unsigned int lcd_display_pins[] = {
+ /* DON */
+ 222,
+};
+static const unsigned int lcd_display_mux[] = {
+ LCDDON_MARK,
+};
+static const unsigned int lcd_lclk_pins[] = {
+ /* LCLK */
+ 221,
+};
+static const unsigned int lcd_lclk_mux[] = {
+ LCDLCLK_MARK,
+};
+static const unsigned int lcd_sync_pins[] = {
+ /* VSYN, HSYN, DCK, DISP */
+ 220, 218, 216, 219,
+};
+static const unsigned int lcd_sync_mux[] = {
+ LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
+};
+static const unsigned int lcd_sys_pins[] = {
+ /* CS, WR, RD, RS */
+ 218, 216, 217, 219,
+};
+static const unsigned int lcd_sys_mux[] = {
+ LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
+};
+/* - LCD2 ------------------------------------------------------------------- */
+static const unsigned int lcd2_data8_pins[] = {
+ /* D[0:7] */
+ 128, 129, 142, 143, 144, 145, 138, 139,
+};
+static const unsigned int lcd2_data8_mux[] = {
+ LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+ LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+};
+static const unsigned int lcd2_data9_pins[] = {
+ /* D[0:8] */
+ 128, 129, 142, 143, 144, 145, 138, 139,
+ 140,
+};
+static const unsigned int lcd2_data9_mux[] = {
+ LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+ LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+ LCD2D8_MARK,
+};
+static const unsigned int lcd2_data12_pins[] = {
+ /* D[0:12] */
+ 128, 129, 142, 143, 144, 145, 138, 139,
+ 140, 141, 130, 131,
+};
+static const unsigned int lcd2_data12_mux[] = {
+ LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+ LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+ LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
+};
+static const unsigned int lcd2_data16_pins[] = {
+ /* D[0:15] */
+ 128, 129, 142, 143, 144, 145, 138, 139,
+ 140, 141, 130, 131, 132, 133, 134, 135,
+};
+static const unsigned int lcd2_data16_mux[] = {
+ LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+ LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+ LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
+ LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
+};
+static const unsigned int lcd2_data18_pins[] = {
+ /* D[0:17] */
+ 128, 129, 142, 143, 144, 145, 138, 139,
+ 140, 141, 130, 131, 132, 133, 134, 135,
+ 136, 137,
+};
+static const unsigned int lcd2_data18_mux[] = {
+ LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+ LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+ LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
+ LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
+ LCD2D16_MARK, LCD2D17_MARK,
+};
+static const unsigned int lcd2_data24_pins[] = {
+ /* D[0:23] */
+ 128, 129, 142, 143, 144, 145, 138, 139,
+ 140, 141, 130, 131, 132, 133, 134, 135,
+ 136, 137, 146, 147, 234, 235, 238, 239
+};
+static const unsigned int lcd2_data24_mux[] = {
+ LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+ LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+ LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
+ LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
+ LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
+ LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
+};
+static const unsigned int lcd2_sync_0_pins[] = {
+ /* VSYN, HSYN, DCK, DISP */
+ 128, 129, 146, 145,
+};
+static const unsigned int lcd2_sync_0_mux[] = {
+ PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
+ LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
+};
+static const unsigned int lcd2_sync_1_pins[] = {
+ /* VSYN, HSYN, DCK, DISP */
+ 222, 221, 219, 217,
+};
+static const unsigned int lcd2_sync_1_mux[] = {
+ PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
+ LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
+};
+static const unsigned int lcd2_sys_0_pins[] = {
+ /* CS, WR, RD, RS */
+ 129, 146, 147, 145,
+};
+static const unsigned int lcd2_sys_0_mux[] = {
+ PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
+ LCD2RD__MARK, PORT145_LCD2RS_MARK,
+};
+static const unsigned int lcd2_sys_1_pins[] = {
+ /* CS, WR, RD, RS */
+ 221, 219, 147, 217,
+};
+static const unsigned int lcd2_sys_1_mux[] = {
+ PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
+ LCD2RD__MARK, PORT217_LCD2RS_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(lcd_data8),
+ SH_PFC_PIN_GROUP(lcd_data9),
+ SH_PFC_PIN_GROUP(lcd_data12),
+ SH_PFC_PIN_GROUP(lcd_data16),
+ SH_PFC_PIN_GROUP(lcd_data18),
+ SH_PFC_PIN_GROUP(lcd_data24),
+ SH_PFC_PIN_GROUP(lcd_display),
+ SH_PFC_PIN_GROUP(lcd_lclk),
+ SH_PFC_PIN_GROUP(lcd_sync),
+ SH_PFC_PIN_GROUP(lcd_sys),
+ SH_PFC_PIN_GROUP(lcd2_data8),
+ SH_PFC_PIN_GROUP(lcd2_data9),
+ SH_PFC_PIN_GROUP(lcd2_data12),
+ SH_PFC_PIN_GROUP(lcd2_data16),
+ SH_PFC_PIN_GROUP(lcd2_data18),
+ SH_PFC_PIN_GROUP(lcd2_data24),
+ SH_PFC_PIN_GROUP(lcd2_sync_0),
+ SH_PFC_PIN_GROUP(lcd2_sync_1),
+ SH_PFC_PIN_GROUP(lcd2_sys_0),
+ SH_PFC_PIN_GROUP(lcd2_sys_1),
+};
+
+static const char * const lcd_groups[] = {
+ "lcd_data8",
+ "lcd_data9",
+ "lcd_data12",
+ "lcd_data16",
+ "lcd_data18",
+ "lcd_data24",
+ "lcd_display",
+ "lcd_lclk",
+ "lcd_sync",
+ "lcd_sys",
+};
+
+static const char * const lcd2_groups[] = {
+ "lcd2_data8",
+ "lcd2_data9",
+ "lcd2_data12",
+ "lcd2_data16",
+ "lcd2_data18",
+ "lcd2_data24",
+ "lcd2_sync_0",
+ "lcd2_sync_1",
+ "lcd2_sys_0",
+ "lcd2_sys_1",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(lcd),
+ SH_PFC_FUNCTION(lcd2),
+};
+
#define PINMUX_FN_BASE GPIO_FN_VBUS_0
static const struct pinmux_func pinmux_func_gpios[] = {
@@ -3140,6 +3389,11 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
.nr_pins = ARRAY_SIZE(pinmux_pins),
.ranges = pinmux_ranges,
.nr_ranges = ARRAY_SIZE(pinmux_ranges),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 058/142] sh-pfc: sh73a0: Add SCIFA and SCIFB pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (55 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 057/142] sh-pfc: sh73a0: Add LCD and LCD2 pin groups and functions Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 059/142] sh-pfc: sh73a0: Add I2C2 and I2C3 " Simon Horman
` (84 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 351 +++++++++++++++++++++++++++++++++++
1 file changed, 351 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index c8b2604..4b0a349 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2040,6 +2040,253 @@ static const unsigned int lcd2_sys_1_mux[] = {
PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
LCD2RD__MARK, PORT217_LCD2RS_MARK,
};
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+ /* RXD, TXD */
+ 43, 17,
+};
+static const unsigned int scifa0_data_mux[] = {
+ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+ /* SCK */
+ 16,
+};
+static const unsigned int scifa0_clk_mux[] = {
+ SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+ /* RTS, CTS */
+ 42, 44,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+ SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+ /* RXD, TXD */
+ 228, 225,
+};
+static const unsigned int scifa1_data_mux[] = {
+ SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+ /* SCK */
+ 226,
+};
+static const unsigned int scifa1_clk_mux[] = {
+ SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+ /* RTS, CTS */
+ 227, 229,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+ SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_0_pins[] = {
+ /* RXD, TXD */
+ 155, 154,
+};
+static const unsigned int scifa2_data_0_mux[] = {
+ SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
+};
+static const unsigned int scifa2_clk_0_pins[] = {
+ /* SCK */
+ 158,
+};
+static const unsigned int scifa2_clk_0_mux[] = {
+ SCIFA2_SCK1_MARK,
+};
+static const unsigned int scifa2_ctrl_0_pins[] = {
+ /* RTS, CTS */
+ 156, 157,
+};
+static const unsigned int scifa2_ctrl_0_mux[] = {
+ SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
+};
+static const unsigned int scifa2_data_1_pins[] = {
+ /* RXD, TXD */
+ 233, 230,
+};
+static const unsigned int scifa2_data_1_mux[] = {
+ SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
+};
+static const unsigned int scifa2_clk_1_pins[] = {
+ /* SCK */
+ 232,
+};
+static const unsigned int scifa2_clk_1_mux[] = {
+ SCIFA2_SCK2_MARK,
+};
+static const unsigned int scifa2_ctrl_1_pins[] = {
+ /* RTS, CTS */
+ 234, 231,
+};
+static const unsigned int scifa2_ctrl_1_mux[] = {
+ SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_pins[] = {
+ /* RXD, TXD */
+ 108, 110,
+};
+static const unsigned int scifa3_data_mux[] = {
+ SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
+};
+static const unsigned int scifa3_ctrl_pins[] = {
+ /* RTS, CTS */
+ 109, 107,
+};
+static const unsigned int scifa3_ctrl_mux[] = {
+ SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_pins[] = {
+ /* RXD, TXD */
+ 33, 32,
+};
+static const unsigned int scifa4_data_mux[] = {
+ SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
+};
+static const unsigned int scifa4_ctrl_pins[] = {
+ /* RTS, CTS */
+ 34, 35,
+};
+static const unsigned int scifa4_ctrl_mux[] = {
+ SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_0_pins[] = {
+ /* RXD, TXD */
+ 246, 247,
+};
+static const unsigned int scifa5_data_0_mux[] = {
+ PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
+};
+static const unsigned int scifa5_clk_0_pins[] = {
+ /* SCK */
+ 248,
+};
+static const unsigned int scifa5_clk_0_mux[] = {
+ PORT248_SCIFA5_SCK_MARK,
+};
+static const unsigned int scifa5_ctrl_0_pins[] = {
+ /* RTS, CTS */
+ 245, 244,
+};
+static const unsigned int scifa5_ctrl_0_mux[] = {
+ PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
+};
+static const unsigned int scifa5_data_1_pins[] = {
+ /* RXD, TXD */
+ 195, 196,
+};
+static const unsigned int scifa5_data_1_mux[] = {
+ PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
+};
+static const unsigned int scifa5_clk_1_pins[] = {
+ /* SCK */
+ 197,
+};
+static const unsigned int scifa5_clk_1_mux[] = {
+ PORT197_SCIFA5_SCK_MARK,
+};
+static const unsigned int scifa5_ctrl_1_pins[] = {
+ /* RTS, CTS */
+ 194, 193,
+};
+static const unsigned int scifa5_ctrl_1_mux[] = {
+ PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
+};
+static const unsigned int scifa5_data_2_pins[] = {
+ /* RXD, TXD */
+ 162, 160,
+};
+static const unsigned int scifa5_data_2_mux[] = {
+ PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
+};
+static const unsigned int scifa5_clk_2_pins[] = {
+ /* SCK */
+ 159,
+};
+static const unsigned int scifa5_clk_2_mux[] = {
+ PORT159_SCIFA5_SCK_MARK,
+};
+static const unsigned int scifa5_ctrl_2_pins[] = {
+ /* RTS, CTS */
+ 163, 161,
+};
+static const unsigned int scifa5_ctrl_2_mux[] = {
+ PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
+};
+/* - SCIFA6 ----------------------------------------------------------------- */
+static const unsigned int scifa6_pins[] = {
+ /* TXD */
+ 240,
+};
+static const unsigned int scifa6_mux[] = {
+ SCIFA6_TXD_MARK,
+};
+/* - SCIFA7 ----------------------------------------------------------------- */
+static const unsigned int scifa7_data_pins[] = {
+ /* RXD, TXD */
+ 12, 18,
+};
+static const unsigned int scifa7_data_mux[] = {
+ SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
+};
+static const unsigned int scifa7_ctrl_pins[] = {
+ /* RTS, CTS */
+ 19, 13,
+};
+static const unsigned int scifa7_ctrl_mux[] = {
+ SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_0_pins[] = {
+ /* RXD, TXD */
+ 162, 160,
+};
+static const unsigned int scifb_data_0_mux[] = {
+ PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
+};
+static const unsigned int scifb_clk_0_pins[] = {
+ /* SCK */
+ 159,
+};
+static const unsigned int scifb_clk_0_mux[] = {
+ PORT159_SCIFB_SCK_MARK,
+};
+static const unsigned int scifb_ctrl_0_pins[] = {
+ /* RTS, CTS */
+ 163, 161,
+};
+static const unsigned int scifb_ctrl_0_mux[] = {
+ PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
+};
+static const unsigned int scifb_data_1_pins[] = {
+ /* RXD, TXD */
+ 246, 247,
+};
+static const unsigned int scifb_data_1_mux[] = {
+ PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
+};
+static const unsigned int scifb_clk_1_pins[] = {
+ /* SCK */
+ 248,
+};
+static const unsigned int scifb_clk_1_mux[] = {
+ PORT248_SCIFB_SCK_MARK,
+};
+static const unsigned int scifb_ctrl_1_pins[] = {
+ /* RTS, CTS */
+ 245, 244,
+};
+static const unsigned int scifb_ctrl_1_mux[] = {
+ PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
+};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lcd_data8),
@@ -2062,6 +2309,40 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lcd2_sync_1),
SH_PFC_PIN_GROUP(lcd2_sys_0),
SH_PFC_PIN_GROUP(lcd2_sys_1),
+ SH_PFC_PIN_GROUP(scifa0_data),
+ SH_PFC_PIN_GROUP(scifa0_clk),
+ SH_PFC_PIN_GROUP(scifa0_ctrl),
+ SH_PFC_PIN_GROUP(scifa1_data),
+ SH_PFC_PIN_GROUP(scifa1_clk),
+ SH_PFC_PIN_GROUP(scifa1_ctrl),
+ SH_PFC_PIN_GROUP(scifa2_data_0),
+ SH_PFC_PIN_GROUP(scifa2_clk_0),
+ SH_PFC_PIN_GROUP(scifa2_ctrl_0),
+ SH_PFC_PIN_GROUP(scifa2_data_1),
+ SH_PFC_PIN_GROUP(scifa2_clk_1),
+ SH_PFC_PIN_GROUP(scifa2_ctrl_1),
+ SH_PFC_PIN_GROUP(scifa3_data),
+ SH_PFC_PIN_GROUP(scifa3_ctrl),
+ SH_PFC_PIN_GROUP(scifa4_data),
+ SH_PFC_PIN_GROUP(scifa4_ctrl),
+ SH_PFC_PIN_GROUP(scifa5_data_0),
+ SH_PFC_PIN_GROUP(scifa5_clk_0),
+ SH_PFC_PIN_GROUP(scifa5_ctrl_0),
+ SH_PFC_PIN_GROUP(scifa5_data_1),
+ SH_PFC_PIN_GROUP(scifa5_clk_1),
+ SH_PFC_PIN_GROUP(scifa5_ctrl_1),
+ SH_PFC_PIN_GROUP(scifa5_data_2),
+ SH_PFC_PIN_GROUP(scifa5_clk_2),
+ SH_PFC_PIN_GROUP(scifa5_ctrl_2),
+ SH_PFC_PIN_GROUP(scifa6),
+ SH_PFC_PIN_GROUP(scifa7_data),
+ SH_PFC_PIN_GROUP(scifa7_ctrl),
+ SH_PFC_PIN_GROUP(scifb_data_0),
+ SH_PFC_PIN_GROUP(scifb_clk_0),
+ SH_PFC_PIN_GROUP(scifb_ctrl_0),
+ SH_PFC_PIN_GROUP(scifb_data_1),
+ SH_PFC_PIN_GROUP(scifb_clk_1),
+ SH_PFC_PIN_GROUP(scifb_ctrl_1),
};
static const char * const lcd_groups[] = {
@@ -2090,9 +2371,79 @@ static const char * const lcd2_groups[] = {
"lcd2_sys_1",
};
+static const char * const scifa0_groups[] = {
+ "scifa0_data",
+ "scifa0_clk",
+ "scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+ "scifa1_data",
+ "scifa1_clk",
+ "scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+ "scifa2_data_0",
+ "scifa2_clk_0",
+ "scifa2_ctrl_0",
+ "scifa2_data_1",
+ "scifa2_clk_1",
+ "scifa2_ctrl_1",
+};
+
+static const char * const scifa3_groups[] = {
+ "scifa3_data",
+ "scifa3_ctrl",
+};
+
+static const char * const scifa4_groups[] = {
+ "scifa4_data",
+ "scifa4_ctrl",
+};
+
+static const char * const scifa5_groups[] = {
+ "scifa5_data_0",
+ "scifa5_clk_0",
+ "scifa5_ctrl_0",
+ "scifa5_data_1",
+ "scifa5_clk_1",
+ "scifa5_ctrl_1",
+ "scifa5_data_2",
+ "scifa5_clk_2",
+ "scifa5_ctrl_2",
+};
+
+static const char * const scifa6_groups[] = {
+ "scifa6",
+};
+
+static const char * const scifa7_groups[] = {
+ "scifa7_data",
+ "scifa7_ctrl",
+};
+
+static const char * const scifb_groups[] = {
+ "scifb_data_0",
+ "scifb_clk_0",
+ "scifb_ctrl_0",
+ "scifb_data_1",
+ "scifb_clk_1",
+ "scifb_ctrl_1",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(lcd),
SH_PFC_FUNCTION(lcd2),
+ SH_PFC_FUNCTION(scifa0),
+ SH_PFC_FUNCTION(scifa1),
+ SH_PFC_FUNCTION(scifa2),
+ SH_PFC_FUNCTION(scifa3),
+ SH_PFC_FUNCTION(scifa4),
+ SH_PFC_FUNCTION(scifa5),
+ SH_PFC_FUNCTION(scifa6),
+ SH_PFC_FUNCTION(scifa7),
+ SH_PFC_FUNCTION(scifb),
};
#define PINMUX_FN_BASE GPIO_FN_VBUS_0
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 059/142] sh-pfc: sh73a0: Add I2C2 and I2C3 pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (56 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 058/142] sh-pfc: sh73a0: Add SCIFA and SCIFB " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 060/142] sh-pfc: sh73a0: Add FSI " Simon Horman
` (83 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 64 +++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 4b0a349..fad11d7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -1846,6 +1846,50 @@ static const struct pinmux_range pinmux_ranges[] = {
{.begin = 288, .end = 309,},
};
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_0_pins[] = {
+ /* SCL, SDA */
+ 237, 236,
+};
+static const unsigned int i2c2_0_mux[] = {
+ PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
+};
+static const unsigned int i2c2_1_pins[] = {
+ /* SCL, SDA */
+ 27, 28,
+};
+static const unsigned int i2c2_1_mux[] = {
+ PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
+};
+static const unsigned int i2c2_2_pins[] = {
+ /* SCL, SDA */
+ 115, 116,
+};
+static const unsigned int i2c2_2_mux[] = {
+ PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
+};
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_0_pins[] = {
+ /* SCL, SDA */
+ 248, 249,
+};
+static const unsigned int i2c3_0_mux[] = {
+ PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
+};
+static const unsigned int i2c3_1_pins[] = {
+ /* SCL, SDA */
+ 27, 28,
+};
+static const unsigned int i2c3_1_mux[] = {
+ PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
+};
+static const unsigned int i2c3_2_pins[] = {
+ /* SCL, SDA */
+ 115, 116,
+};
+static const unsigned int i2c3_2_mux[] = {
+ PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
+};
/* - LCD -------------------------------------------------------------------- */
static const unsigned int lcd_data8_pins[] = {
/* D[0:7] */
@@ -2289,6 +2333,12 @@ static const unsigned int scifb_ctrl_1_mux[] = {
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(i2c2_0),
+ SH_PFC_PIN_GROUP(i2c2_1),
+ SH_PFC_PIN_GROUP(i2c2_2),
+ SH_PFC_PIN_GROUP(i2c3_0),
+ SH_PFC_PIN_GROUP(i2c3_1),
+ SH_PFC_PIN_GROUP(i2c3_2),
SH_PFC_PIN_GROUP(lcd_data8),
SH_PFC_PIN_GROUP(lcd_data9),
SH_PFC_PIN_GROUP(lcd_data12),
@@ -2345,6 +2395,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb_ctrl_1),
};
+static const char * const i2c2_groups[] = {
+ "i2c2_0",
+ "i2c2_1",
+ "i2c2_2",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3_0",
+ "i2c3_1",
+ "i2c3_2",
+};
+
static const char * const lcd_groups[] = {
"lcd_data8",
"lcd_data9",
@@ -2433,6 +2495,8 @@ static const char * const scifb_groups[] = {
};
static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(lcd),
SH_PFC_FUNCTION(lcd2),
SH_PFC_FUNCTION(scifa0),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 060/142] sh-pfc: sh73a0: Add FSI pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (57 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 059/142] sh-pfc: sh73a0: Add I2C2 and I2C3 " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 061/142] sh-pfc: sh73a0: Add SDHI and MMCIF " Simon Horman
` (82 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 244 +++++++++++++++++++++++++++++++++++
1 file changed, 244 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index fad11d7..0d35f7b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -1846,6 +1846,185 @@ static const struct pinmux_range pinmux_ranges[] = {
{.begin = 288, .end = 309,},
};
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+ /* CK */
+ 49,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+ FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+ /* OMC */
+ 49,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+ FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+ /* ILR, IBT */
+ 50, 51,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+ FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+ /* OLR, OBT */
+ 50, 51,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+ FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_pins[] = {
+ /* ISLD */
+ 55,
+};
+static const unsigned int fsia_data_in_mux[] = {
+ FSIAISLD_MARK,
+};
+static const unsigned int fsia_data_out_pins[] = {
+ /* OSLD */
+ 52,
+};
+static const unsigned int fsia_data_out_mux[] = {
+ FSIAOSLD_MARK,
+};
+static const unsigned int fsia_spdif_pins[] = {
+ /* SPDIF */
+ 53,
+};
+static const unsigned int fsia_spdif_mux[] = {
+ FSIASPDIF_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+ /* CK */
+ 54,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+ FSIBCK_MARK,
+};
+static const unsigned int fsib_mclk_out_pins[] = {
+ /* OMC */
+ 54,
+};
+static const unsigned int fsib_mclk_out_mux[] = {
+ FSIBOMC_MARK,
+};
+static const unsigned int fsib_sclk_in_pins[] = {
+ /* ILR, IBT */
+ 37, 36,
+};
+static const unsigned int fsib_sclk_in_mux[] = {
+ FSIBILR_MARK, FSIBIBT_MARK,
+};
+static const unsigned int fsib_sclk_out_pins[] = {
+ /* OLR, OBT */
+ 37, 36,
+};
+static const unsigned int fsib_sclk_out_mux[] = {
+ FSIBOLR_MARK, FSIBOBT_MARK,
+};
+static const unsigned int fsib_data_in_pins[] = {
+ /* ISLD */
+ 39,
+};
+static const unsigned int fsib_data_in_mux[] = {
+ FSIBISLD_MARK,
+};
+static const unsigned int fsib_data_out_pins[] = {
+ /* OSLD */
+ 38,
+};
+static const unsigned int fsib_data_out_mux[] = {
+ FSIBOSLD_MARK,
+};
+static const unsigned int fsib_spdif_pins[] = {
+ /* SPDIF */
+ 53,
+};
+static const unsigned int fsib_spdif_mux[] = {
+ FSIBSPDIF_MARK,
+};
+/* - FSIC ------------------------------------------------------------------- */
+static const unsigned int fsic_mclk_in_pins[] = {
+ /* CK */
+ 54,
+};
+static const unsigned int fsic_mclk_in_mux[] = {
+ FSICCK_MARK,
+};
+static const unsigned int fsic_mclk_out_pins[] = {
+ /* OMC */
+ 54,
+};
+static const unsigned int fsic_mclk_out_mux[] = {
+ FSICOMC_MARK,
+};
+static const unsigned int fsic_sclk_in_pins[] = {
+ /* ILR, IBT */
+ 46, 45,
+};
+static const unsigned int fsic_sclk_in_mux[] = {
+ FSICILR_MARK, FSICIBT_MARK,
+};
+static const unsigned int fsic_sclk_out_pins[] = {
+ /* OLR, OBT */
+ 46, 45,
+};
+static const unsigned int fsic_sclk_out_mux[] = {
+ FSICOLR_MARK, FSICOBT_MARK,
+};
+static const unsigned int fsic_data_in_pins[] = {
+ /* ISLD */
+ 48,
+};
+static const unsigned int fsic_data_in_mux[] = {
+ FSICISLD_MARK,
+};
+static const unsigned int fsic_data_out_pins[] = {
+ /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
+ 47, 44, 42, 16,
+};
+static const unsigned int fsic_data_out_mux[] = {
+ FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
+};
+static const unsigned int fsic_spdif_0_pins[] = {
+ /* SPDIF */
+ 53,
+};
+static const unsigned int fsic_spdif_0_mux[] = {
+ PORT53_FSICSPDIF_MARK,
+};
+static const unsigned int fsic_spdif_1_pins[] = {
+ /* SPDIF */
+ 47,
+};
+static const unsigned int fsic_spdif_1_mux[] = {
+ PORT47_FSICSPDIF_MARK,
+};
+/* - FSID ------------------------------------------------------------------- */
+static const unsigned int fsid_sclk_in_pins[] = {
+ /* ILR, IBT */
+ 46, 45,
+};
+static const unsigned int fsid_sclk_in_mux[] = {
+ FSIDILR_MARK, FSIDIBT_MARK,
+};
+static const unsigned int fsid_sclk_out_pins[] = {
+ /* OLR, OBT */
+ 46, 45,
+};
+static const unsigned int fsid_sclk_out_mux[] = {
+ FSIDOLR_MARK, FSIDOBT_MARK,
+};
+static const unsigned int fsid_data_in_pins[] = {
+ /* ISLD */
+ 48,
+};
+static const unsigned int fsid_data_in_mux[] = {
+ FSIDISLD_MARK,
+};
/* - I2C2 ------------------------------------------------------------------- */
static const unsigned int i2c2_0_pins[] = {
/* SCL, SDA */
@@ -2333,6 +2512,31 @@ static const unsigned int scifb_ctrl_1_mux[] = {
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(fsia_mclk_in),
+ SH_PFC_PIN_GROUP(fsia_mclk_out),
+ SH_PFC_PIN_GROUP(fsia_sclk_in),
+ SH_PFC_PIN_GROUP(fsia_sclk_out),
+ SH_PFC_PIN_GROUP(fsia_data_in),
+ SH_PFC_PIN_GROUP(fsia_data_out),
+ SH_PFC_PIN_GROUP(fsia_spdif),
+ SH_PFC_PIN_GROUP(fsib_mclk_in),
+ SH_PFC_PIN_GROUP(fsib_mclk_out),
+ SH_PFC_PIN_GROUP(fsib_sclk_in),
+ SH_PFC_PIN_GROUP(fsib_sclk_out),
+ SH_PFC_PIN_GROUP(fsib_data_in),
+ SH_PFC_PIN_GROUP(fsib_data_out),
+ SH_PFC_PIN_GROUP(fsib_spdif),
+ SH_PFC_PIN_GROUP(fsic_mclk_in),
+ SH_PFC_PIN_GROUP(fsic_mclk_out),
+ SH_PFC_PIN_GROUP(fsic_sclk_in),
+ SH_PFC_PIN_GROUP(fsic_sclk_out),
+ SH_PFC_PIN_GROUP(fsic_data_in),
+ SH_PFC_PIN_GROUP(fsic_data_out),
+ SH_PFC_PIN_GROUP(fsic_spdif_0),
+ SH_PFC_PIN_GROUP(fsic_spdif_1),
+ SH_PFC_PIN_GROUP(fsid_sclk_in),
+ SH_PFC_PIN_GROUP(fsid_sclk_out),
+ SH_PFC_PIN_GROUP(fsid_data_in),
SH_PFC_PIN_GROUP(i2c2_0),
SH_PFC_PIN_GROUP(i2c2_1),
SH_PFC_PIN_GROUP(i2c2_2),
@@ -2395,6 +2599,42 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb_ctrl_1),
};
+static const char * const fsia_groups[] = {
+ "fsia_mclk_in",
+ "fsia_mclk_out",
+ "fsia_sclk_in",
+ "fsia_sclk_out",
+ "fsia_data_in",
+ "fsia_data_out",
+ "fsia_spdif",
+};
+
+static const char * const fsib_groups[] = {
+ "fsib_mclk_in",
+ "fsib_mclk_out",
+ "fsib_sclk_in",
+ "fsib_sclk_out",
+ "fsib_data_in",
+ "fsib_data_out",
+ "fsib_spdif",
+};
+
+static const char * const fsic_groups[] = {
+ "fsic_mclk_in",
+ "fsic_mclk_out",
+ "fsic_sclk_in",
+ "fsic_sclk_out",
+ "fsic_data_in",
+ "fsic_data_out",
+ "fsic_spdif",
+};
+
+static const char * const fsid_groups[] = {
+ "fsid_sclk_in",
+ "fsid_sclk_out",
+ "fsid_data_in",
+};
+
static const char * const i2c2_groups[] = {
"i2c2_0",
"i2c2_1",
@@ -2495,6 +2735,10 @@ static const char * const scifb_groups[] = {
};
static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(fsia),
+ SH_PFC_FUNCTION(fsib),
+ SH_PFC_FUNCTION(fsic),
+ SH_PFC_FUNCTION(fsid),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(lcd),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 061/142] sh-pfc: sh73a0: Add SDHI and MMCIF pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (58 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 060/142] sh-pfc: sh73a0: Add FSI " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 062/142] sh-pfc: sh73a0: Add KEYSC " Simon Horman
` (81 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Add pin group definitions for SDHI0, SDHI1, SDHI2 and MMCIF interfaces on
sh73a0.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 194 +++++++++++++++++++++++++++++++++++
1 file changed, 194 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 0d35f7b..ed5cbaf 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2263,6 +2263,66 @@ static const unsigned int lcd2_sys_1_mux[] = {
PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
LCD2RD__MARK, PORT217_LCD2RS_MARK,
};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_0_pins[] = {
+ /* D[0] */
+ 271,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+ MMCD0_0_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+ /* D[0:3] */
+ 271, 272, 273, 274,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+ MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+ /* D[0:7] */
+ 271, 272, 273, 274, 275, 276, 277, 278,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+ MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+ MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+ /* CMD, CLK */
+ 279, 270,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+ MMCCMD0_MARK, MMCCLK0_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+ /* D[0] */
+ 305,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+ MMCD1_0_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+ /* D[0:3] */
+ 305, 304, 303, 302,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+ MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+ /* D[0:7] */
+ 305, 304, 303, 302, 301, 300, 299, 298,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+ MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+ MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+ /* CMD, CLK */
+ 297, 289,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+ MMCCMD1_MARK, MMCCLK1_MARK,
+};
/* - SCIFA0 ----------------------------------------------------------------- */
static const unsigned int scifa0_data_pins[] = {
/* RXD, TXD */
@@ -2510,6 +2570,86 @@ static const unsigned int scifb_ctrl_1_pins[] = {
static const unsigned int scifb_ctrl_1_mux[] = {
PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ 252,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SDHID0_0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ 252, 253, 254, 255,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CMD, CLK */
+ 256, 250,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SDHICMD0_MARK, SDHICLK0_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ 251,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SDHICD0_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ 257,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SDHIWP0_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ 259,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SDHID1_0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ 259, 260, 261, 262,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CMD, CLK */
+ 263, 258,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SDHICMD1_MARK, SDHICLK1_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ 265,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SDHID2_0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ 265, 266, 267, 268,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CMD, CLK */
+ 269, 264,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SDHICMD2_MARK, SDHICLK2_MARK,
+};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(fsia_mclk_in),
@@ -2563,6 +2703,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lcd2_sync_1),
SH_PFC_PIN_GROUP(lcd2_sys_0),
SH_PFC_PIN_GROUP(lcd2_sys_1),
+ SH_PFC_PIN_GROUP(mmc0_data1_0),
+ SH_PFC_PIN_GROUP(mmc0_data4_0),
+ SH_PFC_PIN_GROUP(mmc0_data8_0),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+ SH_PFC_PIN_GROUP(mmc0_data1_1),
+ SH_PFC_PIN_GROUP(mmc0_data4_1),
+ SH_PFC_PIN_GROUP(mmc0_data8_1),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_1),
SH_PFC_PIN_GROUP(scifa0_data),
SH_PFC_PIN_GROUP(scifa0_clk),
SH_PFC_PIN_GROUP(scifa0_ctrl),
@@ -2597,6 +2745,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb_data_1),
SH_PFC_PIN_GROUP(scifb_clk_1),
SH_PFC_PIN_GROUP(scifb_ctrl_1),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
};
static const char * const fsia_groups[] = {
@@ -2673,6 +2832,17 @@ static const char * const lcd2_groups[] = {
"lcd2_sys_1",
};
+static const char * const mmc0_groups[] = {
+ "mmc0_data1_0",
+ "mmc0_data4_0",
+ "mmc0_data8_0",
+ "mmc0_ctrl_0",
+ "mmc0_data1_1",
+ "mmc0_data4_1",
+ "mmc0_data8_1",
+ "mmc0_ctrl_1",
+};
+
static const char * const scifa0_groups[] = {
"scifa0_data",
"scifa0_clk",
@@ -2734,6 +2904,26 @@ static const char * const scifb_groups[] = {
"scifb_ctrl_1",
};
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(fsia),
SH_PFC_FUNCTION(fsib),
@@ -2743,6 +2933,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(lcd),
SH_PFC_FUNCTION(lcd2),
+ SH_PFC_FUNCTION(mmc0),
SH_PFC_FUNCTION(scifa0),
SH_PFC_FUNCTION(scifa1),
SH_PFC_FUNCTION(scifa2),
@@ -2752,6 +2943,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scifa6),
SH_PFC_FUNCTION(scifa7),
SH_PFC_FUNCTION(scifb),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
};
#define PINMUX_FN_BASE GPIO_FN_VBUS_0
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 062/142] sh-pfc: sh73a0: Add KEYSC pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (59 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 061/142] sh-pfc: sh73a0: Add SDHI and MMCIF " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:05 ` [PATCH 063/142] sh-pfc: sh73a0: Add BSC " Simon Horman
` (80 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 213 +++++++++++++++++++++++++++++++++++
1 file changed, 213 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index ed5cbaf..aad8004 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -1846,6 +1846,12 @@ static const struct pinmux_range pinmux_ranges[] = {
{.begin = 288, .end = 309,},
};
+/* Pin numbers for pins without a corresponding GPIO port number are computed
+ * from the row and column numbers with a 1000 offset to avoid collisions with
+ * GPIO port numbers.
+ */
+#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
+
/* - FSIA ------------------------------------------------------------------- */
static const unsigned int fsia_mclk_in_pins[] = {
/* CK */
@@ -2069,6 +2075,165 @@ static const unsigned int i2c3_2_pins[] = {
static const unsigned int i2c3_2_mux[] = {
PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
};
+/* - KEYSC ------------------------------------------------------------------ */
+static const unsigned int keysc_in5_pins[] = {
+ /* KEYIN[0:4] */
+ 66, 67, 68, 69, 70,
+};
+static const unsigned int keysc_in5_mux[] = {
+ KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+ KEYIN4_MARK,
+};
+static const unsigned int keysc_in6_pins[] = {
+ /* KEYIN[0:5] */
+ 66, 67, 68, 69, 70, 71,
+};
+static const unsigned int keysc_in6_mux[] = {
+ KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+ KEYIN4_MARK, KEYIN5_MARK,
+};
+static const unsigned int keysc_in7_pins[] = {
+ /* KEYIN[0:6] */
+ 66, 67, 68, 69, 70, 71, 72,
+};
+static const unsigned int keysc_in7_mux[] = {
+ KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+ KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
+};
+static const unsigned int keysc_in8_pins[] = {
+ /* KEYIN[0:7] */
+ 66, 67, 68, 69, 70, 71, 72, 73,
+};
+static const unsigned int keysc_in8_mux[] = {
+ KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+ KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
+};
+static const unsigned int keysc_out04_pins[] = {
+ /* KEYOUT[0:4] */
+ 65, 64, 63, 62, 61,
+};
+static const unsigned int keysc_out04_mux[] = {
+ KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
+};
+static const unsigned int keysc_out5_pins[] = {
+ /* KEYOUT5 */
+ 60,
+};
+static const unsigned int keysc_out5_mux[] = {
+ KEYOUT5_MARK,
+};
+static const unsigned int keysc_out6_0_pins[] = {
+ /* KEYOUT6 */
+ 59,
+};
+static const unsigned int keysc_out6_0_mux[] = {
+ PORT59_KEYOUT6_MARK,
+};
+static const unsigned int keysc_out6_1_pins[] = {
+ /* KEYOUT6 */
+ 131,
+};
+static const unsigned int keysc_out6_1_mux[] = {
+ PORT131_KEYOUT6_MARK,
+};
+static const unsigned int keysc_out6_2_pins[] = {
+ /* KEYOUT6 */
+ 143,
+};
+static const unsigned int keysc_out6_2_mux[] = {
+ PORT143_KEYOUT6_MARK,
+};
+static const unsigned int keysc_out7_0_pins[] = {
+ /* KEYOUT7 */
+ 58,
+};
+static const unsigned int keysc_out7_0_mux[] = {
+ PORT58_KEYOUT7_MARK,
+};
+static const unsigned int keysc_out7_1_pins[] = {
+ /* KEYOUT7 */
+ 132,
+};
+static const unsigned int keysc_out7_1_mux[] = {
+ PORT132_KEYOUT7_MARK,
+};
+static const unsigned int keysc_out7_2_pins[] = {
+ /* KEYOUT7 */
+ 144,
+};
+static const unsigned int keysc_out7_2_mux[] = {
+ PORT144_KEYOUT7_MARK,
+};
+static const unsigned int keysc_out8_0_pins[] = {
+ /* KEYOUT8 */
+ PIN_NUMBER(6, 26),
+};
+static const unsigned int keysc_out8_0_mux[] = {
+ KEYOUT8_MARK,
+};
+static const unsigned int keysc_out8_1_pins[] = {
+ /* KEYOUT8 */
+ 136,
+};
+static const unsigned int keysc_out8_1_mux[] = {
+ PORT136_KEYOUT8_MARK,
+};
+static const unsigned int keysc_out8_2_pins[] = {
+ /* KEYOUT8 */
+ 138,
+};
+static const unsigned int keysc_out8_2_mux[] = {
+ PORT138_KEYOUT8_MARK,
+};
+static const unsigned int keysc_out9_0_pins[] = {
+ /* KEYOUT9 */
+ 137,
+};
+static const unsigned int keysc_out9_0_mux[] = {
+ PORT137_KEYOUT9_MARK,
+};
+static const unsigned int keysc_out9_1_pins[] = {
+ /* KEYOUT9 */
+ 139,
+};
+static const unsigned int keysc_out9_1_mux[] = {
+ PORT139_KEYOUT9_MARK,
+};
+static const unsigned int keysc_out9_2_pins[] = {
+ /* KEYOUT9 */
+ 149,
+};
+static const unsigned int keysc_out9_2_mux[] = {
+ PORT149_KEYOUT9_MARK,
+};
+static const unsigned int keysc_out10_0_pins[] = {
+ /* KEYOUT10 */
+ 132,
+};
+static const unsigned int keysc_out10_0_mux[] = {
+ PORT132_KEYOUT10_MARK,
+};
+static const unsigned int keysc_out10_1_pins[] = {
+ /* KEYOUT10 */
+ 142,
+};
+static const unsigned int keysc_out10_1_mux[] = {
+ PORT142_KEYOUT10_MARK,
+};
+static const unsigned int keysc_out11_0_pins[] = {
+ /* KEYOUT11 */
+ 131,
+};
+static const unsigned int keysc_out11_0_mux[] = {
+ PORT131_KEYOUT11_MARK,
+};
+static const unsigned int keysc_out11_1_pins[] = {
+ /* KEYOUT11 */
+ 143,
+};
+static const unsigned int keysc_out11_1_mux[] = {
+ PORT143_KEYOUT11_MARK,
+};
/* - LCD -------------------------------------------------------------------- */
static const unsigned int lcd_data8_pins[] = {
/* D[0:7] */
@@ -2683,6 +2848,28 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c3_0),
SH_PFC_PIN_GROUP(i2c3_1),
SH_PFC_PIN_GROUP(i2c3_2),
+ SH_PFC_PIN_GROUP(keysc_in5),
+ SH_PFC_PIN_GROUP(keysc_in6),
+ SH_PFC_PIN_GROUP(keysc_in7),
+ SH_PFC_PIN_GROUP(keysc_in8),
+ SH_PFC_PIN_GROUP(keysc_out04),
+ SH_PFC_PIN_GROUP(keysc_out5),
+ SH_PFC_PIN_GROUP(keysc_out6_0),
+ SH_PFC_PIN_GROUP(keysc_out6_1),
+ SH_PFC_PIN_GROUP(keysc_out6_2),
+ SH_PFC_PIN_GROUP(keysc_out7_0),
+ SH_PFC_PIN_GROUP(keysc_out7_1),
+ SH_PFC_PIN_GROUP(keysc_out7_2),
+ SH_PFC_PIN_GROUP(keysc_out8_0),
+ SH_PFC_PIN_GROUP(keysc_out8_1),
+ SH_PFC_PIN_GROUP(keysc_out8_2),
+ SH_PFC_PIN_GROUP(keysc_out9_0),
+ SH_PFC_PIN_GROUP(keysc_out9_1),
+ SH_PFC_PIN_GROUP(keysc_out9_2),
+ SH_PFC_PIN_GROUP(keysc_out10_0),
+ SH_PFC_PIN_GROUP(keysc_out10_1),
+ SH_PFC_PIN_GROUP(keysc_out11_0),
+ SH_PFC_PIN_GROUP(keysc_out11_1),
SH_PFC_PIN_GROUP(lcd_data8),
SH_PFC_PIN_GROUP(lcd_data9),
SH_PFC_PIN_GROUP(lcd_data12),
@@ -2806,6 +2993,31 @@ static const char * const i2c3_groups[] = {
"i2c3_2",
};
+static const char * const keysc_groups[] = {
+ "keysc_in5",
+ "keysc_in6",
+ "keysc_in7",
+ "keysc_in8",
+ "keysc_out04",
+ "keysc_out5",
+ "keysc_out6_0",
+ "keysc_out6_1",
+ "keysc_out6_2",
+ "keysc_out7_0",
+ "keysc_out7_1",
+ "keysc_out7_2",
+ "keysc_out8_0",
+ "keysc_out8_1",
+ "keysc_out8_2",
+ "keysc_out9_0",
+ "keysc_out9_1",
+ "keysc_out9_2",
+ "keysc_out10_0",
+ "keysc_out10_1",
+ "keysc_out11_0",
+ "keysc_out11_1",
+};
+
static const char * const lcd_groups[] = {
"lcd_data8",
"lcd_data9",
@@ -2931,6 +3143,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(fsid),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(keysc),
SH_PFC_FUNCTION(lcd),
SH_PFC_FUNCTION(lcd2),
SH_PFC_FUNCTION(mmc0),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 063/142] sh-pfc: sh73a0: Add BSC pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (60 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 062/142] sh-pfc: sh73a0: Add KEYSC " Simon Horman
@ 2013-03-18 11:05 ` Simon Horman
2013-03-18 11:06 ` [PATCH 064/142] sh-pfc: sh73a0: Add USB " Simon Horman
` (79 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 124 +++++++++++++++++++++++++++++++++++
1 file changed, 124 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index aad8004..76674af 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -1852,6 +1852,100 @@ static const struct pinmux_range pinmux_ranges[] = {
*/
#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data_0_7_pins[] = {
+ /* D[0:7] */
+ 74, 75, 76, 77, 78, 79, 80, 81,
+};
+static const unsigned int bsc_data_0_7_mux[] = {
+ D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+ D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data_8_15_pins[] = {
+ /* D[8:15] */
+ 82, 83, 84, 85, 86, 87, 88, 89,
+};
+static const unsigned int bsc_data_8_15_mux[] = {
+ D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+ D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+ /* CS */
+ 90,
+};
+static const unsigned int bsc_cs4_mux[] = {
+ CS4__MARK,
+};
+static const unsigned int bsc_cs5_a_pins[] = {
+ /* CS */
+ 91,
+};
+static const unsigned int bsc_cs5_a_mux[] = {
+ CS5A__MARK,
+};
+static const unsigned int bsc_cs5_b_pins[] = {
+ /* CS */
+ 92,
+};
+static const unsigned int bsc_cs5_b_mux[] = {
+ CS5B__MARK,
+};
+static const unsigned int bsc_cs6_a_pins[] = {
+ /* CS */
+ 94,
+};
+static const unsigned int bsc_cs6_a_mux[] = {
+ CS6A__MARK,
+};
+static const unsigned int bsc_cs6_b_pins[] = {
+ /* CS */
+ 93,
+};
+static const unsigned int bsc_cs6_b_mux[] = {
+ CS6B__MARK,
+};
+static const unsigned int bsc_rd_pins[] = {
+ /* RD */
+ 96,
+};
+static const unsigned int bsc_rd_mux[] = {
+ RD__FSC_MARK,
+};
+static const unsigned int bsc_rdwr_0_pins[] = {
+ /* RDWR */
+ 91,
+};
+static const unsigned int bsc_rdwr_0_mux[] = {
+ PORT91_RDWR_MARK,
+};
+static const unsigned int bsc_rdwr_1_pins[] = {
+ /* RDWR */
+ 97,
+};
+static const unsigned int bsc_rdwr_1_mux[] = {
+ RDWR_FWE_MARK,
+};
+static const unsigned int bsc_rdwr_2_pins[] = {
+ /* RDWR */
+ 149,
+};
+static const unsigned int bsc_rdwr_2_mux[] = {
+ PORT149_RDWR_MARK,
+};
+static const unsigned int bsc_we0_pins[] = {
+ /* WE0 */
+ 97,
+};
+static const unsigned int bsc_we0_mux[] = {
+ WE0__FWE_MARK,
+};
+static const unsigned int bsc_we1_pins[] = {
+ /* WE1 */
+ 98,
+};
+static const unsigned int bsc_we1_mux[] = {
+ WE1__MARK,
+};
/* - FSIA ------------------------------------------------------------------- */
static const unsigned int fsia_mclk_in_pins[] = {
/* CK */
@@ -2817,6 +2911,19 @@ static const unsigned int sdhi2_ctrl_mux[] = {
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(bsc_data_0_7),
+ SH_PFC_PIN_GROUP(bsc_data_8_15),
+ SH_PFC_PIN_GROUP(bsc_cs4),
+ SH_PFC_PIN_GROUP(bsc_cs5_a),
+ SH_PFC_PIN_GROUP(bsc_cs5_b),
+ SH_PFC_PIN_GROUP(bsc_cs6_a),
+ SH_PFC_PIN_GROUP(bsc_cs6_b),
+ SH_PFC_PIN_GROUP(bsc_rd),
+ SH_PFC_PIN_GROUP(bsc_rdwr_0),
+ SH_PFC_PIN_GROUP(bsc_rdwr_1),
+ SH_PFC_PIN_GROUP(bsc_rdwr_2),
+ SH_PFC_PIN_GROUP(bsc_we0),
+ SH_PFC_PIN_GROUP(bsc_we1),
SH_PFC_PIN_GROUP(fsia_mclk_in),
SH_PFC_PIN_GROUP(fsia_mclk_out),
SH_PFC_PIN_GROUP(fsia_sclk_in),
@@ -2945,6 +3052,22 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(sdhi2_ctrl),
};
+static const char * const bsc_groups[] = {
+ "bsc_data_0_7",
+ "bsc_data_8_15",
+ "bsc_cs4",
+ "bsc_cs5_a",
+ "bsc_cs5_b",
+ "bsc_cs6_a",
+ "bsc_cs6_b",
+ "bsc_rd",
+ "bsc_rdwr_0",
+ "bsc_rdwr_1",
+ "bsc_rdwr_2",
+ "bsc_we0",
+ "bsc_we1",
+};
+
static const char * const fsia_groups[] = {
"fsia_mclk_in",
"fsia_mclk_out",
@@ -3137,6 +3260,7 @@ static const char * const sdhi2_groups[] = {
};
static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(bsc),
SH_PFC_FUNCTION(fsia),
SH_PFC_FUNCTION(fsib),
SH_PFC_FUNCTION(fsic),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 064/142] sh-pfc: sh73a0: Add USB pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (61 preceding siblings ...)
2013-03-18 11:05 ` [PATCH 063/142] sh-pfc: sh73a0: Add BSC " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 065/142] sh-pfc: sh73a0: Add IrDA " Simon Horman
` (78 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 76674af..61c682a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2909,6 +2909,14 @@ static const unsigned int sdhi2_ctrl_pins[] = {
static const unsigned int sdhi2_ctrl_mux[] = {
SDHICMD2_MARK, SDHICLK2_MARK,
};
+/* - USB -------------------------------------------------------------------- */
+static const unsigned int usb_vbus_pins[] = {
+ /* VBUS */
+ 0,
+};
+static const unsigned int usb_vbus_mux[] = {
+ VBUS_0_MARK,
+};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(bsc_data_0_7),
@@ -3050,6 +3058,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(usb_vbus),
};
static const char * const bsc_groups[] = {
@@ -3259,6 +3268,10 @@ static const char * const sdhi2_groups[] = {
"sdhi2_ctrl",
};
+static const char * const usb_groups[] = {
+ "usb_vbus",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(bsc),
SH_PFC_FUNCTION(fsia),
@@ -3283,6 +3296,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(usb),
};
#define PINMUX_FN_BASE GPIO_FN_VBUS_0
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 065/142] sh-pfc: sh73a0: Add IrDA pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (62 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 064/142] sh-pfc: sh73a0: Add USB " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 066/142] sh-pfc: r8a7740: Add LCDC0 and LCDC1 " Simon Horman
` (77 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 61c682a..8fc5eb0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2169,6 +2169,21 @@ static const unsigned int i2c3_2_pins[] = {
static const unsigned int i2c3_2_mux[] = {
PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
};
+/* - IrDA ------------------------------------------------------------------- */
+static const unsigned int irda_0_pins[] = {
+ /* OUT, IN, FIRSEL */
+ 241, 242, 243,
+};
+static const unsigned int irda_0_mux[] = {
+ PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
+};
+static const unsigned int irda_1_pins[] = {
+ /* OUT, IN, FIRSEL */
+ 49, 53, 54,
+};
+static const unsigned int irda_1_mux[] = {
+ PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
+};
/* - KEYSC ------------------------------------------------------------------ */
static const unsigned int keysc_in5_pins[] = {
/* KEYIN[0:4] */
@@ -2963,6 +2978,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c3_0),
SH_PFC_PIN_GROUP(i2c3_1),
SH_PFC_PIN_GROUP(i2c3_2),
+ SH_PFC_PIN_GROUP(irda_0),
+ SH_PFC_PIN_GROUP(irda_1),
SH_PFC_PIN_GROUP(keysc_in5),
SH_PFC_PIN_GROUP(keysc_in6),
SH_PFC_PIN_GROUP(keysc_in7),
@@ -3125,6 +3142,11 @@ static const char * const i2c3_groups[] = {
"i2c3_2",
};
+static const char * const irda_groups[] = {
+ "irda_0",
+ "irda_1",
+};
+
static const char * const keysc_groups[] = {
"keysc_in5",
"keysc_in6",
@@ -3280,6 +3302,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(fsid),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(irda),
SH_PFC_FUNCTION(keysc),
SH_PFC_FUNCTION(lcd),
SH_PFC_FUNCTION(lcd2),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 066/142] sh-pfc: r8a7740: Add LCDC0 and LCDC1 pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (63 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 065/142] sh-pfc: sh73a0: Add IrDA " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 067/142] sh-pfc: r8a7740: Add SDHI and MMCIF " Simon Horman
` (76 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 276 ++++++++++++++++++++++++++++++++++
1 file changed, 276 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index de13348..e16ec10 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1658,6 +1658,277 @@ static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
};
+/* - LCD0 ------------------------------------------------------------------- */
+static const unsigned int lcd0_data8_pins[] = {
+ /* D[0:7] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+};
+static const unsigned int lcd0_data8_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+};
+static const unsigned int lcd0_data9_pins[] = {
+ /* D[0:8] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50,
+};
+static const unsigned int lcd0_data9_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK,
+};
+static const unsigned int lcd0_data12_pins[] = {
+ /* D[0:11] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47,
+};
+static const unsigned int lcd0_data12_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+};
+static const unsigned int lcd0_data16_pins[] = {
+ /* D[0:15] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47, 46, 45, 44, 43,
+};
+static const unsigned int lcd0_data16_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+ LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+};
+static const unsigned int lcd0_data18_pins[] = {
+ /* D[0:17] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47, 46, 45, 44, 43,
+ 42, 41,
+};
+static const unsigned int lcd0_data18_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+ LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+ LCD0_D16_MARK, LCD0_D17_MARK,
+};
+static const unsigned int lcd0_data24_0_pins[] = {
+ /* D[0:23] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47, 46, 45, 44, 43,
+ 42, 41, 40, 4, 3, 2, 0, 1,
+};
+static const unsigned int lcd0_data24_0_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+ LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+ LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
+ LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
+ LCD0_D23_PORT1_MARK,
+};
+static const unsigned int lcd0_data24_1_pins[] = {
+ /* D[0:23] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47, 46, 45, 44, 43,
+ 42, 41, 163, 162, 161, 158, 160, 159,
+};
+static const unsigned int lcd0_data24_1_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+ LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
+ LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
+ LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
+};
+static const unsigned int lcd0_display_pins[] = {
+ /* DON, VCPWC, VEPWC */
+ 61, 59, 60,
+};
+static const unsigned int lcd0_display_mux[] = {
+ LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
+};
+static const unsigned int lcd0_lclk_0_pins[] = {
+ /* LCLK */
+ 102,
+};
+static const unsigned int lcd0_lclk_0_mux[] = {
+ LCD0_LCLK_PORT102_MARK,
+};
+static const unsigned int lcd0_lclk_1_pins[] = {
+ /* LCLK */
+ 165,
+};
+static const unsigned int lcd0_lclk_1_mux[] = {
+ LCD0_LCLK_PORT165_MARK,
+};
+static const unsigned int lcd0_sync_pins[] = {
+ /* VSYN, HSYN, DCK, DISP */
+ 63, 64, 62, 65,
+};
+static const unsigned int lcd0_sync_mux[] = {
+ LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
+};
+static const unsigned int lcd0_sys_pins[] = {
+ /* CS, WR, RD, RS */
+ 64, 62, 164, 65,
+};
+static const unsigned int lcd0_sys_mux[] = {
+ LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
+};
+/* - LCD1 ------------------------------------------------------------------- */
+static const unsigned int lcd1_data8_pins[] = {
+ /* D[0:7] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+};
+static const unsigned int lcd1_data8_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+};
+static const unsigned int lcd1_data9_pins[] = {
+ /* D[0:8] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+ 93,
+};
+static const unsigned int lcd1_data9_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK,
+};
+static const unsigned int lcd1_data12_pins[] = {
+ /* D[0:12] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+ 93, 94, 21, 201,
+};
+static const unsigned int lcd1_data12_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+};
+static const unsigned int lcd1_data16_pins[] = {
+ /* D[0:15] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+ 93, 94, 21, 201, 200, 199, 196, 195,
+};
+static const unsigned int lcd1_data16_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+ LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+};
+static const unsigned int lcd1_data18_pins[] = {
+ /* D[0:17] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+ 93, 94, 21, 201, 200, 199, 196, 195,
+ 194, 193,
+};
+static const unsigned int lcd1_data18_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+ LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+ LCD1_D16_MARK, LCD1_D17_MARK,
+};
+static const unsigned int lcd1_data24_pins[] = {
+ /* D[0:23] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+ 93, 94, 21, 201, 200, 199, 196, 195,
+ 194, 193, 198, 197, 75, 74, 15, 14,
+};
+static const unsigned int lcd1_data24_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+ LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+ LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
+ LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
+};
+static const unsigned int lcd1_display_pins[] = {
+ /* DON, VCPWC, VEPWC */
+ 100, 5, 6,
+};
+static const unsigned int lcd1_display_mux[] = {
+ LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
+};
+static const unsigned int lcd1_lclk_pins[] = {
+ /* LCLK */
+ 40,
+};
+static const unsigned int lcd1_lclk_mux[] = {
+ LCD1_LCLK_MARK,
+};
+static const unsigned int lcd1_sync_pins[] = {
+ /* VSYN, HSYN, DCK, DISP */
+ 98, 97, 99, 12,
+};
+static const unsigned int lcd1_sync_mux[] = {
+ LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
+};
+static const unsigned int lcd1_sys_pins[] = {
+ /* CS, WR, RD, RS */
+ 97, 99, 13, 12,
+};
+static const unsigned int lcd1_sys_mux[] = {
+ LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(lcd0_data8),
+ SH_PFC_PIN_GROUP(lcd0_data9),
+ SH_PFC_PIN_GROUP(lcd0_data12),
+ SH_PFC_PIN_GROUP(lcd0_data16),
+ SH_PFC_PIN_GROUP(lcd0_data18),
+ SH_PFC_PIN_GROUP(lcd0_data24_0),
+ SH_PFC_PIN_GROUP(lcd0_data24_1),
+ SH_PFC_PIN_GROUP(lcd0_display),
+ SH_PFC_PIN_GROUP(lcd0_lclk_0),
+ SH_PFC_PIN_GROUP(lcd0_lclk_1),
+ SH_PFC_PIN_GROUP(lcd0_sync),
+ SH_PFC_PIN_GROUP(lcd0_sys),
+ SH_PFC_PIN_GROUP(lcd1_data8),
+ SH_PFC_PIN_GROUP(lcd1_data9),
+ SH_PFC_PIN_GROUP(lcd1_data12),
+ SH_PFC_PIN_GROUP(lcd1_data16),
+ SH_PFC_PIN_GROUP(lcd1_data18),
+ SH_PFC_PIN_GROUP(lcd1_data24),
+ SH_PFC_PIN_GROUP(lcd1_display),
+ SH_PFC_PIN_GROUP(lcd1_lclk),
+ SH_PFC_PIN_GROUP(lcd1_sync),
+ SH_PFC_PIN_GROUP(lcd1_sys),
+};
+
+static const char * const lcd0_groups[] = {
+ "lcd0_data8",
+ "lcd0_data9",
+ "lcd0_data12",
+ "lcd0_data16",
+ "lcd0_data18",
+ "lcd0_data24_0",
+ "lcd0_data24_1",
+ "lcd0_display",
+ "lcd0_lclk_0",
+ "lcd0_lclk_1",
+ "lcd0_sync",
+ "lcd0_sys",
+};
+
+static const char * const lcd1_groups[] = {
+ "lcd1_data8",
+ "lcd1_data9",
+ "lcd1_data12",
+ "lcd1_data16",
+ "lcd1_data18",
+ "lcd1_data24",
+ "lcd1_display",
+ "lcd1_lclk",
+ "lcd1_sync",
+ "lcd1_sys",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(lcd0),
+ SH_PFC_FUNCTION(lcd1),
+};
+
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
@@ -2596,6 +2867,11 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = {
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 067/142] sh-pfc: r8a7740: Add SDHI and MMCIF pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (64 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 066/142] sh-pfc: r8a7740: Add LCDC0 and LCDC1 " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 068/142] sh-pfc: r8a7779: Add DU " Simon Horman
` (75 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Add pin groups for the first two SDHI interfaces and two alternative pin
groups for the MMCIF interface on the r8a7740 SoC.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 248 ++++++++++++++++++++++++++++++++++
1 file changed, 248 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index e16ec10..a2f909a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1870,6 +1870,188 @@ static const unsigned int lcd1_sys_pins[] = {
static const unsigned int lcd1_sys_mux[] = {
LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_0_pins[] = {
+ /* D[0] */
+ 68,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+ MMC0_D0_PORT68_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+ /* D[0:3] */
+ 68, 69, 70, 71,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+ MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+ /* D[0:7] */
+ 68, 69, 70, 71, 72, 73, 74, 75,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+ MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+ MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+ /* CMD, CLK */
+ 67, 66,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+ MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+ /* D[0] */
+ 149,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+ MMC1_D0_PORT149_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+ /* D[0:3] */
+ 149, 148, 147, 146,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+ MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+ /* D[0:7] */
+ 149, 148, 147, 146, 145, 144, 143, 142,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+ MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+ MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+ /* CMD, CLK */
+ 104, 103,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+ MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ 77,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SDHI0_D0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ 77, 78, 79, 80,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CMD, CLK */
+ 76, 82,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SDHI0_CMD_MARK, SDHI0_CLK_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ 81,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SDHI0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ 83,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SDHI0_WP_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ 68,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SDHI1_D0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ 68, 69, 70, 71,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CMD, CLK */
+ 67, 66,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SDHI1_CMD_MARK, SDHI1_CLK_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+ /* CD */
+ 72,
+};
+static const unsigned int sdhi1_cd_mux[] = {
+ SDHI1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+ /* WP */
+ 73,
+};
+static const unsigned int sdhi1_wp_mux[] = {
+ SDHI1_WP_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ 205,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SDHI2_D0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ 205, 206, 207, 208,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CMD, CLK */
+ 204, 203,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SDHI2_CMD_MARK, SDHI2_CLK_MARK,
+};
+static const unsigned int sdhi2_cd_0_pins[] = {
+ /* CD */
+ 202,
+};
+static const unsigned int sdhi2_cd_0_mux[] = {
+ SDHI2_CD_PORT202_MARK,
+};
+static const unsigned int sdhi2_wp_0_pins[] = {
+ /* WP */
+ 177,
+};
+static const unsigned int sdhi2_wp_0_mux[] = {
+ SDHI2_WP_PORT177_MARK,
+};
+static const unsigned int sdhi2_cd_1_pins[] = {
+ /* CD */
+ 24,
+};
+static const unsigned int sdhi2_cd_1_mux[] = {
+ SDHI2_CD_PORT24_MARK,
+};
+static const unsigned int sdhi2_wp_1_pins[] = {
+ /* WP */
+ 25,
+};
+static const unsigned int sdhi2_wp_1_mux[] = {
+ SDHI2_WP_PORT25_MARK,
+};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lcd0_data8),
@@ -1894,6 +2076,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lcd1_lclk),
SH_PFC_PIN_GROUP(lcd1_sync),
SH_PFC_PIN_GROUP(lcd1_sys),
+ SH_PFC_PIN_GROUP(mmc0_data1_0),
+ SH_PFC_PIN_GROUP(mmc0_data4_0),
+ SH_PFC_PIN_GROUP(mmc0_data8_0),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+ SH_PFC_PIN_GROUP(mmc0_data1_1),
+ SH_PFC_PIN_GROUP(mmc0_data4_1),
+ SH_PFC_PIN_GROUP(mmc0_data8_1),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd_0),
+ SH_PFC_PIN_GROUP(sdhi2_wp_0),
+ SH_PFC_PIN_GROUP(sdhi2_cd_1),
+ SH_PFC_PIN_GROUP(sdhi2_wp_1),
};
static const char * const lcd0_groups[] = {
@@ -1924,9 +2131,50 @@ static const char * const lcd1_groups[] = {
"lcd1_sys",
};
+static const char * const mmc0_groups[] = {
+ "mmc0_data1_0",
+ "mmc0_data4_0",
+ "mmc0_data8_0",
+ "mmc0_ctrl_0",
+ "mmc0_data1_1",
+ "mmc0_data4_1",
+ "mmc0_data8_1",
+ "mmc0_ctrl_1",
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+ "sdhi1_cd",
+ "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+ "sdhi2_cd_0",
+ "sdhi2_wp_0",
+ "sdhi2_cd_1",
+ "sdhi2_wp_1",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(lcd0),
SH_PFC_FUNCTION(lcd1),
+ SH_PFC_FUNCTION(mmc0),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 068/142] sh-pfc: r8a7779: Add DU pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (65 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 067/142] sh-pfc: r8a7740: Add SDHI and MMCIF " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 069/142] sh-pfc: r8a7779: Add SDHI and MMCIF " Simon Horman
` (74 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 283 ++++++++++++++++++++++++++++------
1 file changed, 236 insertions(+), 47 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index eb56858..9046a8f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1436,6 +1436,190 @@ static struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
+/* - DU0 -------------------------------------------------------------------- */
+static const unsigned int du0_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ 188, 187, 186, 185, 184, 183,
+ 194, 193, 192, 191, 190, 189,
+ 200, 199, 198, 197, 196, 195,
+};
+static const unsigned int du0_rgb666_mux[] = {
+ DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
+ DU0_DR3_MARK, DU0_DR2_MARK,
+ DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
+ DU0_DG3_MARK, DU0_DG2_MARK,
+ DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
+ DU0_DB3_MARK, DU0_DB2_MARK,
+};
+static const unsigned int du0_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ 188, 187, 186, 185, 184, 183, 24, 23,
+ 194, 193, 192, 191, 190, 189, 26, 25,
+ 200, 199, 198, 197, 196, 195, 28, 27,
+};
+static const unsigned int du0_rgb888_mux[] = {
+ DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
+ DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
+ DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
+ DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
+ DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
+ DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
+};
+static const unsigned int du0_clk_0_pins[] = {
+ /* CLKIN, CLKOUT */
+ 29, 180,
+};
+static const unsigned int du0_clk_0_mux[] = {
+ DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT0_MARK,
+};
+static const unsigned int du0_clk_1_pins[] = {
+ /* CLKIN, CLKOUT */
+ 29, 30,
+};
+static const unsigned int du0_clk_1_mux[] = {
+ DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT1_MARK,
+};
+static const unsigned int du0_sync_0_pins[] = {
+ /* VSYNC, HSYNC, DISP */
+ 182, 181, 31,
+};
+static const unsigned int du0_sync_0_mux[] = {
+ DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du0_sync_1_pins[] = {
+ /* VSYNC, HSYNC, DISP */
+ 182, 181, 32,
+};
+static const unsigned int du0_sync_1_mux[] = {
+ DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
+ DU0_DISP_MARK
+};
+static const unsigned int du0_oddf_pins[] = {
+ /* ODDF */
+ 31,
+};
+static const unsigned int du0_oddf_mux[] = {
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du0_cde_pins[] = {
+ /* CDE */
+ 33,
+};
+static const unsigned int du0_cde_mux[] = {
+ DU0_CDE_MARK
+};
+/* - DU1 -------------------------------------------------------------------- */
+static const unsigned int du1_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ 41, 40, 39, 38, 37, 36,
+ 49, 48, 47, 46, 45, 44,
+ 57, 56, 55, 54, 53, 52,
+};
+static const unsigned int du1_rgb666_mux[] = {
+ DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+ DU1_DR3_MARK, DU1_DR2_MARK,
+ DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+ DU1_DG3_MARK, DU1_DG2_MARK,
+ DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+ DU1_DB3_MARK, DU1_DB2_MARK,
+};
+static const unsigned int du1_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ 41, 40, 39, 38, 37, 36, 35, 34,
+ 49, 48, 47, 46, 45, 44, 43, 32,
+ 57, 56, 55, 54, 53, 52, 51, 50,
+};
+static const unsigned int du1_rgb888_mux[] = {
+ DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+ DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
+ DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+ DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
+ DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+ DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
+};
+static const unsigned int du1_clk_pins[] = {
+ /* CLKIN, CLKOUT */
+ 58, 59,
+};
+static const unsigned int du1_clk_mux[] = {
+ DU1_DOTCLKIN_MARK, DU1_DOTCLKOUT_MARK,
+};
+static const unsigned int du1_sync_0_pins[] = {
+ /* VSYNC, HSYNC, DISP */
+ 61, 60, 62,
+};
+static const unsigned int du1_sync_0_mux[] = {
+ DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du1_sync_1_pins[] = {
+ /* VSYNC, HSYNC, DISP */
+ 61, 60, 63,
+};
+static const unsigned int du1_sync_1_mux[] = {
+ DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+ DU1_DISP_MARK
+};
+static const unsigned int du1_oddf_pins[] = {
+ /* ODDF */
+ 62,
+};
+static const unsigned int du1_oddf_mux[] = {
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du1_cde_pins[] = {
+ /* CDE */
+ 64,
+};
+static const unsigned int du1_cde_mux[] = {
+ DU1_CDE_MARK
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(du0_rgb666),
+ SH_PFC_PIN_GROUP(du0_rgb888),
+ SH_PFC_PIN_GROUP(du0_clk_0),
+ SH_PFC_PIN_GROUP(du0_clk_1),
+ SH_PFC_PIN_GROUP(du0_sync_0),
+ SH_PFC_PIN_GROUP(du0_sync_1),
+ SH_PFC_PIN_GROUP(du0_oddf),
+ SH_PFC_PIN_GROUP(du0_cde),
+ SH_PFC_PIN_GROUP(du1_rgb666),
+ SH_PFC_PIN_GROUP(du1_rgb888),
+ SH_PFC_PIN_GROUP(du1_clk),
+ SH_PFC_PIN_GROUP(du1_sync_0),
+ SH_PFC_PIN_GROUP(du1_sync_1),
+ SH_PFC_PIN_GROUP(du1_oddf),
+ SH_PFC_PIN_GROUP(du1_cde),
+};
+
+static const char * const du0_groups[] = {
+ "du0_rgb666",
+ "du0_rgb888",
+ "du0_clk_0",
+ "du0_clk_1",
+ "du0_sync_0",
+ "du0_sync_1",
+ "du0_oddf",
+ "du0_cde",
+};
+
+static const char * const du1_groups[] = {
+ "du1_rgb666",
+ "du1_rgb888",
+ "du1_clk",
+ "du1_sync_0",
+ "du1_sync_1",
+ "du1_oddf",
+ "du1_cde",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(du0),
+ SH_PFC_FUNCTION(du1),
+};
+
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
@@ -1494,79 +1678,79 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS),
GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
- GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0),
+ GPIO_FN(CC5_STATE33), GPIO_FN(LCDOUT0),
GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
- GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
+ GPIO_FN(TX5_C), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C),
- GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3),
- GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5),
- GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7),
- GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
+ GPIO_FN(LCDOUT2), GPIO_FN(LCDOUT3),
+ GPIO_FN(LCDOUT4), GPIO_FN(LCDOUT5),
+ GPIO_FN(LCDOUT6), GPIO_FN(LCDOUT7),
+ GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
GPIO_FN(AUDATA2),
/* IPSR3 */
- GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
- GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10),
- GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4),
- GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13),
- GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7),
- GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16),
+ GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
+ GPIO_FN(AUDATA3), GPIO_FN(LCDOUT10),
+ GPIO_FN(LCDOUT11),
+ GPIO_FN(LCDOUT12), GPIO_FN(LCDOUT13),
+ GPIO_FN(LCDOUT14),
+ GPIO_FN(LCDOUT15), GPIO_FN(LCDOUT16),
GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
- GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
+ GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C),
- GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3),
- GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20),
- GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6),
- GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23),
- GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
- GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK),
- GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
+ GPIO_FN(LCDOUT18),
+ GPIO_FN(LCDOUT19), GPIO_FN(LCDOUT20),
+ GPIO_FN(LCDOUT21),
+ GPIO_FN(LCDOUT22), GPIO_FN(LCDOUT23),
+ GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
+ GPIO_FN(SCL3_B), GPIO_FN(QCLK),
+ GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
- GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS),
- GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
- GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE),
+ GPIO_FN(QSTH_QHS),
+ GPIO_FN(QSTB_QHE),
+ GPIO_FN(QCPV_QDE),
GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
/* IPSR4 */
- GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
- GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
+ GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
+ GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
- GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
+ GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
- GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1),
+ GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1),
GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E),
- GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0),
- GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2),
- GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4),
- GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0),
+ GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(VI2_G0),
+ GPIO_FN(VI2_G1), GPIO_FN(VI2_G2),
+ GPIO_FN(VI2_G3), GPIO_FN(VI2_G4),
+ GPIO_FN(VI2_G5),
GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
- GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1),
+ GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D),
GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
- GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2),
- GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4),
- GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6),
- GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0),
+ GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D),
+ GPIO_FN(VI2_G6), GPIO_FN(VI2_G7),
+ GPIO_FN(VI2_R0), GPIO_FN(VI2_R1),
+ GPIO_FN(VI2_R2), GPIO_FN(VI2_R3),
GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
GPIO_FN(TX5), GPIO_FN(SCK0_D),
/* IPSR5 */
- GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
+ GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
- GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5),
- GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7),
- GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D),
- GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
- GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD),
- GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC),
- GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC),
- GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ GPIO_FN(VI2_R4), GPIO_FN(VI2_R5),
+ GPIO_FN(VI2_R6), GPIO_FN(VI2_R7),
+ GPIO_FN(SCL2_D), GPIO_FN(SDA2_D),
+ GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
+ GPIO_FN(SCL1_D), GPIO_FN(VI2_FIELD),
+ GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC),
+ GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC),
+ GPIO_FN(VI3_VSYNC),
GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
- GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6),
+ GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6),
GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
- GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
+ GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
@@ -2598,6 +2782,11 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 069/142] sh-pfc: r8a7779: Add SDHI and MMCIF pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (66 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 068/142] sh-pfc: r8a7779: Add DU " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 070/142] sh-pfc: r8a7779: Add SCIF " Simon Horman
` (73 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 284 ++++++++++++++++++++++++++++++++++
1 file changed, 284 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 9046a8f..ca16b04 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1575,6 +1575,210 @@ static const unsigned int du1_cde_pins[] = {
static const unsigned int du1_cde_mux[] = {
DU1_CDE_MARK
};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_pins[] = {
+ /* D[0] */
+ 19,
+};
+static const unsigned int mmc0_data1_mux[] = {
+ MMC0_D0_MARK,
+};
+static const unsigned int mmc0_data4_pins[] = {
+ /* D[0:3] */
+ 19, 20, 21, 2,
+};
+static const unsigned int mmc0_data4_mux[] = {
+ MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+};
+static const unsigned int mmc0_data8_pins[] = {
+ /* D[0:7] */
+ 19, 20, 21, 2, 10, 11, 15, 16,
+};
+static const unsigned int mmc0_data8_mux[] = {
+ MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+ MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
+};
+static const unsigned int mmc0_ctrl_pins[] = {
+ /* CMD, CLK */
+ 18, 17,
+};
+static const unsigned int mmc0_ctrl_mux[] = {
+ MMC0_CMD_MARK, MMC0_CLK_MARK,
+};
+
+static const unsigned int mmc1_data1_pins[] = {
+ /* D[0] */
+ 72,
+};
+static const unsigned int mmc1_data1_mux[] = {
+ MMC1_D0_MARK,
+};
+static const unsigned int mmc1_data4_pins[] = {
+ /* D[0:3] */
+ 72, 73, 74, 75,
+};
+static const unsigned int mmc1_data4_mux[] = {
+ MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+};
+static const unsigned int mmc1_data8_pins[] = {
+ /* D[0:7] */
+ 72, 73, 74, 75, 76, 77, 80, 81,
+};
+static const unsigned int mmc1_data8_mux[] = {
+ MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+ MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
+};
+static const unsigned int mmc1_ctrl_pins[] = {
+ /* CMD, CLK */
+ 68, 65,
+};
+static const unsigned int mmc1_ctrl_mux[] = {
+ MMC1_CMD_MARK, MMC1_CLK_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ 117,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ 117, 118, 119, 120,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CMD, CLK */
+ 114, 113,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SD0_CMD_MARK, SD0_CLK_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ 115,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ 116,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SD0_WP_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ 19,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SD1_DAT0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ 19, 20, 21, 2,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CMD, CLK */
+ 18, 17,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SD1_CMD_MARK, SD1_CLK_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+ /* CD */
+ 10,
+};
+static const unsigned int sdhi1_cd_mux[] = {
+ SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+ /* WP */
+ 11,
+};
+static const unsigned int sdhi1_wp_mux[] = {
+ SD1_WP_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ 97,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SD2_DAT0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ 97, 98, 99, 100,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CMD, CLK */
+ 102, 101,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SD2_CMD_MARK, SD2_CLK_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+ /* CD */
+ 103,
+};
+static const unsigned int sdhi2_cd_mux[] = {
+ SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+ /* WP */
+ 104,
+};
+static const unsigned int sdhi2_wp_mux[] = {
+ SD2_WP_MARK,
+};
+/* - SDHI3 ------------------------------------------------------------------ */
+static const unsigned int sdhi3_data1_pins[] = {
+ /* D0 */
+ 50,
+};
+static const unsigned int sdhi3_data1_mux[] = {
+ SD3_DAT0_MARK,
+};
+static const unsigned int sdhi3_data4_pins[] = {
+ /* D[0:3] */
+ 50, 51, 52, 53,
+};
+static const unsigned int sdhi3_data4_mux[] = {
+ SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+static const unsigned int sdhi3_ctrl_pins[] = {
+ /* CMD, CLK */
+ 35, 34,
+};
+static const unsigned int sdhi3_ctrl_mux[] = {
+ SD3_CMD_MARK, SD3_CLK_MARK,
+};
+static const unsigned int sdhi3_cd_pins[] = {
+ /* CD */
+ 62,
+};
+static const unsigned int sdhi3_cd_mux[] = {
+ SD3_CD_MARK,
+};
+static const unsigned int sdhi3_wp_pins[] = {
+ /* WP */
+ 64,
+};
+static const unsigned int sdhi3_wp_mux[] = {
+ SD3_WP_MARK,
+};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du0_rgb666),
@@ -1592,6 +1796,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du1_sync_1),
SH_PFC_PIN_GROUP(du1_oddf),
SH_PFC_PIN_GROUP(du1_cde),
+ SH_PFC_PIN_GROUP(mmc0_data1),
+ SH_PFC_PIN_GROUP(mmc0_data4),
+ SH_PFC_PIN_GROUP(mmc0_data8),
+ SH_PFC_PIN_GROUP(mmc0_ctrl),
+ SH_PFC_PIN_GROUP(mmc1_data1),
+ SH_PFC_PIN_GROUP(mmc1_data4),
+ SH_PFC_PIN_GROUP(mmc1_data8),
+ SH_PFC_PIN_GROUP(mmc1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd),
+ SH_PFC_PIN_GROUP(sdhi2_wp),
+ SH_PFC_PIN_GROUP(sdhi3_data1),
+ SH_PFC_PIN_GROUP(sdhi3_data4),
+ SH_PFC_PIN_GROUP(sdhi3_ctrl),
+ SH_PFC_PIN_GROUP(sdhi3_cd),
+ SH_PFC_PIN_GROUP(sdhi3_wp),
};
static const char * const du0_groups[] = {
@@ -1615,9 +1847,61 @@ static const char * const du1_groups[] = {
"du1_cde",
};
+static const char * const mmc0_groups[] = {
+ "mmc0_data1",
+ "mmc0_data4",
+ "mmc0_data8",
+ "mmc0_ctrl",
+};
+
+static const char * const mmc1_groups[] = {
+ "mmc1_data1",
+ "mmc1_data4",
+ "mmc1_data8",
+ "mmc1_ctrl",
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+ "sdhi1_cd",
+ "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+ "sdhi2_cd",
+ "sdhi2_wp",
+};
+
+static const char * const sdhi3_groups[] = {
+ "sdhi3_data1",
+ "sdhi3_data4",
+ "sdhi3_ctrl",
+ "sdhi3_cd",
+ "sdhi3_wp",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
+ SH_PFC_FUNCTION(mmc0),
+ SH_PFC_FUNCTION(mmc1),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(sdhi3),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 070/142] sh-pfc: r8a7779: Add SCIF pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (67 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 069/142] sh-pfc: r8a7779: Add SDHI and MMCIF " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 071/142] sh-pfc: r8a7779: Add HSPI " Simon Horman
` (72 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 490 ++++++++++++++++++++++++++++++++++
1 file changed, 490 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index ca16b04..a01adea 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1635,6 +1635,370 @@ static const unsigned int mmc1_ctrl_pins[] = {
static const unsigned int mmc1_ctrl_mux[] = {
MMC1_CMD_MARK, MMC1_CLK_MARK,
};
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RXD, TXD */
+ 153, 152,
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+ /* SCK */
+ 156,
+};
+static const unsigned int scif0_clk_mux[] = {
+ SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ 151, 150,
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_TANS_MARK, CTS0_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+ /* RXD, TXD */
+ 20, 19,
+};
+static const unsigned int scif0_data_b_mux[] = {
+ RX0_B_MARK, TX0_B_MARK,
+};
+static const unsigned int scif0_clk_b_pins[] = {
+ /* SCK */
+ 33,
+};
+static const unsigned int scif0_clk_b_mux[] = {
+ SCK0_B_MARK,
+};
+static const unsigned int scif0_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ 18, 11,
+};
+static const unsigned int scif0_ctrl_b_mux[] = {
+ RTS0_B_TANS_B_MARK, CTS0_B_MARK,
+};
+static const unsigned int scif0_data_c_pins[] = {
+ /* RXD, TXD */
+ 146, 147,
+};
+static const unsigned int scif0_data_c_mux[] = {
+ RX0_C_MARK, TX0_C_MARK,
+};
+static const unsigned int scif0_clk_c_pins[] = {
+ /* SCK */
+ 145,
+};
+static const unsigned int scif0_clk_c_mux[] = {
+ SCK0_C_MARK,
+};
+static const unsigned int scif0_ctrl_c_pins[] = {
+ /* RTS, CTS */
+ 149, 148,
+};
+static const unsigned int scif0_ctrl_c_mux[] = {
+ RTS0_C_TANS_C_MARK, CTS0_C_MARK,
+};
+static const unsigned int scif0_data_d_pins[] = {
+ /* RXD, TXD */
+ 43, 42,
+};
+static const unsigned int scif0_data_d_mux[] = {
+ RX0_D_MARK, TX0_D_MARK,
+};
+static const unsigned int scif0_clk_d_pins[] = {
+ /* SCK */
+ 50,
+};
+static const unsigned int scif0_clk_d_mux[] = {
+ SCK0_D_MARK,
+};
+static const unsigned int scif0_ctrl_d_pins[] = {
+ /* RTS, CTS */
+ 51, 35,
+};
+static const unsigned int scif0_ctrl_d_mux[] = {
+ RTS0_D_TANS_D_MARK, CTS0_D_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+ /* RXD, TXD */
+ 149, 148,
+};
+static const unsigned int scif1_data_mux[] = {
+ RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK */
+ 145,
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ 147, 146,
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_TANS_MARK, CTS1_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RXD, TXD */
+ 117, 114,
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_clk_b_pins[] = {
+ /* SCK */
+ 113,
+};
+static const unsigned int scif1_clk_b_mux[] = {
+ SCK1_B_MARK,
+};
+static const unsigned int scif1_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ 115, 116,
+};
+static const unsigned int scif1_ctrl_b_mux[] = {
+ RTS1_B_TANS_B_MARK, CTS1_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+ /* RXD, TXD */
+ 67, 66,
+};
+static const unsigned int scif1_data_c_mux[] = {
+ RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_clk_c_pins[] = {
+ /* SCK */
+ 86,
+};
+static const unsigned int scif1_clk_c_mux[] = {
+ SCK1_C_MARK,
+};
+static const unsigned int scif1_ctrl_c_pins[] = {
+ /* RTS, CTS */
+ 69, 68,
+};
+static const unsigned int scif1_ctrl_c_mux[] = {
+ RTS1_C_TANS_C_MARK, CTS1_C_MARK,
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_pins[] = {
+ /* RXD, TXD */
+ 106, 105,
+};
+static const unsigned int scif2_data_mux[] = {
+ RX2_MARK, TX2_MARK,
+};
+static const unsigned int scif2_clk_pins[] = {
+ /* SCK */
+ 107,
+};
+static const unsigned int scif2_clk_mux[] = {
+ SCK2_MARK,
+};
+static const unsigned int scif2_data_b_pins[] = {
+ /* RXD, TXD */
+ 120, 119,
+};
+static const unsigned int scif2_data_b_mux[] = {
+ RX2_B_MARK, TX2_B_MARK,
+};
+static const unsigned int scif2_clk_b_pins[] = {
+ /* SCK */
+ 118,
+};
+static const unsigned int scif2_clk_b_mux[] = {
+ SCK2_B_MARK,
+};
+static const unsigned int scif2_data_c_pins[] = {
+ /* RXD, TXD */
+ 33, 31,
+};
+static const unsigned int scif2_data_c_mux[] = {
+ RX2_C_MARK, TX2_C_MARK,
+};
+static const unsigned int scif2_clk_c_pins[] = {
+ /* SCK */
+ 32,
+};
+static const unsigned int scif2_clk_c_mux[] = {
+ SCK2_C_MARK,
+};
+static const unsigned int scif2_data_d_pins[] = {
+ /* RXD, TXD */
+ 64, 62,
+};
+static const unsigned int scif2_data_d_mux[] = {
+ RX2_D_MARK, TX2_D_MARK,
+};
+static const unsigned int scif2_clk_d_pins[] = {
+ /* SCK */
+ 63,
+};
+static const unsigned int scif2_clk_d_mux[] = {
+ SCK2_D_MARK,
+};
+static const unsigned int scif2_data_e_pins[] = {
+ /* RXD, TXD */
+ 20, 19,
+};
+static const unsigned int scif2_data_e_mux[] = {
+ RX2_E_MARK, TX2_E_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RXD, TXD */
+ 137, 136,
+};
+static const unsigned int scif3_data_mux[] = {
+ RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK */
+ 135,
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCK3_MARK,
+};
+
+static const unsigned int scif3_data_b_pins[] = {
+ /* RXD, TXD */
+ 64, 62,
+};
+static const unsigned int scif3_data_b_mux[] = {
+ RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
+};
+static const unsigned int scif3_data_c_pins[] = {
+ /* RXD, TXD */
+ 15, 12,
+};
+static const unsigned int scif3_data_c_mux[] = {
+ RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
+};
+static const unsigned int scif3_data_d_pins[] = {
+ /* RXD, TXD */
+ 30, 29,
+};
+static const unsigned int scif3_data_d_mux[] = {
+ RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
+};
+static const unsigned int scif3_data_e_pins[] = {
+ /* RXD, TXD */
+ 35, 34,
+};
+static const unsigned int scif3_data_e_mux[] = {
+ RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
+};
+static const unsigned int scif3_clk_e_pins[] = {
+ /* SCK */
+ 42,
+};
+static const unsigned int scif3_clk_e_mux[] = {
+ SCK3_E_MARK,
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+ /* RXD, TXD */
+ 123, 122,
+};
+static const unsigned int scif4_data_mux[] = {
+ RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+ /* SCK */
+ 121,
+};
+static const unsigned int scif4_clk_mux[] = {
+ SCK4_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+ /* RXD, TXD */
+ 111, 110,
+};
+static const unsigned int scif4_data_b_mux[] = {
+ RX4_B_MARK, TX4_B_MARK,
+};
+static const unsigned int scif4_clk_b_pins[] = {
+ /* SCK */
+ 112,
+};
+static const unsigned int scif4_clk_b_mux[] = {
+ SCK4_B_MARK,
+};
+static const unsigned int scif4_data_c_pins[] = {
+ /* RXD, TXD */
+ 22, 21,
+};
+static const unsigned int scif4_data_c_mux[] = {
+ RX4_C_MARK, TX4_C_MARK,
+};
+static const unsigned int scif4_data_d_pins[] = {
+ /* RXD, TXD */
+ 69, 68,
+};
+static const unsigned int scif4_data_d_mux[] = {
+ RX4_D_MARK, TX4_D_MARK,
+};
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_pins[] = {
+ /* RXD, TXD */
+ 51, 50,
+};
+static const unsigned int scif5_data_mux[] = {
+ RX5_MARK, TX5_MARK,
+};
+static const unsigned int scif5_clk_pins[] = {
+ /* SCK */
+ 43,
+};
+static const unsigned int scif5_clk_mux[] = {
+ SCK5_MARK,
+};
+static const unsigned int scif5_data_b_pins[] = {
+ /* RXD, TXD */
+ 18, 11,
+};
+static const unsigned int scif5_data_b_mux[] = {
+ RX5_B_MARK, TX5_B_MARK,
+};
+static const unsigned int scif5_clk_b_pins[] = {
+ /* SCK */
+ 19,
+};
+static const unsigned int scif5_clk_b_mux[] = {
+ SCK5_B_MARK,
+};
+static const unsigned int scif5_data_c_pins[] = {
+ /* RXD, TXD */
+ 24, 23,
+};
+static const unsigned int scif5_data_c_mux[] = {
+ RX5_C_MARK, TX5_C_MARK,
+};
+static const unsigned int scif5_clk_c_pins[] = {
+ /* SCK */
+ 28,
+};
+static const unsigned int scif5_clk_c_mux[] = {
+ SCK5_C_MARK,
+};
+static const unsigned int scif5_data_d_pins[] = {
+ /* RXD, TXD */
+ 8, 6,
+};
+static const unsigned int scif5_data_d_mux[] = {
+ RX5_D_MARK, TX5_D_MARK,
+};
+static const unsigned int scif5_clk_d_pins[] = {
+ /* SCK */
+ 7,
+};
+static const unsigned int scif5_clk_d_mux[] = {
+ SCK5_D_MARK,
+};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
@@ -1804,6 +2168,57 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(mmc1_data4),
SH_PFC_PIN_GROUP(mmc1_data8),
SH_PFC_PIN_GROUP(mmc1_ctrl),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif0_data_b),
+ SH_PFC_PIN_GROUP(scif0_clk_b),
+ SH_PFC_PIN_GROUP(scif0_ctrl_b),
+ SH_PFC_PIN_GROUP(scif0_data_c),
+ SH_PFC_PIN_GROUP(scif0_clk_c),
+ SH_PFC_PIN_GROUP(scif0_ctrl_c),
+ SH_PFC_PIN_GROUP(scif0_data_d),
+ SH_PFC_PIN_GROUP(scif0_clk_d),
+ SH_PFC_PIN_GROUP(scif0_ctrl_d),
+ SH_PFC_PIN_GROUP(scif1_data),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_clk_b),
+ SH_PFC_PIN_GROUP(scif1_ctrl_b),
+ SH_PFC_PIN_GROUP(scif1_data_c),
+ SH_PFC_PIN_GROUP(scif1_clk_c),
+ SH_PFC_PIN_GROUP(scif1_ctrl_c),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_clk),
+ SH_PFC_PIN_GROUP(scif2_data_b),
+ SH_PFC_PIN_GROUP(scif2_clk_b),
+ SH_PFC_PIN_GROUP(scif2_data_c),
+ SH_PFC_PIN_GROUP(scif2_clk_c),
+ SH_PFC_PIN_GROUP(scif2_data_d),
+ SH_PFC_PIN_GROUP(scif2_clk_d),
+ SH_PFC_PIN_GROUP(scif2_data_e),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif3_data_c),
+ SH_PFC_PIN_GROUP(scif3_data_d),
+ SH_PFC_PIN_GROUP(scif3_data_e),
+ SH_PFC_PIN_GROUP(scif3_clk_e),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_clk),
+ SH_PFC_PIN_GROUP(scif4_data_b),
+ SH_PFC_PIN_GROUP(scif4_clk_b),
+ SH_PFC_PIN_GROUP(scif4_data_c),
+ SH_PFC_PIN_GROUP(scif4_data_d),
+ SH_PFC_PIN_GROUP(scif5_data),
+ SH_PFC_PIN_GROUP(scif5_clk),
+ SH_PFC_PIN_GROUP(scif5_data_b),
+ SH_PFC_PIN_GROUP(scif5_clk_b),
+ SH_PFC_PIN_GROUP(scif5_data_c),
+ SH_PFC_PIN_GROUP(scif5_clk_c),
+ SH_PFC_PIN_GROUP(scif5_data_d),
+ SH_PFC_PIN_GROUP(scif5_clk_d),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -1861,6 +2276,75 @@ static const char * const mmc1_groups[] = {
"mmc1_ctrl",
};
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_clk",
+ "scif0_ctrl",
+ "scif0_data_b",
+ "scif0_clk_b",
+ "scif0_ctrl_b",
+ "scif0_data_c",
+ "scif0_clk_c",
+ "scif0_ctrl_c",
+ "scif0_data_d",
+ "scif0_clk_d",
+ "scif0_ctrl_d",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data",
+ "scif1_clk",
+ "scif1_ctrl",
+ "scif1_data_b",
+ "scif1_clk_b",
+ "scif1_ctrl_b",
+ "scif1_data_c",
+ "scif1_clk_c",
+ "scif1_ctrl_c",
+};
+
+static const char * const scif2_groups[] = {
+ "scif2_data",
+ "scif2_clk",
+ "scif2_data_b",
+ "scif2_clk_b",
+ "scif2_data_c",
+ "scif2_clk_c",
+ "scif2_data_d",
+ "scif2_clk_d",
+ "scif2_data_e",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+ "scif3_data_b",
+ "scif3_data_c",
+ "scif3_data_d",
+ "scif3_data_e",
+ "scif3_clk_e",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data",
+ "scif4_clk",
+ "scif4_data_b",
+ "scif4_clk_b",
+ "scif4_data_c",
+ "scif4_data_d",
+};
+
+static const char * const scif5_groups[] = {
+ "scif5_data",
+ "scif5_clk",
+ "scif5_data_b",
+ "scif5_clk_b",
+ "scif5_data_c",
+ "scif5_clk_c",
+ "scif5_data_d",
+ "scif5_clk_d",
+};
+
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
@@ -1902,6 +2386,12 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif5),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 071/142] sh-pfc: r8a7779: Add HSPI pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (68 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 070/142] sh-pfc: r8a7779: Add SCIF " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 072/142] sh-pfc: r8a7779: Add USB0 and USB1 PENC pinmux support Simon Horman
` (71 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 79 +++++++++++++++++++++++++++++++++-
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index a01adea..361b162 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1575,6 +1575,58 @@ static const unsigned int du1_cde_pins[] = {
static const unsigned int du1_cde_mux[] = {
DU1_CDE_MARK
};
+/* - HSPI0 ------------------------------------------------------------------ */
+static const unsigned int hspi0_pins[] = {
+ /* CLK, CS, RX, TX */
+ 150, 151, 153, 152,
+};
+static const unsigned int hspi0_mux[] = {
+ HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
+};
+/* - HSPI1 ------------------------------------------------------------------ */
+static const unsigned int hspi1_pins[] = {
+ /* CLK, CS, RX, TX */
+ 63, 58, 64, 62,
+};
+static const unsigned int hspi1_mux[] = {
+ HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
+};
+static const unsigned int hspi1_b_pins[] = {
+ /* CLK, CS, RX, TX */
+ 90, 91, 93, 92,
+};
+static const unsigned int hspi1_b_mux[] = {
+ HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
+};
+static const unsigned int hspi1_c_pins[] = {
+ /* CLK, CS, RX, TX */
+ 141, 142, 144, 143,
+};
+static const unsigned int hspi1_c_mux[] = {
+ HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
+};
+static const unsigned int hspi1_d_pins[] = {
+ /* CLK, CS, RX, TX */
+ 101, 102, 104, 103,
+};
+static const unsigned int hspi1_d_mux[] = {
+ HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
+};
+/* - HSPI2 ------------------------------------------------------------------ */
+static const unsigned int hspi2_pins[] = {
+ /* CLK, CS, RX, TX */
+ 9, 10, 11, 14,
+};
+static const unsigned int hspi2_mux[] = {
+ HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
+};
+static const unsigned int hspi2_b_pins[] = {
+ /* CLK, CS, RX, TX */
+ 7, 13, 8, 6,
+};
+static const unsigned int hspi2_b_mux[] = {
+ HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
+};
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc0_data1_pins[] = {
/* D[0] */
@@ -1605,7 +1657,6 @@ static const unsigned int mmc0_ctrl_pins[] = {
static const unsigned int mmc0_ctrl_mux[] = {
MMC0_CMD_MARK, MMC0_CLK_MARK,
};
-
static const unsigned int mmc1_data1_pins[] = {
/* D[0] */
72,
@@ -2160,6 +2211,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du1_sync_1),
SH_PFC_PIN_GROUP(du1_oddf),
SH_PFC_PIN_GROUP(du1_cde),
+ SH_PFC_PIN_GROUP(hspi0),
+ SH_PFC_PIN_GROUP(hspi1),
+ SH_PFC_PIN_GROUP(hspi1_b),
+ SH_PFC_PIN_GROUP(hspi1_c),
+ SH_PFC_PIN_GROUP(hspi1_d),
+ SH_PFC_PIN_GROUP(hspi2),
+ SH_PFC_PIN_GROUP(hspi2_b),
SH_PFC_PIN_GROUP(mmc0_data1),
SH_PFC_PIN_GROUP(mmc0_data4),
SH_PFC_PIN_GROUP(mmc0_data8),
@@ -2262,6 +2320,22 @@ static const char * const du1_groups[] = {
"du1_cde",
};
+static const char * const hspi0_groups[] = {
+ "hspi0",
+};
+
+static const char * const hspi1_groups[] = {
+ "hspi1",
+ "hspi1_b",
+ "hspi1_c",
+ "hspi1_d",
+};
+
+static const char * const hspi2_groups[] = {
+ "hspi2",
+ "hspi2_b",
+};
+
static const char * const mmc0_groups[] = {
"mmc0_data1",
"mmc0_data4",
@@ -2380,6 +2454,9 @@ static const char * const sdhi3_groups[] = {
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
+ SH_PFC_FUNCTION(hspi0),
+ SH_PFC_FUNCTION(hspi1),
+ SH_PFC_FUNCTION(hspi2),
SH_PFC_FUNCTION(mmc0),
SH_PFC_FUNCTION(mmc1),
SH_PFC_FUNCTION(sdhi0),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 072/142] sh-pfc: r8a7779: Add USB0 and USB1 PENC pinmux support
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (69 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 071/142] sh-pfc: r8a7779: Add HSPI " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 073/142] sh-pfc: r8a7779: Add USB pin groups and functions Simon Horman
` (70 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The USB0 and USB1 PENC functions were missing. Add them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 361b162..946572bc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -429,7 +429,8 @@ enum {
A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
- USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
+ USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
+ SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
SCIF_CLK_MARK, TCLK0_C_MARK,
EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
@@ -640,6 +641,9 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(A18_MARK, FN_A18),
PINMUX_DATA(A19_MARK, FN_A19),
+ PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0),
+ PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
+
PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
PINMUX_IPSR_DATA(IP0_2_0, PWM1),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 073/142] sh-pfc: r8a7779: Add USB pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (70 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 072/142] sh-pfc: r8a7779: Add USB0 and USB1 PENC pinmux support Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 074/142] sh-pfc: r8a7779: Add LBSC " Simon Horman
` (69 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 42 ++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 946572bc..6043d2c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2198,6 +2198,30 @@ static const unsigned int sdhi3_wp_pins[] = {
static const unsigned int sdhi3_wp_mux[] = {
SD3_WP_MARK,
};
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pins[] = {
+ /* OVC */
+ 150, 154,
+};
+static const unsigned int usb0_mux[] = {
+ USB_OVC0_MARK, USB_PENC0_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pins[] = {
+ /* OVC */
+ 152, 155,
+};
+static const unsigned int usb1_mux[] = {
+ USB_OVC1_MARK, USB_PENC1_MARK,
+};
+/* - USB2 ------------------------------------------------------------------- */
+static const unsigned int usb2_pins[] = {
+ /* OVC, PENC */
+ 125, 156,
+};
+static const unsigned int usb2_mux[] = {
+ USB_OVC2_MARK, USB_PENC2_MARK,
+};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du0_rgb666),
@@ -2301,6 +2325,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
+ SH_PFC_PIN_GROUP(usb0),
+ SH_PFC_PIN_GROUP(usb1),
+ SH_PFC_PIN_GROUP(usb2),
};
static const char * const du0_groups[] = {
@@ -2455,6 +2482,18 @@ static const char * const sdhi3_groups[] = {
"sdhi3_wp",
};
+static const char * const usb0_groups[] = {
+ "usb0",
+};
+
+static const char * const usb1_groups[] = {
+ "usb1",
+};
+
+static const char * const usb2_groups[] = {
+ "usb2",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
@@ -2473,6 +2512,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif5),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+ SH_PFC_FUNCTION(usb2),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 074/142] sh-pfc: r8a7779: Add LBSC pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (71 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 073/142] sh-pfc: r8a7779: Add USB pin groups and functions Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 075/142] sh-pfc: r8a7779: Add INTC " Simon Horman
` (68 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Only the CS pins and functions are currently handled.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 77 ++++++++++++++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 6043d2c..3f67143 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1631,6 +1631,63 @@ static const unsigned int hspi2_b_pins[] = {
static const unsigned int hspi2_b_mux[] = {
HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
};
+/* - LSBC ------------------------------------------------------------------- */
+static const unsigned int lbsc_cs0_pins[] = {
+ /* CS */
+ 13,
+};
+static const unsigned int lbsc_cs0_mux[] = {
+ CS0_MARK,
+};
+static const unsigned int lbsc_cs1_pins[] = {
+ /* CS */
+ 14,
+};
+static const unsigned int lbsc_cs1_mux[] = {
+ CS1_A26_MARK,
+};
+static const unsigned int lbsc_ex_cs0_pins[] = {
+ /* CS */
+ 15,
+};
+static const unsigned int lbsc_ex_cs0_mux[] = {
+ EX_CS0_MARK,
+};
+static const unsigned int lbsc_ex_cs1_pins[] = {
+ /* CS */
+ 16,
+};
+static const unsigned int lbsc_ex_cs1_mux[] = {
+ EX_CS1_MARK,
+};
+static const unsigned int lbsc_ex_cs2_pins[] = {
+ /* CS */
+ 17,
+};
+static const unsigned int lbsc_ex_cs2_mux[] = {
+ EX_CS2_MARK,
+};
+static const unsigned int lbsc_ex_cs3_pins[] = {
+ /* CS */
+ 18,
+};
+static const unsigned int lbsc_ex_cs3_mux[] = {
+ EX_CS3_MARK,
+};
+static const unsigned int lbsc_ex_cs4_pins[] = {
+ /* CS */
+ 19,
+};
+static const unsigned int lbsc_ex_cs4_mux[] = {
+ EX_CS4_MARK,
+};
+static const unsigned int lbsc_ex_cs5_pins[] = {
+ /* CS */
+ 20,
+};
+static const unsigned int lbsc_ex_cs5_mux[] = {
+ EX_CS5_MARK,
+};
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc0_data1_pins[] = {
/* D[0] */
@@ -2246,6 +2303,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(hspi1_d),
SH_PFC_PIN_GROUP(hspi2),
SH_PFC_PIN_GROUP(hspi2_b),
+ SH_PFC_PIN_GROUP(lbsc_cs0),
+ SH_PFC_PIN_GROUP(lbsc_cs1),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs0),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs1),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs2),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs3),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs4),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs5),
SH_PFC_PIN_GROUP(mmc0_data1),
SH_PFC_PIN_GROUP(mmc0_data4),
SH_PFC_PIN_GROUP(mmc0_data8),
@@ -2367,6 +2432,17 @@ static const char * const hspi2_groups[] = {
"hspi2_b",
};
+static const char * const lbsc_groups[] = {
+ "lbsc_cs0",
+ "lbsc_cs1",
+ "lbsc_ex_cs0",
+ "lbsc_ex_cs1",
+ "lbsc_ex_cs2",
+ "lbsc_ex_cs3",
+ "lbsc_ex_cs4",
+ "lbsc_ex_cs5",
+};
+
static const char * const mmc0_groups[] = {
"mmc0_data1",
"mmc0_data4",
@@ -2500,6 +2576,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(hspi0),
SH_PFC_FUNCTION(hspi1),
SH_PFC_FUNCTION(hspi2),
+ SH_PFC_FUNCTION(lbsc),
SH_PFC_FUNCTION(mmc0),
SH_PFC_FUNCTION(mmc1),
SH_PFC_FUNCTION(sdhi0),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 075/142] sh-pfc: r8a7779: Add INTC pin groups and functions
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (72 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 074/142] sh-pfc: r8a7779: Add LBSC " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 076/142] ARM: shmobile: ag5evm: Register pinctrl mappings for SCIF Simon Horman
` (67 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 77 ++++++++++++++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 3f67143..5b498ff 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1631,6 +1631,63 @@ static const unsigned int hspi2_b_pins[] = {
static const unsigned int hspi2_b_mux[] = {
HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+ /* IRQ */
+ 78,
+};
+static const unsigned int intc_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_irq0_b_pins[] = {
+ /* IRQ */
+ 141,
+};
+static const unsigned int intc_irq0_b_mux[] = {
+ IRQ0_B_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+ /* IRQ */
+ 79,
+};
+static const unsigned int intc_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_irq1_b_pins[] = {
+ /* IRQ */
+ 142,
+};
+static const unsigned int intc_irq1_b_mux[] = {
+ IRQ1_B_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+ /* IRQ */
+ 88,
+};
+static const unsigned int intc_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_irq2_b_pins[] = {
+ /* IRQ */
+ 143,
+};
+static const unsigned int intc_irq2_b_mux[] = {
+ IRQ2_B_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+ /* IRQ */
+ 89,
+};
+static const unsigned int intc_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_irq3_b_pins[] = {
+ /* IRQ */
+ 144,
+};
+static const unsigned int intc_irq3_b_mux[] = {
+ IRQ3_B_MARK,
+};
/* - LSBC ------------------------------------------------------------------- */
static const unsigned int lbsc_cs0_pins[] = {
/* CS */
@@ -2303,6 +2360,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(hspi1_d),
SH_PFC_PIN_GROUP(hspi2),
SH_PFC_PIN_GROUP(hspi2_b),
+ SH_PFC_PIN_GROUP(intc_irq0),
+ SH_PFC_PIN_GROUP(intc_irq0_b),
+ SH_PFC_PIN_GROUP(intc_irq1),
+ SH_PFC_PIN_GROUP(intc_irq1_b),
+ SH_PFC_PIN_GROUP(intc_irq2),
+ SH_PFC_PIN_GROUP(intc_irq2_b),
+ SH_PFC_PIN_GROUP(intc_irq3),
+ SH_PFC_PIN_GROUP(intc_irq3_b),
SH_PFC_PIN_GROUP(lbsc_cs0),
SH_PFC_PIN_GROUP(lbsc_cs1),
SH_PFC_PIN_GROUP(lbsc_ex_cs0),
@@ -2432,6 +2497,17 @@ static const char * const hspi2_groups[] = {
"hspi2_b",
};
+static const char * const intc_groups[] = {
+ "intc_irq0",
+ "intc_irq0_b",
+ "intc_irq1",
+ "intc_irq1_b",
+ "intc_irq2",
+ "intc_irq2_b",
+ "intc_irq3",
+ "intc_irq4_b",
+};
+
static const char * const lbsc_groups[] = {
"lbsc_cs0",
"lbsc_cs1",
@@ -2576,6 +2652,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(hspi0),
SH_PFC_FUNCTION(hspi1),
SH_PFC_FUNCTION(hspi2),
+ SH_PFC_FUNCTION(intc),
SH_PFC_FUNCTION(lbsc),
SH_PFC_FUNCTION(mmc0),
SH_PFC_FUNCTION(mmc1),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 076/142] ARM: shmobile: ag5evm: Register pinctrl mappings for SCIF
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (73 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 075/142] sh-pfc: r8a7779: Add INTC " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 077/142] ARM: shmobile: ag5evm: Register pinctrl mappings for I2C Simon Horman
` (66 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based SCIF pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-ag5evm.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index a4ac46a..5b8dcdc 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -23,6 +23,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -550,6 +551,14 @@ static struct platform_device *ag5evm_devices[] __initdata = {
&sdhi1_device,
};
+static const struct pinctrl_map ag5evm_pinctrl_map[] = {
+ /* SCIFA2 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+ "scifa2_data_0", "scifa2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+ "scifa2_ctrl_0", "scifa2"),
+};
+
static void __init ag5evm_init(void)
{
regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -558,14 +567,10 @@ static void __init ag5evm_init(void)
ARRAY_SIZE(fixed2v8_power_consumers), 3300000);
regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+ pinctrl_register_mappings(ag5evm_pinctrl_map,
+ ARRAY_SIZE(ag5evm_pinctrl_map));
sh73a0_pinmux_init();
- /* enable SCIFA2 */
- gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
- gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
- gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
- gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
-
/* enable KEYSC */
gpio_request(GPIO_FN_KEYIN0_PU, NULL);
gpio_request(GPIO_FN_KEYIN1_PU, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 077/142] ARM: shmobile: ag5evm: Register pinctrl mappings for I2C
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (74 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 076/142] ARM: shmobile: ag5evm: Register pinctrl mappings for SCIF Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 078/142] ARM: shmobile: ag5evm: Register pinctrl mappings for FSI Simon Horman
` (65 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based I2C pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-ag5evm.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 5b8dcdc..e19dade 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -552,6 +552,11 @@ static struct platform_device *ag5evm_devices[] __initdata = {
};
static const struct pinctrl_map ag5evm_pinctrl_map[] = {
+ /* I2C2 & I2C3 */
+ PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0",
+ "i2c2_0", "i2c2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
+ "i2c3_0", "i2c3"),
/* SCIFA2 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
"scifa2_data_0", "scifa2"),
@@ -591,12 +596,6 @@ static void __init ag5evm_init(void)
gpio_request(GPIO_FN_KEYOUT8, NULL);
gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
- /* enable I2C channel 2 and 3 */
- gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
- gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
- gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
- gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
-
/* enable MMCIF */
gpio_request(GPIO_FN_MMCCLK0, NULL);
gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 078/142] ARM: shmobile: ag5evm: Register pinctrl mappings for FSI
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (75 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 077/142] ARM: shmobile: ag5evm: Register pinctrl mappings for I2C Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 079/142] ARM: shmobile: ag5evm: Register pinctrl mappings for SDHI and MMCIF Simon Horman
` (64 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based FSI pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-ag5evm.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index e19dade..178bfd1 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -552,6 +552,15 @@ static struct platform_device *ag5evm_devices[] __initdata = {
};
static const struct pinctrl_map ag5evm_pinctrl_map[] = {
+ /* FSIA */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_mclk_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_sclk_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_data_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_data_out", "fsia"),
/* I2C2 & I2C3 */
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0",
"i2c2_0", "i2c2"),
@@ -613,13 +622,6 @@ static void __init ag5evm_init(void)
gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
- /* FSI A */
- gpio_request(GPIO_FN_FSIACK, NULL);
- gpio_request(GPIO_FN_FSIAILR, NULL);
- gpio_request(GPIO_FN_FSIAIBT, NULL);
- gpio_request(GPIO_FN_FSIAISLD, NULL);
- gpio_request(GPIO_FN_FSIAOSLD, NULL);
-
/* IrDA */
gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 079/142] ARM: shmobile: ag5evm: Register pinctrl mappings for SDHI and MMCIF
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (76 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 078/142] ARM: shmobile: ag5evm: Register pinctrl mappings for FSI Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 080/142] ARM: shmobile: ag5evm: Register pinctrl mappings for KEYSC Simon Horman
` (63 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl
mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-ag5evm.c | 57 +++++++++++++++++----------------
1 file changed, 30 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 178bfd1..987b9b6 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -24,6 +24,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -551,6 +552,10 @@ static struct platform_device *ag5evm_devices[] __initdata = {
&sdhi1_device,
};
+static unsigned long pin_pullup_conf[] = {
+ PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
static const struct pinctrl_map ag5evm_pinctrl_map[] = {
/* FSIA */
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
@@ -566,11 +571,36 @@ static const struct pinctrl_map ag5evm_pinctrl_map[] = {
"i2c2_0", "i2c2"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
"i2c3_0", "i2c3"),
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_ctrl_0", "mmc0"),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "PORT279", pin_pullup_conf),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", pin_pullup_conf),
/* SCIFA2 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
"scifa2_data_0", "scifa2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
"scifa2_ctrl_0", "scifa2"),
+ /* SDHI0 (CN15 [SD I/F]) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_wp", "sdhi0"),
+ /* SDHI1 (CN4 [WLAN I/F]) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_data4", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_ctrl", "sdhi1"),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_data4", pin_pullup_conf),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "PORT263", pin_pullup_conf),
};
static void __init ag5evm_init(void)
@@ -606,16 +636,6 @@ static void __init ag5evm_init(void)
gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
/* enable MMCIF */
- gpio_request(GPIO_FN_MMCCLK0, NULL);
- gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
/* enable SMSC911X */
@@ -637,23 +657,6 @@ static void __init ag5evm_init(void)
gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
lcd_backlight_set_brightness(0);
- /* enable SDHI0 on CN15 [SD I/F] */
- gpio_request(GPIO_FN_SDHIWP0, NULL);
- gpio_request(GPIO_FN_SDHICMD0, NULL);
- gpio_request(GPIO_FN_SDHICLK0, NULL);
- gpio_request(GPIO_FN_SDHID0_3, NULL);
- gpio_request(GPIO_FN_SDHID0_2, NULL);
- gpio_request(GPIO_FN_SDHID0_1, NULL);
- gpio_request(GPIO_FN_SDHID0_0, NULL);
-
- /* enable SDHI1 on CN4 [WLAN I/F] */
- gpio_request(GPIO_FN_SDHICLK1, NULL);
- gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
-
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 080/142] ARM: shmobile: ag5evm: Register pinctrl mappings for KEYSC
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (77 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 079/142] ARM: shmobile: ag5evm: Register pinctrl mappings for SDHI and MMCIF Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 081/142] ARM: shmobile: ag5evm: Register pinctrl mappings for IrDA Simon Horman
` (62 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based KEYSC pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-ag5evm.c | 37 +++++++++++++++------------------
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 987b9b6..22b9655 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -571,6 +571,23 @@ static const struct pinctrl_map ag5evm_pinctrl_map[] = {
"i2c2_0", "i2c2"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
"i2c3_0", "i2c3"),
+ /* KEYSC */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_in8", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out04", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out5", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out6_0", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out7_0", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out8_0", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out9_2", "keysc"),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_in8", pin_pullup_conf),
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", "mmc0"),
@@ -615,26 +632,6 @@ static void __init ag5evm_init(void)
ARRAY_SIZE(ag5evm_pinctrl_map));
sh73a0_pinmux_init();
- /* enable KEYSC */
- gpio_request(GPIO_FN_KEYIN0_PU, NULL);
- gpio_request(GPIO_FN_KEYIN1_PU, NULL);
- gpio_request(GPIO_FN_KEYIN2_PU, NULL);
- gpio_request(GPIO_FN_KEYIN3_PU, NULL);
- gpio_request(GPIO_FN_KEYIN4_PU, NULL);
- gpio_request(GPIO_FN_KEYIN5_PU, NULL);
- gpio_request(GPIO_FN_KEYIN6_PU, NULL);
- gpio_request(GPIO_FN_KEYIN7_PU, NULL);
- gpio_request(GPIO_FN_KEYOUT0, NULL);
- gpio_request(GPIO_FN_KEYOUT1, NULL);
- gpio_request(GPIO_FN_KEYOUT2, NULL);
- gpio_request(GPIO_FN_KEYOUT3, NULL);
- gpio_request(GPIO_FN_KEYOUT4, NULL);
- gpio_request(GPIO_FN_KEYOUT5, NULL);
- gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
- gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
- gpio_request(GPIO_FN_KEYOUT8, NULL);
- gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
-
/* enable MMCIF */
gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 081/142] ARM: shmobile: ag5evm: Register pinctrl mappings for IrDA
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (78 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 080/142] ARM: shmobile: ag5evm: Register pinctrl mappings for KEYSC Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 082/142] ARM: shmobile: ap4evb: Register pinctrl mappings for SDHI and MMCIF Simon Horman
` (61 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based IrDA pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-ag5evm.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 22b9655..c754071 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -571,6 +571,9 @@ static const struct pinctrl_map ag5evm_pinctrl_map[] = {
"i2c2_0", "i2c2"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
"i2c3_0", "i2c3"),
+ /* IrDA */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0",
+ "irda_0", "irda"),
/* KEYSC */
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_in8", "keysc"),
@@ -639,11 +642,6 @@ static void __init ag5evm_init(void)
gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
- /* IrDA */
- gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
- gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL);
- gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
-
/* LCD panel */
gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
mdelay(1);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 082/142] ARM: shmobile: ap4evb: Register pinctrl mappings for SDHI and MMCIF
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (79 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 081/142] ARM: shmobile: ag5evm: Register pinctrl mappings for IrDA Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 083/142] ARM: shmobile: armadillo800eva: Register pinctrl mappings for LCDC0 Simon Horman
` (60 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl
mappings
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-ap4evb.c | 55 +++++++++++++++------------------
1 file changed, 25 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 0a2b6e4..45f78ca 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -34,6 +34,7 @@
#include <linux/i2c.h>
#include <linux/i2c/tsc2007.h>
#include <linux/io.h>
+#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
@@ -1084,6 +1085,28 @@ static struct i2c_board_info i2c1_devices[] = {
};
+static const struct pinctrl_map ap4evb_pinctrl_map[] = {
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+ "mmc0_data8_0", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+ "mmc0_ctrl_0", "mmc0"),
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_cd", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_wp", "sdhi0"),
+ /* SDHI1 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+ "sdhi1_data4", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+ "sdhi1_ctrl", "sdhi1"),
+};
+
#define GPIO_PORT9CR IOMEM(0xE6051009)
#define GPIO_PORT10CR IOMEM(0xE605100A)
#define USCCR1 IOMEM(0xE6058144)
@@ -1110,6 +1133,8 @@ static void __init ap4evb_init(void)
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+ pinctrl_register_mappings(ap4evb_pinctrl_map,
+ ARRAY_SIZE(ap4evb_pinctrl_map));
sh7372_pinmux_init();
/* enable SCIFA0 */
@@ -1126,36 +1151,6 @@ static void __init ap4evb_init(void)
gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
- /* SDHI0 */
- gpio_request(GPIO_FN_SDHICD0, NULL);
- gpio_request(GPIO_FN_SDHIWP0, NULL);
- gpio_request(GPIO_FN_SDHICMD0, NULL);
- gpio_request(GPIO_FN_SDHICLK0, NULL);
- gpio_request(GPIO_FN_SDHID0_3, NULL);
- gpio_request(GPIO_FN_SDHID0_2, NULL);
- gpio_request(GPIO_FN_SDHID0_1, NULL);
- gpio_request(GPIO_FN_SDHID0_0, NULL);
-
- /* SDHI1 */
- gpio_request(GPIO_FN_SDHICMD1, NULL);
- gpio_request(GPIO_FN_SDHICLK1, NULL);
- gpio_request(GPIO_FN_SDHID1_3, NULL);
- gpio_request(GPIO_FN_SDHID1_2, NULL);
- gpio_request(GPIO_FN_SDHID1_1, NULL);
- gpio_request(GPIO_FN_SDHID1_0, NULL);
-
- /* MMCIF */
- gpio_request(GPIO_FN_MMCD0_0, NULL);
- gpio_request(GPIO_FN_MMCD0_1, NULL);
- gpio_request(GPIO_FN_MMCD0_2, NULL);
- gpio_request(GPIO_FN_MMCD0_3, NULL);
- gpio_request(GPIO_FN_MMCD0_4, NULL);
- gpio_request(GPIO_FN_MMCD0_5, NULL);
- gpio_request(GPIO_FN_MMCD0_6, NULL);
- gpio_request(GPIO_FN_MMCD0_7, NULL);
- gpio_request(GPIO_FN_MMCCMD0, NULL);
- gpio_request(GPIO_FN_MMCCLK0, NULL);
-
/* USB enable */
gpio_request(GPIO_FN_VBUS0_1, NULL);
gpio_request(GPIO_FN_IDIN_1_18, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 083/142] ARM: shmobile: armadillo800eva: Register pinctrl mappings for LCDC0
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (80 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 082/142] ARM: shmobile: ap4evb: Register pinctrl mappings for SDHI and MMCIF Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 084/142] ARM: shmobile: armadillo800eva: Register pinctrl mappings for SDHI and MMCIF Simon Horman
` (59 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based LCDC0 pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-shmobile/board-armadillo800eva.c | 42 ++++++++----------------
1 file changed, 13 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 92d7991..aa812cf 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -28,6 +28,7 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
+#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/sh_eth.h>
@@ -914,6 +915,16 @@ static struct platform_device *eva_devices[] __initdata = {
&i2c_gpio_device,
};
+static const struct pinctrl_map eva_pinctrl_map[] = {
+ /* LCD0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_data24_0", "lcd0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_lclk_1", "lcd0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_sync", "lcd0"),
+};
+
static void __init eva_clock_init(void)
{
struct clk *system = clk_get(NULL, "system_clk");
@@ -961,6 +972,8 @@ static void __init eva_init(void)
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+ pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
+
r8a7740_pinmux_init();
r8a7740_meram_workaround();
@@ -970,35 +983,6 @@ static void __init eva_init(void)
/* LCDC0 */
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
- gpio_request(GPIO_FN_LCD0_D0, NULL);
- gpio_request(GPIO_FN_LCD0_D1, NULL);
- gpio_request(GPIO_FN_LCD0_D2, NULL);
- gpio_request(GPIO_FN_LCD0_D3, NULL);
- gpio_request(GPIO_FN_LCD0_D4, NULL);
- gpio_request(GPIO_FN_LCD0_D5, NULL);
- gpio_request(GPIO_FN_LCD0_D6, NULL);
- gpio_request(GPIO_FN_LCD0_D7, NULL);
- gpio_request(GPIO_FN_LCD0_D8, NULL);
- gpio_request(GPIO_FN_LCD0_D9, NULL);
- gpio_request(GPIO_FN_LCD0_D10, NULL);
- gpio_request(GPIO_FN_LCD0_D11, NULL);
- gpio_request(GPIO_FN_LCD0_D12, NULL);
- gpio_request(GPIO_FN_LCD0_D13, NULL);
- gpio_request(GPIO_FN_LCD0_D14, NULL);
- gpio_request(GPIO_FN_LCD0_D15, NULL);
- gpio_request(GPIO_FN_LCD0_D16, NULL);
- gpio_request(GPIO_FN_LCD0_D17, NULL);
- gpio_request(GPIO_FN_LCD0_D18_PORT40, NULL);
- gpio_request(GPIO_FN_LCD0_D19_PORT4, NULL);
- gpio_request(GPIO_FN_LCD0_D20_PORT3, NULL);
- gpio_request(GPIO_FN_LCD0_D21_PORT2, NULL);
- gpio_request(GPIO_FN_LCD0_D22_PORT0, NULL);
- gpio_request(GPIO_FN_LCD0_D23_PORT1, NULL);
- gpio_request(GPIO_FN_LCD0_DCK, NULL);
- gpio_request(GPIO_FN_LCD0_VSYN, NULL);
- gpio_request(GPIO_FN_LCD0_HSYN, NULL);
- gpio_request(GPIO_FN_LCD0_DISP, NULL);
- gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 084/142] ARM: shmobile: armadillo800eva: Register pinctrl mappings for SDHI and MMCIF
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (81 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 083/142] ARM: shmobile: armadillo800eva: Register pinctrl mappings for LCDC0 Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 085/142] ARM: shmobile: bonito: Register pinctrl mappings for LCDC0 Simon Horman
` (58 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl
mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-armadillo800eva.c | 58 ++++++++++--------------
1 file changed, 25 insertions(+), 33 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index aa812cf..04eff93 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -657,6 +657,17 @@ static struct platform_device sdhi1_device = {
.resource = sdhi1_resources,
};
+static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = {
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+ "sdhi1_data4", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+ "sdhi1_ctrl", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+ "sdhi1_cd", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+ "sdhi1_wp", "sdhi1"),
+};
+
/* MMCIF */
static struct sh_mmcif_plat_data sh_mmcif_plat = {
.sup_pclk = 0,
@@ -923,6 +934,18 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
"lcd0_lclk_1", "lcd0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
"lcd0_sync", "lcd0"),
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
+ "mmc0_data8_1", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
+ "mmc0_ctrl_1", "mmc0"),
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+ "sdhi0_wp", "sdhi0"),
};
static void __init eva_clock_init(void)
@@ -1036,37 +1059,12 @@ static void __init eva_init(void)
}
/* SDHI0 */
- gpio_request(GPIO_FN_SDHI0_CMD, NULL);
- gpio_request(GPIO_FN_SDHI0_CLK, NULL);
- gpio_request(GPIO_FN_SDHI0_D0, NULL);
- gpio_request(GPIO_FN_SDHI0_D1, NULL);
- gpio_request(GPIO_FN_SDHI0_D2, NULL);
- gpio_request(GPIO_FN_SDHI0_D3, NULL);
- gpio_request(GPIO_FN_SDHI0_WP, NULL);
-
gpio_request_one(17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */
gpio_request_one(74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
gpio_request_one(75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
/* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
- /*
- * MMCIF
- *
- * Here doesn't care SW1.4 status,
- * since CON2 is not mounted.
- */
- gpio_request(GPIO_FN_MMC1_CLK_PORT103, NULL);
- gpio_request(GPIO_FN_MMC1_CMD_PORT104, NULL);
- gpio_request(GPIO_FN_MMC1_D0_PORT149, NULL);
- gpio_request(GPIO_FN_MMC1_D1_PORT148, NULL);
- gpio_request(GPIO_FN_MMC1_D2_PORT147, NULL);
- gpio_request(GPIO_FN_MMC1_D3_PORT146, NULL);
- gpio_request(GPIO_FN_MMC1_D4_PORT145, NULL);
- gpio_request(GPIO_FN_MMC1_D5_PORT144, NULL);
- gpio_request(GPIO_FN_MMC1_D6_PORT143, NULL);
- gpio_request(GPIO_FN_MMC1_D7_PORT142, NULL);
-
/* CEU0 */
gpio_request(GPIO_FN_VIO0_D7, NULL);
gpio_request(GPIO_FN_VIO0_D6, NULL);
@@ -1124,14 +1122,8 @@ static void __init eva_init(void)
/* CON14 enable */
} else {
/* CON8 (SDHI1) enable */
- gpio_request(GPIO_FN_SDHI1_CLK, NULL);
- gpio_request(GPIO_FN_SDHI1_CMD, NULL);
- gpio_request(GPIO_FN_SDHI1_D0, NULL);
- gpio_request(GPIO_FN_SDHI1_D1, NULL);
- gpio_request(GPIO_FN_SDHI1_D2, NULL);
- gpio_request(GPIO_FN_SDHI1_D3, NULL);
- gpio_request(GPIO_FN_SDHI1_CD, NULL);
- gpio_request(GPIO_FN_SDHI1_WP, NULL);
+ pinctrl_register_mappings(eva_sdhi1_pinctrl_map,
+ ARRAY_SIZE(eva_sdhi1_pinctrl_map));
/* SDSLOT2_PON */
gpio_request_one(16, GPIOF_OUT_INIT_HIGH, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 085/142] ARM: shmobile: bonito: Register pinctrl mappings for LCDC0
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (82 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 084/142] ARM: shmobile: armadillo800eva: Register pinctrl mappings for SDHI and MMCIF Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 086/142] ARM: shmobile: kota2: Register pinctrl mappings for SCIF Simon Horman
` (57 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based LCDC0 pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-bonito.c | 44 +++++++++++----------------------
1 file changed, 14 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index d363526..70d992c 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -24,6 +24,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/regulator/fixed.h>
@@ -288,6 +289,16 @@ static struct platform_device lcdc0_device = {
},
};
+static const struct pinctrl_map lcdc0_pinctrl_map[] = {
+ /* LCD0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_data24_1", "lcd0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_lclk_1", "lcd0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_sync", "lcd0"),
+};
+
/*
* SMSC 9221
*/
@@ -430,36 +441,9 @@ static void __init bonito_init(void)
*/
if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
- gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
- gpio_request(GPIO_FN_LCD0_D0, NULL);
- gpio_request(GPIO_FN_LCD0_D1, NULL);
- gpio_request(GPIO_FN_LCD0_D2, NULL);
- gpio_request(GPIO_FN_LCD0_D3, NULL);
- gpio_request(GPIO_FN_LCD0_D4, NULL);
- gpio_request(GPIO_FN_LCD0_D5, NULL);
- gpio_request(GPIO_FN_LCD0_D6, NULL);
- gpio_request(GPIO_FN_LCD0_D7, NULL);
- gpio_request(GPIO_FN_LCD0_D8, NULL);
- gpio_request(GPIO_FN_LCD0_D9, NULL);
- gpio_request(GPIO_FN_LCD0_D10, NULL);
- gpio_request(GPIO_FN_LCD0_D11, NULL);
- gpio_request(GPIO_FN_LCD0_D12, NULL);
- gpio_request(GPIO_FN_LCD0_D13, NULL);
- gpio_request(GPIO_FN_LCD0_D14, NULL);
- gpio_request(GPIO_FN_LCD0_D15, NULL);
- gpio_request(GPIO_FN_LCD0_D16, NULL);
- gpio_request(GPIO_FN_LCD0_D17, NULL);
- gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
- gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
- gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
- gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
- gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
- gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
- gpio_request(GPIO_FN_LCD0_DCK, NULL);
- gpio_request(GPIO_FN_LCD0_VSYN, NULL);
- gpio_request(GPIO_FN_LCD0_HSYN, NULL);
- gpio_request(GPIO_FN_LCD0_DISP, NULL);
- gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
+ pinctrl_register_mappings(lcdc0_pinctrl_map,
+ ARRAY_SIZE(lcdc0_pinctrl_map));
+ gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
NULL); /* LCDDON */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 086/142] ARM: shmobile: kota2: Register pinctrl mappings for SCIF
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (83 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 085/142] ARM: shmobile: bonito: Register pinctrl mappings for LCDC0 Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 087/142] ARM: shmobile: kota2: Register pinctrl mappings for SDHI and MMCIF Simon Horman
` (56 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based SCIF pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-kota2.c | 42 +++++++++++++++++++---------------
1 file changed, 23 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index b6f0515..09c4f00 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -24,6 +24,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -433,6 +434,26 @@ static struct platform_device *kota2_devices[] __initdata = {
&sdhi1_device,
};
+static const struct pinctrl_map kota2_pinctrl_map[] = {
+ /* SCIFA2 (UART2) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+ "scifa2_data_0", "scifa2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+ "scifa2_ctrl_0", "scifa2"),
+ /* SCIFA4 (UART1) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+ "scifa4_data", "scifa4"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+ "scifa4_ctrl", "scifa4"),
+ /* SCIFB (BT) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+ "scifb_data_0", "scifb"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+ "scifb_clk_0", "scifb"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+ "scifb_ctrl_0", "scifb"),
+};
+
static void __init kota2_init(void)
{
regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -441,20 +462,10 @@ static void __init kota2_init(void)
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+ pinctrl_register_mappings(kota2_pinctrl_map,
+ ARRAY_SIZE(kota2_pinctrl_map));
sh73a0_pinmux_init();
- /* SCIFA2 (UART2) */
- gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
- gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
- gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
- gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
-
- /* SCIFA4 (UART1) */
- gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
- gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
- gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
- gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
-
/* SMSC911X */
gpio_request(GPIO_FN_D0_NAF0, NULL);
gpio_request(GPIO_FN_D1_NAF1, NULL);
@@ -518,13 +529,6 @@ static void __init kota2_init(void)
gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
- /* SCIFB (BT) */
- gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL);
- gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL);
- gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL);
- gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL);
- gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL);
-
/* SDHI1 (BCM4330) */
gpio_request(GPIO_FN_SDHICLK1, NULL);
gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 087/142] ARM: shmobile: kota2: Register pinctrl mappings for SDHI and MMCIF
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (84 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 086/142] ARM: shmobile: kota2: Register pinctrl mappings for SCIF Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 088/142] ARM: shmobile: kota2: Register pinctrl mappings for KEYSC Simon Horman
` (55 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl
mappings.
Board code used the non-pulled-up version of the function GPIOs, but
those are defined in the PFC driver as enabling the pull-ups anyway.
Enable pull-ups on the MMCIF data and command pins through the pinconf
API.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-kota2.c | 63 +++++++++++++++++++---------------
1 file changed, 36 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 09c4f00..7fa71f5 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -25,6 +25,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -434,7 +435,20 @@ static struct platform_device *kota2_devices[] __initdata = {
&sdhi1_device,
};
+static unsigned long pin_pullup_conf[] = {
+ PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
static const struct pinctrl_map kota2_pinctrl_map[] = {
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_ctrl_0", "mmc0"),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "PORT279", pin_pullup_conf),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", pin_pullup_conf),
/* SCIFA2 (UART2) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
"scifa2_data_0", "scifa2"),
@@ -452,6 +466,28 @@ static const struct pinctrl_map kota2_pinctrl_map[] = {
"scifb_clk_0", "scifb"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
"scifb_ctrl_0", "scifb"),
+ /* SDHI0 (microSD) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_cd", "sdhi0"),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_data4", pin_pullup_conf),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "PORT256", pin_pullup_conf),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "PORT251", pin_pullup_conf),
+ /* SDHI1 (BCM4330) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_data4", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_ctrl", "sdhi1"),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_data4", pin_pullup_conf),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "PORT263", pin_pullup_conf),
};
static void __init kota2_init(void)
@@ -508,35 +544,8 @@ static void __init kota2_init(void)
gpio_request(GPIO_FN_KEYOUT8, NULL);
/* MMCIF */
- gpio_request(GPIO_FN_MMCCLK0, NULL);
- gpio_request(GPIO_FN_MMCD0_0, NULL);
- gpio_request(GPIO_FN_MMCD0_1, NULL);
- gpio_request(GPIO_FN_MMCD0_2, NULL);
- gpio_request(GPIO_FN_MMCD0_3, NULL);
- gpio_request(GPIO_FN_MMCD0_4, NULL);
- gpio_request(GPIO_FN_MMCD0_5, NULL);
- gpio_request(GPIO_FN_MMCD0_6, NULL);
- gpio_request(GPIO_FN_MMCD0_7, NULL);
- gpio_request(GPIO_FN_MMCCMD0, NULL);
gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
- /* SDHI0 (microSD) */
- gpio_request(GPIO_FN_SDHICD0_PU, NULL);
- gpio_request(GPIO_FN_SDHICMD0_PU, NULL);
- gpio_request(GPIO_FN_SDHICLK0, NULL);
- gpio_request(GPIO_FN_SDHID0_3_PU, NULL);
- gpio_request(GPIO_FN_SDHID0_2_PU, NULL);
- gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
- gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
-
- /* SDHI1 (BCM4330) */
- gpio_request(GPIO_FN_SDHICLK1, NULL);
- gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
-
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 088/142] ARM: shmobile: kota2: Register pinctrl mappings for KEYSC
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (85 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 087/142] ARM: shmobile: kota2: Register pinctrl mappings for SDHI and MMCIF Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 089/142] ARM: shmobile: kota2: Register pinctrl mappings for BSC Simon Horman
` (54 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based KEYSC pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-kota2.c | 34 +++++++++++++++-------------------
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 7fa71f5..3f36557 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -440,6 +440,21 @@ static unsigned long pin_pullup_conf[] = {
};
static const struct pinctrl_map kota2_pinctrl_map[] = {
+ /* KEYSC */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_in8", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out04", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out5", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out6_0", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out7_0", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out8_0", "keysc"),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_in8", pin_pullup_conf),
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", "mmc0"),
@@ -524,25 +539,6 @@ static void __init kota2_init(void)
gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
- /* KEYSC */
- gpio_request(GPIO_FN_KEYIN0_PU, NULL);
- gpio_request(GPIO_FN_KEYIN1_PU, NULL);
- gpio_request(GPIO_FN_KEYIN2_PU, NULL);
- gpio_request(GPIO_FN_KEYIN3_PU, NULL);
- gpio_request(GPIO_FN_KEYIN4_PU, NULL);
- gpio_request(GPIO_FN_KEYIN5_PU, NULL);
- gpio_request(GPIO_FN_KEYIN6_PU, NULL);
- gpio_request(GPIO_FN_KEYIN7_PU, NULL);
- gpio_request(GPIO_FN_KEYOUT0, NULL);
- gpio_request(GPIO_FN_KEYOUT1, NULL);
- gpio_request(GPIO_FN_KEYOUT2, NULL);
- gpio_request(GPIO_FN_KEYOUT3, NULL);
- gpio_request(GPIO_FN_KEYOUT4, NULL);
- gpio_request(GPIO_FN_KEYOUT5, NULL);
- gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
- gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
- gpio_request(GPIO_FN_KEYOUT8, NULL);
-
/* MMCIF */
gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 089/142] ARM: shmobile: kota2: Register pinctrl mappings for BSC
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (86 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 088/142] ARM: shmobile: kota2: Register pinctrl mappings for KEYSC Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 090/142] ARM: shmobile: kzm9g: Register pinctrl mappings for LCD Simon Horman
` (53 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based BSC pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-kota2.c | 27 +++++++++------------------
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 3f36557..ef5ca0e 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -503,6 +503,15 @@ static const struct pinctrl_map kota2_pinctrl_map[] = {
"sdhi1_data4", pin_pullup_conf),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"PORT263", pin_pullup_conf),
+ /* SMSC911X */
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+ "bsc_data_0_7", "bsc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+ "bsc_data_8_15", "bsc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+ "bsc_cs5_a", "bsc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+ "bsc_we0", "bsc"),
};
static void __init kota2_init(void)
@@ -518,24 +527,6 @@ static void __init kota2_init(void)
sh73a0_pinmux_init();
/* SMSC911X */
- gpio_request(GPIO_FN_D0_NAF0, NULL);
- gpio_request(GPIO_FN_D1_NAF1, NULL);
- gpio_request(GPIO_FN_D2_NAF2, NULL);
- gpio_request(GPIO_FN_D3_NAF3, NULL);
- gpio_request(GPIO_FN_D4_NAF4, NULL);
- gpio_request(GPIO_FN_D5_NAF5, NULL);
- gpio_request(GPIO_FN_D6_NAF6, NULL);
- gpio_request(GPIO_FN_D7_NAF7, NULL);
- gpio_request(GPIO_FN_D8_NAF8, NULL);
- gpio_request(GPIO_FN_D9_NAF9, NULL);
- gpio_request(GPIO_FN_D10_NAF10, NULL);
- gpio_request(GPIO_FN_D11_NAF11, NULL);
- gpio_request(GPIO_FN_D12_NAF12, NULL);
- gpio_request(GPIO_FN_D13_NAF13, NULL);
- gpio_request(GPIO_FN_D14_NAF14, NULL);
- gpio_request(GPIO_FN_D15_NAF15, NULL);
- gpio_request(GPIO_FN_CS5A_, NULL);
- gpio_request(GPIO_FN_WE0__FWE, NULL);
gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 090/142] ARM: shmobile: kzm9g: Register pinctrl mappings for LCD
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (87 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 089/142] ARM: shmobile: kota2: Register pinctrl mappings for BSC Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 091/142] ARM: shmobile: kzm9g: Register pinctrl mappings for SCIF Simon Horman
` (52 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based LCD pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-shmobile/board-kzm9g.c | 38 ++++++++++------------------------
1 file changed, 11 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 65a5e0b..7cef005 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -30,6 +30,7 @@
#include <linux/mmc/sh_mmcif.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
+#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
@@ -599,6 +600,14 @@ static struct platform_device *kzm_devices[] __initdata = {
&fsi_ak4648_device,
};
+static const struct pinctrl_map kzm_pinctrl_map[] = {
+ /* LCD */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
+ "lcd_data24", "lcd"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
+ "lcd_sync", "lcd"),
+};
+
/*
* FIXME
*
@@ -660,6 +669,8 @@ static void __init kzm_init(void)
ARRAY_SIZE(fixed2v8_power_consumers), 2800000);
regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+ pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
+
sh73a0_pinmux_init();
/* enable SCIFA4 */
@@ -675,33 +686,6 @@ static void __init kzm_init(void)
gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
/* LCDC */
- gpio_request(GPIO_FN_LCDD23, NULL);
- gpio_request(GPIO_FN_LCDD22, NULL);
- gpio_request(GPIO_FN_LCDD21, NULL);
- gpio_request(GPIO_FN_LCDD20, NULL);
- gpio_request(GPIO_FN_LCDD19, NULL);
- gpio_request(GPIO_FN_LCDD18, NULL);
- gpio_request(GPIO_FN_LCDD17, NULL);
- gpio_request(GPIO_FN_LCDD16, NULL);
- gpio_request(GPIO_FN_LCDD15, NULL);
- gpio_request(GPIO_FN_LCDD14, NULL);
- gpio_request(GPIO_FN_LCDD13, NULL);
- gpio_request(GPIO_FN_LCDD12, NULL);
- gpio_request(GPIO_FN_LCDD11, NULL);
- gpio_request(GPIO_FN_LCDD10, NULL);
- gpio_request(GPIO_FN_LCDD9, NULL);
- gpio_request(GPIO_FN_LCDD8, NULL);
- gpio_request(GPIO_FN_LCDD7, NULL);
- gpio_request(GPIO_FN_LCDD6, NULL);
- gpio_request(GPIO_FN_LCDD5, NULL);
- gpio_request(GPIO_FN_LCDD4, NULL);
- gpio_request(GPIO_FN_LCDD3, NULL);
- gpio_request(GPIO_FN_LCDD2, NULL);
- gpio_request(GPIO_FN_LCDD1, NULL);
- gpio_request(GPIO_FN_LCDD0, NULL);
- gpio_request(GPIO_FN_LCDDISP, NULL);
- gpio_request(GPIO_FN_LCDDCK, NULL);
-
gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 091/142] ARM: shmobile: kzm9g: Register pinctrl mappings for SCIF
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (88 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 090/142] ARM: shmobile: kzm9g: Register pinctrl mappings for LCD Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 092/142] ARM: shmobile: kzm9g: Register pinctrl mappings for I2C Simon Horman
` (51 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based SCIF pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-kzm9g.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 7cef005..3d2cdc4 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -606,6 +606,11 @@ static const struct pinctrl_map kzm_pinctrl_map[] = {
"lcd_data24", "lcd"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
"lcd_sync", "lcd"),
+ /* SCIFA4 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+ "scifa4_data", "scifa4"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+ "scifa4_ctrl", "scifa4"),
};
/*
@@ -673,12 +678,6 @@ static void __init kzm_init(void)
sh73a0_pinmux_init();
- /* enable SCIFA4 */
- gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
- gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
- gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
- gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
-
/* CS4 for SMSC/USB */
gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 092/142] ARM: shmobile: kzm9g: Register pinctrl mappings for I2C
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (89 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 091/142] ARM: shmobile: kzm9g: Register pinctrl mappings for SCIF Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 093/142] ARM: shmobile: kzm9g: Register pinctrl mappings for FSI Simon Horman
` (50 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based I2C pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-kzm9g.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 3d2cdc4..df3c5ca 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -601,6 +601,9 @@ static struct platform_device *kzm_devices[] __initdata = {
};
static const struct pinctrl_map kzm_pinctrl_map[] = {
+ /* I2C3 */
+ PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
+ "i2c3_1", "i2c3"),
/* LCD */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
"lcd_data24", "lcd"),
@@ -724,10 +727,6 @@ static void __init kzm_init(void)
gpio_request(GPIO_FN_SDHICLK2, NULL);
gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
- /* I2C 3 */
- gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
- gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
-
/* enable FSI2 port A (ak4648) */
gpio_request(GPIO_FN_FSIACK, NULL);
gpio_request(GPIO_FN_FSIAILR, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 093/142] ARM: shmobile: kzm9g: Register pinctrl mappings for FSI
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (90 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 092/142] ARM: shmobile: kzm9g: Register pinctrl mappings for I2C Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 094/142] ARM: shmobile: kzm9g: Register pinctrl mappings for SDHI and MMCIF Simon Horman
` (49 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based FSI pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-kzm9g.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index df3c5ca..a628d1b 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -601,6 +601,15 @@ static struct platform_device *kzm_devices[] __initdata = {
};
static const struct pinctrl_map kzm_pinctrl_map[] = {
+ /* FSIA (AK4648) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_mclk_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_sclk_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_data_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_data_out", "fsia"),
/* I2C3 */
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
"i2c3_1", "i2c3"),
@@ -727,13 +736,6 @@ static void __init kzm_init(void)
gpio_request(GPIO_FN_SDHICLK2, NULL);
gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
- /* enable FSI2 port A (ak4648) */
- gpio_request(GPIO_FN_FSIACK, NULL);
- gpio_request(GPIO_FN_FSIAILR, NULL);
- gpio_request(GPIO_FN_FSIAIBT, NULL);
- gpio_request(GPIO_FN_FSIAISLD, NULL);
- gpio_request(GPIO_FN_FSIAOSLD, NULL);
-
/* enable USB */
gpio_request(GPIO_FN_VBUS_0, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 094/142] ARM: shmobile: kzm9g: Register pinctrl mappings for SDHI and MMCIF
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (91 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 093/142] ARM: shmobile: kzm9g: Register pinctrl mappings for FSI Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 095/142] ARM: shmobile: kzm9g: Register pinctrl mappings for BSC Simon Horman
` (48 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl
mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-kzm9g.c | 54 ++++++++++++++++++----------------
1 file changed, 28 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index a628d1b..335bdbb 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -31,6 +31,7 @@
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
@@ -600,6 +601,10 @@ static struct platform_device *kzm_devices[] __initdata = {
&fsi_ak4648_device,
};
+static unsigned long pin_pullup_conf[] = {
+ PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
static const struct pinctrl_map kzm_pinctrl_map[] = {
/* FSIA (AK4648) */
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
@@ -618,11 +623,34 @@ static const struct pinctrl_map kzm_pinctrl_map[] = {
"lcd_data24", "lcd"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
"lcd_sync", "lcd"),
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_ctrl_0", "mmc0"),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "PORT279", pin_pullup_conf),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", pin_pullup_conf),
/* SCIFA4 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_data", "scifa4"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_ctrl", "scifa4"),
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_cd", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_wp", "sdhi0"),
+ /* SDHI2 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
+ "sdhi2_data4", "sdhi2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
+ "sdhi2_ctrl", "sdhi2"),
};
/*
@@ -703,37 +731,11 @@ static void __init kzm_init(void)
/* Touchscreen */
gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
- /* enable MMCIF */
- gpio_request(GPIO_FN_MMCCLK0, NULL);
- gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
-
/* enable SD */
- gpio_request(GPIO_FN_SDHIWP0, NULL);
- gpio_request(GPIO_FN_SDHICD0, NULL);
- gpio_request(GPIO_FN_SDHICMD0, NULL);
- gpio_request(GPIO_FN_SDHICLK0, NULL);
- gpio_request(GPIO_FN_SDHID0_3, NULL);
- gpio_request(GPIO_FN_SDHID0_2, NULL);
- gpio_request(GPIO_FN_SDHID0_1, NULL);
- gpio_request(GPIO_FN_SDHID0_0, NULL);
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
/* enable Micro SD */
- gpio_request(GPIO_FN_SDHID2_0, NULL);
- gpio_request(GPIO_FN_SDHID2_1, NULL);
- gpio_request(GPIO_FN_SDHID2_2, NULL);
- gpio_request(GPIO_FN_SDHID2_3, NULL);
- gpio_request(GPIO_FN_SDHICMD2, NULL);
- gpio_request(GPIO_FN_SDHICLK2, NULL);
gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
/* enable USB */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 095/142] ARM: shmobile: kzm9g: Register pinctrl mappings for BSC
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (92 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 094/142] ARM: shmobile: kzm9g: Register pinctrl mappings for SDHI and MMCIF Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 096/142] ARM: shmobile: kzm9g: Register pinctrl mappings for USB Simon Horman
` (47 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based BSC pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-kzm9g.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 335bdbb..7427041 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -651,6 +651,9 @@ static const struct pinctrl_map kzm_pinctrl_map[] = {
"sdhi2_data4", "sdhi2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
"sdhi2_ctrl", "sdhi2"),
+ /* SMSC */
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+ "bsc_cs4", "bsc"),
};
/*
@@ -718,9 +721,6 @@ static void __init kzm_init(void)
sh73a0_pinmux_init();
- /* CS4 for SMSC/USB */
- gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
-
/* SMSC */
gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 096/142] ARM: shmobile: kzm9g: Register pinctrl mappings for USB
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (93 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 095/142] ARM: shmobile: kzm9g: Register pinctrl mappings for BSC Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 097/142] ARM: shmobile: mackerel: Register pinctrl mappings for SDHI and MMCIF Simon Horman
` (46 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based USB pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-kzm9g.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 7427041..c1c0401 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -654,6 +654,9 @@ static const struct pinctrl_map kzm_pinctrl_map[] = {
/* SMSC */
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
"bsc_cs4", "bsc"),
+ /* USB */
+ PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0",
+ "usb_vbus", "usb"),
};
/*
@@ -738,9 +741,6 @@ static void __init kzm_init(void)
/* enable Micro SD */
gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
- /* enable USB */
- gpio_request(GPIO_FN_VBUS_0, NULL);
-
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 097/142] ARM: shmobile: mackerel: Register pinctrl mappings for SDHI and MMCIF
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (94 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 096/142] ARM: shmobile: kzm9g: Register pinctrl mappings for USB Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 098/142] ARM: shmobile: marzen: " Simon Horman
` (45 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl
mappings
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-mackerel.c | 68 ++++++++++++++-----------------
1 file changed, 30 insertions(+), 38 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 172d472..336ccb4 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -40,6 +40,7 @@
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/sh_flctl.h>
+#include <linux/pinctrl/machine.h>
#include <linux/pm_clock.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
@@ -1328,6 +1329,33 @@ static struct i2c_board_info i2c1_devices[] = {
},
};
+static const struct pinctrl_map mackerel_pinctrl_map[] = {
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+ "mmc0_data8_0", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+ "mmc0_ctrl_0", "mmc0"),
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_wp", "sdhi0"),
+ /* SDHI1 */
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+ "sdhi1_data4", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+ "sdhi1_ctrl", "sdhi1"),
+#endif
+ /* SDHI2 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
+ "sdhi2_data4", "sdhi2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
+ "sdhi2_ctrl", "sdhi2"),
+};
+
#define GPIO_PORT9CR IOMEM(0xE6051009)
#define GPIO_PORT10CR IOMEM(0xE605100A)
#define GPIO_PORT167CR IOMEM(0xE60520A7)
@@ -1364,6 +1392,8 @@ static void __init mackerel_init(void)
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+ pinctrl_register_mappings(mackerel_pinctrl_map,
+ ARRAY_SIZE(mackerel_pinctrl_map));
sh7372_pinmux_init();
/* enable SCIFA0 */
@@ -1453,53 +1483,15 @@ static void __init mackerel_init(void)
gpio_request(GPIO_FN_IRQ21, NULL);
irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
- /* enable SDHI0 */
- gpio_request(GPIO_FN_SDHIWP0, NULL);
- gpio_request(GPIO_FN_SDHICMD0, NULL);
- gpio_request(GPIO_FN_SDHICLK0, NULL);
- gpio_request(GPIO_FN_SDHID0_3, NULL);
- gpio_request(GPIO_FN_SDHID0_2, NULL);
- gpio_request(GPIO_FN_SDHID0_1, NULL);
- gpio_request(GPIO_FN_SDHID0_0, NULL);
-
/* SDHI0 PORT172 card-detect IRQ26 */
gpio_request(GPIO_FN_IRQ26_172, NULL);
-#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
- /* enable SDHI1 */
- gpio_request(GPIO_FN_SDHICMD1, NULL);
- gpio_request(GPIO_FN_SDHICLK1, NULL);
- gpio_request(GPIO_FN_SDHID1_3, NULL);
- gpio_request(GPIO_FN_SDHID1_2, NULL);
- gpio_request(GPIO_FN_SDHID1_1, NULL);
- gpio_request(GPIO_FN_SDHID1_0, NULL);
-#endif
/* card detect pin for MMC slot (CN7) */
gpio_request_one(41, GPIOF_IN, NULL);
- /* enable SDHI2 */
- gpio_request(GPIO_FN_SDHICMD2, NULL);
- gpio_request(GPIO_FN_SDHICLK2, NULL);
- gpio_request(GPIO_FN_SDHID2_3, NULL);
- gpio_request(GPIO_FN_SDHID2_2, NULL);
- gpio_request(GPIO_FN_SDHID2_1, NULL);
- gpio_request(GPIO_FN_SDHID2_0, NULL);
-
/* card detect pin for microSD slot (CN23) */
gpio_request_one(162, GPIOF_IN, NULL);
- /* MMCIF */
- gpio_request(GPIO_FN_MMCD0_0, NULL);
- gpio_request(GPIO_FN_MMCD0_1, NULL);
- gpio_request(GPIO_FN_MMCD0_2, NULL);
- gpio_request(GPIO_FN_MMCD0_3, NULL);
- gpio_request(GPIO_FN_MMCD0_4, NULL);
- gpio_request(GPIO_FN_MMCD0_5, NULL);
- gpio_request(GPIO_FN_MMCD0_6, NULL);
- gpio_request(GPIO_FN_MMCD0_7, NULL);
- gpio_request(GPIO_FN_MMCCMD0, NULL);
- gpio_request(GPIO_FN_MMCCLK0, NULL);
-
/* FLCTL */
gpio_request(GPIO_FN_D0_NAF0, NULL);
gpio_request(GPIO_FN_D1_NAF1, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 098/142] ARM: shmobile: marzen: Register pinctrl mappings for SDHI and MMCIF
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (95 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 097/142] ARM: shmobile: mackerel: Register pinctrl mappings for SDHI and MMCIF Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 099/142] ARM: shmobile: marzen: Register pinctrl mappings for SCIF Simon Horman
` (44 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based SDHI and MMCIF pinmux configuration by pinctrl
mappings
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-marzen.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index fec49eb..f00677f 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -27,6 +27,7 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
+#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
@@ -327,6 +328,18 @@ void __init marzen_init_late(void)
ARRAY_SIZE(marzen_late_devices));
}
+static const struct pinctrl_map marzen_pinctrl_map[] = {
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_cd", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_wp", "sdhi0"),
+};
+
static void __init marzen_init(void)
{
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -334,6 +347,8 @@ static void __init marzen_init(void)
regulator_register_fixed(1, dummy_supplies,
ARRAY_SIZE(dummy_supplies));
+ pinctrl_register_mappings(marzen_pinctrl_map,
+ ARRAY_SIZE(marzen_pinctrl_map));
r8a7779_pinmux_init();
/* SCIF2 (CN18: DEBUG0) */
@@ -348,16 +363,6 @@ static void __init marzen_init(void)
gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
- /* SD0 (CN20) */
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_DAT0, NULL);
- gpio_request(GPIO_FN_SD0_DAT1, NULL);
- gpio_request(GPIO_FN_SD0_DAT2, NULL);
- gpio_request(GPIO_FN_SD0_DAT3, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
- gpio_request(GPIO_FN_SD0_WP, NULL);
-
/* HSPI 0 */
gpio_request(GPIO_FN_HSPI_CLK0, NULL);
gpio_request(GPIO_FN_HSPI_CS0, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 099/142] ARM: shmobile: marzen: Register pinctrl mappings for SCIF
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (96 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 098/142] ARM: shmobile: marzen: " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 100/142] ARM: shmobile: marzen: Register pinctrl mappings for HSPI Simon Horman
` (43 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based SCIF pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-marzen.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index f00677f..4097366 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -329,6 +329,12 @@ void __init marzen_init_late(void)
}
static const struct pinctrl_map marzen_pinctrl_map[] = {
+ /* SCIF2 (CN18: DEBUG0) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
+ "scif2_data_c", "scif2"),
+ /* SCIF4 (CN19: DEBUG1) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
+ "scif4_data", "scif4"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_data4", "sdhi0"),
@@ -351,14 +357,6 @@ static void __init marzen_init(void)
ARRAY_SIZE(marzen_pinctrl_map));
r8a7779_pinmux_init();
- /* SCIF2 (CN18: DEBUG0) */
- gpio_request(GPIO_FN_TX2_C, NULL);
- gpio_request(GPIO_FN_RX2_C, NULL);
-
- /* SCIF4 (CN19: DEBUG1) */
- gpio_request(GPIO_FN_TX4, NULL);
- gpio_request(GPIO_FN_RX4, NULL);
-
/* LAN89218 */
gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 100/142] ARM: shmobile: marzen: Register pinctrl mappings for HSPI
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (97 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 099/142] ARM: shmobile: marzen: Register pinctrl mappings for SCIF Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 101/142] ARM: shmobile: marzen: Register pinctrl mappings for USB Simon Horman
` (42 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based HSPI pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-marzen.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 4097366..8871af3 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -329,6 +329,9 @@ void __init marzen_init_late(void)
}
static const struct pinctrl_map marzen_pinctrl_map[] = {
+ /* HSPI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
+ "hspi0", "hspi0"),
/* SCIF2 (CN18: DEBUG0) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
"scif2_data_c", "scif2"),
@@ -361,12 +364,6 @@ static void __init marzen_init(void)
gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
- /* HSPI 0 */
- gpio_request(GPIO_FN_HSPI_CLK0, NULL);
- gpio_request(GPIO_FN_HSPI_CS0, NULL);
- gpio_request(GPIO_FN_HSPI_TX0, NULL);
- gpio_request(GPIO_FN_HSPI_RX0, NULL);
-
/* USB (CN21) */
gpio_request(GPIO_FN_USB_OVC0, NULL);
gpio_request(GPIO_FN_USB_OVC1, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 101/142] ARM: shmobile: marzen: Register pinctrl mappings for USB
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (98 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 100/142] ARM: shmobile: marzen: Register pinctrl mappings for HSPI Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 102/142] ARM: shmobile: marzen: Register pinctrl mappings for LBSC Simon Horman
` (41 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based USB pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-marzen.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 8871af3..04bcf88 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -347,6 +347,15 @@ static const struct pinctrl_map marzen_pinctrl_map[] = {
"sdhi0_cd", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_wp", "sdhi0"),
+ /* USB0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
+ "usb0", "usb0"),
+ /* USB1 */
+ PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
+ "usb1", "usb1"),
+ /* USB2 */
+ PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
+ "usb2", "usb2"),
};
static void __init marzen_init(void)
@@ -364,14 +373,6 @@ static void __init marzen_init(void)
gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
- /* USB (CN21) */
- gpio_request(GPIO_FN_USB_OVC0, NULL);
- gpio_request(GPIO_FN_USB_OVC1, NULL);
- gpio_request(GPIO_FN_USB_OVC2, NULL);
-
- /* USB (CN22) */
- gpio_request(GPIO_FN_USB_PENC2, NULL);
-
r8a7779_add_standard_devices();
platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 102/142] ARM: shmobile: marzen: Register pinctrl mappings for LBSC
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (99 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 101/142] ARM: shmobile: marzen: Register pinctrl mappings for USB Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 103/142] ARM: shmobile: marzen: Register pinctrl mappings for INTC Simon Horman
` (40 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based LBSC pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-marzen.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 04bcf88..b16f85f 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -347,6 +347,9 @@ static const struct pinctrl_map marzen_pinctrl_map[] = {
"sdhi0_cd", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_wp", "sdhi0"),
+ /* SMSC */
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+ "lbsc_ex_cs0", "lbsc"),
/* USB0 */
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
"usb0", "usb0"),
@@ -370,7 +373,6 @@ static void __init marzen_init(void)
r8a7779_pinmux_init();
/* LAN89218 */
- gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
r8a7779_add_standard_devices();
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 103/142] ARM: shmobile: marzen: Register pinctrl mappings for INTC
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (100 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 102/142] ARM: shmobile: marzen: Register pinctrl mappings for LBSC Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 104/142] sh-pfc: sh7372: Remove SDHI and MMCIF function GPIOS Simon Horman
` (39 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Replace the GPIO-based INTC pinmux configuration by pinctrl mappings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/board-marzen.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index b16f85f..5852331 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -25,7 +25,6 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
@@ -349,6 +348,8 @@ static const struct pinctrl_map marzen_pinctrl_map[] = {
"sdhi0_wp", "sdhi0"),
/* SMSC */
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+ "intc_irq1_b", "intc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
"lbsc_ex_cs0", "lbsc"),
/* USB0 */
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
@@ -372,9 +373,6 @@ static void __init marzen_init(void)
ARRAY_SIZE(marzen_pinctrl_map));
r8a7779_pinmux_init();
- /* LAN89218 */
- gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
-
r8a7779_add_standard_devices();
platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 104/142] sh-pfc: sh7372: Remove SDHI and MMCIF function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (101 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 103/142] ARM: shmobile: marzen: Register pinctrl mappings for INTC Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 105/142] sh-pfc: sh73a0: Remove LCD and LCD2 " Simon Horman
` (38 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All sh7372 platforms now use the pinctrl API to control the SDHI and
MMCIF pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh7372.c | 25 -------------------------
1 file changed, 25 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index cef4d6a..df0ae21 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1277,18 +1277,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13),
GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15),
- /* MMCIF(1) */
- GPIO_FN(MMCD0_0), GPIO_FN(MMCD0_1), GPIO_FN(MMCD0_2),
- GPIO_FN(MMCD0_3), GPIO_FN(MMCD0_4), GPIO_FN(MMCD0_5),
- GPIO_FN(MMCD0_6), GPIO_FN(MMCD0_7), GPIO_FN(MMCCMD0),
- GPIO_FN(MMCCLK0),
-
- /* MMCIF(2) */
- GPIO_FN(MMCD1_0), GPIO_FN(MMCD1_1), GPIO_FN(MMCD1_2),
- GPIO_FN(MMCD1_3), GPIO_FN(MMCD1_4), GPIO_FN(MMCD1_5),
- GPIO_FN(MMCD1_6), GPIO_FN(MMCD1_7), GPIO_FN(MMCCLK1),
- GPIO_FN(MMCCMD1),
-
/* SPU2 */
GPIO_FN(VINT_I),
@@ -1385,19 +1373,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
/* HDMI */
GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC),
- /* SDHI0 */
- GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), GPIO_FN(SDHICMD0),
- GPIO_FN(SDHIWP0), GPIO_FN(SDHID0_0), GPIO_FN(SDHID0_1),
- GPIO_FN(SDHID0_2), GPIO_FN(SDHID0_3),
-
- /* SDHI1 */
- GPIO_FN(SDHICLK1), GPIO_FN(SDHICMD1), GPIO_FN(SDHID1_0),
- GPIO_FN(SDHID1_1), GPIO_FN(SDHID1_2), GPIO_FN(SDHID1_3),
-
- /* SDHI2 */
- GPIO_FN(SDHICLK2), GPIO_FN(SDHICMD2), GPIO_FN(SDHID2_0),
- GPIO_FN(SDHID2_1), GPIO_FN(SDHID2_2), GPIO_FN(SDHID2_3),
-
/* SDENC */
GPIO_FN(SDENC_CPG),
GPIO_FN(SDENC_DV_CLKI),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 105/142] sh-pfc: sh73a0: Remove LCD and LCD2 function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (102 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 104/142] sh-pfc: sh7372: Remove SDHI and MMCIF function GPIOS Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 106/142] sh-pfc: sh73a0: Remove SCIFA and SCIFB " Simon Horman
` (37 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All sh73a0 platforms now use the pinctrl API to control the LCD and
LCD2 pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 76 -----------------------------------
1 file changed, 76 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 8fc5eb0..1054a42 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3545,87 +3545,59 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(BBIF1_FLOW),
GPIO_FN(HSI_TX_FLAG),
GPIO_FN(VIO_VD), \
- GPIO_FN(PORT128_LCD2VSYN), \
GPIO_FN(VIO2_VD), \
- GPIO_FN(LCD2D0),
GPIO_FN(VIO_HD), \
- GPIO_FN(PORT129_LCD2HSYN), \
- GPIO_FN(PORT129_LCD2CS_), \
GPIO_FN(VIO2_HD), \
- GPIO_FN(LCD2D1),
GPIO_FN(VIO_D0), \
GPIO_FN(PORT130_MSIOF2_RXD), \
- GPIO_FN(LCD2D10),
GPIO_FN(VIO_D1), \
GPIO_FN(PORT131_KEYOUT6), \
GPIO_FN(PORT131_MSIOF2_SS1), \
GPIO_FN(PORT131_KEYOUT11), \
- GPIO_FN(LCD2D11),
GPIO_FN(VIO_D2), \
GPIO_FN(PORT132_KEYOUT7), \
GPIO_FN(PORT132_MSIOF2_SS2), \
GPIO_FN(PORT132_KEYOUT10), \
- GPIO_FN(LCD2D12),
GPIO_FN(VIO_D3), \
GPIO_FN(MSIOF2_TSYNC), \
- GPIO_FN(LCD2D13),
GPIO_FN(VIO_D4), \
GPIO_FN(MSIOF2_TXD), \
- GPIO_FN(LCD2D14),
GPIO_FN(VIO_D5), \
GPIO_FN(MSIOF2_TSCK), \
- GPIO_FN(LCD2D15),
GPIO_FN(VIO_D6), \
GPIO_FN(PORT136_KEYOUT8), \
- GPIO_FN(LCD2D16),
GPIO_FN(VIO_D7), \
GPIO_FN(PORT137_KEYOUT9), \
- GPIO_FN(LCD2D17),
GPIO_FN(VIO_D8), \
GPIO_FN(PORT138_KEYOUT8), \
GPIO_FN(VIO2_D0), \
- GPIO_FN(LCD2D6),
GPIO_FN(VIO_D9), \
GPIO_FN(PORT139_KEYOUT9), \
GPIO_FN(VIO2_D1), \
- GPIO_FN(LCD2D7),
GPIO_FN(VIO_D10), \
GPIO_FN(TPU0TO2), \
GPIO_FN(VIO2_D2), \
- GPIO_FN(LCD2D8),
GPIO_FN(VIO_D11), \
GPIO_FN(TPU0TO3), \
GPIO_FN(VIO2_D3), \
- GPIO_FN(LCD2D9),
GPIO_FN(VIO_D12), \
GPIO_FN(PORT142_KEYOUT10), \
GPIO_FN(VIO2_D4), \
- GPIO_FN(LCD2D2),
GPIO_FN(VIO_D13), \
GPIO_FN(PORT143_KEYOUT11), \
GPIO_FN(PORT143_KEYOUT6), \
GPIO_FN(VIO2_D5), \
- GPIO_FN(LCD2D3),
GPIO_FN(VIO_D14), \
GPIO_FN(PORT144_KEYOUT7), \
GPIO_FN(VIO2_D6), \
- GPIO_FN(LCD2D4),
GPIO_FN(VIO_D15), \
GPIO_FN(TPU1TO3), \
- GPIO_FN(PORT145_LCD2DISP), \
- GPIO_FN(PORT145_LCD2RS), \
GPIO_FN(VIO2_D7), \
- GPIO_FN(LCD2D5),
GPIO_FN(VIO_CLK), \
- GPIO_FN(LCD2DCK), \
- GPIO_FN(PORT146_LCD2WR_), \
GPIO_FN(VIO2_CLK), \
- GPIO_FN(LCD2D18),
GPIO_FN(VIO_FIELD), \
- GPIO_FN(LCD2RD_), \
GPIO_FN(VIO2_FIELD), \
- GPIO_FN(LCD2D19),
GPIO_FN(VIO_CKO),
GPIO_FN(A27), \
GPIO_FN(PORT149_RDWR), \
@@ -3662,107 +3634,63 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(PORT163_SCIFB_RTS_), \
GPIO_FN(PORT163_SCIFA5_RTS_), \
GPIO_FN(TPU3TO0),
- GPIO_FN(LCDD0),
- GPIO_FN(LCDD1), \
GPIO_FN(PORT193_SCIFA5_CTS_), \
GPIO_FN(BBIF2_TSYNC1),
- GPIO_FN(LCDD2), \
GPIO_FN(PORT194_SCIFA5_RTS_), \
GPIO_FN(BBIF2_TSCK1),
- GPIO_FN(LCDD3), \
GPIO_FN(PORT195_SCIFA5_RXD), \
GPIO_FN(BBIF2_TXD1),
- GPIO_FN(LCDD4), \
GPIO_FN(PORT196_SCIFA5_TXD),
- GPIO_FN(LCDD5), \
GPIO_FN(PORT197_SCIFA5_SCK), \
GPIO_FN(MFG2_OUT2), \
GPIO_FN(TPU2TO1),
- GPIO_FN(LCDD6),
- GPIO_FN(LCDD7), \
GPIO_FN(TPU4TO1), \
GPIO_FN(MFG4_OUT2),
- GPIO_FN(LCDD8), \
GPIO_FN(D16),
- GPIO_FN(LCDD9), \
GPIO_FN(D17),
- GPIO_FN(LCDD10), \
GPIO_FN(D18),
- GPIO_FN(LCDD11), \
GPIO_FN(D19),
- GPIO_FN(LCDD12), \
GPIO_FN(D20),
- GPIO_FN(LCDD13), \
GPIO_FN(D21),
- GPIO_FN(LCDD14), \
GPIO_FN(D22),
- GPIO_FN(LCDD15), \
GPIO_FN(PORT207_MSIOF0L_SS1), \
GPIO_FN(D23),
- GPIO_FN(LCDD16), \
GPIO_FN(PORT208_MSIOF0L_SS2), \
GPIO_FN(D24),
- GPIO_FN(LCDD17), \
GPIO_FN(D25),
- GPIO_FN(LCDD18), \
GPIO_FN(DREQ2), \
GPIO_FN(PORT210_MSIOF0L_SS1), \
GPIO_FN(D26),
- GPIO_FN(LCDD19), \
GPIO_FN(PORT211_MSIOF0L_SS2), \
GPIO_FN(D27),
- GPIO_FN(LCDD20), \
GPIO_FN(TS_SPSYNC1), \
GPIO_FN(MSIOF0L_MCK0), \
GPIO_FN(D28),
- GPIO_FN(LCDD21), \
GPIO_FN(TS_SDAT1), \
GPIO_FN(MSIOF0L_MCK1), \
GPIO_FN(D29),
- GPIO_FN(LCDD22), \
GPIO_FN(TS_SDEN1), \
GPIO_FN(MSIOF0L_RSCK), \
GPIO_FN(D30),
- GPIO_FN(LCDD23), \
GPIO_FN(TS_SCK1), \
GPIO_FN(MSIOF0L_RSYNC), \
GPIO_FN(D31),
- GPIO_FN(LCDDCK), \
- GPIO_FN(LCDWR_),
- GPIO_FN(LCDRD_), \
GPIO_FN(DACK2), \
- GPIO_FN(PORT217_LCD2RS), \
GPIO_FN(MSIOF0L_TSYNC), \
GPIO_FN(VIO2_FIELD3), \
- GPIO_FN(PORT217_LCD2DISP),
- GPIO_FN(LCDHSYN), \
- GPIO_FN(LCDCS_), \
- GPIO_FN(LCDCS2_), \
GPIO_FN(DACK3), \
GPIO_FN(PORT218_VIO_CKOR),
- GPIO_FN(LCDDISP), \
- GPIO_FN(LCDRS), \
- GPIO_FN(PORT219_LCD2WR_), \
GPIO_FN(DREQ3), \
GPIO_FN(MSIOF0L_TSCK), \
GPIO_FN(VIO2_CLK3), \
- GPIO_FN(LCD2DCK_2),
- GPIO_FN(LCDVSYN), \
- GPIO_FN(LCDVSYN2),
- GPIO_FN(LCDLCLK), \
GPIO_FN(DREQ1), \
- GPIO_FN(PORT221_LCD2CS_), \
GPIO_FN(PWEN), \
GPIO_FN(MSIOF0L_RXD), \
GPIO_FN(VIO2_HD3), \
- GPIO_FN(PORT221_LCD2HSYN),
- GPIO_FN(LCDDON), \
- GPIO_FN(LCDDON2), \
GPIO_FN(DACK1), \
GPIO_FN(OVCN), \
GPIO_FN(MSIOF0L_TXD), \
GPIO_FN(VIO2_VD3), \
- GPIO_FN(PORT222_LCD2VSYN),
GPIO_FN(SCIFA1_TXD), \
GPIO_FN(OVCN2),
@@ -3785,21 +3713,17 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(MSIOF1_RSCK), \
GPIO_FN(SCIFA2_RTS2_), \
GPIO_FN(VIO2_CLK2), \
- GPIO_FN(LCD2D20),
GPIO_FN(MSIOF1_RSYNC), \
GPIO_FN(MFG1_IN2), \
GPIO_FN(VIO2_VD2), \
- GPIO_FN(LCD2D21),
GPIO_FN(MSIOF1_MCK0), \
GPIO_FN(PORT236_I2C_SDA2),
GPIO_FN(MSIOF1_MCK1), \
GPIO_FN(PORT237_I2C_SCL2),
GPIO_FN(MSIOF1_SS1), \
GPIO_FN(VIO2_FIELD2), \
- GPIO_FN(LCD2D22),
GPIO_FN(MSIOF1_SS2), \
GPIO_FN(VIO2_HD2), \
- GPIO_FN(LCD2D23),
GPIO_FN(SCIFA6_TXD),
GPIO_FN(PORT241_IRDA_OUT), \
GPIO_FN(PORT241_IROUT), \
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 106/142] sh-pfc: sh73a0: Remove SCIFA and SCIFB function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (103 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 105/142] sh-pfc: sh73a0: Remove LCD and LCD2 " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 107/142] sh-pfc: sh73a0: Remove I2C " Simon Horman
` (36 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All sh73a0 platforms now use the pinctrl API to control the SCIFA and
SCIFB pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 58 -----------------------------------
1 file changed, 58 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 1054a42..6d36ebb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3335,19 +3335,13 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(GPI5),
GPIO_FN(GPI6),
GPIO_FN(GPI7),
- GPIO_FN(SCIFA7_RXD),
- GPIO_FN(SCIFA7_CTS_),
GPIO_FN(GPO7), \
GPIO_FN(MFG0_OUT2),
GPIO_FN(GPO6), \
GPIO_FN(MFG1_OUT2),
GPIO_FN(GPO5), \
- GPIO_FN(SCIFA0_SCK), \
GPIO_FN(FSICOSLDT3), \
GPIO_FN(PORT16_VIO_CKOR),
- GPIO_FN(SCIFA0_TXD),
- GPIO_FN(SCIFA7_TXD),
- GPIO_FN(SCIFA7_RTS_), \
GPIO_FN(PORT19_VIO_CKO2),
GPIO_FN(GPO0),
GPIO_FN(GPO1),
@@ -3374,11 +3368,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(PORT30_VIO_CKOR),
GPIO_FN(SIM_D), \
GPIO_FN(PORT31_IROUT),
- GPIO_FN(SCIFA4_TXD),
- GPIO_FN(SCIFA4_RXD), \
GPIO_FN(XWUP),
- GPIO_FN(SCIFA4_RTS_),
- GPIO_FN(SCIFA4_CTS_),
GPIO_FN(FSIBOBT), \
GPIO_FN(FSIBIBT),
GPIO_FN(FSIBOLR), \
@@ -3387,10 +3377,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(FSIBISLD),
GPIO_FN(VACK),
GPIO_FN(XTAL1L),
- GPIO_FN(SCIFA0_RTS_), \
GPIO_FN(FSICOSLDT2),
- GPIO_FN(SCIFA0_RXD),
- GPIO_FN(SCIFA0_CTS_), \
GPIO_FN(FSICOSLDT1),
GPIO_FN(FSICOBT), \
GPIO_FN(FSICIBT), \
@@ -3516,14 +3503,10 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(BBIF2_RXD),
GPIO_FN(BBIF2_SYNC),
GPIO_FN(BBIF2_SCK),
- GPIO_FN(SCIFA3_CTS_), \
GPIO_FN(MFG3_IN2),
- GPIO_FN(SCIFA3_RXD), \
GPIO_FN(MFG3_IN1),
GPIO_FN(BBIF1_SS2), \
- GPIO_FN(SCIFA3_RTS_), \
GPIO_FN(MFG3_OUT1),
- GPIO_FN(SCIFA3_TXD),
GPIO_FN(HSI_RX_DATA), \
GPIO_FN(BBIF1_RXD),
GPIO_FN(HSI_TX_WAKE), \
@@ -3611,37 +3594,17 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(TPU1TO2), \
GPIO_FN(TS_SDEN3), \
GPIO_FN(PORT153_MSIOF2_SS1),
- GPIO_FN(SCIFA2_TXD1), \
GPIO_FN(MSIOF2_MCK0),
- GPIO_FN(SCIFA2_RXD1), \
GPIO_FN(MSIOF2_MCK1),
- GPIO_FN(SCIFA2_RTS1_), \
GPIO_FN(PORT156_MSIOF2_SS2),
- GPIO_FN(SCIFA2_CTS1_), \
GPIO_FN(PORT157_MSIOF2_RXD),
GPIO_FN(DINT_), \
- GPIO_FN(SCIFA2_SCK1), \
GPIO_FN(TS_SCK3),
- GPIO_FN(PORT159_SCIFB_SCK), \
- GPIO_FN(PORT159_SCIFA5_SCK), \
GPIO_FN(NMI),
- GPIO_FN(PORT160_SCIFB_TXD), \
- GPIO_FN(PORT160_SCIFA5_TXD),
- GPIO_FN(PORT161_SCIFB_CTS_), \
- GPIO_FN(PORT161_SCIFA5_CTS_),
- GPIO_FN(PORT162_SCIFB_RXD), \
- GPIO_FN(PORT162_SCIFA5_RXD),
- GPIO_FN(PORT163_SCIFB_RTS_), \
- GPIO_FN(PORT163_SCIFA5_RTS_), \
GPIO_FN(TPU3TO0),
- GPIO_FN(PORT193_SCIFA5_CTS_), \
GPIO_FN(BBIF2_TSYNC1),
- GPIO_FN(PORT194_SCIFA5_RTS_), \
GPIO_FN(BBIF2_TSCK1),
- GPIO_FN(PORT195_SCIFA5_RXD), \
GPIO_FN(BBIF2_TXD1),
- GPIO_FN(PORT196_SCIFA5_TXD),
- GPIO_FN(PORT197_SCIFA5_SCK), \
GPIO_FN(MFG2_OUT2), \
GPIO_FN(TPU2TO1),
GPIO_FN(TPU4TO1), \
@@ -3692,26 +3655,16 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(MSIOF0L_TXD), \
GPIO_FN(VIO2_VD3), \
- GPIO_FN(SCIFA1_TXD), \
GPIO_FN(OVCN2),
GPIO_FN(EXTLP), \
- GPIO_FN(SCIFA1_SCK), \
GPIO_FN(PORT226_VIO_CKO2),
- GPIO_FN(SCIFA1_RTS_), \
GPIO_FN(IDIN),
- GPIO_FN(SCIFA1_RXD),
- GPIO_FN(SCIFA1_CTS_), \
GPIO_FN(MFG1_IN1),
GPIO_FN(MSIOF1_TXD), \
- GPIO_FN(SCIFA2_TXD2),
GPIO_FN(MSIOF1_TSYNC), \
- GPIO_FN(SCIFA2_CTS2_),
GPIO_FN(MSIOF1_TSCK), \
- GPIO_FN(SCIFA2_SCK2),
GPIO_FN(MSIOF1_RXD), \
- GPIO_FN(SCIFA2_RXD2),
GPIO_FN(MSIOF1_RSCK), \
- GPIO_FN(SCIFA2_RTS2_), \
GPIO_FN(VIO2_CLK2), \
GPIO_FN(MSIOF1_RSYNC), \
GPIO_FN(MFG1_IN2), \
@@ -3724,7 +3677,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VIO2_FIELD2), \
GPIO_FN(MSIOF1_SS2), \
GPIO_FN(VIO2_HD2), \
- GPIO_FN(SCIFA6_TXD),
GPIO_FN(PORT241_IRDA_OUT), \
GPIO_FN(PORT241_IROUT), \
GPIO_FN(MFG4_OUT1), \
@@ -3733,25 +3685,15 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(MFG4_IN2),
GPIO_FN(PORT243_IRDA_FIRSEL), \
GPIO_FN(PORT243_VIO_CKO2),
- GPIO_FN(PORT244_SCIFA5_CTS_), \
GPIO_FN(MFG2_IN1), \
- GPIO_FN(PORT244_SCIFB_CTS_), \
GPIO_FN(MSIOF2R_RXD),
- GPIO_FN(PORT245_SCIFA5_RTS_), \
GPIO_FN(MFG2_IN2), \
- GPIO_FN(PORT245_SCIFB_RTS_), \
GPIO_FN(MSIOF2R_TXD),
- GPIO_FN(PORT246_SCIFA5_RXD), \
GPIO_FN(MFG1_OUT1), \
- GPIO_FN(PORT246_SCIFB_RXD), \
GPIO_FN(TPU1TO0),
- GPIO_FN(PORT247_SCIFA5_TXD), \
GPIO_FN(MFG3_OUT2), \
- GPIO_FN(PORT247_SCIFB_TXD), \
GPIO_FN(TPU3TO1),
- GPIO_FN(PORT248_SCIFA5_SCK), \
GPIO_FN(MFG2_OUT1), \
- GPIO_FN(PORT248_SCIFB_SCK), \
GPIO_FN(TPU2TO0), \
GPIO_FN(PORT248_I2C_SCL3), \
GPIO_FN(MSIOF2R_TSCK),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 107/142] sh-pfc: sh73a0: Remove I2C function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (104 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 106/142] sh-pfc: sh73a0: Remove SCIFA and SCIFB " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 108/142] sh-pfc: sh73a0: Remove FSI " Simon Horman
` (35 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All sh73a0 platforms now use the pinctrl API to control the I2C pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 6d36ebb..13bd138 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3354,13 +3354,9 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VINT),
GPIO_FN(TCKON),
GPIO_FN(XDVFS1), \
- GPIO_FN(PORT27_I2C_SCL2), \
- GPIO_FN(PORT27_I2C_SCL3), \
GPIO_FN(MFG0_OUT1), \
GPIO_FN(PORT27_IROUT),
GPIO_FN(XDVFS2), \
- GPIO_FN(PORT28_I2C_SDA2), \
- GPIO_FN(PORT28_I2C_SDA3), \
GPIO_FN(PORT28_TPU1TO1),
GPIO_FN(SIM_RST), \
GPIO_FN(PORT29_TPU1TO1),
@@ -3517,12 +3513,8 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(BBIF1_TXD),
GPIO_FN(HSI_RX_READY), \
GPIO_FN(BBIF1_RSCK), \
- GPIO_FN(PORT115_I2C_SCL2), \
- GPIO_FN(PORT115_I2C_SCL3),
GPIO_FN(HSI_RX_WAKE), \
GPIO_FN(BBIF1_RSYNC), \
- GPIO_FN(PORT116_I2C_SDA2), \
- GPIO_FN(PORT116_I2C_SDA3),
GPIO_FN(HSI_RX_FLAG), \
GPIO_FN(BBIF1_SS1), \
GPIO_FN(BBIF1_FLOW),
@@ -3670,9 +3662,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(MFG1_IN2), \
GPIO_FN(VIO2_VD2), \
GPIO_FN(MSIOF1_MCK0), \
- GPIO_FN(PORT236_I2C_SDA2),
GPIO_FN(MSIOF1_MCK1), \
- GPIO_FN(PORT237_I2C_SCL2),
GPIO_FN(MSIOF1_SS1), \
GPIO_FN(VIO2_FIELD2), \
GPIO_FN(MSIOF1_SS2), \
@@ -3695,11 +3685,9 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(TPU3TO1),
GPIO_FN(MFG2_OUT1), \
GPIO_FN(TPU2TO0), \
- GPIO_FN(PORT248_I2C_SCL3), \
GPIO_FN(MSIOF2R_TSCK),
GPIO_FN(PORT249_IROUT), \
GPIO_FN(MFG4_IN1), \
- GPIO_FN(PORT249_I2C_SDA3), \
GPIO_FN(MSIOF2R_TSYNC),
GPIO_FN(SDHICLK0),
GPIO_FN(SDHICD0),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 108/142] sh-pfc: sh73a0: Remove FSI function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (105 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 107/142] sh-pfc: sh73a0: Remove I2C " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 109/142] sh-pfc: sh73a0: Remove pull-up " Simon Horman
` (34 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All sh73a0 platforms now use the pinctrl API to control the FSI pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 36 -----------------------------------
1 file changed, 36 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 13bd138..1a638f2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3340,7 +3340,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(GPO6), \
GPIO_FN(MFG1_OUT2),
GPIO_FN(GPO5), \
- GPIO_FN(FSICOSLDT3), \
GPIO_FN(PORT16_VIO_CKOR),
GPIO_FN(PORT19_VIO_CKO2),
GPIO_FN(GPO0),
@@ -3365,55 +3364,20 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SIM_D), \
GPIO_FN(PORT31_IROUT),
GPIO_FN(XWUP),
- GPIO_FN(FSIBOBT), \
- GPIO_FN(FSIBIBT),
- GPIO_FN(FSIBOLR), \
- GPIO_FN(FSIBILR),
- GPIO_FN(FSIBOSLD),
- GPIO_FN(FSIBISLD),
GPIO_FN(VACK),
GPIO_FN(XTAL1L),
- GPIO_FN(FSICOSLDT2),
- GPIO_FN(FSICOSLDT1),
- GPIO_FN(FSICOBT), \
- GPIO_FN(FSICIBT), \
- GPIO_FN(FSIDOBT), \
- GPIO_FN(FSIDIBT),
- GPIO_FN(FSICOLR), \
- GPIO_FN(FSICILR), \
- GPIO_FN(FSIDOLR), \
- GPIO_FN(FSIDILR),
- GPIO_FN(FSICOSLD), \
- GPIO_FN(PORT47_FSICSPDIF),
- GPIO_FN(FSICISLD), \
- GPIO_FN(FSIDISLD),
- GPIO_FN(FSIACK), \
GPIO_FN(PORT49_IRDA_OUT), \
GPIO_FN(PORT49_IROUT), \
- GPIO_FN(FSIAOMC),
- GPIO_FN(FSIAOLR), \
GPIO_FN(BBIF2_TSYNC2), \
GPIO_FN(TPU2TO2), \
- GPIO_FN(FSIAILR),
- GPIO_FN(FSIAOBT), \
GPIO_FN(BBIF2_TSCK2), \
GPIO_FN(TPU2TO3), \
- GPIO_FN(FSIAIBT),
- GPIO_FN(FSIAOSLD), \
GPIO_FN(BBIF2_TXD2),
- GPIO_FN(FSIASPDIF), \
GPIO_FN(PORT53_IRDA_IN), \
GPIO_FN(TPU3TO3), \
- GPIO_FN(FSIBSPDIF), \
- GPIO_FN(PORT53_FSICSPDIF),
- GPIO_FN(FSIBCK), \
GPIO_FN(PORT54_IRDA_FIRSEL), \
GPIO_FN(TPU3TO2), \
- GPIO_FN(FSIBOMC), \
- GPIO_FN(FSICCK), \
- GPIO_FN(FSICOMC),
- GPIO_FN(FSIAISLD), \
GPIO_FN(TPU0TO0),
GPIO_FN(A0), \
GPIO_FN(BS_),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 109/142] sh-pfc: sh73a0: Remove pull-up function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (106 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 108/142] sh-pfc: sh73a0: Remove FSI " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 110/142] sh-pfc: sh73a0: Remove KEYSC " Simon Horman
` (33 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All sh73a0 platforms now use the pinconf API to control pull-ups, the
corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 465 ++---------------------------------
1 file changed, 23 insertions(+), 442 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 1a638f2..1249a3f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -66,14 +66,6 @@ enum {
PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
PINMUX_INPUT_END,
- PINMUX_INPUT_PULLUP_BEGIN,
- PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
- PINMUX_INPUT_PULLUP_END,
-
- PINMUX_INPUT_PULLDOWN_BEGIN,
- PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
- PINMUX_INPUT_PULLDOWN_END,
-
PINMUX_OUTPUT_BEGIN,
PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
PINMUX_OUTPUT_END,
@@ -468,328 +460,15 @@ enum {
EDBGREQ_PD_MARK,
EDBGREQ_PU_MARK,
- /* Functions with pull-ups */
- KEYIN0_PU_MARK,
- KEYIN1_PU_MARK,
- KEYIN2_PU_MARK,
- KEYIN3_PU_MARK,
- KEYIN4_PU_MARK,
- KEYIN5_PU_MARK,
- KEYIN6_PU_MARK,
- KEYIN7_PU_MARK,
- SDHICD0_PU_MARK,
- SDHID0_0_PU_MARK,
- SDHID0_1_PU_MARK,
- SDHID0_2_PU_MARK,
- SDHID0_3_PU_MARK,
- SDHICMD0_PU_MARK,
- SDHIWP0_PU_MARK,
- SDHID1_0_PU_MARK,
- SDHID1_1_PU_MARK,
- SDHID1_2_PU_MARK,
- SDHID1_3_PU_MARK,
- SDHICMD1_PU_MARK,
- SDHID2_0_PU_MARK,
- SDHID2_1_PU_MARK,
- SDHID2_2_PU_MARK,
- SDHID2_3_PU_MARK,
- SDHICMD2_PU_MARK,
- MMCCMD0_PU_MARK,
- MMCCMD1_PU_MARK,
- MMCD0_0_PU_MARK,
- MMCD0_1_PU_MARK,
- MMCD0_2_PU_MARK,
- MMCD0_3_PU_MARK,
- MMCD0_4_PU_MARK,
- MMCD0_5_PU_MARK,
- MMCD0_6_PU_MARK,
- MMCD0_7_PU_MARK,
- FSIBISLD_PU_MARK,
- FSIACK_PU_MARK,
- FSIAILR_PU_MARK,
- FSIAIBT_PU_MARK,
- FSIAISLD_PU_MARK,
-
PINMUX_MARK_END,
};
+#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
+
static const pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
-
- /* Table 25-1 (I/O and Pull U/D) */
- PORT_DATA_I_PD(0),
- PORT_DATA_I_PU(1),
- PORT_DATA_I_PU(2),
- PORT_DATA_I_PU(3),
- PORT_DATA_I_PU(4),
- PORT_DATA_I_PU(5),
- PORT_DATA_I_PU(6),
- PORT_DATA_I_PU(7),
- PORT_DATA_I_PU(8),
- PORT_DATA_I_PD(9),
- PORT_DATA_I_PD(10),
- PORT_DATA_I_PU_PD(11),
- PORT_DATA_IO_PU_PD(12),
- PORT_DATA_IO_PU_PD(13),
- PORT_DATA_IO_PU_PD(14),
- PORT_DATA_IO_PU_PD(15),
- PORT_DATA_IO_PD(16),
- PORT_DATA_IO_PD(17),
- PORT_DATA_IO_PU(18),
- PORT_DATA_IO_PU(19),
- PORT_DATA_O(20),
- PORT_DATA_O(21),
- PORT_DATA_O(22),
- PORT_DATA_O(23),
- PORT_DATA_O(24),
- PORT_DATA_I_PD(25),
- PORT_DATA_I_PD(26),
- PORT_DATA_IO_PU(27),
- PORT_DATA_IO_PU(28),
- PORT_DATA_IO_PD(29),
- PORT_DATA_IO_PD(30),
- PORT_DATA_IO_PU(31),
- PORT_DATA_IO_PD(32),
- PORT_DATA_I_PU_PD(33),
- PORT_DATA_IO_PD(34),
- PORT_DATA_I_PU_PD(35),
- PORT_DATA_IO_PD(36),
- PORT_DATA_IO(37),
- PORT_DATA_O(38),
- PORT_DATA_I_PU(39),
- PORT_DATA_I_PU_PD(40),
- PORT_DATA_O(41),
- PORT_DATA_IO_PD(42),
- PORT_DATA_IO_PU_PD(43),
- PORT_DATA_IO_PU_PD(44),
- PORT_DATA_IO_PD(45),
- PORT_DATA_IO_PD(46),
- PORT_DATA_IO_PD(47),
- PORT_DATA_I_PD(48),
- PORT_DATA_IO_PU_PD(49),
- PORT_DATA_IO_PD(50),
-
- PORT_DATA_IO_PD(51),
- PORT_DATA_O(52),
- PORT_DATA_IO_PU_PD(53),
- PORT_DATA_IO_PU_PD(54),
- PORT_DATA_IO_PD(55),
- PORT_DATA_I_PU_PD(56),
- PORT_DATA_IO(57),
- PORT_DATA_IO(58),
- PORT_DATA_IO(59),
- PORT_DATA_IO(60),
- PORT_DATA_IO(61),
- PORT_DATA_IO_PD(62),
- PORT_DATA_IO_PD(63),
- PORT_DATA_IO_PU_PD(64),
- PORT_DATA_IO_PD(65),
- PORT_DATA_IO_PU_PD(66),
- PORT_DATA_IO_PU_PD(67),
- PORT_DATA_IO_PU_PD(68),
- PORT_DATA_IO_PU_PD(69),
- PORT_DATA_IO_PU_PD(70),
- PORT_DATA_IO_PU_PD(71),
- PORT_DATA_IO_PU_PD(72),
- PORT_DATA_I_PU_PD(73),
- PORT_DATA_IO_PU(74),
- PORT_DATA_IO_PU(75),
- PORT_DATA_IO_PU(76),
- PORT_DATA_IO_PU(77),
- PORT_DATA_IO_PU(78),
- PORT_DATA_IO_PU(79),
- PORT_DATA_IO_PU(80),
- PORT_DATA_IO_PU(81),
- PORT_DATA_IO_PU(82),
- PORT_DATA_IO_PU(83),
- PORT_DATA_IO_PU(84),
- PORT_DATA_IO_PU(85),
- PORT_DATA_IO_PU(86),
- PORT_DATA_IO_PU(87),
- PORT_DATA_IO_PU(88),
- PORT_DATA_IO_PU(89),
- PORT_DATA_O(90),
- PORT_DATA_IO_PU(91),
- PORT_DATA_O(92),
- PORT_DATA_IO_PU(93),
- PORT_DATA_O(94),
- PORT_DATA_I_PU_PD(95),
- PORT_DATA_IO(96),
- PORT_DATA_IO(97),
- PORT_DATA_IO(98),
- PORT_DATA_I_PU(99),
- PORT_DATA_O(100),
- PORT_DATA_O(101),
- PORT_DATA_I_PU(102),
- PORT_DATA_IO_PD(103),
- PORT_DATA_I_PU_PD(104),
- PORT_DATA_I_PD(105),
- PORT_DATA_I_PD(106),
- PORT_DATA_I_PU_PD(107),
- PORT_DATA_I_PU_PD(108),
- PORT_DATA_IO_PD(109),
- PORT_DATA_IO_PD(110),
- PORT_DATA_IO_PU_PD(111),
- PORT_DATA_IO_PU_PD(112),
- PORT_DATA_IO_PU_PD(113),
- PORT_DATA_IO_PD(114),
- PORT_DATA_IO_PU(115),
- PORT_DATA_IO_PU(116),
- PORT_DATA_IO_PU_PD(117),
- PORT_DATA_IO_PU_PD(118),
- PORT_DATA_IO_PD(128),
-
- PORT_DATA_IO_PD(129),
- PORT_DATA_IO_PU_PD(130),
- PORT_DATA_IO_PD(131),
- PORT_DATA_IO_PD(132),
- PORT_DATA_IO_PD(133),
- PORT_DATA_IO_PU_PD(134),
- PORT_DATA_IO_PU_PD(135),
- PORT_DATA_IO_PU_PD(136),
- PORT_DATA_IO_PU_PD(137),
- PORT_DATA_IO_PD(138),
- PORT_DATA_IO_PD(139),
- PORT_DATA_IO_PD(140),
- PORT_DATA_IO_PD(141),
- PORT_DATA_IO_PD(142),
- PORT_DATA_IO_PD(143),
- PORT_DATA_IO_PU_PD(144),
- PORT_DATA_IO_PD(145),
- PORT_DATA_IO_PU_PD(146),
- PORT_DATA_IO_PU_PD(147),
- PORT_DATA_IO_PU_PD(148),
- PORT_DATA_IO_PU_PD(149),
- PORT_DATA_I_PU_PD(150),
- PORT_DATA_IO_PU_PD(151),
- PORT_DATA_IO_PU_PD(152),
- PORT_DATA_IO_PD(153),
- PORT_DATA_IO_PD(154),
- PORT_DATA_I_PU_PD(155),
- PORT_DATA_IO_PU_PD(156),
- PORT_DATA_I_PD(157),
- PORT_DATA_IO_PD(158),
- PORT_DATA_IO_PU_PD(159),
- PORT_DATA_IO_PU_PD(160),
- PORT_DATA_I_PU_PD(161),
- PORT_DATA_I_PU_PD(162),
- PORT_DATA_IO_PU_PD(163),
- PORT_DATA_I_PU_PD(164),
- PORT_DATA_IO_PD(192),
- PORT_DATA_IO_PU_PD(193),
- PORT_DATA_IO_PD(194),
- PORT_DATA_IO_PU_PD(195),
- PORT_DATA_IO_PD(196),
- PORT_DATA_IO_PD(197),
- PORT_DATA_IO_PD(198),
- PORT_DATA_IO_PD(199),
- PORT_DATA_IO_PU_PD(200),
- PORT_DATA_IO_PU_PD(201),
- PORT_DATA_IO_PU_PD(202),
- PORT_DATA_IO_PU_PD(203),
- PORT_DATA_IO_PU_PD(204),
- PORT_DATA_IO_PU_PD(205),
- PORT_DATA_IO_PU_PD(206),
- PORT_DATA_IO_PD(207),
- PORT_DATA_IO_PD(208),
- PORT_DATA_IO_PD(209),
- PORT_DATA_IO_PD(210),
- PORT_DATA_IO_PD(211),
- PORT_DATA_IO_PD(212),
- PORT_DATA_IO_PD(213),
- PORT_DATA_IO_PU_PD(214),
- PORT_DATA_IO_PU_PD(215),
- PORT_DATA_IO_PD(216),
- PORT_DATA_IO_PD(217),
- PORT_DATA_O(218),
- PORT_DATA_IO_PD(219),
- PORT_DATA_IO_PD(220),
- PORT_DATA_IO_PU_PD(221),
- PORT_DATA_IO_PU_PD(222),
- PORT_DATA_I_PU_PD(223),
- PORT_DATA_I_PU_PD(224),
-
- PORT_DATA_IO_PU_PD(225),
- PORT_DATA_O(226),
- PORT_DATA_IO_PU_PD(227),
- PORT_DATA_I_PU_PD(228),
- PORT_DATA_I_PD(229),
- PORT_DATA_IO(230),
- PORT_DATA_IO_PU_PD(231),
- PORT_DATA_IO_PU_PD(232),
- PORT_DATA_I_PU_PD(233),
- PORT_DATA_IO_PU_PD(234),
- PORT_DATA_IO_PU_PD(235),
- PORT_DATA_IO_PU_PD(236),
- PORT_DATA_IO_PD(237),
- PORT_DATA_IO_PU_PD(238),
- PORT_DATA_IO_PU_PD(239),
- PORT_DATA_IO_PU_PD(240),
- PORT_DATA_O(241),
- PORT_DATA_I_PD(242),
- PORT_DATA_IO_PU_PD(243),
- PORT_DATA_IO_PU_PD(244),
- PORT_DATA_IO_PU_PD(245),
- PORT_DATA_IO_PU_PD(246),
- PORT_DATA_IO_PU_PD(247),
- PORT_DATA_IO_PU_PD(248),
- PORT_DATA_IO_PU_PD(249),
- PORT_DATA_IO_PU_PD(250),
- PORT_DATA_IO_PU_PD(251),
- PORT_DATA_IO_PU_PD(252),
- PORT_DATA_IO_PU_PD(253),
- PORT_DATA_IO_PU_PD(254),
- PORT_DATA_IO_PU_PD(255),
- PORT_DATA_IO_PU_PD(256),
- PORT_DATA_IO_PU_PD(257),
- PORT_DATA_IO_PU_PD(258),
- PORT_DATA_IO_PU_PD(259),
- PORT_DATA_IO_PU_PD(260),
- PORT_DATA_IO_PU_PD(261),
- PORT_DATA_IO_PU_PD(262),
- PORT_DATA_IO_PU_PD(263),
- PORT_DATA_IO_PU_PD(264),
- PORT_DATA_IO_PU_PD(265),
- PORT_DATA_IO_PU_PD(266),
- PORT_DATA_IO_PU_PD(267),
- PORT_DATA_IO_PU_PD(268),
- PORT_DATA_IO_PU_PD(269),
- PORT_DATA_IO_PU_PD(270),
- PORT_DATA_IO_PU_PD(271),
- PORT_DATA_IO_PU_PD(272),
- PORT_DATA_IO_PU_PD(273),
- PORT_DATA_IO_PU_PD(274),
- PORT_DATA_IO_PU_PD(275),
- PORT_DATA_IO_PU_PD(276),
- PORT_DATA_IO_PU_PD(277),
- PORT_DATA_IO_PU_PD(278),
- PORT_DATA_IO_PU_PD(279),
- PORT_DATA_IO_PU_PD(280),
- PORT_DATA_O(281),
- PORT_DATA_O(282),
- PORT_DATA_I_PU(288),
- PORT_DATA_IO_PU_PD(289),
- PORT_DATA_IO_PU_PD(290),
- PORT_DATA_IO_PU_PD(291),
- PORT_DATA_IO_PU_PD(292),
- PORT_DATA_IO_PU_PD(293),
- PORT_DATA_IO_PU_PD(294),
- PORT_DATA_IO_PU_PD(295),
- PORT_DATA_IO_PU_PD(296),
- PORT_DATA_IO_PU_PD(297),
- PORT_DATA_IO_PU_PD(298),
-
- PORT_DATA_IO_PU_PD(299),
- PORT_DATA_IO_PU_PD(300),
- PORT_DATA_IO_PU_PD(301),
- PORT_DATA_IO_PU_PD(302),
- PORT_DATA_IO_PU_PD(303),
- PORT_DATA_IO_PU_PD(304),
- PORT_DATA_IO_PU_PD(305),
- PORT_DATA_O(306),
- PORT_DATA_O(307),
- PORT_DATA_I_PU(308),
- PORT_DATA_O(309),
+ PINMUX_DATA_GP_ALL(),
/* Table 25-1 (Function 0-7) */
PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
@@ -1358,28 +1037,19 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
- MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
- MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
- MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
- MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
- MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
- PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
- MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
- PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
- MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
- PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
- MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
- PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
- MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
@@ -1485,62 +1155,6 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
-
- /* Functions with pull-ups */
- PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
- PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
- PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
- PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
- PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
- PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
- PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
- PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
-
- PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU),
- PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU),
- PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU),
- PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU),
- PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU),
- PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU),
- PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT257_IN_PU),
- PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU),
- PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU),
- PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU),
- PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU),
- PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU),
- PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU),
- PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU),
- PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU),
- PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU),
- PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU),
-
- PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
- MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
- MSEL4CR_MSEL15_1),
-
- PINMUX_DATA(MMCD0_0_PU_MARK,
- PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_1_PU_MARK,
- PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_2_PU_MARK,
- PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_3_PU_MARK,
- PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_4_PU_MARK,
- PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_5_PU_MARK,
- PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_6_PU_MARK,
- PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_7_PU_MARK,
- PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
-
- PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
- PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
- PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
- PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
- PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
};
#define SH73A0_PIN(pin, cfgs) \
@@ -3775,49 +3389,18 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(RESETA_N_PU_OFF),
GPIO_FN(EDBGREQ_PD),
GPIO_FN(EDBGREQ_PU),
-
- /* Functions with pull-ups */
- GPIO_FN(KEYIN0_PU),
- GPIO_FN(KEYIN1_PU),
- GPIO_FN(KEYIN2_PU),
- GPIO_FN(KEYIN3_PU),
- GPIO_FN(KEYIN4_PU),
- GPIO_FN(KEYIN5_PU),
- GPIO_FN(KEYIN6_PU),
- GPIO_FN(KEYIN7_PU),
- GPIO_FN(SDHICD0_PU),
- GPIO_FN(SDHID0_0_PU),
- GPIO_FN(SDHID0_1_PU),
- GPIO_FN(SDHID0_2_PU),
- GPIO_FN(SDHID0_3_PU),
- GPIO_FN(SDHICMD0_PU),
- GPIO_FN(SDHIWP0_PU),
- GPIO_FN(SDHID1_0_PU),
- GPIO_FN(SDHID1_1_PU),
- GPIO_FN(SDHID1_2_PU),
- GPIO_FN(SDHID1_3_PU),
- GPIO_FN(SDHICMD1_PU),
- GPIO_FN(SDHID2_0_PU),
- GPIO_FN(SDHID2_1_PU),
- GPIO_FN(SDHID2_2_PU),
- GPIO_FN(SDHID2_3_PU),
- GPIO_FN(SDHICMD2_PU),
- GPIO_FN(MMCCMD0_PU),
- GPIO_FN(MMCCMD1_PU),
- GPIO_FN(MMCD0_0_PU),
- GPIO_FN(MMCD0_1_PU),
- GPIO_FN(MMCD0_2_PU),
- GPIO_FN(MMCD0_3_PU),
- GPIO_FN(MMCD0_4_PU),
- GPIO_FN(MMCD0_5_PU),
- GPIO_FN(MMCD0_6_PU),
- GPIO_FN(MMCD0_7_PU),
- GPIO_FN(FSIACK_PU),
- GPIO_FN(FSIAILR_PU),
- GPIO_FN(FSIAIBT_PU),
- GPIO_FN(FSIAISLD_PU),
};
+#undef PORTCR
+#define PORTCR(nr, reg) \
+ { \
+ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
+ _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
+ PORT##nr##_FN0, PORT##nr##_FN1, \
+ PORT##nr##_FN2, PORT##nr##_FN3, \
+ PORT##nr##_FN4, PORT##nr##_FN5, \
+ PORT##nr##_FN6, PORT##nr##_FN7 } \
+ }
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
@@ -4425,8 +4008,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
.ops = &sh73a0_pinmux_ops,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
- .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 110/142] sh-pfc: sh73a0: Remove KEYSC function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (107 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 109/142] sh-pfc: sh73a0: Remove pull-up " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 111/142] sh-pfc: sh73a0: Remove BSC " Simon Horman
` (32 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All sh73a0 platforms now use the pinctrl API to control the KEYSC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 30 ------------------------------
1 file changed, 30 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 1249a3f..33e2b3f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2996,48 +2996,32 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(A0), \
GPIO_FN(BS_),
GPIO_FN(A12), \
- GPIO_FN(PORT58_KEYOUT7), \
GPIO_FN(TPU4TO2),
GPIO_FN(A13), \
- GPIO_FN(PORT59_KEYOUT6), \
GPIO_FN(TPU0TO1),
GPIO_FN(A14), \
- GPIO_FN(KEYOUT5),
GPIO_FN(A15), \
- GPIO_FN(KEYOUT4),
GPIO_FN(A16), \
- GPIO_FN(KEYOUT3), \
GPIO_FN(MSIOF0_SS1),
GPIO_FN(A17), \
- GPIO_FN(KEYOUT2), \
GPIO_FN(MSIOF0_TSYNC),
GPIO_FN(A18), \
- GPIO_FN(KEYOUT1), \
GPIO_FN(MSIOF0_TSCK),
GPIO_FN(A19), \
- GPIO_FN(KEYOUT0), \
GPIO_FN(MSIOF0_TXD),
GPIO_FN(A20), \
- GPIO_FN(KEYIN0), \
GPIO_FN(MSIOF0_RSCK),
GPIO_FN(A21), \
- GPIO_FN(KEYIN1), \
GPIO_FN(MSIOF0_RSYNC),
GPIO_FN(A22), \
- GPIO_FN(KEYIN2), \
GPIO_FN(MSIOF0_MCK0),
GPIO_FN(A23), \
- GPIO_FN(KEYIN3), \
GPIO_FN(MSIOF0_MCK1),
GPIO_FN(A24), \
- GPIO_FN(KEYIN4), \
GPIO_FN(MSIOF0_RXD),
GPIO_FN(A25), \
- GPIO_FN(KEYIN5), \
GPIO_FN(MSIOF0_SS2),
GPIO_FN(A26), \
- GPIO_FN(KEYIN6),
- GPIO_FN(KEYIN7),
GPIO_FN(D0_NAF0),
GPIO_FN(D1_NAF1),
GPIO_FN(D2_NAF2),
@@ -3105,13 +3089,9 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VIO_D0), \
GPIO_FN(PORT130_MSIOF2_RXD), \
GPIO_FN(VIO_D1), \
- GPIO_FN(PORT131_KEYOUT6), \
GPIO_FN(PORT131_MSIOF2_SS1), \
- GPIO_FN(PORT131_KEYOUT11), \
GPIO_FN(VIO_D2), \
- GPIO_FN(PORT132_KEYOUT7), \
GPIO_FN(PORT132_MSIOF2_SS2), \
- GPIO_FN(PORT132_KEYOUT10), \
GPIO_FN(VIO_D3), \
GPIO_FN(MSIOF2_TSYNC), \
GPIO_FN(VIO_D4), \
@@ -3119,14 +3099,10 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VIO_D5), \
GPIO_FN(MSIOF2_TSCK), \
GPIO_FN(VIO_D6), \
- GPIO_FN(PORT136_KEYOUT8), \
GPIO_FN(VIO_D7), \
- GPIO_FN(PORT137_KEYOUT9), \
GPIO_FN(VIO_D8), \
- GPIO_FN(PORT138_KEYOUT8), \
GPIO_FN(VIO2_D0), \
GPIO_FN(VIO_D9), \
- GPIO_FN(PORT139_KEYOUT9), \
GPIO_FN(VIO2_D1), \
GPIO_FN(VIO_D10), \
GPIO_FN(TPU0TO2), \
@@ -3135,14 +3111,10 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(TPU0TO3), \
GPIO_FN(VIO2_D3), \
GPIO_FN(VIO_D12), \
- GPIO_FN(PORT142_KEYOUT10), \
GPIO_FN(VIO2_D4), \
GPIO_FN(VIO_D13), \
- GPIO_FN(PORT143_KEYOUT11), \
- GPIO_FN(PORT143_KEYOUT6), \
GPIO_FN(VIO2_D5), \
GPIO_FN(VIO_D14), \
- GPIO_FN(PORT144_KEYOUT7), \
GPIO_FN(VIO2_D6), \
GPIO_FN(VIO_D15), \
GPIO_FN(TPU1TO3), \
@@ -3155,7 +3127,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(A27), \
GPIO_FN(PORT149_RDWR), \
GPIO_FN(MFG0_IN1), \
- GPIO_FN(PORT149_KEYOUT9),
GPIO_FN(MFG0_IN2),
GPIO_FN(TS_SPSYNC3), \
GPIO_FN(MSIOF2_RSCK),
@@ -3383,7 +3354,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(IRQ9_MEM_INT),
GPIO_FN(IRQ9_MCP_INT),
GPIO_FN(A11),
- GPIO_FN(KEYOUT8),
GPIO_FN(TPU4TO3),
GPIO_FN(RESETA_N_PU_ON),
GPIO_FN(RESETA_N_PU_OFF),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 111/142] sh-pfc: sh73a0: Remove BSC function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (108 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 110/142] sh-pfc: sh73a0: Remove KEYSC " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 112/142] sh-pfc: sh73a0: Remove USB " Simon Horman
` (31 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All sh73a0 platforms now use the pinctrl API to control the BSC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 27 ---------------------------
1 file changed, 27 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 33e2b3f..7b010b6 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3022,37 +3022,11 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(A25), \
GPIO_FN(MSIOF0_SS2),
GPIO_FN(A26), \
- GPIO_FN(D0_NAF0),
- GPIO_FN(D1_NAF1),
- GPIO_FN(D2_NAF2),
- GPIO_FN(D3_NAF3),
- GPIO_FN(D4_NAF4),
- GPIO_FN(D5_NAF5),
- GPIO_FN(D6_NAF6),
- GPIO_FN(D7_NAF7),
- GPIO_FN(D8_NAF8),
- GPIO_FN(D9_NAF9),
- GPIO_FN(D10_NAF10),
- GPIO_FN(D11_NAF11),
- GPIO_FN(D12_NAF12),
- GPIO_FN(D13_NAF13),
- GPIO_FN(D14_NAF14),
- GPIO_FN(D15_NAF15),
- GPIO_FN(CS4_),
- GPIO_FN(CS5A_), \
- GPIO_FN(PORT91_RDWR),
- GPIO_FN(CS5B_), \
GPIO_FN(FCE1_),
- GPIO_FN(CS6B_), \
GPIO_FN(DACK0),
GPIO_FN(FCE0_), \
- GPIO_FN(CS6A_),
GPIO_FN(WAIT_), \
GPIO_FN(DREQ0),
- GPIO_FN(RD__FSC),
- GPIO_FN(WE0__FWE), \
- GPIO_FN(RDWR_FWE),
- GPIO_FN(WE1_),
GPIO_FN(FRB),
GPIO_FN(CKO),
GPIO_FN(NBRSTOUT_),
@@ -3125,7 +3099,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VIO2_FIELD), \
GPIO_FN(VIO_CKO),
GPIO_FN(A27), \
- GPIO_FN(PORT149_RDWR), \
GPIO_FN(MFG0_IN1), \
GPIO_FN(MFG0_IN2),
GPIO_FN(TS_SPSYNC3), \
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 112/142] sh-pfc: sh73a0: Remove USB function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (109 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 111/142] sh-pfc: sh73a0: Remove BSC " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 113/142] sh-pfc: sh73a0: Remove IrDA " Simon Horman
` (30 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All sh73a0 platforms now use the pinctrl API to control the USB pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 7b010b6..273345c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2936,11 +2936,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(usb),
};
-#define PINMUX_FN_BASE GPIO_FN_VBUS_0
+#define PINMUX_FN_BASE GPIO_FN_GPI0
static const struct pinmux_func pinmux_func_gpios[] = {
/* Table 25-1 (Functions 0-7) */
- GPIO_FN(VBUS_0),
GPIO_FN(GPI0),
GPIO_FN(GPI1),
GPIO_FN(GPI2),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 113/142] sh-pfc: sh73a0: Remove IrDA function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (110 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 112/142] sh-pfc: sh73a0: Remove USB " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 114/142] sh-pfc: r8a7740: Remove LCD0 and LCD1 " Simon Horman
` (29 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All sh73a0 platforms now use the pinctrl API to control the IrDA pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 273345c..cde4387 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2979,7 +2979,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(XWUP),
GPIO_FN(VACK),
GPIO_FN(XTAL1L),
- GPIO_FN(PORT49_IRDA_OUT), \
GPIO_FN(PORT49_IROUT), \
GPIO_FN(BBIF2_TSYNC2), \
GPIO_FN(TPU2TO2), \
@@ -2987,9 +2986,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(BBIF2_TSCK2), \
GPIO_FN(TPU2TO3), \
GPIO_FN(BBIF2_TXD2),
- GPIO_FN(PORT53_IRDA_IN), \
GPIO_FN(TPU3TO3), \
- GPIO_FN(PORT54_IRDA_FIRSEL), \
GPIO_FN(TPU3TO2), \
GPIO_FN(TPU0TO0),
GPIO_FN(A0), \
@@ -3188,13 +3185,10 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VIO2_FIELD2), \
GPIO_FN(MSIOF1_SS2), \
GPIO_FN(VIO2_HD2), \
- GPIO_FN(PORT241_IRDA_OUT), \
GPIO_FN(PORT241_IROUT), \
GPIO_FN(MFG4_OUT1), \
GPIO_FN(TPU4TO0),
- GPIO_FN(PORT242_IRDA_IN), \
GPIO_FN(MFG4_IN2),
- GPIO_FN(PORT243_IRDA_FIRSEL), \
GPIO_FN(PORT243_VIO_CKO2),
GPIO_FN(MFG2_IN1), \
GPIO_FN(MSIOF2R_RXD),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 114/142] sh-pfc: r8a7740: Remove LCD0 and LCD1 function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (111 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 113/142] sh-pfc: sh73a0: Remove IrDA " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 115/142] sh-pfc: r8a7740: Remove SDHI and MMCIF " Simon Horman
` (28 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All r8a7740 platforms now use the pinctrl API to control the LCD0 and
LCD1 pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 37 ----------------------------------
1 file changed, 37 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index a2f909a..de1212d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2313,43 +2313,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SCIFB_RTS_PORT172),
GPIO_FN(SCIFB_CTS_PORT173),
- /* LCD0 */
- GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
- GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
- GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
- GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
- GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
- GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
- GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
- GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
- GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
- GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
- GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
-
- GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
- GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
- GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
- GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
-
- GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
- GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
- GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
- GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
-
- /* LCD1 */
- GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
- GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
- GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
- GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
- GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
- GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
- GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
- GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
- GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
- GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
- GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
- GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
-
/* RSPI */
GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 115/142] sh-pfc: r8a7740: Remove SDHI and MMCIF function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (112 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 114/142] sh-pfc: r8a7740: Remove LCD0 and LCD1 " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 116/142] sh-pfc: r8a7779: Remove DU1_DOTCLKOUT1 GPIO Simon Horman
` (27 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All r8a7740 platforms now use the pinctrl API to control the SDHI and
MMCIF pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 35 ----------------------------------
1 file changed, 35 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index de1212d..3621d3e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2373,26 +2373,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
GPIO_FN(SIM_D_PORT199),
- /* SDHI0 */
- GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
- GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
- GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
-
- /* SDHI1 */
- GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
- GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
- GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
-
- /* SDHI2 */
- GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
- GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
-
- GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
- GPIO_FN(SDHI2_WP_PORT25),
-
- GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
- GPIO_FN(SDHI2_CD_PORT202),
-
/* MSIOF2 */
GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
@@ -2437,21 +2417,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
GPIO_FN(MEMC_A0),
- /* MMC */
- GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
- GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
- GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
- GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
- GPIO_FN(MMC0_CLK_PORT66),
- GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
-
- GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
- GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
- GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
- GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
- GPIO_FN(MMC1_CLK_PORT103),
- GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
-
/* MSIOF0 */
GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 116/142] sh-pfc: r8a7779: Remove DU1_DOTCLKOUT1 GPIO
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (113 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 115/142] sh-pfc: r8a7740: Remove SDHI and MMCIF " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 117/142] sh-pfc: r8a7779: Remove SDHI and MMCIF function GPIOS Simon Horman
` (26 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The function is not documented in the r8a7779 datasheet. Remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 5b498ff..f1fa355 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -353,7 +353,7 @@ enum {
FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
- FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
+ FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
@@ -615,7 +615,7 @@ enum {
HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
- VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK,
+ VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
@@ -1385,7 +1385,6 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
- PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
PINMUX_IPSR_DATA(IP11_26_24, TX2),
@@ -2926,7 +2925,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
- GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1),
+ GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0),
GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
@@ -3634,7 +3633,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
/* IP11_26_24 [3] */
- FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1,
+ FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
/* IP11_23_21 [3] */
FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 117/142] sh-pfc: r8a7779: Remove SDHI and MMCIF function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (114 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 116/142] sh-pfc: r8a7779: Remove DU1_DOTCLKOUT1 GPIO Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 118/142] sh-pfc: r8a7779: Remove SCIF " Simon Horman
` (25 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All r8a7779 platforms now use the pinctrl API to control the SDHI and
MMCIF pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 112 +++++++++++++++++-----------------
1 file changed, 56 insertions(+), 56 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index f1fa355..0a65003 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2678,16 +2678,16 @@ static const struct pinmux_func pinmux_func_gpios[] = {
/* IPSR0 */
GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
- GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
- GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
- GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
- GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
+ GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS),
+ GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
+ GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0),
+ GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D),
GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D),
GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
- GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD),
- GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
- GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5),
+ GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24),
+ GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
+ GPIO_FN(SSI_WS78_B), GPIO_FN(A25),
GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B),
GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT),
GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0),
@@ -2696,17 +2696,17 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C),
/* IPSR1 */
- GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6),
- GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7),
- GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE),
- GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD),
+ GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C),
+ GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(FD7),
+ GPIO_FN(EX_CS2), GPIO_FN(FALE),
+ GPIO_FN(ATACS00), GPIO_FN(EX_CS3),
GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B),
GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B),
- GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0),
- GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
+ GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4),
+ GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B),
- GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1),
- GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
+ GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5),
+ GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9),
GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG),
GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
@@ -2766,26 +2766,26 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
- GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
+ GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1),
- GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E),
+ GPIO_FN(PWM0), GPIO_FN(RX3_E_IRDA_RX_E),
GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(VI2_G0),
GPIO_FN(VI2_G1), GPIO_FN(VI2_G2),
GPIO_FN(VI2_G3), GPIO_FN(VI2_G4),
GPIO_FN(VI2_G5),
- GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
+ GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B),
GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D),
- GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
+ GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B),
GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D),
GPIO_FN(VI2_G6), GPIO_FN(VI2_G7),
GPIO_FN(VI2_R0), GPIO_FN(VI2_R1),
GPIO_FN(VI2_R2), GPIO_FN(VI2_R3),
- GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
+ GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B),
GPIO_FN(TX5), GPIO_FN(SCK0_D),
/* IPSR5 */
GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
- GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
+ GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
GPIO_FN(VI2_R4), GPIO_FN(VI2_R5),
GPIO_FN(VI2_R6), GPIO_FN(VI2_R7),
GPIO_FN(SCL2_D), GPIO_FN(SDA2_D),
@@ -2794,14 +2794,14 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC),
GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC),
GPIO_FN(VI3_VSYNC),
- GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
+ GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B),
GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6),
GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
- GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
+ GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
@@ -2835,14 +2835,14 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
- GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK),
- GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11),
- GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1),
- GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1),
- GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1),
- GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1),
- GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2),
- GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
+ GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C),
+ GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(ATACS11),
+ GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1),
+ GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(ATAG1),
+ GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(ATARD1),
+ GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1),
+ GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(DREQ2),
+ GPIO_FN(RTS1_B_TANS_B), GPIO_FN(DACK2),
GPIO_FN(CTS1_B),
/* IPSR8 */
@@ -2859,46 +2859,46 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
- GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB),
+ GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB),
GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
- GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B),
+ GPIO_FN(TX4_D), GPIO_FN(HSCK1_B),
GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
/* IPSR9 */
GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
- GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3),
- GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2),
- GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6),
- GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
- GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
+ GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(VI0_DATA3_VI0_B3),
+ GPIO_FN(VI0_DATA4_VI0_B4),
+ GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(VI0_DATA6_VI0_B6),
+ GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
+ GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2),
GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1),
GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
- GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
- GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7),
+ GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
+ GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV),
GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
- GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6),
- GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B),
+ GPIO_FN(ETH_TX_EN), GPIO_FN(ARM_TRACEDATA_6),
+ GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER),
GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
- GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
- GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9),
+ GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
+ GPIO_FN(ETH_RXD1), GPIO_FN(ARM_TRACEDATA_9),
/* IPSR10 */
GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C),
GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
- GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2),
+ GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(IRQ2),
GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
- GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
- GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B),
+ GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
+ GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK),
GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
- GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
+ GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
@@ -2911,19 +2911,19 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
/* IPSR11 */
- GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST),
+ GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SIM_RST),
GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
- GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
- GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2),
+ GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
+ GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2),
GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
- GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN),
+ GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(MT0_BEN),
GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
- GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
+ GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
- GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
+ GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
- GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
- GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
+ GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
+ GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7),
GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0),
GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 118/142] sh-pfc: r8a7779: Remove SCIF function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (115 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 117/142] sh-pfc: r8a7779: Remove SDHI and MMCIF function GPIOS Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 119/142] sh-pfc: r8a7779: Remove HSPI " Simon Horman
` (24 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All r8a7779 platforms now use the pinctrl API to control the SCIF pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 141 +++++++++++++++++-----------------
1 file changed, 69 insertions(+), 72 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 0a65003..ecc300d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2677,61 +2677,61 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(A19),
/* IPSR0 */
- GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
+ GPIO_FN(USB_PENC2), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS),
GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
- GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0),
- GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
- GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D),
- GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D),
+ GPIO_FN(HCTS1), GPIO_FN(A0),
+ GPIO_FN(FD3), GPIO_FN(A20),
+ GPIO_FN(HSPI_TX2_B), GPIO_FN(A21),
+ GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22),
GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24),
GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
GPIO_FN(SSI_WS78_B), GPIO_FN(A25),
- GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B),
- GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT),
- GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0),
+ GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3),
+ GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT),
+ GPIO_FN(PWM0_B), GPIO_FN(CS0),
GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
- GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C),
+ GPIO_FN(VI1_R7), GPIO_FN(HRTS1),
/* IPSR1 */
- GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C),
+ GPIO_FN(EX_CS0),
GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(FD7),
GPIO_FN(EX_CS2), GPIO_FN(FALE),
GPIO_FN(ATACS00), GPIO_FN(EX_CS3),
- GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B),
- GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B),
+ GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4),
+ GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B),
GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4),
GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
- GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B),
+ GPIO_FN(HTX1),
GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5),
GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
- GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9),
- GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG),
- GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
- GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA),
- GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
+ GPIO_FN(HRX1), GPIO_FN(SSI_WS9),
+ GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(MLB_SIG),
+ GPIO_FN(PWM3), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
+ GPIO_FN(HTX0), GPIO_FN(SDATA),
+ GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
GPIO_FN(CC5_STATE34),
/* IPSR2 */
- GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C),
+ GPIO_FN(HRX0), GPIO_FN(SCKZ),
GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
- GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5),
- GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
+ GPIO_FN(HSCK0), GPIO_FN(MTS), GPIO_FN(PWM5),
+ GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
- GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C),
+ GPIO_FN(STM), GPIO_FN(PWM0_D),
GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
- GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS),
- GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
+ GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0),
+ GPIO_FN(MDATA), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
GPIO_FN(CC5_STATE33), GPIO_FN(LCDOUT0),
GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
- GPIO_FN(TX5_C), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
- GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C),
+ GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
+ GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1),
GPIO_FN(LCDOUT2), GPIO_FN(LCDOUT3),
GPIO_FN(LCDOUT4), GPIO_FN(LCDOUT5),
GPIO_FN(LCDOUT6), GPIO_FN(LCDOUT7),
@@ -2747,45 +2747,43 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(LCDOUT15), GPIO_FN(LCDOUT16),
GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
- GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C),
+ GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5),
GPIO_FN(LCDOUT18),
GPIO_FN(LCDOUT19), GPIO_FN(LCDOUT20),
GPIO_FN(LCDOUT21),
GPIO_FN(LCDOUT22), GPIO_FN(LCDOUT23),
- GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
+ GPIO_FN(QSTVA_QVS),
GPIO_FN(SCL3_B), GPIO_FN(QCLK),
- GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
+ GPIO_FN(QSTVB_QVE),
GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
GPIO_FN(QSTH_QHS),
GPIO_FN(QSTB_QHE),
GPIO_FN(QCPV_QDE),
- GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
+ GPIO_FN(CAN1_TX), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
/* IPSR4 */
- GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
- GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
- GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
+ GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C),
+ GPIO_FN(QPOLB), GPIO_FN(CAN1_RX),
+ GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B),
GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
- GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
+ GPIO_FN(AUDCK),
GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1),
- GPIO_FN(PWM0), GPIO_FN(RX3_E_IRDA_RX_E),
- GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(VI2_G0),
+ GPIO_FN(PWM0),
+ GPIO_FN(AUDSYNC), GPIO_FN(VI2_G0),
GPIO_FN(VI2_G1), GPIO_FN(VI2_G2),
GPIO_FN(VI2_G3), GPIO_FN(VI2_G4),
GPIO_FN(VI2_G5),
GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B),
- GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D),
+ GPIO_FN(AUDATA6),
GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B),
- GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D),
+ GPIO_FN(AUDATA7),
GPIO_FN(VI2_G6), GPIO_FN(VI2_G7),
GPIO_FN(VI2_R0), GPIO_FN(VI2_R1),
GPIO_FN(VI2_R2), GPIO_FN(VI2_R3),
GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B),
- GPIO_FN(TX5), GPIO_FN(SCK0_D),
/* IPSR5 */
GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
- GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
GPIO_FN(VI2_R4), GPIO_FN(VI2_R5),
GPIO_FN(VI2_R6), GPIO_FN(VI2_R7),
GPIO_FN(SCL2_D), GPIO_FN(SDA2_D),
@@ -2794,15 +2792,15 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC),
GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC),
GPIO_FN(VI3_VSYNC),
- GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B),
+ GPIO_FN(VI2_CLK),
GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
- GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
+ GPIO_FN(AUDIO_CLKC), GPIO_FN(SPEEDIN),
GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6),
GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
- GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
- GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
+ GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
+ GPIO_FN(VI2_DATA7_VI2_B7),
GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
- GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
+ GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT),
GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
@@ -2820,10 +2818,10 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
- GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D),
+ GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(TCLK0_D),
GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
- GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
- GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6),
+ GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
+ GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6),
GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
/* IPSR7 */
@@ -2836,36 +2834,35 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C),
- GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(ATACS11),
- GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1),
- GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(ATAG1),
- GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(ATARD1),
- GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1),
- GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(DREQ2),
- GPIO_FN(RTS1_B_TANS_B), GPIO_FN(DACK2),
- GPIO_FN(CTS1_B),
+ GPIO_FN(ATACS01), GPIO_FN(ATACS11),
+ GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1),
+ GPIO_FN(CC5_TRST), GPIO_FN(ATAG1),
+ GPIO_FN(CC5_TMS), GPIO_FN(ATARD1),
+ GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1),
+ GPIO_FN(CC5_TDI), GPIO_FN(DREQ2),
+ GPIO_FN(DACK2),
/* IPSR8 */
- GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
+ GPIO_FN(HSPI_CLK0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0),
- GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
+ GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0),
- GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
+ GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0),
- GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
+ GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB),
- GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
- GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
- GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
- GPIO_FN(TX4_D), GPIO_FN(HSCK1_B),
+ GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
+ GPIO_FN(VI0_FIELD), GPIO_FN(HRX1_B),
+ GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B),
+ GPIO_FN(HSCK1_B),
GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
- GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
+ GPIO_FN(PWMFSW0_C),
/* IPSR9 */
GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
@@ -2888,7 +2885,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(ETH_RXD1), GPIO_FN(ARM_TRACEDATA_9),
/* IPSR10 */
- GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C),
+ GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C),
GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
@@ -2926,22 +2923,22 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7),
GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0),
- GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
+ GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(SPA_TDO),
GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
- GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
+ GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B),
GPIO_FN(HRTS0_B),
/* IPSR12 */
GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
- GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
+ GPIO_FN(TS_SPSYNC1), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
- GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B),
+ GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(SIM_D_B),
GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
- GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
- GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B),
+ GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
+ GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 119/142] sh-pfc: r8a7779: Remove HSPI function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (116 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 118/142] sh-pfc: r8a7779: Remove SCIF " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 120/142] sh-pfc: r8a7779: Remove USB " Simon Horman
` (23 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All r8a7779 platforms now use the pinctrl API to control the HSPI pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 54 +++++++++++++++++-----------------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index ecc300d..ca59a18 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2682,16 +2682,16 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
GPIO_FN(HCTS1), GPIO_FN(A0),
GPIO_FN(FD3), GPIO_FN(A20),
- GPIO_FN(HSPI_TX2_B), GPIO_FN(A21),
- GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22),
- GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
- GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24),
- GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
+ GPIO_FN(A21),
+ GPIO_FN(A22),
+ GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
+ GPIO_FN(VI1_R1), GPIO_FN(A24),
+ GPIO_FN(FD4), GPIO_FN(VI1_R2),
GPIO_FN(SSI_WS78_B), GPIO_FN(A25),
- GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3),
+ GPIO_FN(FD5), GPIO_FN(VI1_R3),
GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT),
GPIO_FN(PWM0_B), GPIO_FN(CS0),
- GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
+ GPIO_FN(CS1_A26),
GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
GPIO_FN(VI1_R7), GPIO_FN(HRTS1),
@@ -2787,19 +2787,19 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VI2_R4), GPIO_FN(VI2_R5),
GPIO_FN(VI2_R6), GPIO_FN(VI2_R7),
GPIO_FN(SCL2_D), GPIO_FN(SDA2_D),
- GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
+ GPIO_FN(VI2_CLKENB),
GPIO_FN(SCL1_D), GPIO_FN(VI2_FIELD),
GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC),
GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC),
GPIO_FN(VI3_VSYNC),
GPIO_FN(VI2_CLK),
- GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
+ GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
GPIO_FN(AUDIO_CLKC), GPIO_FN(SPEEDIN),
GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6),
- GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
+ GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B),
GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
GPIO_FN(VI2_DATA7_VI2_B7),
- GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
+ GPIO_FN(VI1_FIELD),
GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT),
GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
@@ -2828,12 +2828,12 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
- GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C),
+ GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B),
GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
- GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
+ GPIO_FN(SSI_WS9_B), GPIO_FN(SSI_SDATA7),
GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
- GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
- GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C),
+ GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
+ GPIO_FN(IRQ3_B),
GPIO_FN(ATACS01), GPIO_FN(ATACS11),
GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1),
GPIO_FN(CC5_TRST), GPIO_FN(ATAG1),
@@ -2843,15 +2843,15 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(DACK2),
/* IPSR8 */
- GPIO_FN(HSPI_CLK0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
+ GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
- GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0),
+ GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36),
GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
- GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0),
+ GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37),
GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
- GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0),
+ GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38),
GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
@@ -2893,13 +2893,13 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK),
- GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
+ GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
- GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
+ GPIO_FN(ARM_TRACEDATA_15),
GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
- GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
+ GPIO_FN(DREQ2_C), GPIO_FN(TRACECLK),
GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
- GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B),
+ GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C),
GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
@@ -2916,12 +2916,12 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(MT0_BEN),
GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
- GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
+ GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
- GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
+ GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
- GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7),
- GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
+ GPIO_FN(VI1_DATA7_VI1_B7),
+ GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI),
GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0),
GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(SPA_TDO),
GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 120/142] sh-pfc: r8a7779: Remove USB function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (117 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 119/142] sh-pfc: r8a7779: Remove HSPI " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 121/142] sh-pfc: r8a7779: Remove LBSC " Simon Horman
` (22 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All r8a7779 platforms now use the pinctrl API to control the USB pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index ca59a18..6f8cc53 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2677,7 +2677,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(A19),
/* IPSR0 */
- GPIO_FN(USB_PENC2), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
+ GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS),
GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
GPIO_FN(HCTS1), GPIO_FN(A0),
@@ -2802,7 +2802,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VI1_FIELD),
GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT),
GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
- GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
+ GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB),
GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
/* IPSR6 */
@@ -2843,10 +2843,10 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(DACK2),
/* IPSR8 */
- GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
+ GPIO_FN(AD_CLK),
GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36),
- GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
+ GPIO_FN(AD_DI),
GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37),
GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 121/142] sh-pfc: r8a7779: Remove LBSC function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (118 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 120/142] sh-pfc: r8a7779: Remove USB " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 122/142] sh-pfc: r8a7779: Remove INTC " Simon Horman
` (21 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All r8a7779 platforms now use the pinctrl API to control the LBSC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 6f8cc53..5d65499 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2690,22 +2690,20 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SSI_WS78_B), GPIO_FN(A25),
GPIO_FN(FD5), GPIO_FN(VI1_R3),
GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT),
- GPIO_FN(PWM0_B), GPIO_FN(CS0),
- GPIO_FN(CS1_A26),
+ GPIO_FN(PWM0_B),
GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
GPIO_FN(VI1_R7), GPIO_FN(HRTS1),
/* IPSR1 */
- GPIO_FN(EX_CS0),
- GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(FD7),
- GPIO_FN(EX_CS2), GPIO_FN(FALE),
- GPIO_FN(ATACS00), GPIO_FN(EX_CS3),
+ GPIO_FN(FD6), GPIO_FN(FD7),
+ GPIO_FN(FALE),
+ GPIO_FN(ATACS00),
GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4),
GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B),
- GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4),
+ GPIO_FN(SSI_SDATA9),
GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
GPIO_FN(HTX1),
- GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5),
+ GPIO_FN(SSI_SCK9),
GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
GPIO_FN(HRX1), GPIO_FN(SSI_WS9),
GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(MLB_SIG),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 122/142] sh-pfc: r8a7779: Remove INTC function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (119 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 121/142] sh-pfc: r8a7779: Remove LBSC " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:06 ` [PATCH 123/142] ARM: shmobile: sh7372: Remove SDHI and MMCIF function GPIOs Simon Horman
` (20 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
All r8a7779 platforms now use the pinctrl API to control the INTC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 5d65499..1d7b0df 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -2826,12 +2826,11 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
- GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B),
- GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
+ GPIO_FN(SSI_SCK9_B),
+ GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14),
GPIO_FN(SSI_WS9_B), GPIO_FN(SSI_SDATA7),
- GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
+ GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(TCLK1_C),
GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
- GPIO_FN(IRQ3_B),
GPIO_FN(ATACS01), GPIO_FN(ATACS11),
GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1),
GPIO_FN(CC5_TRST), GPIO_FN(ATAG1),
@@ -2870,8 +2869,8 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(VI0_DATA6_VI0_B6),
GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
- GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2),
- GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1),
+ GPIO_FN(SSI_SCK78_C), GPIO_FN(ARM_TRACEDATA_2),
+ GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C),
GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV),
@@ -2887,9 +2886,9 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
- GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(IRQ2),
+ GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK),
GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
- GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
+ GPIO_FN(ARM_TRACEDATA_13),
GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK),
GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 123/142] ARM: shmobile: sh7372: Remove SDHI and MMCIF function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (120 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 122/142] sh-pfc: r8a7779: Remove INTC " Simon Horman
@ 2013-03-18 11:06 ` Simon Horman
2013-03-18 11:07 ` [PATCH 124/142] ARM: shmobile: sh73a0: Remove LCDC and LCDC2 " Simon Horman
` (19 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/sh7372.h | 29 --------------------------
1 file changed, 29 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index b582fac..7ded4eb 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -294,21 +294,6 @@ enum {
GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14,
GPIO_FN_D15_NAF15,
- /*
- * MMCIF(1) (PORT 84, 85, 86, 87, 88, 89,
- * 90, 91, 92, 99)
- */
- GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2,
- GPIO_FN_MMCD0_3, GPIO_FN_MMCD0_4, GPIO_FN_MMCD0_5,
- GPIO_FN_MMCD0_6, GPIO_FN_MMCD0_7,
- GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0,
-
- /* MMCIF(2) (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */
- GPIO_FN_MMCD1_0, GPIO_FN_MMCD1_1, GPIO_FN_MMCD1_2,
- GPIO_FN_MMCD1_3, GPIO_FN_MMCD1_4, GPIO_FN_MMCD1_5,
- GPIO_FN_MMCD1_6, GPIO_FN_MMCD1_7,
- GPIO_FN_MMCCLK1, GPIO_FN_MMCCMD1,
-
/* SPU2 (PORT 65) */
GPIO_FN_VINT_I,
@@ -416,20 +401,6 @@ enum {
/* HDMI (PORT 169, 170) */
GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC,
- /* SDHI0 (PORT 171, 172, 173, 174, 175, 176, 177, 178) */
- GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0,
- GPIO_FN_SDHICMD0, GPIO_FN_SDHIWP0,
- GPIO_FN_SDHID0_0, GPIO_FN_SDHID0_1,
- GPIO_FN_SDHID0_2, GPIO_FN_SDHID0_3,
-
- /* SDHI1 (PORT 179, 180, 181, 182, 183, 184) */
- GPIO_FN_SDHICLK1, GPIO_FN_SDHICMD1, GPIO_FN_SDHID1_0,
- GPIO_FN_SDHID1_1, GPIO_FN_SDHID1_2, GPIO_FN_SDHID1_3,
-
- /* SDHI2 (PORT 185, 186, 187, 188, 189, 190) */
- GPIO_FN_SDHICLK2, GPIO_FN_SDHICMD2, GPIO_FN_SDHID2_0,
- GPIO_FN_SDHID2_1, GPIO_FN_SDHID2_2, GPIO_FN_SDHID2_3,
-
/* SDENC see MSEL4CR 19 */
GPIO_FN_SDENC_CPG,
GPIO_FN_SDENC_DV_CLKI,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 124/142] ARM: shmobile: sh73a0: Remove LCDC and LCDC2 function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (121 preceding siblings ...)
2013-03-18 11:06 ` [PATCH 123/142] ARM: shmobile: sh7372: Remove SDHI and MMCIF function GPIOs Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 125/142] ARM: shmobile: sh73a0: Remove SCIFA and SCIFB " Simon Horman
` (18 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/sh73a0.h | 112 +++++++++++---------------
1 file changed, 49 insertions(+), 63 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 4dca135..a7b7a3c 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -218,38 +218,33 @@ enum {
GPIO_FN_PORT116_I2C_SDA3,
GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
GPIO_FN_HSI_TX_FLAG,
- GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
- GPIO_FN_LCD2D0,
+ GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD,
- GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
- GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
- GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
+ GPIO_FN_VIO_HD,
+ GPIO_FN_VIO2_HD,
+ GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD,
GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
- GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
+ GPIO_FN_PORT131_KEYOUT11,
GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
- GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
- GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
- GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
- GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
- GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
- GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
+ GPIO_FN_PORT132_KEYOUT10,
+ GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC,
+ GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD,
+ GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK,
+ GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8,
+ GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9,
GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
- GPIO_FN_LCD2D6,
GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
- GPIO_FN_LCD2D7,
- GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
- GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
+ GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2,
+ GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3,
GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
- GPIO_FN_LCD2D2,
GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
- GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
+ GPIO_FN_VIO2_D5,
GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
- GPIO_FN_LCD2D4,
- GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
- GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
- GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
- GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
- GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+ GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3,
+ GPIO_FN_VIO2_D7,
+ GPIO_FN_VIO_CLK,
+ GPIO_FN_VIO2_CLK,
+ GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD,
GPIO_FN_VIO_CKO,
GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
GPIO_FN_PORT149_KEYOUT9,
@@ -268,45 +263,38 @@ enum {
GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
GPIO_FN_TPU3TO0,
- GPIO_FN_LCDD0,
- GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
- GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
- GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
- GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
- GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+ GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
+ GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
+ GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
+ GPIO_FN_PORT196_SCIFA5_TXD,
+ GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2,
GPIO_FN_TPU2TO1,
- GPIO_FN_LCDD6,
- GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
- GPIO_FN_LCDD8, GPIO_FN_D16,
- GPIO_FN_LCDD9, GPIO_FN_D17,
- GPIO_FN_LCDD10, GPIO_FN_D18,
- GPIO_FN_LCDD11, GPIO_FN_D19,
- GPIO_FN_LCDD12, GPIO_FN_D20,
- GPIO_FN_LCDD13, GPIO_FN_D21,
- GPIO_FN_LCDD14, GPIO_FN_D22,
- GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
- GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
- GPIO_FN_LCDD17, GPIO_FN_D25,
- GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
- GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
- GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
- GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
- GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
- GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
- GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
- GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
- GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
- GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+ GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+ GPIO_FN_D16,
+ GPIO_FN_D17,
+ GPIO_FN_D18,
+ GPIO_FN_D19,
+ GPIO_FN_D20,
+ GPIO_FN_D21,
+ GPIO_FN_D22,
+ GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+ GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+ GPIO_FN_D25,
+ GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+ GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+ GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+ GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+ GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+ GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+ GPIO_FN_DACK2,
+ GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3,
+ GPIO_FN_DACK3,
GPIO_FN_PORT218_VIO_CKOR,
- GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
- GPIO_FN_LCD2DCK_2,
- GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
- GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+ GPIO_FN_DREQ1,
GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
- GPIO_FN_PORT221_LCD2HSYN,
- GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
- GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
+ GPIO_FN_DACK1, GPIO_FN_OVCN,
+ GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3,
GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
@@ -318,13 +306,11 @@ enum {
GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
- GPIO_FN_LCD2D20,
GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
- GPIO_FN_LCD2D21,
GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
- GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
- GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
+ GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
+ GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
GPIO_FN_SCIFA6_TXD,
GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
GPIO_FN_TPU4TO0,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 125/142] ARM: shmobile: sh73a0: Remove SCIFA and SCIFB function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (122 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 124/142] ARM: shmobile: sh73a0: Remove LCDC and LCDC2 " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 126/142] ARM: shmobile: sh73a0: Remove I2C " Simon Horman
` (17 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/sh73a0.h | 90 +++++++++++---------------
1 file changed, 37 insertions(+), 53 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index a7b7a3c..b843cd7 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -103,15 +103,11 @@ enum {
GPIO_FN_GPI5,
GPIO_FN_GPI6,
GPIO_FN_GPI7,
- GPIO_FN_SCIFA7_RXD,
- GPIO_FN_SCIFA7_CTS_,
GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
- GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+ GPIO_FN_GPO5, GPIO_FN_FSICOSLDT3,
GPIO_FN_PORT16_VIO_CKOR,
- GPIO_FN_SCIFA0_TXD,
- GPIO_FN_SCIFA7_TXD,
- GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+ GPIO_FN_PORT19_VIO_CKO2,
GPIO_FN_GPO0,
GPIO_FN_GPO1,
GPIO_FN_GPO2, GPIO_FN_STATUS0,
@@ -126,19 +122,15 @@ enum {
GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
- GPIO_FN_SCIFA4_TXD,
- GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
- GPIO_FN_SCIFA4_RTS_,
- GPIO_FN_SCIFA4_CTS_,
+ GPIO_FN_XWUP,
GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
GPIO_FN_FSIBOSLD,
GPIO_FN_FSIBISLD,
GPIO_FN_VACK,
GPIO_FN_XTAL1L,
- GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
- GPIO_FN_SCIFA0_RXD,
- GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
+ GPIO_FN_FSICOSLDT2,
+ GPIO_FN_FSICOSLDT1,
GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
@@ -204,10 +196,9 @@ enum {
GPIO_FN_BBIF2_RXD,
GPIO_FN_BBIF2_SYNC,
GPIO_FN_BBIF2_SCK,
- GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
- GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
- GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
- GPIO_FN_SCIFA3_TXD,
+ GPIO_FN_MFG3_IN2,
+ GPIO_FN_MFG3_IN1,
+ GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1,
GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
@@ -252,22 +243,17 @@ enum {
GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
- GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
- GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
- GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
- GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
- GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
- GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
- GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
- GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
- GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
- GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+ GPIO_FN_MSIOF2_MCK0,
+ GPIO_FN_MSIOF2_MCK1,
+ GPIO_FN_PORT156_MSIOF2_SS2,
+ GPIO_FN_PORT157_MSIOF2_RXD,
+ GPIO_FN_DINT_, GPIO_FN_TS_SCK3,
+ GPIO_FN_NMI,
GPIO_FN_TPU3TO0,
- GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
- GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
- GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
- GPIO_FN_PORT196_SCIFA5_TXD,
- GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2,
+ GPIO_FN_BBIF2_TSYNC1,
+ GPIO_FN_BBIF2_TSCK1,
+ GPIO_FN_BBIF2_TXD1,
+ GPIO_FN_MFG2_OUT2,
GPIO_FN_TPU2TO1,
GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
GPIO_FN_D16,
@@ -296,36 +282,34 @@ enum {
GPIO_FN_DACK1, GPIO_FN_OVCN,
GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3,
- GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
- GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
- GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
- GPIO_FN_SCIFA1_RXD,
- GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
- GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
- GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
- GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
- GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
- GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
+ GPIO_FN_OVCN2,
+ GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2,
+ GPIO_FN_IDIN,
+ GPIO_FN_MFG1_IN1,
+ GPIO_FN_MSIOF1_TXD,
+ GPIO_FN_MSIOF1_TSYNC,
+ GPIO_FN_MSIOF1_TSCK,
+ GPIO_FN_MSIOF1_RXD,
+ GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2,
GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
- GPIO_FN_SCIFA6_TXD,
GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
GPIO_FN_TPU4TO0,
GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
- GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
- GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
- GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
- GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
- GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
- GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
- GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
- GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
- GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
- GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
+ GPIO_FN_MFG2_IN1,
+ GPIO_FN_MSIOF2R_RXD,
+ GPIO_FN_MFG2_IN2,
+ GPIO_FN_MSIOF2R_TXD,
+ GPIO_FN_MFG1_OUT1,
+ GPIO_FN_TPU1TO0,
+ GPIO_FN_MFG3_OUT2,
+ GPIO_FN_TPU3TO1,
+ GPIO_FN_MFG2_OUT1,
+ GPIO_FN_TPU2TO0,
GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 126/142] ARM: shmobile: sh73a0: Remove I2C function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (123 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 125/142] ARM: shmobile: sh73a0: Remove SCIFA and SCIFB " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 127/142] ARM: shmobile: sh73a0: Remove FSI " Simon Horman
` (16 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/sh73a0.h | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index b843cd7..3d7950c 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -115,9 +115,9 @@ enum {
GPIO_FN_GPO4, GPIO_FN_STATUS2,
GPIO_FN_VINT,
GPIO_FN_TCKON,
- GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+ GPIO_FN_XDVFS1,
GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
- GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+ GPIO_FN_XDVFS2,
GPIO_FN_PORT28_TPU1TO1,
GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
@@ -203,10 +203,8 @@ enum {
GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
- GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
- GPIO_FN_PORT115_I2C_SCL3,
- GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
- GPIO_FN_PORT116_I2C_SDA3,
+ GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK,
+ GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC,
GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
GPIO_FN_HSI_TX_FLAG,
GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD,
@@ -292,8 +290,8 @@ enum {
GPIO_FN_MSIOF1_RXD,
GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2,
GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
- GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
- GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
+ GPIO_FN_MSIOF1_MCK0,
+ GPIO_FN_MSIOF1_MCK1,
GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
@@ -310,9 +308,9 @@ enum {
GPIO_FN_TPU3TO1,
GPIO_FN_MFG2_OUT1,
GPIO_FN_TPU2TO0,
- GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+ GPIO_FN_MSIOF2R_TSCK,
GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
- GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+ GPIO_FN_MSIOF2R_TSYNC,
GPIO_FN_SDHICLK0,
GPIO_FN_SDHICD0,
GPIO_FN_SDHID0_0,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 127/142] ARM: shmobile: sh73a0: Remove FSI function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (124 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 126/142] ARM: shmobile: sh73a0: Remove I2C " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 128/142] ARM: shmobile: sh73a0: Remove pull-up function GPIOS Simon Horman
` (15 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/sh73a0.h | 31 ++++++++------------------
1 file changed, 9 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 3d7950c..563a48d 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -105,7 +105,7 @@ enum {
GPIO_FN_GPI7,
GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
- GPIO_FN_GPO5, GPIO_FN_FSICOSLDT3,
+ GPIO_FN_GPO5,
GPIO_FN_PORT16_VIO_CKOR,
GPIO_FN_PORT19_VIO_CKO2,
GPIO_FN_GPO0,
@@ -123,29 +123,16 @@ enum {
GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
GPIO_FN_XWUP,
- GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
- GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
- GPIO_FN_FSIBOSLD,
- GPIO_FN_FSIBISLD,
GPIO_FN_VACK,
GPIO_FN_XTAL1L,
- GPIO_FN_FSICOSLDT2,
- GPIO_FN_FSICOSLDT1,
- GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
- GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
- GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
- GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
- GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
- GPIO_FN_FSIAOMC,
- GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
-
- GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
- GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
- GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
- GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
- GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
- GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
- GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+ GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT,
+ GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2,
+
+ GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3,
+ GPIO_FN_BBIF2_TXD2,
+ GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3,
+ GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2,
+ GPIO_FN_TPU0TO0,
GPIO_FN_A0, GPIO_FN_BS_,
GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 128/142] ARM: shmobile: sh73a0: Remove pull-up function GPIOS
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (125 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 127/142] ARM: shmobile: sh73a0: Remove FSI " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 129/142] ARM: shmobile: sh73a0: Remove KEYSC function GPIOs Simon Horman
` (14 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinconf API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/sh73a0.h | 41 --------------------------
1 file changed, 41 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 563a48d..5b9620e 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -397,47 +397,6 @@ enum {
GPIO_FN_EDBGREQ_PD,
GPIO_FN_EDBGREQ_PU,
- /* Functions with pull-ups */
- GPIO_FN_KEYIN0_PU,
- GPIO_FN_KEYIN1_PU,
- GPIO_FN_KEYIN2_PU,
- GPIO_FN_KEYIN3_PU,
- GPIO_FN_KEYIN4_PU,
- GPIO_FN_KEYIN5_PU,
- GPIO_FN_KEYIN6_PU,
- GPIO_FN_KEYIN7_PU,
- GPIO_FN_SDHICD0_PU,
- GPIO_FN_SDHID0_0_PU,
- GPIO_FN_SDHID0_1_PU,
- GPIO_FN_SDHID0_2_PU,
- GPIO_FN_SDHID0_3_PU,
- GPIO_FN_SDHICMD0_PU,
- GPIO_FN_SDHIWP0_PU,
- GPIO_FN_SDHID1_0_PU,
- GPIO_FN_SDHID1_1_PU,
- GPIO_FN_SDHID1_2_PU,
- GPIO_FN_SDHID1_3_PU,
- GPIO_FN_SDHICMD1_PU,
- GPIO_FN_SDHID2_0_PU,
- GPIO_FN_SDHID2_1_PU,
- GPIO_FN_SDHID2_2_PU,
- GPIO_FN_SDHID2_3_PU,
- GPIO_FN_SDHICMD2_PU,
- GPIO_FN_MMCCMD0_PU,
- GPIO_FN_MMCCMD1_PU,
- GPIO_FN_MMCD0_0_PU,
- GPIO_FN_MMCD0_1_PU,
- GPIO_FN_MMCD0_2_PU,
- GPIO_FN_MMCD0_3_PU,
- GPIO_FN_MMCD0_4_PU,
- GPIO_FN_MMCD0_5_PU,
- GPIO_FN_MMCD0_6_PU,
- GPIO_FN_MMCD0_7_PU,
- GPIO_FN_FSIACK_PU,
- GPIO_FN_FSIAILR_PU,
- GPIO_FN_FSIAIBT_PU,
- GPIO_FN_FSIAISLD_PU,
-
/* end of GPIO */
GPIO_NR,
};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 129/142] ARM: shmobile: sh73a0: Remove KEYSC function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (126 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 128/142] ARM: shmobile: sh73a0: Remove pull-up function GPIOS Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 130/142] ARM: shmobile: sh73a0: Remove BSC " Simon Horman
` (13 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/sh73a0.h | 53 ++++++++++++--------------
1 file changed, 24 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 5b9620e..f1b85ff 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -134,22 +134,21 @@ enum {
GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2,
GPIO_FN_TPU0TO0,
GPIO_FN_A0, GPIO_FN_BS_,
- GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
- GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
- GPIO_FN_A14, GPIO_FN_KEYOUT5,
- GPIO_FN_A15, GPIO_FN_KEYOUT4,
- GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
- GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
- GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
- GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
- GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
- GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
- GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
- GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
- GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
- GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
- GPIO_FN_A26, GPIO_FN_KEYIN6,
- GPIO_FN_KEYIN7,
+ GPIO_FN_A12, GPIO_FN_TPU4TO2,
+ GPIO_FN_A13, GPIO_FN_TPU0TO1,
+ GPIO_FN_A14,
+ GPIO_FN_A15,
+ GPIO_FN_A16, GPIO_FN_MSIOF0_SS1,
+ GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC,
+ GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK,
+ GPIO_FN_A19, GPIO_FN_MSIOF0_TXD,
+ GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK,
+ GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC,
+ GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0,
+ GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1,
+ GPIO_FN_A24, GPIO_FN_MSIOF0_RXD,
+ GPIO_FN_A25, GPIO_FN_MSIOF0_SS2,
+ GPIO_FN_A26,
GPIO_FN_D0_NAF0,
GPIO_FN_D1_NAF1,
GPIO_FN_D2_NAF2,
@@ -199,23 +198,21 @@ enum {
GPIO_FN_VIO_HD,
GPIO_FN_VIO2_HD,
GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD,
- GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
- GPIO_FN_PORT131_KEYOUT11,
- GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
- GPIO_FN_PORT132_KEYOUT10,
+ GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1,
+ GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2,
GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC,
GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD,
GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK,
- GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8,
- GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9,
- GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
- GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
+ GPIO_FN_VIO_D6,
+ GPIO_FN_VIO_D7,
+ GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0,
+ GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1,
GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2,
GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3,
- GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
- GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
+ GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4,
+ GPIO_FN_VIO_D13,
GPIO_FN_VIO2_D5,
- GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
+ GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6,
GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3,
GPIO_FN_VIO2_D7,
GPIO_FN_VIO_CLK,
@@ -223,7 +220,6 @@ enum {
GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD,
GPIO_FN_VIO_CKO,
GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
- GPIO_FN_PORT149_KEYOUT9,
GPIO_FN_MFG0_IN2,
GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
@@ -390,7 +386,6 @@ enum {
GPIO_FN_IRQ9_MEM_INT,
GPIO_FN_IRQ9_MCP_INT,
GPIO_FN_A11,
- GPIO_FN_KEYOUT8,
GPIO_FN_TPU4TO3,
GPIO_FN_RESETA_N_PU_ON,
GPIO_FN_RESETA_N_PU_OFF,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 130/142] ARM: shmobile: sh73a0: Remove BSC function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (127 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 129/142] ARM: shmobile: sh73a0: Remove KEYSC function GPIOs Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 131/142] ARM: shmobile: sh73a0: Remove USB " Simon Horman
` (12 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/sh73a0.h | 29 ++++----------------------
1 file changed, 4 insertions(+), 25 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index f1b85ff..218e6b7 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -149,31 +149,10 @@ enum {
GPIO_FN_A24, GPIO_FN_MSIOF0_RXD,
GPIO_FN_A25, GPIO_FN_MSIOF0_SS2,
GPIO_FN_A26,
- GPIO_FN_D0_NAF0,
- GPIO_FN_D1_NAF1,
- GPIO_FN_D2_NAF2,
- GPIO_FN_D3_NAF3,
- GPIO_FN_D4_NAF4,
- GPIO_FN_D5_NAF5,
- GPIO_FN_D6_NAF6,
- GPIO_FN_D7_NAF7,
- GPIO_FN_D8_NAF8,
- GPIO_FN_D9_NAF9,
- GPIO_FN_D10_NAF10,
- GPIO_FN_D11_NAF11,
- GPIO_FN_D12_NAF12,
- GPIO_FN_D13_NAF13,
- GPIO_FN_D14_NAF14,
- GPIO_FN_D15_NAF15,
- GPIO_FN_CS4_,
- GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
- GPIO_FN_CS5B_, GPIO_FN_FCE1_,
- GPIO_FN_CS6B_, GPIO_FN_DACK0,
- GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+ GPIO_FN_FCE1_,
+ GPIO_FN_DACK0,
+ GPIO_FN_FCE0_,
GPIO_FN_WAIT_, GPIO_FN_DREQ0,
- GPIO_FN_RD__FSC,
- GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
- GPIO_FN_WE1_,
GPIO_FN_FRB,
GPIO_FN_CKO,
GPIO_FN_NBRSTOUT_,
@@ -219,7 +198,7 @@ enum {
GPIO_FN_VIO2_CLK,
GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD,
GPIO_FN_VIO_CKO,
- GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
+ GPIO_FN_A27, GPIO_FN_MFG0_IN1,
GPIO_FN_MFG0_IN2,
GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 131/142] ARM: shmobile: sh73a0: Remove USB function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (128 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 130/142] ARM: shmobile: sh73a0: Remove BSC " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 132/142] ARM: shmobile: sh73a0: Remove IrDA " Simon Horman
` (11 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/sh73a0.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 218e6b7..d488e2b 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -94,8 +94,7 @@ enum {
GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
/* Table 25-1 (Function 0-7) */
- GPIO_FN_VBUS_0 = 310,
- GPIO_FN_GPI0,
+ GPIO_FN_GPI0 = 310,
GPIO_FN_GPI1,
GPIO_FN_GPI2,
GPIO_FN_GPI3,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 132/142] ARM: shmobile: sh73a0: Remove IrDA function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (129 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 131/142] ARM: shmobile: sh73a0: Remove USB " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 133/142] ARM: shmobile: r8a7740: Remove LCD0 and LCD1 " Simon Horman
` (10 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/sh73a0.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index d488e2b..fbc1584 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -124,13 +124,13 @@ enum {
GPIO_FN_XWUP,
GPIO_FN_VACK,
GPIO_FN_XTAL1L,
- GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT,
+ GPIO_FN_PORT49_IROUT,
GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2,
GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3,
GPIO_FN_BBIF2_TXD2,
- GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3,
- GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2,
+ GPIO_FN_TPU3TO3,
+ GPIO_FN_TPU3TO2,
GPIO_FN_TPU0TO0,
GPIO_FN_A0, GPIO_FN_BS_,
GPIO_FN_A12, GPIO_FN_TPU4TO2,
@@ -255,10 +255,10 @@ enum {
GPIO_FN_MSIOF1_MCK1,
GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
- GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+ GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
GPIO_FN_TPU4TO0,
- GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
- GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
+ GPIO_FN_MFG4_IN2,
+ GPIO_FN_PORT243_VIO_CKO2,
GPIO_FN_MFG2_IN1,
GPIO_FN_MSIOF2R_RXD,
GPIO_FN_MFG2_IN2,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 133/142] ARM: shmobile: r8a7740: Remove LCD0 and LCD1 function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (130 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 132/142] ARM: shmobile: sh73a0: Remove IrDA " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 134/142] ARM: shmobile: r8a7740: Remove SDHI and MMCIF " Simon Horman
` (9 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/r8a7740.h | 39 -------------------------
1 file changed, 39 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 59d252f..0c417da 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -241,48 +241,9 @@ enum {
/* LCD0 */
GPIO_FN_LCDC0_SELECT,
- GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
- GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
- GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
- GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
- GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
- GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
- GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
-
- GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
- GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
-
- GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
- GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
-
- GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
- GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
- GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
- GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
-
- GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
- GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
- GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
- GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
/* LCD1 */
GPIO_FN_LCDC1_SELECT,
- GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
- GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
- GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
- GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
- GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
- GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
- GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
- GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
- GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
- GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
-
- GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
- GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
-
- GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
- GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
/* RSPI */
GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 134/142] ARM: shmobile: r8a7740: Remove SDHI and MMCIF function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (131 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 133/142] ARM: shmobile: r8a7740: Remove LCD0 and LCD1 " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 135/142] ARM: shmobile: r8a7779: Remove DU1_DOTCLKOUT1 GPIO Simon Horman
` (8 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/r8a7740.h | 35 -------------------------
1 file changed, 35 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 0c417da..c258361 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -307,26 +307,6 @@ enum {
GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
GPIO_FN_SIM_D_PORT199,
- /* SDHI0 */
- GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
- GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
- GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
-
- /* SDHI1 */
- GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
- GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
- GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
-
- /* SDHI2 */
- GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
- GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
-
- GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
- GPIO_FN_SDHI2_WP_PORT25,
-
- GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
- GPIO_FN_SDHI2_CD_PORT202,
-
/* MSIOF2 */
GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
@@ -378,21 +358,6 @@ enum {
GPIO_FN_MEMC_DREQ1,
GPIO_FN_MEMC_A0,
- /* MMC */
- GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
- GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
- GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
- GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
- GPIO_FN_MMC0_CLK_PORT66,
- GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
-
- GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
- GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
- GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
- GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
- GPIO_FN_MMC1_CLK_PORT103,
- GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
-
/* MSIOF0 */
GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 135/142] ARM: shmobile: r8a7779: Remove DU1_DOTCLKOUT1 GPIO
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (132 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 134/142] ARM: shmobile: r8a7740: Remove SDHI and MMCIF " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 136/142] ARM: shmobile: r8a7779: Remove DU function GPIOs Simon Horman
` (7 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The function is not documented in the r8a7779 datasheet. Remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/r8a7779.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 8ab0cd6..badba57 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -308,7 +308,7 @@ enum {
GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
- GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
+ GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
GPIO_FN_HRTS0_B,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 136/142] ARM: shmobile: r8a7779: Remove DU function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (133 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 135/142] ARM: shmobile: r8a7779: Remove DU1_DOTCLKOUT1 GPIO Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 137/142] ARM: shmobile: r8a7779: Remove SDHI and MMCIF " Simon Horman
` (6 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/r8a7779.h | 88 ++++++++++++-------------
1 file changed, 44 insertions(+), 44 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index badba57..c25f66b 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -119,76 +119,76 @@ enum {
GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
- GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
+ GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33,
GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
- GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
+ GPIO_FN_TX5_C, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
- GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
- GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
- GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
- GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
+ GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3,
+ GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5,
+ GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7,
+ GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
GPIO_FN_AUDATA2,
/* IPSR3 */
- GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
- GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
- GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
- GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
- GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
- GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
+ GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
+ GPIO_FN_AUDATA3, GPIO_FN_LCDOUT10,
+ GPIO_FN_LCDOUT11, GPIO_FN_LCDOUT12,
+ GPIO_FN_LCDOUT13, GPIO_FN_LCDOUT14,
+ GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
+ GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4,
GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
- GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
- GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
- GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
- GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
+ GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_LCDOUT18,
+ GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20,
+ GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22,
+ GPIO_FN_LCDOUT23,
GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
- GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
+ GPIO_FN_QCLK,
GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
- GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
- GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
- GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
+ GPIO_FN_QSTH_QHS,
+ GPIO_FN_QSTB_QHE,
+ GPIO_FN_QCPV_QDE,
GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
/* IPSR4 */
- GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
- GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
- GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
+ GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
+ GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
+ GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B,
GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
- GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
+ GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
- GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
- GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
- GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
- GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
+ GPIO_FN_CTS0_D, GPIO_FN_VI2_G0,
+ GPIO_FN_VI2_G1, GPIO_FN_VI2_G2,
+ GPIO_FN_VI2_G3, GPIO_FN_VI2_G4,
+ GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2,
GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
- GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
+ GPIO_FN_TX0_D, GPIO_FN_VI2_DATA3_VI2_B3,
GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
- GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
- GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
- GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
- GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
+ GPIO_FN_RX0_D, GPIO_FN_VI2_G6,
+ GPIO_FN_VI2_G7, GPIO_FN_VI2_R0,
+ GPIO_FN_VI2_R1, GPIO_FN_VI2_R2,
+ GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4,
GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
/* IPSR5 */
- GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
+ GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
- GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
- GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
- GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
- GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
- GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
- GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
- GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
- GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+ GPIO_FN_VI2_R4, GPIO_FN_VI2_R5,
+ GPIO_FN_VI2_R6, GPIO_FN_VI2_R7,
+ GPIO_FN_SCL2_D, GPIO_FN_SDA2_D,
+ GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
+ GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD,
+ GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC,
+ GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC,
+ GPIO_FN_VI3_VSYNC,
GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
- GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
+ GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6,
GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
- GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
+ GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 137/142] ARM: shmobile: r8a7779: Remove SDHI and MMCIF function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (134 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 136/142] ARM: shmobile: r8a7779: Remove DU function GPIOs Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 138/142] ARM: shmobile: r8a7779: Remove SCIF " Simon Horman
` (5 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/r8a7779.h | 104 ++++++++++++-------------
1 file changed, 52 insertions(+), 52 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index c25f66b..11fdb1b 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -72,16 +72,16 @@ enum {
/* IPSR0 */
GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
- GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
- GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
- GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
- GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
+ GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS,
+ GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
+ GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0,
+ GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
- GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
+ GPIO_FN_A24, GPIO_FN_FD4,
GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
- GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
+ GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
@@ -89,16 +89,16 @@ enum {
GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
/* IPSR1 */
- GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
- GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
- GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
- GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
+ GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C,
+ GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_FD7,
+ GPIO_FN_EX_CS2, GPIO_FN_FALE,
+ GPIO_FN_ATACS00, GPIO_FN_EX_CS3,
GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
- GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
+ GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4,
GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
- GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
+ GPIO_FN_EX_CS5, GPIO_FN_FD1,
GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
@@ -154,26 +154,26 @@ enum {
GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B,
- GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
+ GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6,
GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
- GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
+ GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
GPIO_FN_CTS0_D, GPIO_FN_VI2_G0,
GPIO_FN_VI2_G1, GPIO_FN_VI2_G2,
GPIO_FN_VI2_G3, GPIO_FN_VI2_G4,
GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2,
- GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
+ GPIO_FN_SCL1_B, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
GPIO_FN_TX0_D, GPIO_FN_VI2_DATA3_VI2_B3,
- GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
+ GPIO_FN_SDA1_B, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
GPIO_FN_RX0_D, GPIO_FN_VI2_G6,
GPIO_FN_VI2_G7, GPIO_FN_VI2_R0,
GPIO_FN_VI2_R1, GPIO_FN_VI2_R2,
GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4,
- GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
+ GPIO_FN_SCL2_B, GPIO_FN_TX5, GPIO_FN_SCK0_D,
/* IPSR5 */
GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
- GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
+ GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
GPIO_FN_VI2_R4, GPIO_FN_VI2_R5,
GPIO_FN_VI2_R6, GPIO_FN_VI2_R7,
GPIO_FN_SCL2_D, GPIO_FN_SDA2_D,
@@ -182,14 +182,14 @@ enum {
GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC,
GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC,
GPIO_FN_VI3_VSYNC,
- GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
+ GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B,
GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6,
GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
- GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
+ GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
@@ -222,13 +222,13 @@ enum {
GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
- GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
- GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
- GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
- GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
- GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
- GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
- GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
+ GPIO_FN_ATACS01, GPIO_FN_SCK1_B,
+ GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO,
+ GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST,
+ GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS,
+ GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK,
+ GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI,
+ GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_DACK2,
GPIO_FN_CTS1_B,
/* IPSR8 */
@@ -245,44 +245,44 @@ enum {
GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
- GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
+ GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
- GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
+ GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_HSCK1_B,
GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
/* IPSR9 */
GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
- GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
- GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
- GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
- GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
- GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
+ GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_VI0_DATA3_VI0_B3,
+ GPIO_FN_VI0_DATA4_VI0_B4,
+ GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6,
+ GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
+ GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
- GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
- GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
+ GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
+ GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV,
GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
- GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
- GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
+ GPIO_FN_ETH_TX_EN, GPIO_FN_ARM_TRACEDATA_6,
+ GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER,
GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
- GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
- GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
+ GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
+ GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9,
/* IPSR10 */
GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
- GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
- GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
+ GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
+ GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_IRQ3,
GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
- GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
+ GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
- GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
+ GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
@@ -294,19 +294,19 @@ enum {
GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
/* IPSR11 */
- GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
+ GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SIM_RST,
GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
- GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
- GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
+ GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
+ GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2,
GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
- GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
+ GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN,
GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
- GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
+ GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
- GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
+ GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
- GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
- GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
+ GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
+ GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM,
GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 138/142] ARM: shmobile: r8a7779: Remove SCIF function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (135 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 137/142] ARM: shmobile: r8a7779: Remove SDHI and MMCIF " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 139/142] ARM: shmobile: r8a7779: Remove HSPI " Simon Horman
` (4 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/r8a7779.h | 144 ++++++++++++-------------
1 file changed, 71 insertions(+), 73 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 11fdb1b..e901316 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -71,58 +71,58 @@ enum {
GPIO_FN_A19,
/* IPSR0 */
- GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
+ GPIO_FN_USB_PENC2, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS,
GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
- GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0,
- GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
- GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
- GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
+ GPIO_FN_HCTS1, GPIO_FN_A0,
+ GPIO_FN_FD3, GPIO_FN_A20,
+ GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_HSPI_CLK2_B,
+ GPIO_FN_A22, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
GPIO_FN_A24, GPIO_FN_FD4,
GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
- GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
- GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
+ GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B,
+ GPIO_FN_CLKOUT, GPIO_FN_PWM0_B, GPIO_FN_CS0,
GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
- GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
+ GPIO_FN_VI1_R7, GPIO_FN_HRTS1,
/* IPSR1 */
- GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C,
+ GPIO_FN_EX_CS0,
GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_FD7,
GPIO_FN_EX_CS2, GPIO_FN_FALE,
GPIO_FN_ATACS00, GPIO_FN_EX_CS3,
- GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
- GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
+ GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4,
+ GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B,
GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4,
- GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
- GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
+ GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5,
+ GPIO_FN_HTX1, GPIO_FN_SSI_SCK9,
GPIO_FN_EX_CS5, GPIO_FN_FD1,
- GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
- GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
- GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
- GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
- GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
+ GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1,
+ GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
+ GPIO_FN_MLB_SIG, GPIO_FN_PWM3,
+ GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_HTX0,
+ GPIO_FN_SDATA, GPIO_FN_SUB_TCK,
GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
/* IPSR2 */
- GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
+ GPIO_FN_HRX0, GPIO_FN_SCKZ,
GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
- GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
- GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
+ GPIO_FN_HSCK0, GPIO_FN_MTS, GPIO_FN_PWM5,
+ GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
- GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
- GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
+ GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0,
+ GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_SCIF_CLK_C,
GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
- GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
+ GPIO_FN_MDATA, GPIO_FN_SUB_TMS,
GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33,
GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
- GPIO_FN_TX5_C, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
- GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
+ GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
+ GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1,
GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3,
GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5,
GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7,
@@ -137,43 +137,42 @@ enum {
GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4,
GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
- GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_LCDOUT18,
+ GPIO_FN_AUDATA5, GPIO_FN_LCDOUT18,
GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20,
GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22,
GPIO_FN_LCDOUT23,
- GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
+ GPIO_FN_QSTVA_QVS, GPIO_FN_SCL3_B,
GPIO_FN_QCLK,
- GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
+ GPIO_FN_QSTVB_QVE, GPIO_FN_SDA3_B,
GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
GPIO_FN_QSTH_QHS,
GPIO_FN_QSTB_QHE,
GPIO_FN_QCPV_QDE,
- GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
+ GPIO_FN_CAN1_TX, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
/* IPSR4 */
- GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
- GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
- GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B,
+ GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C,
+ GPIO_FN_QPOLB, GPIO_FN_CAN1_RX,
+ GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B,
GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6,
- GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
+ GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
- GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
- GPIO_FN_CTS0_D, GPIO_FN_VI2_G0,
+ GPIO_FN_AUDSYNC,
+ GPIO_FN_VI2_G0,
GPIO_FN_VI2_G1, GPIO_FN_VI2_G2,
GPIO_FN_VI2_G3, GPIO_FN_VI2_G4,
GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2,
- GPIO_FN_SCL1_B, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
- GPIO_FN_TX0_D, GPIO_FN_VI2_DATA3_VI2_B3,
- GPIO_FN_SDA1_B, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
- GPIO_FN_RX0_D, GPIO_FN_VI2_G6,
+ GPIO_FN_SCL1_B, GPIO_FN_AUDATA6,
+ GPIO_FN_VI2_DATA3_VI2_B3,
+ GPIO_FN_SDA1_B, GPIO_FN_AUDATA7,
+ GPIO_FN_VI2_G6,
GPIO_FN_VI2_G7, GPIO_FN_VI2_R0,
GPIO_FN_VI2_R1, GPIO_FN_VI2_R2,
GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4,
- GPIO_FN_SCL2_B, GPIO_FN_TX5, GPIO_FN_SCK0_D,
+ GPIO_FN_SCL2_B,
/* IPSR5 */
GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
- GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
GPIO_FN_VI2_R4, GPIO_FN_VI2_R5,
GPIO_FN_VI2_R6, GPIO_FN_VI2_R7,
GPIO_FN_SCL2_D, GPIO_FN_SDA2_D,
@@ -182,15 +181,15 @@ enum {
GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC,
GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC,
GPIO_FN_VI3_VSYNC,
- GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B,
+ GPIO_FN_VI2_CLK,
GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
- GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
+ GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN,
GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6,
GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
- GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
- GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
+ GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
+ GPIO_FN_VI2_DATA7_VI2_B7,
GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
- GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
+ GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C,
GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
GPIO_FN_MOUT0,
@@ -208,9 +207,9 @@ enum {
GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
- GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
- GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
- GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
+ GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
+ GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
+ GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12,
GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
/* IPSR7 */
@@ -222,35 +221,34 @@ enum {
GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
- GPIO_FN_ATACS01, GPIO_FN_SCK1_B,
- GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO,
- GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST,
- GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS,
- GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK,
- GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI,
- GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_DACK2,
- GPIO_FN_CTS1_B,
+ GPIO_FN_ATACS01,
+ GPIO_FN_ATACS11, GPIO_FN_CC5_TDO,
+ GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST,
+ GPIO_FN_ATAG1, GPIO_FN_CC5_TMS,
+ GPIO_FN_ATARD1, GPIO_FN_CC5_TCK,
+ GPIO_FN_ATAWR1, GPIO_FN_CC5_TDI,
+ GPIO_FN_DREQ2, GPIO_FN_DACK2,
/* IPSR8 */
- GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
+ GPIO_FN_HSPI_CLK0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
- GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
+ GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
- GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
+ GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
- GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
+ GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
- GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
- GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
+ GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB,
+ GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD,
GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
- GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_HSCK1_B,
+ GPIO_FN_HSCK1_B,
GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
- GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
+ GPIO_FN_PWMFSW0_C,
/* IPSR9 */
GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
@@ -273,7 +271,7 @@ enum {
GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9,
/* IPSR10 */
- GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
+ GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_DREQ1_B,
GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
@@ -308,21 +306,21 @@ enum {
GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM,
GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
- GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
+ GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B,
GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
- GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
+ GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B,
GPIO_FN_HRTS0_B,
/* IPSR12 */
GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
- GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
+ GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
- GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
+ GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_SIM_D_B,
GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
- GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
- GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
+ GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
+ GPIO_FN_GPS_MAG, GPIO_FN_FCE,
};
struct platform_device;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 139/142] ARM: shmobile: r8a7779: Remove HSPI function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (136 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 138/142] ARM: shmobile: r8a7779: Remove SCIF " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 140/142] ARM: shmobile: r8a7779: Remove USB " Simon Horman
` (3 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/r8a7779.h | 52 ++++++++++++-------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index e901316..f3ae551 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -76,15 +76,15 @@ enum {
GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
GPIO_FN_HCTS1, GPIO_FN_A0,
GPIO_FN_FD3, GPIO_FN_A20,
- GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_HSPI_CLK2_B,
- GPIO_FN_A22, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
- GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
+ GPIO_FN_A21,
+ GPIO_FN_A22, GPIO_FN_VI1_R0,
+ GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_VI1_R1,
GPIO_FN_A24, GPIO_FN_FD4,
- GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
- GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
+ GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
+ GPIO_FN_FD5,
GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B,
GPIO_FN_CLKOUT, GPIO_FN_PWM0_B, GPIO_FN_CS0,
- GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
+ GPIO_FN_CS1_A26,
GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
GPIO_FN_VI1_R7, GPIO_FN_HRTS1,
@@ -176,19 +176,19 @@ enum {
GPIO_FN_VI2_R4, GPIO_FN_VI2_R5,
GPIO_FN_VI2_R6, GPIO_FN_VI2_R7,
GPIO_FN_SCL2_D, GPIO_FN_SDA2_D,
- GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
+ GPIO_FN_VI2_CLKENB,
GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD,
GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC,
GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC,
GPIO_FN_VI3_VSYNC,
GPIO_FN_VI2_CLK,
- GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
+ GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN,
GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6,
- GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
+ GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B,
GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
GPIO_FN_VI2_DATA7_VI2_B7,
- GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
+ GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C,
GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
@@ -216,11 +216,11 @@ enum {
GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
- GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
+ GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78,
GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
- GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
- GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
- GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
+ GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
+ GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C,
+ GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B,
GPIO_FN_ATACS01,
GPIO_FN_ATACS11, GPIO_FN_CC5_TDO,
GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST,
@@ -230,15 +230,15 @@ enum {
GPIO_FN_DREQ2, GPIO_FN_DACK2,
/* IPSR8 */
- GPIO_FN_HSPI_CLK0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
+ GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
- GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
+ GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36,
GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
- GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
+ GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37,
GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
- GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
+ GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38,
GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
@@ -278,13 +278,13 @@ enum {
GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_IRQ3,
GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
- GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
+ GPIO_FN_ARM_TRACEDATA_14,
GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
- GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
+ GPIO_FN_ARM_TRACEDATA_15,
GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
- GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
+ GPIO_FN_DREQ2_C, GPIO_FN_TRACECLK,
GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
- GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
+ GPIO_FN_DACK2_C, GPIO_FN_SCIF_CLK_D,
GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
@@ -300,12 +300,12 @@ enum {
GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN,
GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
- GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
+ GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
- GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
- GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
+ GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
+ GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS,
GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM,
- GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
+ GPIO_FN_SPA_TDI, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B,
GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 140/142] ARM: shmobile: r8a7779: Remove USB function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (137 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 139/142] ARM: shmobile: r8a7779: Remove HSPI " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 141/142] ARM: shmobile: r8a7779: Remove LBSC " Simon Horman
` (2 subsequent siblings)
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/r8a7779.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index f3ae551..e50bf53 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -71,7 +71,7 @@ enum {
GPIO_FN_A19,
/* IPSR0 */
- GPIO_FN_USB_PENC2, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
+ GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS,
GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
GPIO_FN_HCTS1, GPIO_FN_A0,
@@ -191,7 +191,7 @@ enum {
GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C,
GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
- GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
+ GPIO_FN_AUDIO_CLKB, GPIO_FN_CAN_DEBUGOUT0,
GPIO_FN_MOUT0,
/* IPSR6 */
@@ -230,10 +230,10 @@ enum {
GPIO_FN_DREQ2, GPIO_FN_DACK2,
/* IPSR8 */
- GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
+ GPIO_FN_AD_CLK,
GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36,
- GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
+ GPIO_FN_AD_DI,
GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37,
GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 141/142] ARM: shmobile: r8a7779: Remove LBSC function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (138 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 140/142] ARM: shmobile: r8a7779: Remove USB " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-18 11:07 ` [PATCH 142/142] ARM: shmobile: r8a7779: Remove INTC " Simon Horman
2013-03-21 16:51 ` [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Arnd Bergmann
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/r8a7779.h | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index e50bf53..688c0d2 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -83,22 +83,20 @@ enum {
GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
GPIO_FN_FD5,
GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B,
- GPIO_FN_CLKOUT, GPIO_FN_PWM0_B, GPIO_FN_CS0,
- GPIO_FN_CS1_A26,
+ GPIO_FN_CLKOUT, GPIO_FN_PWM0_B,
GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
GPIO_FN_VI1_R7, GPIO_FN_HRTS1,
/* IPSR1 */
- GPIO_FN_EX_CS0,
- GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_FD7,
- GPIO_FN_EX_CS2, GPIO_FN_FALE,
- GPIO_FN_ATACS00, GPIO_FN_EX_CS3,
+ GPIO_FN_FD6, GPIO_FN_FD7,
+ GPIO_FN_FALE,
+ GPIO_FN_ATACS00,
GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4,
GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B,
- GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4,
+ GPIO_FN_SSI_SDATA9,
GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5,
GPIO_FN_HTX1, GPIO_FN_SSI_SCK9,
- GPIO_FN_EX_CS5, GPIO_FN_FD1,
+ GPIO_FN_FD1,
GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1,
GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
GPIO_FN_MLB_SIG, GPIO_FN_PWM3,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [PATCH 142/142] ARM: shmobile: r8a7779: Remove INTC function GPIOs
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (139 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 141/142] ARM: shmobile: r8a7779: Remove LBSC " Simon Horman
@ 2013-03-18 11:07 ` Simon Horman
2013-03-21 16:51 ` [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Arnd Bergmann
141 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-18 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/include/mach/r8a7779.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 688c0d2..8ea0ad1 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -213,12 +213,12 @@ enum {
/* IPSR7 */
GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
- GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
+ GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13,
GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78,
- GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
+ GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_WS9_B,
GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
- GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C,
- GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B,
+ GPIO_FN_TCLK1_C,
+ GPIO_FN_SSI_SDATA8, GPIO_FN_VSP,
GPIO_FN_ATACS01,
GPIO_FN_ATACS11, GPIO_FN_CC5_TDO,
GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST,
@@ -256,8 +256,8 @@ enum {
GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6,
GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
- GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
- GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
+ GPIO_FN_SSI_SCK78_C, GPIO_FN_ARM_TRACEDATA_2,
+ GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C,
GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV,
@@ -273,8 +273,8 @@ enum {
GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
- GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
- GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_IRQ3,
+ GPIO_FN_ARM_TRACEDATA_12,
+ GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC,
GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
GPIO_FN_ARM_TRACEDATA_14,
GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 144+ messages in thread* [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10
2013-03-18 11:04 [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Simon Horman
` (140 preceding siblings ...)
2013-03-18 11:07 ` [PATCH 142/142] ARM: shmobile: r8a7779: Remove INTC " Simon Horman
@ 2013-03-21 16:51 ` Arnd Bergmann
2013-03-22 0:48 ` Simon Horman
141 siblings, 1 reply; 144+ messages in thread
From: Arnd Bergmann @ 2013-03-21 16:51 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 18 March 2013, Simon Horman wrote:
> ----------------------------------------------------------------
> Renesas ARM and SH based SoC pinmux update for v3.10
>
> As with changes to the Renesas ARM and SH based SoC pinmux code for v3.9
> it has been agreed by the relevant parties, Linus Walleij, Laurent Pinchart,
> Paul Mundt and myself, that it would be best to take these changes through
> the renesas tree and in turn the arm-soc tree.
>
> This pull is based on a merge of the following in order to provide
> the required dependencies. This base has been discussed and agreed upon by
> Linus Walleij, Laurent Pinchart and myself.
>
> git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl devel
> git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl fixes
> git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas fixes
Pulled, thanks!
I'm a bit overwhelmed by the number of patches and pull requests I got from
you at the same time, so it took a little longer to get an overview of what
you are actually doing.
I've used the next/renesas-pinctrl branch again, keeping this one separate
from the other next/* branches given how many patches there are in here,
and given the dependency on the pinctrl tree.
Arnd
^ permalink raw reply [flat|nested] 144+ messages in thread* [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10
2013-03-21 16:51 ` [GIT PULL] Renesas ARM and SH based SoC pinmux update for v3.10 Arnd Bergmann
@ 2013-03-22 0:48 ` Simon Horman
0 siblings, 0 replies; 144+ messages in thread
From: Simon Horman @ 2013-03-22 0:48 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 21, 2013 at 04:51:47PM +0000, Arnd Bergmann wrote:
> On Monday 18 March 2013, Simon Horman wrote:
>
> > ----------------------------------------------------------------
> > Renesas ARM and SH based SoC pinmux update for v3.10
> >
> > As with changes to the Renesas ARM and SH based SoC pinmux code for v3.9
> > it has been agreed by the relevant parties, Linus Walleij, Laurent Pinchart,
> > Paul Mundt and myself, that it would be best to take these changes through
> > the renesas tree and in turn the arm-soc tree.
> >
> > This pull is based on a merge of the following in order to provide
> > the required dependencies. This base has been discussed and agreed upon by
> > Linus Walleij, Laurent Pinchart and myself.
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl devel
> > git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl fixes
> > git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas fixes
>
> Pulled, thanks!
>
> I'm a bit overwhelmed by the number of patches and pull requests I got from
> you at the same time, so it took a little longer to get an overview of what
> you are actually doing.
>
> I've used the next/renesas-pinctrl branch again, keeping this one separate
> from the other next/* branches given how many patches there are in here,
> and given the dependency on the pinctrl tree.
Thanks. Please note that some of my other branches are based
on this branch due to dependencies - some days it seems like everything
is dependant on everything else!
^ permalink raw reply [flat|nested] 144+ messages in thread