From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFCv1 07/11] irqchip: armada-370-xp: add MSI support to interrupt controller driver
Date: Tue, 26 Mar 2013 22:37:48 +0100 [thread overview]
Message-ID: <20130326223748.242f0046@skate> (raw)
In-Reply-To: <201303262110.15582.arnd@arndb.de>
Dear Arnd Bergmann,
On Tue, 26 Mar 2013 21:10:15 +0000, Arnd Bergmann wrote:
> > To which children? Only to the main-intc children? If so,
> > armada_370_xp_mpic_of_init() would be called with a 'device_node *'
> > that points to the main-intc, correct? Then it would have to go back up
> > in the Device Tree to find the msi node? It's doable of course, but
> > sounds strange, no?
>
> I was thinking of registering two init functions as well.
But then which of the two init functions would do the of_iomap() (or
whatever ioremap()ing function you use) ?
Remember, the very reason what we have *one* driver for both interrupt
controllers is because the registers are completely mixed. So to me
it's really the case of *one* device providing *two* features, like a
device that would be both an Ethernet interface and a SPI controller.
You have a single ->probe() function that gets called when the device
is detected, and this ->probe() function registers both an Ethernet
interface and a SPI controller.
To me, the case we have here is really identical: we have one single set
of registers that provide multiple features.
> > To me, the topology of the hardware is really that a single device
> > provides two features: the main interrupt controller and the MSI
> > interrupt controller. But I will adapt to whatever DT binding you
> > propose.
>
> My preference would be to have no sub-nodes but rather make the
> code deal with an interrupt controller that has an interrupt domain
> for regular IRQs but can also handle MSI.
Hum, ok.
> > > I still wonder if the real solution shouldn't instead be to make the
> > > irq domain code MSI aware. For instance, you don't really need a
> > > cell to describe an interrupt because the interrupt number is
> > > not a hardware property. So an MSI using device doesn't really
> > > needs an "msis" or "interrupts" property, just an "msi-parent",
> > > and we can add code to handle as a separate domain even if you
> > > have a single device node that can do both level and message
> > > interrupts.
> >
> > So the msi-parent property should point to the single mpic node? But
> > then the IRQ domain for MSI cannot be registered on this single MPIC
> > node. Then, what would be the first argument of:
> >
> > armada_370_xp_msi_domain =
> > irq_domain_add_linear(msi_node, PCI_MSI_DOORBELL_NR,
> > &armada_370_xp_msi_irq_ops, NULL);
> >
> > and how would the PCIe driver get a pointer to this IRQ domain? (In the
> > currently proposed code, it just does a irq_find_host(), which sounded
> > very simple and straightforward).
>
> I guess one way would be to have a single domain that is responsible
> for the controller and handles both MSI and legacy interrupts. That
> could probably be done without changes to the interrupt domain code.
>
> Another option would be to add an irq_domain_add_msi() function that
> creates a domain which is also tied to the same device node but does
> not interact with it when going through the legacy interrupts.
> You could then add a matching msi_find_host() or irq_find_msi_host()
> function to return the domain.
This option seems doable. Not sure yet how to do it exactly, but at
least I understand the idea.
> > To clarify: I really don't mind reworking the code, but unfortunately
> > "make the IRQ domain code MSI aware" is too vague for me to understand
> > the direction you're thinking of.
>
> I don't have specific code in mind yet, mainly playing around with the
> possibilities for now.
Sure, I understand. But I also don't have specific ideas: the current
code works fine for me, and I don't find it really ugly. So if you don't
point me in the direction that you think would make the code less ugly,
then I'm lost.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
next prev parent reply other threads:[~2013-03-26 21:37 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-26 16:52 [RFCv1 00/11] MSI support for Marvell EBU PCIe driver Thomas Petazzoni
[not found] ` <1364316746-8702-2-git-send-email-thomas.petazzoni@free-electrons.com>
2013-03-26 16:53 ` [RFCv1 01/11] arm: mvebu: move L2 cache initialization in init_early() Arnd Bergmann
2013-03-26 17:02 ` Thomas Petazzoni
2013-03-27 1:53 ` Rob Herring
[not found] ` <1364316746-8702-3-git-send-email-thomas.petazzoni@free-electrons.com>
2013-03-26 16:54 ` [RFCv1 02/11] irqchip: move IRQ driver for Armada 370/XP Arnd Bergmann
2013-03-26 17:05 ` [RFCv1 00/11] MSI support for Marvell EBU PCIe driver Thomas Petazzoni
2013-03-26 17:18 ` Arnd Bergmann
2013-03-26 17:21 ` Thomas Petazzoni
[not found] ` <1364316746-8702-8-git-send-email-thomas.petazzoni@free-electrons.com>
2013-03-26 17:07 ` [RFCv1 07/11] irqchip: armada-370-xp: add MSI support to interrupt controller driver Arnd Bergmann
2013-03-26 17:17 ` Thomas Petazzoni
2013-03-26 18:38 ` Arnd Bergmann
2013-03-26 20:46 ` Thomas Petazzoni
2013-03-26 21:10 ` Arnd Bergmann
2013-03-26 21:37 ` Thomas Petazzoni [this message]
2013-03-26 21:53 ` Arnd Bergmann
2013-03-26 21:14 ` Jason Gunthorpe
2013-03-26 21:41 ` Thomas Petazzoni
2013-03-26 18:02 ` Jason Gunthorpe
2013-03-26 21:16 ` Thomas Petazzoni
2013-03-26 21:31 ` Arnd Bergmann
2013-03-26 21:47 ` Thomas Petazzoni
2013-03-26 21:55 ` Jason Gunthorpe
2013-03-26 22:04 ` Arnd Bergmann
2013-03-26 22:06 ` Thomas Petazzoni
2013-03-26 22:26 ` Jason Gunthorpe
2013-03-26 21:15 ` Arnd Bergmann
2013-03-26 21:42 ` Thomas Petazzoni
[not found] ` <1364316746-8702-10-git-send-email-thomas.petazzoni@free-electrons.com>
2013-03-27 10:07 ` [RFCv1 09/11] pci: mvebu: add MSI support Andrew Murray
2013-04-08 22:29 ` Bjorn Helgaas
2013-05-30 12:15 ` Thierry Reding
2013-05-30 18:13 ` Bjorn Helgaas
2013-04-04 9:16 ` [RFCv1 00/11] MSI support for Marvell EBU PCIe driver Ezequiel Garcia
2013-04-04 9:29 ` Thomas Petazzoni
[not found] ` <1364316746-8702-9-git-send-email-thomas.petazzoni@free-electrons.com>
2013-04-08 22:28 ` [RFCv1 08/11] PCI: Introduce new MSI chip infrastructure Bjorn Helgaas
2013-04-09 8:11 ` Andrew Murray
2013-04-09 8:22 ` Thierry Reding
2013-04-09 8:25 ` Andrew Murray
2013-04-09 8:18 ` Thierry Reding
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