From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFCv1 07/11] irqchip: armada-370-xp: add MSI support to interrupt controller driver
Date: Tue, 26 Mar 2013 22:41:23 +0100 [thread overview]
Message-ID: <20130326224123.2526124b@skate> (raw)
In-Reply-To: <20130326211403.GA5198@obsidianresearch.com>
Dear Jason Gunthorpe,
On Tue, 26 Mar 2013 15:14:03 -0600, Jason Gunthorpe wrote:
> On Tue, Mar 26, 2013 at 09:46:13PM +0100, Thomas Petazzoni wrote:
>
> > To me, the topology of the hardware is really that a single device
> > provides two features: the main interrupt controller and the MSI
> > interrupt controller. But I will adapt to whatever DT binding you
> > propose.
>
> No.. the HW is a single device that provides an interrupt on register
> write capability, so it ideally should be a single DT node..
No, here you're only talking about the interrupt on register write
capability (used for doorbells), but the interrupt controller is also
used for all other devices. Not only IPIs and MSIs are handled by this
piece of code.
> The need to distinguish MSI vs IPI vs other usage is completely a side
> effect of how Linux's IRQ and PCI layers are hooked together today.
Yes. And since I live in today's world, I try to adapt somewhat to
it :-)
> > > I still wonder if the real solution shouldn't instead be to make the
> > > irq domain code MSI aware. For instance, you don't really need a
> > > cell to describe an interrupt because the interrupt number is
>
> Some kind of generic way for an irq chip driver to say 'here, I can
> provide some MSI interrupts' and then for the PCI layer to say 'irq
> layer, find me a driver that can provision a MSI with XXX properties' ?
>
> This need to stack an irq chip under a MSI is not something I think
> the kernel has had to support before, so new common code is probably
> needed...
>
> The interrupt chip should not need to know what the ultimate consumer
> of the interrupt capability will be, it just needs to tell the
> consumer 'write D to physical address A and irq I will trigger'.
I honestly don't see much difference between what you're saying here
and what the proposed code is doing. The IRQ driver says "hay, I
provide two IRQ domains, one is named mpic, one is named msi". And then
all the regular devices have interrupt-parent = <&mpic> to say "I use
legacy interrupts from that controller", and the PCIe controller has
msi-parent = <&msi> to say "I use MSI interrupt from that controller".
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
next prev parent reply other threads:[~2013-03-26 21:41 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-26 16:52 [RFCv1 00/11] MSI support for Marvell EBU PCIe driver Thomas Petazzoni
[not found] ` <1364316746-8702-3-git-send-email-thomas.petazzoni@free-electrons.com>
2013-03-26 16:54 ` [RFCv1 02/11] irqchip: move IRQ driver for Armada 370/XP Arnd Bergmann
2013-03-26 17:05 ` [RFCv1 00/11] MSI support for Marvell EBU PCIe driver Thomas Petazzoni
2013-03-26 17:18 ` Arnd Bergmann
2013-03-26 17:21 ` Thomas Petazzoni
[not found] ` <1364316746-8702-8-git-send-email-thomas.petazzoni@free-electrons.com>
2013-03-26 17:07 ` [RFCv1 07/11] irqchip: armada-370-xp: add MSI support to interrupt controller driver Arnd Bergmann
2013-03-26 17:17 ` Thomas Petazzoni
2013-03-26 18:38 ` Arnd Bergmann
2013-03-26 20:46 ` Thomas Petazzoni
2013-03-26 21:10 ` Arnd Bergmann
2013-03-26 21:37 ` Thomas Petazzoni
2013-03-26 21:53 ` Arnd Bergmann
2013-03-26 21:14 ` Jason Gunthorpe
2013-03-26 21:41 ` Thomas Petazzoni [this message]
2013-03-26 18:02 ` Jason Gunthorpe
2013-03-26 21:16 ` Thomas Petazzoni
2013-03-26 21:31 ` Arnd Bergmann
2013-03-26 21:47 ` Thomas Petazzoni
2013-03-26 21:55 ` Jason Gunthorpe
2013-03-26 22:04 ` Arnd Bergmann
2013-03-26 22:06 ` Thomas Petazzoni
2013-03-26 22:26 ` Jason Gunthorpe
2013-03-26 21:15 ` Arnd Bergmann
2013-03-26 21:42 ` Thomas Petazzoni
[not found] ` <1364316746-8702-2-git-send-email-thomas.petazzoni@free-electrons.com>
2013-03-26 16:53 ` [RFCv1 01/11] arm: mvebu: move L2 cache initialization in init_early() Arnd Bergmann
2013-03-26 17:02 ` Thomas Petazzoni
2013-03-27 1:53 ` Rob Herring
2013-04-04 9:16 ` [RFCv1 00/11] MSI support for Marvell EBU PCIe driver Ezequiel Garcia
2013-04-04 9:29 ` Thomas Petazzoni
[not found] ` <1364316746-8702-9-git-send-email-thomas.petazzoni@free-electrons.com>
2013-04-08 22:28 ` [RFCv1 08/11] PCI: Introduce new MSI chip infrastructure Bjorn Helgaas
2013-04-09 8:11 ` Andrew Murray
2013-04-09 8:22 ` Thierry Reding
2013-04-09 8:25 ` Andrew Murray
2013-04-09 8:18 ` Thierry Reding
[not found] ` <1364316746-8702-10-git-send-email-thomas.petazzoni@free-electrons.com>
2013-03-27 10:07 ` [RFCv1 09/11] pci: mvebu: add MSI support Andrew Murray
2013-04-08 22:29 ` Bjorn Helgaas
2013-05-30 12:15 ` Thierry Reding
2013-05-30 18:13 ` Bjorn Helgaas
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