Anyone implement Cortex A9 FIQ

Anyone implement Cortex A9 FIQ

[Frank Li]

All:
            Recently, we need real time work run in cortex A9.
            Did anyone use FIQ on Cortex A9?

best regards
Frank Li

Anyone implement Cortex A9 FIQ

[Jonathan Austin]

Hi Frank,

On 15/03/13 07:38, Frank Li wrote:
> All:
>              Recently, we need real time work run in cortex A9.
>              Did anyone use FIQ on Cortex A9?
>

What are you actually trying to do? There's quite a lot more complexity 
to being able to do real-time work on an A-class processor than just 
using FIQ, and much of that would be platform specific. For example on 
ARMv7A, we generally can't assume that FIQ can be used by the non-secure 
world...


Jonny

Anyone implement Cortex A9 FIQ

[Frank Li]

2013/3/15 Jonathan Austin <jonathan.austin@arm.com>:
> Hi Frank,
>
>
> On 15/03/13 07:38, Frank Li wrote:
>>
>> All:
>>              Recently, we need real time work run in cortex A9.
>>              Did anyone use FIQ on Cortex A9?
>>
>
> What are you actually trying to do? There's quite a lot more complexity to
> being able to do real-time work on an A-class processor than just using FIQ,
> and much of that would be platform specific. For example on ARMv7A, we
> generally can't assume that FIQ can be used by the non-secure world...

There are period task run every 125us.
Task is quick simply, just put virtual multi DMA queue to real DMA queue.
Small memory copy and set some hardware register.


>
>
> Jonny
>

Anyone implement Cortex A9 FIQ

[Jonathan Austin]

On 17/03/13 01:15, Frank Li wrote:
> 2013/3/15 Jonathan Austin <jonathan.austin@arm.com>:
>> Hi Frank,
>>
>>
>> On 15/03/13 07:38, Frank Li wrote:
>>>
>>> All:
>>>               Recently, we need real time work run in cortex A9.
>>>               Did anyone use FIQ on Cortex A9?
>>>
>>
>> What are you actually trying to do? There's quite a lot more complexity to
>> being able to do real-time work on an A-class processor than just using FIQ,
>> and much of that would be platform specific. For example on ARMv7A, we
>> generally can't assume that FIQ can be used by the non-secure world...
>
> There are period task run every 125us.
> Task is quick simply, just put virtual multi DMA queue to real DMA queue.
> Small memory copy and set some hardware register.
>

Whether this is feasible will really depend on what platform you're on - 
if there's a secure monitor then FIQs are out of the question anyway. 
Can you tell us more about the system?

If your average interrupt latency is low then you should just be able to 
do this with normal IRQs (have you got threaded interrupt handlers?)

What is it about the situation that leads you to believe that you *need* 
FIQ?

Jonny

Anyone implement Cortex A9 FIQ

[Frank Li]

>
> Whether this is feasible will really depend on what platform you're on - if
> there's a secure monitor then FIQs are out of the question anyway. Can you
> tell us more about the system?

Freescale MX6Q.

>
> If your average interrupt latency is low then you should just be able to do
> this with normal IRQs (have you got threaded interrupt handlers?)

Not all drivers use threaded interrupt handler.

>
> What is it about the situation that leads you to believe that you *need*
> FIQ?

FIQ can be executed even in spin_lock_saveirq.
We want do very small hardware set at related precision period (every 125us).

>
> Jonny
>
>
>

Anyone implement Cortex A9 FIQ

[Dave Martin]

On Tue, Mar 19, 2013 at 03:49:50PM +0800, Frank Li wrote:
> >
> > Whether this is feasible will really depend on what platform you're on - if
> > there's a secure monitor then FIQs are out of the question anyway. Can you
> > tell us more about the system?
> 
> Freescale MX6Q.
> 
> >
> > If your average interrupt latency is low then you should just be able to do
> > this with normal IRQs (have you got threaded interrupt handlers?)
> 
> Not all drivers use threaded interrupt handler.
> 
> >
> > What is it about the situation that leads you to believe that you *need*
> > FIQ?
> 
> FIQ can be executed even in spin_lock_saveirq.
> We want do very small hardware set at related precision period (every 125us).

Why is the latency requirement so tight for this one interrupt?

Cheers
---Dave

Anyone implement Cortex A9 FIQ

[Dave Martin]

On Wed, Apr 10, 2013 at 01:45:05PM +0800, Frank Li wrote:
> We already implement FIQ in our platform.
> We want to use it simulate a hardware behavior.  

OK.  If FIQ is available to you, then it should be possible to use it,
but you should avoid relying on it in production code if possible.

There is not much code in the kernel using FIQ today.  You could take
a look at soemthing like drivers/spi/spi-s3c24xx.c, for an example
of how to set up an FIQ handler.

How to route an actual hardware interrupt to FIQ is a separate question.
Depending on what is in your hardware, this may require some interrupt
controller configuration in the GIC and/or elsewhere.

I don't think the GIC support in the kernel has any support for doing
this, but I could be wrong.

Cheers
---Dave

> 
> 
> 2013/4/9 Dave Martin <dave.martin@linaro.org>
> 
>     On Tue, Mar 19, 2013 at 03:49:50PM +0800, Frank Li wrote:
>     > >
>     > > Whether this is feasible will really depend on what platform you're on
>     - if
>     > > there's a secure monitor then FIQs are out of the question anyway. Can
>     you
>     > > tell us more about the system?
>     >
>     > Freescale MX6Q.
>     >
>     > >
>     > > If your average interrupt latency is low then you should just be able
>     to do
>     > > this with normal IRQs (have you got threaded interrupt handlers?)
>     >
>     > Not all drivers use threaded interrupt handler.
>     >
>     > >
>     > > What is it about the situation that leads you to believe that you
>     *need*
>     > > FIQ?
>     >
>     > FIQ can be executed even in spin_lock_saveirq.
>     > We want do very small hardware set at related precision period (every
>     125us).
> 
>     Why is the latency requirement so tight for this one interrupt?
> 
>     Cheers
>     ---Dave
> 
>