* [PATCH 1/7] ARM: u300: push down syscon registers
2013-05-02 16:16 [PATCH 0/7] ARM: u300 multiplatform support Linus Walleij
@ 2013-05-02 16:16 ` Linus Walleij
2013-05-02 16:21 ` Arnd Bergmann
2013-05-03 4:04 ` Mike Turquette
2013-05-02 16:16 ` [PATCH 2/7] ARM: u300: remove deps from debug macro Linus Walleij
` (6 subsequent siblings)
7 siblings, 2 replies; 15+ messages in thread
From: Linus Walleij @ 2013-05-02 16:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
Get rid of the <mach/syscon.h> header as a prerequisite for
multiplatform support. Do this by pushing the registers down
to their respective drivers and deleting the unused remainder.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Mike: I'm seeking an ACK for this to take it through the
ARM SoC tree alongside the big bowl of DT enablement patches.
---
arch/arm/mach-u300/core.c | 26 +-
arch/arm/mach-u300/include/mach/syscon.h | 592 -------------------------------
arch/arm/mach-u300/regulator.c | 9 +-
drivers/clk/clk-u300.c | 343 +++++++++++++++++-
4 files changed, 373 insertions(+), 597 deletions(-)
delete mode 100644 arch/arm/mach-u300/include/mach/syscon.h
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index ff99e26..9a46426 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -26,11 +26,35 @@
#include <asm/mach/arch.h>
#include <mach/u300-regs.h>
-#include <mach/syscon.h>
#include "timer.h"
/*
+ * SYSCON addresses applicable to the core machine.
+ */
+
+/* Chip ID register 16bit (R/-) */
+#define U300_SYSCON_CIDR (0x400)
+/* SMCR */
+#define U300_SYSCON_SMCR (0x4d0)
+#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
+#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
+#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
+#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
+/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
+#define U300_SYSCON_CSDR (0x4f0)
+#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
+/* PRINT_CONTROL Print Control 16bit (R/-) */
+#define U300_SYSCON_PCR (0x4f8)
+#define U300_SYSCON_PCR_SERV_IND (0x0001)
+/* BOOT_CONTROL 16bit (R/-) */
+#define U300_SYSCON_BCR (0x4fc)
+#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
+#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
+#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
+#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
+
+/*
* Static I/O mappings that are needed for booting the U300 platforms. The
* only things we need are the areas where we find the timer, syscon and
* intcon, since the remaining device drivers will map their own memory
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
deleted file mode 100644
index 10bdd0b..0000000
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/syscon.h
- *
- *
- * Copyright (C) 2008-2012 ST-Ericsson AB
- *
- * Author: Rickard Andersson <rickard.andersson@stericsson.com>
- */
-
-#ifndef __MACH_SYSCON_H
-#define __MACH_SYSCON_H
-
-/*
- * All register defines for SYSCON registers that concerns individual
- * block clocks and reset lines are registered here. This is because
- * we don't want any other file to try to fool around with this stuff.
- */
-
-/* APP side SYSCON registers */
-/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
-/* CLK Control Register 16bit (R/W) */
-#define U300_SYSCON_CCR (0x0000)
-#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
-#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
-#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
-/* CLK Status Register 16bit (R/W) */
-#define U300_SYSCON_CSR (0x0004)
-#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
-#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
-/* Reset lines for SLOW devices 16bit (R/W) */
-#define U300_SYSCON_RSR (0x0014)
-#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
-#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
-#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
-#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
-#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
-#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
-#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
-#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
-#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
-#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
-/* Reset lines for FAST devices 16bit (R/W) */
-#define U300_SYSCON_RFR (0x0018)
-#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
-#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
-#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
-#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
-#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
-#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
-#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
-#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
-/* Reset lines for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_RRR (0x001c)
-#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
-#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
-#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
-#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
-#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
-#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
-#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
-#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
-#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
-#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
-#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
-#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
-#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
-/* Clock enable for SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CESR (0x0020)
-#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
-#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
-#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
-#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
-#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
-#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
-#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
-#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
-#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
-/* Clock enable for FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CEFR (0x0024)
-#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
-#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
-#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
-#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
-#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
-#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
-/* Clock enable for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CERR (0x0028)
-#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
-#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
-#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
-#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
-#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
-#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
-#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
-#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
-#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
-#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
-#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
-#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
-#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
-#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
-/* Single block clock enable 16bit (-/W) */
-#define U300_SYSCON_SBCER (0x002c)
-#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
-#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
-#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
-#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
-#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
-#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
-#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
-#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
-#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
-#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
-#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
-#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
-#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
-#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
-#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
-#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
-#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
-#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
-#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
-#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
-#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
-#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
-#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
-#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
-#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
-#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
-#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
-#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
-#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
-#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
-#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
-#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
-#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
-/* Single block clock disable 16bit (-/W) */
-#define U300_SYSCON_SBCDR (0x0030)
-/* Same values as above for SBCER */
-/* Clock force SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CFSR (0x003c)
-#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
-#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
-#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
-#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
-#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
-#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
-#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
-#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
-#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
-/* Clock force FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CFFR (0x40)
-/* Values not defined. Define if you want to use them. */
-/* Clock force the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CFRR (0x44)
-#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
-#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
-#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
-#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
-#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
-#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
-#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
-#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
-#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
-#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
-#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
-#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
-#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
-#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
-/* PLL208 Frequency Control 16bit (R/W) */
-#define U300_SYSCON_PFCR (0x48)
-#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
-/* Power Management Control 16bit (R/W) */
-#define U300_SYSCON_PMCR (0x50)
-#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
-#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
-/*
- * All other clocking registers moved to clock.c!
- */
-/* Reset Out 16bit (R/W) */
-#define U300_SYSCON_RCR (0x6c)
-#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
-/* EMIF Slew Rate Control 16bit (R/W) */
-#define U300_SYSCON_SRCLR (0x70)
-#define U300_SYSCON_SRCLR_MASK (0x03FF)
-#define U300_SYSCON_SRCLR_VALUE (0x03FF)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
-/* EMIF Clock Control Register 16bit (R/W) */
-#define U300_SYSCON_ECCR (0x0078)
-#define U300_SYSCON_ECCR_MASK (0x000F)
-#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
-#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
-#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
-#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
-/* Step one for killing the applications system 16bit (-/W) */
-#define U300_SYSCON_KA1R (0x0080)
-#define U300_SYSCON_KA1R_MASK (0xFFFF)
-#define U300_SYSCON_KA1R_VALUE (0xFFFF)
-/* Step two for killing the application system 16bit (-/W) */
-#define U300_SYSCON_KA2R (0x0084)
-#define U300_SYSCON_KA2R_MASK (0xFFFF)
-#define U300_SYSCON_KA2R_VALUE (0xFFFF)
-/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
-#define U300_SYSCON_MMF0R (0x90)
-#define U300_SYSCON_MMF0R_MASK (0x00FF)
-#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
-#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
-/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
-#define U300_SYSCON_MMF1R (0x94)
-#define U300_SYSCON_MMF1R_MASK (0x00FF)
-#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
-#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
-/* AAIF control register 16 bit (R/W) */
-#define U300_SYSCON_AAIFCR (0x98)
-#define U300_SYSCON_AAIFCR_MASK (0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003)
-/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
-#define U300_SYSCON_MMCR (0x9C)
-#define U300_SYSCON_MMCR_MASK (0x0003)
-#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
-#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
-/* Pull up/down control (R/W) */
-#define U300_SYSCON_PUCR (0x104)
-#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE (0x0200)
-#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE (0x0100)
-#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080)
-#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040)
-#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F)
-/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
-#define U300_SYSCON_S0CCR (0x120)
-#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
-#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
-#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
-#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
-#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
-#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
-#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
-#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
-#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
-/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
-#define U300_SYSCON_S1CCR (0x124)
-#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
-#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
-#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
-#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
-#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
-#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
-#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
-#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
-#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
-/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
-#define U300_SYSCON_S2CCR (0x128)
-#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
-#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
-#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
-#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
-#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
-#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
-#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
-#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
-/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
-#define U300_SYSCON_MCR (0x12c)
-#define U300_SYSCON_MCR_FIELD_MASK (0x00FF)
-#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040)
-#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010)
-#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020)
-#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C)
-#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002)
-#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001)
-/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
-#define U300_SYSCON_PICR (0x0130)
-#define U300_SYSCON_PICR_MASK (0x00FF)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
-/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
-#define U300_SYSCON_PISR (0x0134)
-#define U300_SYSCON_PISR_MASK (0x000F)
-#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
-#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
-#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
-#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
-/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
-#define U300_SYSCON_PICLR (0x0138)
-#define U300_SYSCON_PICLR_MASK (0x000F)
-#define U300_SYSCON_PICLR_RWMASK (0x0000)
-#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
-#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
-#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
-#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
-/* CAMIF_CONTROL 16 bit (-/W) */
-#define U300_SYSCON_CICR (0x013C)
-#define U300_SYSCON_CICR_MASK (0x0FFF)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK (0x0F00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1 (0x0C00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0 (0x0300)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK (0x00F0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1 (0x00C0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0 (0x0030)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK (0x000F)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1 (0x000C)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0 (0x0003)
-/* Clock activity observability register 0 */
-#define U300_SYSCON_C0OAR (0x140)
-#define U300_SYSCON_C0OAR_MASK (0xFFFF)
-#define U300_SYSCON_C0OAR_VALUE (0xFFFF)
-#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
-#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
-#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
-#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
-#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
-#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
-#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
-#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
-#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
-#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
-#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
-#define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
-#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
-#define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
-#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
-#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
-/* Clock activity observability register 1 */
-#define U300_SYSCON_C1OAR (0x144)
-#define U300_SYSCON_C1OAR_MASK (0x3FFE)
-#define U300_SYSCON_C1OAR_VALUE (0x3FFE)
-#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
-#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
-#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
-#define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
-#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
-#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
-#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
-#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
-#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
-#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
-#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
-#define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
-#define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
-/* Clock activity observability register 2 */
-#define U300_SYSCON_C2OAR (0x148)
-#define U300_SYSCON_C2OAR_MASK (0x0FFF)
-#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
-#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
-#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
-#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
-#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
-#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
-#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
-#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
-#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
-
-/* Chip ID register 16bit (R/-) */
-#define U300_SYSCON_CIDR (0x400)
-/* Video IRQ clear 16bit (R/W) */
-#define U300_SYSCON_VICR (0x404)
-#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002)
-#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001)
-/* SMCR */
-#define U300_SYSCON_SMCR (0x4d0)
-#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
-#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
-#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
-#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
-/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
-#define U300_SYSCON_CSDR (0x4f0)
-#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
-/* PRINT_CONTROL Print Control 16bit (R/-) */
-#define U300_SYSCON_PCR (0x4f8)
-#define U300_SYSCON_PCR_SERV_IND (0x0001)
-/* BOOT_CONTROL 16bit (R/-) */
-#define U300_SYSCON_BCR (0x4fc)
-#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
-#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
-#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
-#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
-
-
-/* CPU clock defines */
-/**
- * CPU high frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_HIGH 208
-/**
- * CPU medium frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_MEDIUM 52
-/**
- * CPU low frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_LOW 13
-
-/* EMIF clock defines */
-/**
- * EMIF high frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_HIGH 104
-/**
- * EMIF medium frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_MEDIUM 52
-/**
- * EMIF low frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_LOW 13
-
-/* AHB clock defines */
-/**
- * AHB high frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_HIGH 52
-/**
- * AHB medium frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_MEDIUM 26
-/**
- * AHB low frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */
-
-enum syscon_busmaster {
- SYSCON_BM_DMAC,
- SYSCON_BM_XGAM,
- SYSCON_BM_VIDEO_ENC
-};
-
-/* Selectr a resistor or a set of resistors */
-enum syscon_pull_up_down {
- SYSCON_PU_KEY_IN_EN,
- SYSCON_PU_EMIF_1_8_BIT_EN,
- SYSCON_PU_EMIF_1_16_BIT_EN,
- SYSCON_PU_EMIF_1_NFIF_READY_EN,
- SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
-};
-
-/*
- * Note that this array must match the order of the array "clk_reg"
- * in syscon.c
- */
-enum syscon_clk {
- SYSCON_CLKCONTROL_SLOW_BRIDGE,
- SYSCON_CLKCONTROL_UART,
- SYSCON_CLKCONTROL_BTR,
- SYSCON_CLKCONTROL_EH,
- SYSCON_CLKCONTROL_GPIO,
- SYSCON_CLKCONTROL_KEYPAD,
- SYSCON_CLKCONTROL_APP_TIMER,
- SYSCON_CLKCONTROL_ACC_TIMER,
- SYSCON_CLKCONTROL_FAST_BRIDGE,
- SYSCON_CLKCONTROL_I2C0,
- SYSCON_CLKCONTROL_I2C1,
- SYSCON_CLKCONTROL_I2S0,
- SYSCON_CLKCONTROL_I2S1,
- SYSCON_CLKCONTROL_MMC,
- SYSCON_CLKCONTROL_SPI,
- SYSCON_CLKCONTROL_I2S0_CORE,
- SYSCON_CLKCONTROL_I2S1_CORE,
- SYSCON_CLKCONTROL_UART1,
- SYSCON_CLKCONTROL_AAIF,
- SYSCON_CLKCONTROL_AHB,
- SYSCON_CLKCONTROL_APEX,
- SYSCON_CLKCONTROL_CPU,
- SYSCON_CLKCONTROL_DMA,
- SYSCON_CLKCONTROL_EMIF,
- SYSCON_CLKCONTROL_NAND_IF,
- SYSCON_CLKCONTROL_VIDEO_ENC,
- SYSCON_CLKCONTROL_XGAM,
- SYSCON_CLKCONTROL_SEMI,
- SYSCON_CLKCONTROL_AHB_SUBSYS,
- SYSCON_CLKCONTROL_MSPRO
-};
-
-enum syscon_sysclk_mode {
- SYSCON_SYSCLK_DISABLED,
- SYSCON_SYSCLK_M_CLK,
- SYSCON_SYSCLK_ACC_FSM,
- SYSCON_SYSCLK_PLL60_48,
- SYSCON_SYSCLK_PLL60_60,
- SYSCON_SYSCLK_ACC_PLL208,
- SYSCON_SYSCLK_APP_PLL13,
- SYSCON_SYSCLK_APP_FSM,
- SYSCON_SYSCLK_RTC,
- SYSCON_SYSCLK_APP_PLL208
-};
-
-enum syscon_sysclk_req {
- SYSCON_SYSCLKREQ_DISABLED,
- SYSCON_SYSCLKREQ_ACTIVE_LOW,
- SYSCON_SYSCLKREQ_MONITOR
-};
-
-enum syscon_clk_mode {
- SYSCON_CLKMODE_OFF,
- SYSCON_CLKMODE_DEFAULT,
- SYSCON_CLKMODE_LOW,
- SYSCON_CLKMODE_MEDIUM,
- SYSCON_CLKMODE_HIGH,
- SYSCON_CLKMODE_PERMANENT,
- SYSCON_CLKMODE_ON,
-};
-
-enum syscon_call_mode {
- SYSCON_CLKCALL_NOWAIT,
- SYSCON_CLKCALL_WAIT,
-};
-
-int syscon_dc_on(bool keep_power_on);
-int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
- bool active);
-bool syscon_get_busmaster_active_state(void);
-int syscon_set_sleep_mask(enum syscon_clk,
- bool sleep_ctrl);
-int syscon_config_sysclk(u32 sysclk,
- enum syscon_sysclk_mode sysclkmode,
- bool inverse,
- u32 divisor,
- enum syscon_sysclk_req sysclkreq);
-bool syscon_can_turn_off_semi_clock(void);
-
-/* This function is restricted to core.c */
-int syscon_request_normal_power(bool req);
-
-/* This function is restricted to be used by platform_speed.c */
-int syscon_speed_request(enum syscon_call_mode wait_mode,
- enum syscon_clk_mode req_clk_mode);
-#endif /* __MACH_SYSCON_H */
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index bbda954..ab7d7a5 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -17,9 +17,12 @@
#include <linux/regulator/consumer.h>
/* Those are just for writing in syscon */
#include <linux/io.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/syscon.h>
+#include <mach/u300-regs.h>
+
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR (0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
/*
* Regulators that power the board and chip and which are
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index a15f792..a41e42e 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -11,7 +11,348 @@
#include <linux/io.h>
#include <linux/clk-provider.h>
#include <linux/spinlock.h>
-#include <mach/syscon.h>
+
+/* APP side SYSCON registers */
+/* CLK Control Register 16bit (R/W) */
+#define U300_SYSCON_CCR (0x0000)
+#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
+#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
+#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
+/* CLK Status Register 16bit (R/W) */
+#define U300_SYSCON_CSR (0x0004)
+#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
+#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
+/* Reset lines for SLOW devices 16bit (R/W) */
+#define U300_SYSCON_RSR (0x0014)
+#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
+#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
+#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
+#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
+#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
+#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
+#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
+#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
+#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
+#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
+/* Reset lines for FAST devices 16bit (R/W) */
+#define U300_SYSCON_RFR (0x0018)
+#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
+#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
+#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
+#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
+#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
+#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
+#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
+#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
+/* Reset lines for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_RRR (0x001c)
+#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
+#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
+#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
+#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
+#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
+#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
+#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
+#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
+#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
+#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
+#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
+#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
+#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
+/* Clock enable for SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CESR (0x0020)
+#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
+#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
+#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
+#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
+#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
+#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
+#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
+#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
+#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
+/* Clock enable for FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CEFR (0x0024)
+#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
+#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
+#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
+#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
+#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
+#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
+/* Clock enable for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CERR (0x0028)
+#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
+#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
+#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
+#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
+#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
+#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
+#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
+#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
+#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
+#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
+#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
+#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
+#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
+#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
+/* Single block clock enable 16bit (-/W) */
+#define U300_SYSCON_SBCER (0x002c)
+#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
+#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
+#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
+#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
+#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
+#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
+#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
+#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
+#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
+#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
+#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
+#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
+#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
+#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
+#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
+#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
+#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
+#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
+#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
+#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
+#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
+#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
+#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
+#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
+#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
+#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
+#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
+#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
+#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
+#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
+#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
+#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
+#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
+/* Single block clock disable 16bit (-/W) */
+#define U300_SYSCON_SBCDR (0x0030)
+/* Same values as above for SBCER */
+/* Clock force SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CFSR (0x003c)
+#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
+#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
+#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
+#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
+#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
+#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
+#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
+#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
+#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
+/* Clock force FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CFFR (0x40)
+/* Values not defined. Define if you want to use them. */
+/* Clock force the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CFRR (0x44)
+#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
+#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
+#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
+#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
+#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
+#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
+#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
+#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
+#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
+#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
+#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
+#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
+#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
+#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
+/* PLL208 Frequency Control 16bit (R/W) */
+#define U300_SYSCON_PFCR (0x48)
+#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR (0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
+/* Reset Out 16bit (R/W) */
+#define U300_SYSCON_RCR (0x6c)
+#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
+/* EMIF Slew Rate Control 16bit (R/W) */
+#define U300_SYSCON_SRCLR (0x70)
+#define U300_SYSCON_SRCLR_MASK (0x03FF)
+#define U300_SYSCON_SRCLR_VALUE (0x03FF)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
+/* EMIF Clock Control Register 16bit (R/W) */
+#define U300_SYSCON_ECCR (0x0078)
+#define U300_SYSCON_ECCR_MASK (0x000F)
+#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
+#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
+#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
+#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
+/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
+#define U300_SYSCON_MMF0R (0x90)
+#define U300_SYSCON_MMF0R_MASK (0x00FF)
+#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
+#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
+/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
+#define U300_SYSCON_MMF1R (0x94)
+#define U300_SYSCON_MMF1R_MASK (0x00FF)
+#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
+#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
+/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
+#define U300_SYSCON_MMCR (0x9C)
+#define U300_SYSCON_MMCR_MASK (0x0003)
+#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
+#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
+/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
+#define U300_SYSCON_S0CCR (0x120)
+#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
+#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
+#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
+#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
+#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
+#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
+#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
+#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
+#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
+/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
+#define U300_SYSCON_S1CCR (0x124)
+#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
+#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
+#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
+#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
+#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
+#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
+#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
+#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
+#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
+/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
+#define U300_SYSCON_S2CCR (0x128)
+#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
+#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
+#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
+#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
+#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
+#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
+#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
+#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
+/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
+#define U300_SYSCON_PICR (0x0130)
+#define U300_SYSCON_PICR_MASK (0x00FF)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
+/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
+#define U300_SYSCON_PISR (0x0134)
+#define U300_SYSCON_PISR_MASK (0x000F)
+#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
+#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
+#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
+#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
+/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
+#define U300_SYSCON_PICLR (0x0138)
+#define U300_SYSCON_PICLR_MASK (0x000F)
+#define U300_SYSCON_PICLR_RWMASK (0x0000)
+#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
+#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
+#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
+#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
+/* Clock activity observability register 0 */
+#define U300_SYSCON_C0OAR (0x140)
+#define U300_SYSCON_C0OAR_MASK (0xFFFF)
+#define U300_SYSCON_C0OAR_VALUE (0xFFFF)
+#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
+#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
+#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
+#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
+#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
+#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
+#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
+#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
+#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
+#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
+#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
+#define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
+#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
+#define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
+#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
+#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
+/* Clock activity observability register 1 */
+#define U300_SYSCON_C1OAR (0x144)
+#define U300_SYSCON_C1OAR_MASK (0x3FFE)
+#define U300_SYSCON_C1OAR_VALUE (0x3FFE)
+#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
+#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
+#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
+#define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
+#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
+#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
+#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
+#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
+#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
+#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
+#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
+#define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
+#define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
+/* Clock activity observability register 2 */
+#define U300_SYSCON_C2OAR (0x148)
+#define U300_SYSCON_C2OAR_MASK (0x0FFF)
+#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
+#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
+#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
+#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
+#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
+#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
+#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
+#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
+#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
+
/*
* The clocking hierarchy currently looks like this.
--
1.7.11.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 1/7] ARM: u300: push down syscon registers
2013-05-02 16:16 ` [PATCH 1/7] ARM: u300: push down syscon registers Linus Walleij
@ 2013-05-02 16:21 ` Arnd Bergmann
2013-05-02 16:38 ` Linus Walleij
2013-05-03 4:04 ` Mike Turquette
1 sibling, 1 reply; 15+ messages in thread
From: Arnd Bergmann @ 2013-05-02 16:21 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 02 May 2013, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij@linaro.org>
>
> Get rid of the <mach/syscon.h> header as a prerequisite for
> multiplatform support. Do this by pushing the registers down
> to their respective drivers and deleting the unused remainder.
>
> Cc: Mike Turquette <mturquette@linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Mike: I'm seeking an ACK for this to take it through the
> ARM SoC tree alongside the big bowl of DT enablement patches.
> ---
How do those drivers get to the SYSCON base address? Should they
be using drivers/mfd/syscon.c as the multiplexor instead?
Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/7] ARM: u300: push down syscon registers
2013-05-02 16:21 ` Arnd Bergmann
@ 2013-05-02 16:38 ` Linus Walleij
2013-05-02 17:39 ` Arnd Bergmann
0 siblings, 1 reply; 15+ messages in thread
From: Linus Walleij @ 2013-05-02 16:38 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 2, 2013 at 6:21 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thursday 02 May 2013, Linus Walleij wrote:
>> From: Linus Walleij <linus.walleij@linaro.org>
>>
>> Get rid of the <mach/syscon.h> header as a prerequisite for
>> multiplatform support. Do this by pushing the registers down
>> to their respective drivers and deleting the unused remainder.
>>
>> Cc: Mike Turquette <mturquette@linaro.org>
>> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
>> ---
>> Mike: I'm seeking an ACK for this to take it through the
>> ARM SoC tree alongside the big bowl of DT enablement patches.
>> ---
>
> How do those drivers get to the SYSCON base address? Should they
> be using drivers/mfd/syscon.c as the multiplexor instead?
No, there is no mutex to be taken. The consecutive range of memory
addresses are used by different things (mainly the clocks) but there
is no register that needs to be protected against access from two
subsystems simultaneously.
As a follow-up to this series I plan to move also the U300 clocks
to the device tree (similar three-step ladder as used for the Nomadik)
and then they will (hopefully) get the syscon base address from the
device tree.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/7] ARM: u300: push down syscon registers
2013-05-02 16:38 ` Linus Walleij
@ 2013-05-02 17:39 ` Arnd Bergmann
2013-05-03 8:01 ` Linus Walleij
0 siblings, 1 reply; 15+ messages in thread
From: Arnd Bergmann @ 2013-05-02 17:39 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 02 May 2013, Linus Walleij wrote:
> > How do those drivers get to the SYSCON base address? Should they
> > be using drivers/mfd/syscon.c as the multiplexor instead?
>
> No, there is no mutex to be taken. The consecutive range of memory
> addresses are used by different things (mainly the clocks) but there
> is no register that needs to be protected against access from two
> subsystems simultaneously.
>
> As a follow-up to this series I plan to move also the U300 clocks
> to the device tree (similar three-step ladder as used for the Nomadik)
> and then they will (hopefully) get the syscon base address from the
> device tree.
I was less worried about mutexes than a correct representation
in the device tree. With the syscon driver, you can have the
register ranges described exactly once and just use the offsets
on the regmap in the other drivers.
Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/7] ARM: u300: push down syscon registers
2013-05-02 17:39 ` Arnd Bergmann
@ 2013-05-03 8:01 ` Linus Walleij
2013-05-03 14:43 ` Arnd Bergmann
0 siblings, 1 reply; 15+ messages in thread
From: Linus Walleij @ 2013-05-03 8:01 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 2, 2013 at 7:39 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thursday 02 May 2013, Linus Walleij wrote:
>> > How do those drivers get to the SYSCON base address? Should they
>> > be using drivers/mfd/syscon.c as the multiplexor instead?
>>
>> No, there is no mutex to be taken. The consecutive range of memory
>> addresses are used by different things (mainly the clocks) but there
>> is no register that needs to be protected against access from two
>> subsystems simultaneously.
>>
>> As a follow-up to this series I plan to move also the U300 clocks
>> to the device tree (similar three-step ladder as used for the Nomadik)
>> and then they will (hopefully) get the syscon base address from the
>> device tree.
>
> I was less worried about mutexes than a correct representation
> in the device tree. With the syscon driver, you can have the
> register ranges described exactly once and just use the offsets
> on the regmap in the other drivers.
Hm. This sounds a bit like modeling the Linux subsystems after
the needs of the device tree rather than keeping these two as
separate concepts.
It is true however that the same register base will appear twice:
once for the clk driver, and once for the syscon, which is not
yet in the device tree.
The system controllers on several systems typically share this
aspect.
For the DBx500 PRCMU we have solved the case where the pinctrl
is using a few registers inside the PRCMU range like this:
pinctrl {
compatible = "stericsson,nmk-pinctrl";
prcm = <&prcmu>;
};
prcmu: prcmu at 80157000 {
compatible = "stericsson,db8500-prcmu";
reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
(...)
};
Then in the code:
if (np) {
prcm_np = of_parse_phandle(np, "prcm", 0);
if (prcm_np)
npct->prcm_base = of_iomap(prcm_np, 0);
}
I could do something similar by creating a U300 syscon node
and referring to it from the clk node, so the clk looks up its
syscon to find the base.
If so, I can build this on top of the current patch series
with multiplatform and all, as I convert the clocks to DT
(which is the next and final step).
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 1/7] ARM: u300: push down syscon registers
2013-05-03 8:01 ` Linus Walleij
@ 2013-05-03 14:43 ` Arnd Bergmann
0 siblings, 0 replies; 15+ messages in thread
From: Arnd Bergmann @ 2013-05-03 14:43 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 03 May 2013, Linus Walleij wrote:
> I could do something similar by creating a U300 syscon node
> and referring to it from the clk node, so the clk looks up its
> syscon to find the base.
>
> If so, I can build this on top of the current patch series
> with multiplatform and all, as I convert the clocks to DT
> (which is the next and final step).
Yes, I think this is a good plan. If there are just two drivers,
that is probably the easiest way to do it. Using the syscon
driver is not very different in the end and avoids mapping the
same physical address range multiple times (having a static mapping
avoids this too), and I'd prefer that if you have more drivers
that need to get to the same registers.
Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/7] ARM: u300: push down syscon registers
2013-05-02 16:16 ` [PATCH 1/7] ARM: u300: push down syscon registers Linus Walleij
2013-05-02 16:21 ` Arnd Bergmann
@ 2013-05-03 4:04 ` Mike Turquette
1 sibling, 0 replies; 15+ messages in thread
From: Mike Turquette @ 2013-05-03 4:04 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Linus Walleij (2013-05-02 09:16:49)
> From: Linus Walleij <linus.walleij@linaro.org>
>
> Get rid of the <mach/syscon.h> header as a prerequisite for
> multiplatform support. Do this by pushing the registers down
> to their respective drivers and deleting the unused remainder.
>
> Cc: Mike Turquette <mturquette@linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Mike: I'm seeking an ACK for this to take it through the
> ARM SoC tree alongside the big bowl of DT enablement patches.
For the clk-u300.c part:
Acked-by: Mike Turquette <mturquette@linaro.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/7] ARM: u300: remove deps from debug macro
2013-05-02 16:16 [PATCH 0/7] ARM: u300 multiplatform support Linus Walleij
2013-05-02 16:16 ` [PATCH 1/7] ARM: u300: push down syscon registers Linus Walleij
@ 2013-05-02 16:16 ` Linus Walleij
2013-05-02 16:16 ` [PATCH 3/7] ARM: u300: delete <mach/hardware.h> Linus Walleij
` (5 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Linus Walleij @ 2013-05-02 16:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This rids the dependency to <mach/hardware.h> (which is an
implicit dependency to <mach/u300-regs.h>) from the U300
debug macro. Take this opportunity to update the file
header.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/include/debug/u300.S | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/debug/u300.S b/arch/arm/include/debug/u300.S
index 8ae8e4a..6f04f08 100644
--- a/arch/arm/include/debug/u300.S
+++ b/arch/arm/include/debug/u300.S
@@ -1,14 +1,11 @@
/*
- *
- * arch-arm/mach-u300/include/mach/debug-macro.S
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2013 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Debugging macro include header.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
-#include <mach/hardware.h>
+#define U300_SLOW_PER_PHYS_BASE 0xc0010000
+#define U300_SLOW_PER_VIRT_BASE 0xff000000
.macro addruart, rp, rv, tmp
/* If we move the address using MMU, use this. */
--
1.7.11.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 3/7] ARM: u300: delete <mach/hardware.h>
2013-05-02 16:16 [PATCH 0/7] ARM: u300 multiplatform support Linus Walleij
2013-05-02 16:16 ` [PATCH 1/7] ARM: u300: push down syscon registers Linus Walleij
2013-05-02 16:16 ` [PATCH 2/7] ARM: u300: remove deps from debug macro Linus Walleij
@ 2013-05-02 16:16 ` Linus Walleij
2013-05-02 16:16 ` [PATCH 4/7] ARM: u300: delete <mach/irqs.h> Linus Walleij
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Linus Walleij @ 2013-05-02 16:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This file is now unused and can be deleted.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-u300/include/mach/hardware.h | 5 -----
arch/arm/mach-u300/timer.c | 1 -
2 files changed, 6 deletions(-)
delete mode 100644 arch/arm/mach-u300/include/mach/hardware.h
diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h
deleted file mode 100644
index b99d4ce..0000000
--- a/arch/arm/mach-u300/include/mach/hardware.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/hardware.h
- */
-#include <asm/sizes.h>
-#include <mach/u300-regs.h>
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 564e32d..2e622f9 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -22,7 +22,6 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#include <mach/hardware.h>
#include <mach/irqs.h>
/* Generic stuff */
--
1.7.11.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 4/7] ARM: u300: delete <mach/irqs.h>
2013-05-02 16:16 [PATCH 0/7] ARM: u300 multiplatform support Linus Walleij
` (2 preceding siblings ...)
2013-05-02 16:16 ` [PATCH 3/7] ARM: u300: delete <mach/hardware.h> Linus Walleij
@ 2013-05-02 16:16 ` Linus Walleij
2013-05-02 16:16 ` [PATCH 5/7] ARM: u300: localize <mach/u300-regs.h> Linus Walleij
` (3 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Linus Walleij @ 2013-05-02 16:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
All IRQs are now obtained from the device tree, and this file
is unused, so delete it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-u300/include/mach/irqs.h | 80 ----------------------------------
arch/arm/mach-u300/timer.c | 2 -
2 files changed, 82 deletions(-)
delete mode 100644 arch/arm/mach-u300/include/mach/irqs.h
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
deleted file mode 100644
index 21d5e76..0000000
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/irqs.h
- *
- *
- * Copyright (C) 2006-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * IRQ channel definitions for the U300 platforms.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define IRQ_U300_INTCON0_START 32
-#define IRQ_U300_INTCON1_START 64
-/* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT 32
-#define IRQ_U300_IRQ1_EXT 33
-#define IRQ_U300_DMA 34
-#define IRQ_U300_VIDEO_ENC_0 35
-#define IRQ_U300_VIDEO_ENC_1 36
-#define IRQ_U300_AAIF_RX 37
-#define IRQ_U300_AAIF_TX 38
-#define IRQ_U300_AAIF_VGPIO 39
-#define IRQ_U300_AAIF_WAKEUP 40
-#define IRQ_U300_PCM_I2S0_FRAME 41
-#define IRQ_U300_PCM_I2S0_FIFO 42
-#define IRQ_U300_PCM_I2S1_FRAME 43
-#define IRQ_U300_PCM_I2S1_FIFO 44
-#define IRQ_U300_XGAM_GAMCON 45
-#define IRQ_U300_XGAM_CDI 46
-#define IRQ_U300_XGAM_CDICON 47
-#define IRQ_U300_XGAM_PDI 49
-#define IRQ_U300_XGAM_PDICON 50
-#define IRQ_U300_XGAM_GAMEACC 51
-#define IRQ_U300_XGAM_MCIDCT 52
-#define IRQ_U300_APEX 53
-#define IRQ_U300_UART0 54
-#define IRQ_U300_SPI 55
-#define IRQ_U300_TIMER_APP_OS 56
-#define IRQ_U300_TIMER_APP_DD 57
-#define IRQ_U300_TIMER_APP_GP1 58
-#define IRQ_U300_TIMER_APP_GP2 59
-#define IRQ_U300_TIMER_OS 60
-#define IRQ_U300_TIMER_MS 61
-#define IRQ_U300_KEYPAD_KEYBF 62
-#define IRQ_U300_KEYPAD_KEYBR 63
-/* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0 64
-#define IRQ_U300_GPIO_PORT1 65
-#define IRQ_U300_GPIO_PORT2 66
-
-/* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG 67
-#define IRQ_U300_EVHIST 68
-#define IRQ_U300_MSPRO 69
-#define IRQ_U300_MMCSD_MCIINTR0 70
-#define IRQ_U300_MMCSD_MCIINTR1 71
-#define IRQ_U300_I2C0 72
-#define IRQ_U300_I2C1 73
-#define IRQ_U300_RTC 74
-#define IRQ_U300_NFIF 75
-#define IRQ_U300_NFIF2 76
-
-/* The DB3350-specific interrupt lines */
-#define IRQ_U300_ISP_F0 77
-#define IRQ_U300_ISP_F1 78
-#define IRQ_U300_ISP_F2 79
-#define IRQ_U300_ISP_F3 80
-#define IRQ_U300_ISP_F4 81
-#define IRQ_U300_GPIO_PORT3 82
-#define IRQ_U300_SYSCON_PLL_LOCK 83
-#define IRQ_U300_UART1 84
-#define IRQ_U300_GPIO_PORT4 85
-#define IRQ_U300_GPIO_PORT5 86
-#define IRQ_U300_GPIO_PORT6 87
-#define U300_VIC_IRQS_END 88
-
-#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 2e622f9..188de9b 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -22,8 +22,6 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#include <mach/irqs.h>
-
/* Generic stuff */
#include <asm/sched_clock.h>
#include <asm/mach/map.h>
--
1.7.11.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 5/7] ARM: u300: localize <mach/u300-regs.h>
2013-05-02 16:16 [PATCH 0/7] ARM: u300 multiplatform support Linus Walleij
` (3 preceding siblings ...)
2013-05-02 16:16 ` [PATCH 4/7] ARM: u300: delete <mach/irqs.h> Linus Walleij
@ 2013-05-02 16:16 ` Linus Walleij
2013-05-02 16:16 ` [PATCH 6/7] ARM: u300: convert to multiplatform Linus Walleij
` (2 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Linus Walleij @ 2013-05-02 16:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This register base file is now only used in the machine
itself so move it down into mach-u300.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-u300/core.c | 3 +--
arch/arm/mach-u300/regulator.c | 2 +-
arch/arm/mach-u300/{include/mach => }/u300-regs.h | 0
3 files changed, 2 insertions(+), 3 deletions(-)
rename arch/arm/mach-u300/{include/mach => }/u300-regs.h (100%)
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 9a46426..87fdadb 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -25,9 +25,8 @@
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
-#include <mach/u300-regs.h>
-
#include "timer.h"
+#include "u300-regs.h"
/*
* SYSCON addresses applicable to the core machine.
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index ab7d7a5..1cbe88c 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -17,7 +17,7 @@
#include <linux/regulator/consumer.h>
/* Those are just for writing in syscon */
#include <linux/io.h>
-#include <mach/u300-regs.h>
+#include "u300-regs.h"
/* Power Management Control 16bit (R/W) */
#define U300_SYSCON_PMCR (0x50)
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/u300-regs.h
similarity index 100%
rename from arch/arm/mach-u300/include/mach/u300-regs.h
rename to arch/arm/mach-u300/u300-regs.h
--
1.7.11.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 6/7] ARM: u300: convert to multiplatform
2013-05-02 16:16 [PATCH 0/7] ARM: u300 multiplatform support Linus Walleij
` (4 preceding siblings ...)
2013-05-02 16:16 ` [PATCH 5/7] ARM: u300: localize <mach/u300-regs.h> Linus Walleij
@ 2013-05-02 16:16 ` Linus Walleij
2013-05-02 16:16 ` [PATCH 7/7] ARM: u300: delete remnant machine headers Linus Walleij
2013-05-02 16:23 ` [PATCH 0/7] ARM: u300 multiplatform support Arnd Bergmann
7 siblings, 0 replies; 15+ messages in thread
From: Linus Walleij @ 2013-05-02 16:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
Now that we removed our dependency on <mach/*> the U300
can be converted to mutliplatform. Remove the invalid restriction
that U300 would not support AUTO_ZRELADDR (it does) and update
the defconfig in the process.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/Kconfig | 21 +--------------------
arch/arm/configs/u300_defconfig | 11 ++++-------
arch/arm/mach-u300/Kconfig | 31 +++++++++++++++++++++++++------
3 files changed, 30 insertions(+), 33 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bd0be78..7e6355c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -886,25 +886,6 @@ config ARCH_SHARK
Support for the StrongARM based Digital DNARD machine, also known
as "Shark" (<http://www.shark-linux.de/shark.html>).
-config ARCH_U300
- bool "ST-Ericsson U300 Series"
- depends on MMU
- select ARCH_REQUIRE_GPIOLIB
- select ARM_AMBA
- select ARM_PATCH_PHYS_VIRT
- select ARM_VIC
- select CLKDEV_LOOKUP
- select CLKSRC_MMIO
- select CLKSRC_OF
- select COMMON_CLK
- select CPU_ARM926T
- select GENERIC_CLOCKEVENTS
- select HAVE_TCM
- select SPARSE_IRQ
- select USE_OF
- help
- Support for ST-Ericsson U300 series mobile platforms.
-
config ARCH_U8500
bool "ST-Ericsson U8500 Series"
depends on MMU
@@ -2151,7 +2132,7 @@ config CRASH_DUMP
config AUTO_ZRELADDR
bool "Auto calculation of the decompressed kernel image address"
- depends on !ZBOOT_ROM && !ARCH_U300
+ depends on !ZBOOT_ROM
help
ZRELADDR is the physical address where the decompressed kernel
image will be placed. If AUTO_ZRELADDR is selected, the address
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 374000e..a5fa0d9 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -1,7 +1,8 @@
-CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_AIO is not set
@@ -11,12 +12,9 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_U300=y
-CONFIG_MACH_U300=y
-CONFIG_MACH_U300_BS335=y
CONFIG_MACH_U300_SPIDUMMY=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -44,11 +42,11 @@ CONFIG_I2C=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_CLKGATE=y
@@ -70,4 +68,3 @@ CONFIG_DEBUG_FS=y
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 1f59764..e2f350f 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,24 +1,45 @@
-if ARCH_U300
-
menu "ST-Ericsson AB U300/U335 Platform"
comment "ST-Ericsson Mobile Platform Products"
-config MACH_U300
- bool "U300"
+config ARCH_U300
+ bool "ST-Ericsson U300 Series"
+ depends on MMU
+ select ARCH_REQUIRE_GPIOLIB
+ select ARM_AMBA
+ select ARM_PATCH_PHYS_VIRT
+ select ARM_VIC
+ select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
+ select CLKSRC_OF
+ select COMMON_CLK
+ select CPU_ARM926T
+ select GENERIC_CLOCKEVENTS
+ select HAVE_TCM
select PINCTRL
select PINCTRL_COH901
select PINCTRL_U300
+ select SPARSE_IRQ
+ select USE_OF
+ help
+ Support for ST-Ericsson U300 series mobile platforms.
comment "ST-Ericsson U300/U335 Feature Selections"
+config MACH_U300
+ depends on ARCH_U300
+ bool "U300"
+ default y
+
config U300_DEBUG
+ depends on ARCH_U300
bool "Debug support for U300"
depends on PM
help
Debug support for U300 in sysfs, procfs etc.
config MACH_U300_SPIDUMMY
+ depends on ARCH_U300
bool "SSP/SPI dummy chip"
select SPI
select SPI_MASTER
@@ -31,5 +52,3 @@ config MACH_U300_SPIDUMMY
SPI framework and ARM PL022 support.
endmenu
-
-endif
--
1.7.11.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 7/7] ARM: u300: delete remnant machine headers
2013-05-02 16:16 [PATCH 0/7] ARM: u300 multiplatform support Linus Walleij
` (5 preceding siblings ...)
2013-05-02 16:16 ` [PATCH 6/7] ARM: u300: convert to multiplatform Linus Walleij
@ 2013-05-02 16:16 ` Linus Walleij
2013-05-02 16:23 ` [PATCH 0/7] ARM: u300 multiplatform support Arnd Bergmann
7 siblings, 0 replies; 15+ messages in thread
From: Linus Walleij @ 2013-05-02 16:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
Two files remain in <mach/*> for U300: timex.h and
uncompress.h. The former is done away with by using
defaults, the latter is unused in multiplatform.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-u300/include/mach/timex.h | 17 -----------
arch/arm/mach-u300/include/mach/uncompress.h | 45 ----------------------------
2 files changed, 62 deletions(-)
delete mode 100644 arch/arm/mach-u300/include/mach/timex.h
delete mode 100644 arch/arm/mach-u300/include/mach/uncompress.h
diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h
deleted file mode 100644
index f233b72..0000000
--- a/arch/arm/mach-u300/include/mach/timex.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/timex.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform tick rate definition.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-/* This is for the APP OS GP1 (General Purpose 1) timer */
-#define CLOCK_TICK_RATE 1000000
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h
deleted file mode 100644
index 783e7e6..0000000
--- a/arch/arm/mach-u300/include/mach/uncompress.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/uncompress.h
- *
- * Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define AMBA_UART_DR (*(volatile unsigned char *)0xc0013000)
-#define AMBA_UART_LCRH (*(volatile unsigned char *)0xc001302C)
-#define AMBA_UART_CR (*(volatile unsigned char *)0xc0013030)
-#define AMBA_UART_FR (*(volatile unsigned char *)0xc0013018)
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
- while (AMBA_UART_FR & (1 << 5))
- barrier();
-
- AMBA_UART_DR = c;
-}
-
-static inline void flush(void)
-{
- while (AMBA_UART_FR & (1 << 3))
- barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
--
1.7.11.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 0/7] ARM: u300 multiplatform support
2013-05-02 16:16 [PATCH 0/7] ARM: u300 multiplatform support Linus Walleij
` (6 preceding siblings ...)
2013-05-02 16:16 ` [PATCH 7/7] ARM: u300: delete remnant machine headers Linus Walleij
@ 2013-05-02 16:23 ` Arnd Bergmann
7 siblings, 0 replies; 15+ messages in thread
From: Arnd Bergmann @ 2013-05-02 16:23 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 02 May 2013, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij@linaro.org>
>
> This series builds on top of the recently iterated U300
> device tree support to convert the platform to multiplatform
> (a.k.a. single zImage).
>
> This is intended to be pulled on top of the DT support.
>
Very nice! For the patches 2-7:
Acked-by: Arnd Bergmann <arnd@arndb.de>
For patch 1, I'll wait for your reply. It's probably ok too.
Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread