* [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs
2013-05-02 23:48 ` [PATCH v2 0/5] ARM: orion: add orion irqchip driver Sebastian Hesselbarth
@ 2013-05-02 23:48 ` Sebastian Hesselbarth
2013-05-03 12:55 ` Russell King - ARM Linux
2013-05-02 23:48 ` [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth Sebastian Hesselbarth
` (3 subsequent siblings)
4 siblings, 1 reply; 74+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-02 23:48 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds an irqchip driver for the main interrupt controller found
on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
Corresponding device tree documentation is also added.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Note: This patch triggers a checkpatch warning for
WARNING: Avoid CamelCase: <handle_IRQ>
Changelog:
v1->v2:
- rename compatible string to "marvell,orion-intc" (Suggested by Jason Gunthorpe)
- request mem regions for irq base registers (Suggested by Jason Gunthorpe)
- make orion_handle_irq static (Suggested by Jason Gunthorpe)
- make use of IRQCHIP_DECLARE (Suggested by Jason Gunthorpe)
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Jean-Francois Moine <moinejf@free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
.../interrupt-controller/marvell,orion-intc.txt | 22 ++++
drivers/irqchip/Kconfig | 5 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-orion.c | 133 ++++++++++++++++++++
4 files changed, 161 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt
create mode 100644 drivers/irqchip/irq-orion.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt
new file mode 100644
index 0000000..9b7aee9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt
@@ -0,0 +1,22 @@
+Marvell Orion SoC main interrupt controller
+
+Required properties:
+- compatible: shall be "marvell,orion-intc"
+- reg: base address(es) of interrupt registers starting with CAUSE register
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: number of cells to encode an interrupt source, shall be 1.
+
+The interrupt sources map to the corresponding bits in the interrupt
+registers, i.e.
+- 0 maps to bit 0 of first base address,
+- 1 maps to bit 1 of first base address,
+- 32 maps to bit 0 of second base address, and so on.
+
+Example:
+ intc: interrupt-controller {
+ compatible = "marvell,orion-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ /* Dove has 64 first level interrupts */
+ reg = <0x20200 0x10>, <0x20210 0x10>;
+ };
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index a350969..8da3559 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -2,6 +2,11 @@ config IRQCHIP
def_bool y
depends on OF_IRQ
+config IRQCHIP_ORION
+ bool
+ select IRQ_DOMAIN
+ select MULTI_IRQ_HANDLER
+
config ARM_GIC
bool
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 10ef57f..2cad23d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
obj-$(CONFIG_METAG) += irq-metag-ext.o
obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
+obj-$(CONFIG_IRQCHIP_ORION) += irq-orion.o
obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
obj-$(CONFIG_ARM_GIC) += irq-gic.o
diff --git a/drivers/irqchip/irq-orion.c b/drivers/irqchip/irq-orion.c
new file mode 100644
index 0000000..21ebe6c
--- /dev/null
+++ b/drivers/irqchip/irq-orion.c
@@ -0,0 +1,133 @@
+/*
+ * Marvell Orion SoCs IRQ chip driver.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/exception.h>
+#include <asm/mach/irq.h>
+
+#include "irqchip.h"
+
+/* max number of handled irq register blocks */
+#define ORION_MAX_IRQREG 2
+
+#define ORION_IRQ_CAUSE 0x00
+#define ORION_IRQ_MASK 0x04
+#define ORION_IRQ_FIQ_MASK 0x08
+#define ORION_IRQ_ENDP_MASK 0x0c
+
+static void __iomem *orion_irq_base[ORION_MAX_IRQREG];
+static unsigned int orion_irq_regs;
+static struct irq_domain *orion_irq_domain;
+
+static asmlinkage void __exception_irq_entry orion_handle_irq(
+ struct pt_regs *regs)
+{
+ int n;
+ for (n = 0; n < orion_irq_regs; n++) {
+ u32 hwirq_base = n * 32;
+ u32 stat = readl_relaxed(orion_irq_base[n] + ORION_IRQ_CAUSE) &
+ readl_relaxed(orion_irq_base[n] + ORION_IRQ_MASK);
+ while (stat) {
+ u32 hwirq = ffs(stat) - 1;
+ u32 irq = irq_find_mapping(orion_irq_domain,
+ hwirq_base + hwirq);
+ handle_IRQ(irq, regs);
+ stat &= ~(1 << hwirq);
+ }
+ }
+}
+
+static void orion_irq_mask(struct irq_data *irqd)
+{
+ unsigned int irq = irqd_to_hwirq(irqd);
+ unsigned int irq_off = irq % 32;
+ int reg = irq / 32;
+ u32 val;
+
+ val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
+ writel(val & ~(1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
+}
+
+static void orion_irq_unmask(struct irq_data *irqd)
+{
+ unsigned int irq = irqd_to_hwirq(irqd);
+ unsigned int irq_off = irq % 32;
+ int reg = irq / 32;
+ u32 val;
+
+ val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
+ writel(val | (1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
+}
+
+static struct irq_chip orion_irq_chip = {
+ .name = "orion_irq",
+ .irq_mask = orion_irq_mask,
+ .irq_unmask = orion_irq_unmask,
+};
+
+static int orion_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ irq_set_chip_and_handler(virq, &orion_irq_chip,
+ handle_level_irq);
+ set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+ return 0;
+}
+
+static struct irq_domain_ops orion_irq_ops = {
+ .map = orion_irq_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init orion_of_init(struct device_node *np,
+ struct device_node *parent)
+{
+ int n;
+
+ for (n = 0; n < ORION_MAX_IRQREG; n++) {
+ struct resource r;
+
+ /* parsing reg property may fail silently here */
+ if (of_address_to_resource(np, n, &r))
+ continue;
+
+ if (!request_mem_region(r.start, resource_size(&r), np->name))
+ panic("%s: unable to request mem region %d",
+ np->full_name, n);
+
+ orion_irq_base[n] = ioremap(r.start, resource_size(&r));
+ if (!orion_irq_base[n])
+ panic("%s: unable to map resource %d",
+ np->full_name, n);
+
+ /* mask all interrupts */
+ writel(0, orion_irq_base[n] + ORION_IRQ_MASK);
+ orion_irq_regs++;
+ }
+
+ /* at least one irq reg must be set */
+ if (!orion_irq_regs)
+ panic("%s: unable to map IRQC registers\n", np->full_name);
+
+ orion_irq_domain = irq_domain_add_linear(np, orion_irq_regs * 32,
+ &orion_irq_ops, NULL);
+ if (!orion_irq_domain)
+ panic("%s: unable to create IRQ domain\n", np->full_name);
+
+ set_handle_irq(orion_handle_irq);
+
+ return 0;
+}
+IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_of_init);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 74+ messages in thread* [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs
2013-05-02 23:48 ` [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs Sebastian Hesselbarth
@ 2013-05-03 12:55 ` Russell King - ARM Linux
2013-05-03 13:13 ` Sebastian Hesselbarth
0 siblings, 1 reply; 74+ messages in thread
From: Russell King - ARM Linux @ 2013-05-03 12:55 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 03, 2013 at 01:48:35AM +0200, Sebastian Hesselbarth wrote:
> This patch adds an irqchip driver for the main interrupt controller found
> on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
> Corresponding device tree documentation is also added.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Note: This patch triggers a checkpatch warning for
> WARNING: Avoid CamelCase: <handle_IRQ>
>
> Changelog:
> v1->v2:
> - rename compatible string to "marvell,orion-intc" (Suggested by Jason Gunthorpe)
> - request mem regions for irq base registers (Suggested by Jason Gunthorpe)
> - make orion_handle_irq static (Suggested by Jason Gunthorpe)
> - make use of IRQCHIP_DECLARE (Suggested by Jason Gunthorpe)
It would still be a good idea to convert this to use the generic chip
stuff which Thomas created, though exactly how is hard to see at the
moment.
> +static void orion_irq_mask(struct irq_data *irqd)
> +{
> + unsigned int irq = irqd_to_hwirq(irqd);
> + unsigned int irq_off = irq % 32;
> + int reg = irq / 32;
> + u32 val;
> +
> + val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
> + writel(val & ~(1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
> +}
This could be replaced with irq_gc_mask_clr_bit().
> +
> +static void orion_irq_unmask(struct irq_data *irqd)
> +{
> + unsigned int irq = irqd_to_hwirq(irqd);
> + unsigned int irq_off = irq % 32;
> + int reg = irq / 32;
> + u32 val;
> +
> + val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
> + writel(val | (1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
> +}
This with irq_gc_mask_set_bit().
> +
> +static struct irq_chip orion_irq_chip = {
> + .name = "orion_irq",
> + .irq_mask = orion_irq_mask,
> + .irq_unmask = orion_irq_unmask,
> +};
> +
> +static int orion_irq_map(struct irq_domain *d, unsigned int virq,
> + irq_hw_number_t hw)
> +{
> + irq_set_chip_and_handler(virq, &orion_irq_chip,
> + handle_level_irq);
> + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
This is where it starts to get tricky, because I can't see how you'd
merge the irq_alloc_generic_chip() and irq_setup_generic_chip() with
this. Maybe you don't need to do anything here and just do all that
in orion_of_init() instead? But then you seem to need to know the
virq range before hand, and I can't see how that's known. Maybe Thomas
can provide some enlightenment about how the gc irqchip stuff works
with the irq domain stuff...
However, you wouldn't need the statically defined orion_irq_chip nor
orion_irq_base[] either, because those would be held within the gc
irqchip stuff and stored in the upper layer.
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs
2013-05-03 12:55 ` Russell King - ARM Linux
@ 2013-05-03 13:13 ` Sebastian Hesselbarth
2013-05-03 14:09 ` Thomas Gleixner
0 siblings, 1 reply; 74+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-03 13:13 UTC (permalink / raw)
To: linux-arm-kernel
On 05/03/13 14:55, Russell King - ARM Linux wrote:
> On Fri, May 03, 2013 at 01:48:35AM +0200, Sebastian Hesselbarth wrote:
>> This patch adds an irqchip driver for the main interrupt controller found
>> on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
>> Corresponding device tree documentation is also added.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> ---
>> Note: This patch triggers a checkpatch warning for
>> WARNING: Avoid CamelCase: <handle_IRQ>
>>
>> Changelog:
>> v1->v2:
>> - rename compatible string to "marvell,orion-intc" (Suggested by Jason Gunthorpe)
>> - request mem regions for irq base registers (Suggested by Jason Gunthorpe)
>> - make orion_handle_irq static (Suggested by Jason Gunthorpe)
>> - make use of IRQCHIP_DECLARE (Suggested by Jason Gunthorpe)
>
> It would still be a good idea to convert this to use the generic chip
> stuff which Thomas created, though exactly how is hard to see at the
> moment.
Russel,
that is the plan and that's why the whole patch set is preliminary.
Maybe it would have been more precise to call it RFC instead.
>> +static void orion_irq_mask(struct irq_data *irqd)
>> +{
>> + unsigned int irq = irqd_to_hwirq(irqd);
>> + unsigned int irq_off = irq % 32;
>> + int reg = irq / 32;
>> + u32 val;
>> +
>> + val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
>> + writel(val & ~(1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
>> +}
>
> This could be replaced with irq_gc_mask_clr_bit().
>
>> +
>> +static void orion_irq_unmask(struct irq_data *irqd)
>> +{
>> + unsigned int irq = irqd_to_hwirq(irqd);
>> + unsigned int irq_off = irq % 32;
>> + int reg = irq / 32;
>> + u32 val;
>> +
>> + val = readl(orion_irq_base[reg] + ORION_IRQ_MASK);
>> + writel(val | (1 << irq_off), orion_irq_base[reg] + ORION_IRQ_MASK);
>> +}
>
> This with irq_gc_mask_set_bit().
>
>> +
>> +static struct irq_chip orion_irq_chip = {
>> + .name = "orion_irq",
>> + .irq_mask = orion_irq_mask,
>> + .irq_unmask = orion_irq_unmask,
>> +};
>> +
>> +static int orion_irq_map(struct irq_domain *d, unsigned int virq,
>> + irq_hw_number_t hw)
>> +{
>> + irq_set_chip_and_handler(virq, &orion_irq_chip,
>> + handle_level_irq);
>> + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
>
> This is where it starts to get tricky, because I can't see how you'd
> merge the irq_alloc_generic_chip() and irq_setup_generic_chip() with
> this. Maybe you don't need to do anything here and just do all that
> in orion_of_init() instead? But then you seem to need to know the
> virq range before hand, and I can't see how that's known. Maybe Thomas
> can provide some enlightenment about how the gc irqchip stuff works
> with the irq domain stuff...
Exactly, and that is what I am looking into right now. But hell, I am
not an expert in linux irq yet. Moreover, I am not even sure if it is
okay to rely on irqdomain or at least irq_data->hw_irq at all.
My current impression is, that generic chip knowns nothing about irq
domains. But my first modification of it was to use irqd_to_hwirq(d)
where ever it uses d->irq instead. This should allow to abstract from
virtual irqs and retain compatibility (_if_ hw_irq is also set on
!CONFIG_IRQ_DOMAIN).
To add more juice: IRQF_VALID and IRQF_PROBE are ARM only flags. I
tried to find out what they are good for, but stopped googl'ing after
a while. (I know you explained that before somewhere)
> However, you wouldn't need the statically defined orion_irq_chip nor
> orion_irq_base[] either, because those would be held within the gc
> irqchip stuff and stored in the upper layer.
Yeah, that would be very nice. But the current limitation to one
register set with max 32 irqs of generic chip would still require to
keep a list of primary generic irq chips to flip through in the
irq_handler.
This also raises the question, how to check if an generic irq chip
flow handler has to be called. Current irq_chip_regs don't know nothing
about a cause/status register. And actually you don't even know if it
is high/low active and how to mask it with the high/low active mask
register or mask_cache.
Sebastian
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs
2013-05-03 13:13 ` Sebastian Hesselbarth
@ 2013-05-03 14:09 ` Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
0 siblings, 1 reply; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 14:09 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 3 May 2013, Sebastian Hesselbarth wrote:
> On 05/03/13 14:55, Russell King - ARM Linux wrote:
> > This is where it starts to get tricky, because I can't see how you'd
> > merge the irq_alloc_generic_chip() and irq_setup_generic_chip() with
> > this. Maybe you don't need to do anything here and just do all that
> > in orion_of_init() instead? But then you seem to need to know the
> > virq range before hand, and I can't see how that's known. Maybe Thomas
> > can provide some enlightenment about how the gc irqchip stuff works
> > with the irq domain stuff...
>
> Exactly, and that is what I am looking into right now. But hell, I am
> not an expert in linux irq yet. Moreover, I am not even sure if it is
> okay to rely on irqdomain or at least irq_data->hw_irq at all.
Here is a solution to that problem.
1) It adds a mask field to irq_data so we dont have to compute the
mask over and over
2) For compability with existing users it populates the mask with
1 << (d->irq - gc->irq_base)
3) It gives you the option to disable that mask setup or let it
generate from d->hwirq
I'm still looking into a way how to proper support the generic chip /
linear domain mapping in the setup path. Will send you a draft patch
to play with later.
Thanks,
tglx
Index: linux-2.6/include/linux/irq.h
===================================================================
--- linux-2.6.orig/include/linux/irq.h
+++ linux-2.6/include/linux/irq.h
@@ -119,6 +119,7 @@ struct irq_domain;
/**
* struct irq_data - per irq and irq chip data passed down to chip functions
+ * @mask: precomputed bitmask for accessing the chip registers
* @irq: interrupt number
* @hwirq: hardware interrupt number, local to the interrupt domain
* @node: node index useful for balancing
@@ -138,6 +139,7 @@ struct irq_domain;
* irq_data.
*/
struct irq_data {
+ u32 mask;
unsigned int irq;
unsigned long hwirq;
unsigned int node;
@@ -700,10 +702,14 @@ struct irq_chip_generic {
* @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
* irq chips which need to call irq_set_wake() on
* the parent irq. Usually GPIO implementations
+ * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
+ * @IRQ_GC_MASK_FROM_HWIRQ: Calculate irq_data->mask from the hwirq number
*/
enum irq_gc_flags {
IRQ_GC_INIT_MASK_CACHE = 1 << 0,
IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
+ IRQ_GC_NO_MASK = 1 << 2,
+ IRQ_GC_MASK_FROM_HWIRQ = 1 << 4,
};
/* Generic chip callback functions */
Index: linux-2.6/kernel/irq/generic-chip.c
===================================================================
--- linux-2.6.orig/kernel/irq/generic-chip.c
+++ linux-2.6/kernel/irq/generic-chip.c
@@ -39,7 +39,7 @@ void irq_gc_noop(struct irq_data *d)
void irq_gc_mask_disable_reg(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable);
@@ -57,7 +57,7 @@ void irq_gc_mask_disable_reg(struct irq_
void irq_gc_mask_set_bit(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
gc->mask_cache |= mask;
@@ -75,7 +75,7 @@ void irq_gc_mask_set_bit(struct irq_data
void irq_gc_mask_clr_bit(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
gc->mask_cache &= ~mask;
@@ -93,7 +93,7 @@ void irq_gc_mask_clr_bit(struct irq_data
void irq_gc_unmask_enable_reg(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable);
@@ -108,7 +108,7 @@ void irq_gc_unmask_enable_reg(struct irq
void irq_gc_ack_set_bit(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
@@ -122,7 +122,7 @@ void irq_gc_ack_set_bit(struct irq_data
void irq_gc_ack_clr_bit(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- u32 mask = ~(1 << (d->irq - gc->irq_base));
+ u32 mask = ~d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
@@ -136,7 +136,7 @@ void irq_gc_ack_clr_bit(struct irq_data
void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask);
@@ -151,7 +151,7 @@ void irq_gc_mask_disable_reg_and_ack(str
void irq_gc_eoi(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi);
@@ -169,7 +169,7 @@ void irq_gc_eoi(struct irq_data *d)
int irq_gc_set_wake(struct irq_data *d, unsigned int on)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
if (!(mask & gc->wake_enabled))
return -EINVAL;
@@ -254,6 +254,15 @@ void irq_setup_generic_chip(struct irq_c
if (flags & IRQ_GC_INIT_NESTED_LOCK)
irq_set_lockdep_class(i, &irq_nested_lock_class);
+ if (!(flags & IRQ_GC_NO_MASK)) {
+ struct irq_data *d = irq_get_irq_data(i);
+ u32 mask;
+
+ if (flags & IRQ_GC_MASK_FROM_HWIRQ)
+ d->mask = 1 << (d->hwirq % 32);
+ else
+ d->mask = 1 << (i - gc->irq_base);
+ }
irq_set_chip_and_handler(i, &ct->chip, ct->handler);
irq_set_chip_data(i, gc);
irq_modify_status(i, clr, set);
^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 0/8] genirq: Support for irq domains in generic irq chip
2013-05-03 14:09 ` Thomas Gleixner
@ 2013-05-03 21:50 ` Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 1/8] genirq: generic chip: Remove the local cur_regs() function Thomas Gleixner
` (9 more replies)
0 siblings, 10 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 21:50 UTC (permalink / raw)
To: linux-arm-kernel
The ongoing device tree support for ARM is creating new irq chip
drivers in drivers/irqchip/ in a frenzy. Quite some of them are
ripping out the generic irq chip implementation from arch/arm/* and
just creating the same mess of duplicated code again, which was
cleaned up with the generic irq chip implementation with a lot of
effort. Sigh!
I already prodded a few people in reviews to tackle that issue with no
outcome. Even more sigh!
Poor Sebastian triggered me into rant mode, but he ad hoc
volunteered to give it a try. YAY!
Though he asked for a bit of kickstart help. So I squeezed out a few
spare cycles and implemented the basics as far as I think that they
should work.
The following series contains the missing bits and pieces including a
somehow forgotten and now slightly modified series from Gerlando
adding support for irq chips which need separate mask caches for
different chip (control flow) types.
At the moment this supports only linear irq domains, but it could be
extended to other types as well if the need arises. Though the ARM
chips are pretty much all about linear domains AFAICT.
It also lacks support for removing an irq domain at the moment, but
that should be rather trivial to fix.
The last patch in the series is a blind conversion of the irq-sun4i
irq chip driver, completely untested and not even compiled. I just
added it for demonstration purposes. As Russell expected, there is a
lot of consolidation potential. The changelog of that patch is:
1 file changed, 29 insertions(+), 71 deletions(-)
The preparing series has
4 files changed, 294 insertions(+), 50 deletions(-)
So for removing 42 lines in a single driver the core grows 244 lines
including header changes and comments. Convert 6 drivers and we are
more than even because we get the benefit of sharing and therefor
exposing the same code to broader testing and utilization.
We have already 11 of those candidates in drivers/irqchips and new
ones are knocking on the door.
There might be even more consolidation potential, but I leave that to the
DT/irq domain experts.
WARNING: It's compile tested only. So if you find bugs you can keep
them and fix them yourself :)
Thanks,
tglx
---
drivers/irqchip/irq-sun4i.c | 100 ++++-----------
include/linux/irq.h | 45 ++++++-
include/linux/irqdomain.h | 12 +
kernel/irq/generic-chip.c | 281 +++++++++++++++++++++++++++++++++++++-------
kernel/irq/irqdomain.c | 6
5 files changed, 323 insertions(+), 121 deletions(-)
^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 1/8] genirq: generic chip: Remove the local cur_regs() function
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
@ 2013-05-03 21:50 ` Thomas Gleixner
2013-05-27 13:38 ` Grant Likely
2013-05-03 21:50 ` [RFC patch 2/8] genirq: generic chip: Add support for per chip type mask cache Thomas Gleixner
` (8 subsequent siblings)
9 siblings, 1 reply; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 21:50 UTC (permalink / raw)
To: linux-arm-kernel
An embedded and charset-unspecified text was scrubbed...
Name: genirq-cosmetic-remove-cur_regs.patch
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130503/02ad9cf2/attachment.ksh>
^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 1/8] genirq: generic chip: Remove the local cur_regs() function
2013-05-03 21:50 ` [RFC patch 1/8] genirq: generic chip: Remove the local cur_regs() function Thomas Gleixner
@ 2013-05-27 13:38 ` Grant Likely
0 siblings, 0 replies; 74+ messages in thread
From: Grant Likely @ 2013-05-27 13:38 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 3, 2013 at 10:50 PM, Thomas Gleixner <tglx@linutronix.de> wrote:
> From: Gerlando Falauto <gerlando.falauto@keymile.com>
>
> Since we already have an irq_data_get_chip_type() function which returns
> a pointer to irq_chip_type, use that instead of cur_regs().
>
> Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
> Cc: Lennert Buytenhek <kernel@wantstofly.org>
> Cc: Simon Guinot <simon@sequanux.org>
> Cc: Joey Oravec <joravec@drewtech.com>
> Cc: Ben Dooks <ben-linux@fluff.org>
> Cc: Nicolas Pitre <nico@fluxnic.net>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Holger Brunck <Holger.Brunck@keymile.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
g.
^ permalink raw reply [flat|nested] 74+ messages in thread
* [RFC patch 2/8] genirq: generic chip: Add support for per chip type mask cache
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 1/8] genirq: generic chip: Remove the local cur_regs() function Thomas Gleixner
@ 2013-05-03 21:50 ` Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 3/8] genirq: generic chip: Handle separate mask registers Thomas Gleixner
` (7 subsequent siblings)
9 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 21:50 UTC (permalink / raw)
To: linux-arm-kernel
An embedded and charset-unspecified text was scrubbed...
Name: genirq-add-mask_cache-and-pmask_cache-into-struct-irq_chip_type.patch
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130503/5f6f2dfd/attachment.ksh>
^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 3/8] genirq: generic chip: Handle separate mask registers
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 1/8] genirq: generic chip: Remove the local cur_regs() function Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 2/8] genirq: generic chip: Add support for per chip type mask cache Thomas Gleixner
@ 2013-05-03 21:50 ` Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 4/8] genirq: generic chip: Cache per irq bit mask Thomas Gleixner
` (6 subsequent siblings)
9 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 21:50 UTC (permalink / raw)
To: linux-arm-kernel
An embedded and charset-unspecified text was scrubbed...
Name: genirq-handle-separate-mask-registers.patch
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130503/3e593862/attachment.ksh>
^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 4/8] genirq: generic chip: Cache per irq bit mask
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
` (2 preceding siblings ...)
2013-05-03 21:50 ` [RFC patch 3/8] genirq: generic chip: Handle separate mask registers Thomas Gleixner
@ 2013-05-03 21:50 ` Thomas Gleixner
2013-05-03 22:24 ` Russell King - ARM Linux
2013-05-03 21:50 ` [RFC patch 5/8] genirq: Add a mask calculation function Thomas Gleixner
` (5 subsequent siblings)
9 siblings, 1 reply; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 21:50 UTC (permalink / raw)
To: linux-arm-kernel
An embedded and charset-unspecified text was scrubbed...
Name: genirq-generic-chip-cache-mask.patch
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130503/bb9b7d10/attachment.ksh>
^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 4/8] genirq: generic chip: Cache per irq bit mask
2013-05-03 21:50 ` [RFC patch 4/8] genirq: generic chip: Cache per irq bit mask Thomas Gleixner
@ 2013-05-03 22:24 ` Russell King - ARM Linux
2013-05-03 22:39 ` Thomas Gleixner
0 siblings, 1 reply; 74+ messages in thread
From: Russell King - ARM Linux @ 2013-05-03 22:24 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 03, 2013 at 09:50:50PM -0000, Thomas Gleixner wrote:
> - u32 mask = ~(1 << (d->irq - gc->irq_base));
> + u32 mask = ~(d->mask);
I suspect the above changes are all a result of a search-and-replace
which results in the cosmetic parens remaining. Would be nice to get
rid of them too as they're completely unnecessary.
^ permalink raw reply [flat|nested] 74+ messages in thread
* [RFC patch 4/8] genirq: generic chip: Cache per irq bit mask
2013-05-03 22:24 ` Russell King - ARM Linux
@ 2013-05-03 22:39 ` Thomas Gleixner
0 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 22:39 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 3 May 2013, Russell King - ARM Linux wrote:
> On Fri, May 03, 2013 at 09:50:50PM -0000, Thomas Gleixner wrote:
> > - u32 mask = ~(1 << (d->irq - gc->irq_base));
> > + u32 mask = ~(d->mask);
>
> I suspect the above changes are all a result of a search-and-replace
> which results in the cosmetic parens remaining. Would be nice to get
> rid of them too as they're completely unnecessary.
Fair enough.
Thanks,
tglx
^ permalink raw reply [flat|nested] 74+ messages in thread
* [RFC patch 5/8] genirq: Add a mask calculation function
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
` (3 preceding siblings ...)
2013-05-03 21:50 ` [RFC patch 4/8] genirq: generic chip: Cache per irq bit mask Thomas Gleixner
@ 2013-05-03 21:50 ` Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 6/8] genirq: Split out code in generic chip Thomas Gleixner
` (4 subsequent siblings)
9 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 21:50 UTC (permalink / raw)
To: linux-arm-kernel
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Name: genirq-generic-chip-add-mask-calculation-function.patch
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^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 6/8] genirq: Split out code in generic chip
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
` (4 preceding siblings ...)
2013-05-03 21:50 ` [RFC patch 5/8] genirq: Add a mask calculation function Thomas Gleixner
@ 2013-05-03 21:50 ` Thomas Gleixner
2013-05-27 13:45 ` Grant Likely
2013-05-03 21:50 ` [RFC patch 7/8] genirq: generic chip: Add linear irq domain support Thomas Gleixner
` (3 subsequent siblings)
9 siblings, 1 reply; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 21:50 UTC (permalink / raw)
To: linux-arm-kernel
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^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 7/8] genirq: generic chip: Add linear irq domain support
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
` (5 preceding siblings ...)
2013-05-03 21:50 ` [RFC patch 6/8] genirq: Split out code in generic chip Thomas Gleixner
@ 2013-05-03 21:50 ` Thomas Gleixner
2013-05-03 22:23 ` Russell King - ARM Linux
` (2 more replies)
2013-05-03 21:50 ` [RFC patch 8/8] irqchip: sun4i: Convert to generic irq chip Thomas Gleixner
` (2 subsequent siblings)
9 siblings, 3 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 21:50 UTC (permalink / raw)
To: linux-arm-kernel
An embedded and charset-unspecified text was scrubbed...
Name: genirq-add-linear-domain-support.patch
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130503/fb5e5408/attachment.ksh>
^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 7/8] genirq: generic chip: Add linear irq domain support
2013-05-03 21:50 ` [RFC patch 7/8] genirq: generic chip: Add linear irq domain support Thomas Gleixner
@ 2013-05-03 22:23 ` Russell King - ARM Linux
2013-05-03 22:38 ` Thomas Gleixner
2013-05-04 2:30 ` Sebastian Hesselbarth
2013-05-06 12:32 ` [RFC patch 7/8] fixup 1/2: " Sebastian Hesselbarth
2 siblings, 1 reply; 74+ messages in thread
From: Russell King - ARM Linux @ 2013-05-03 22:23 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 03, 2013 at 09:50:53PM -0000, Thomas Gleixner wrote:
> + /* Init mask cache ? */
> + if (dgc->gc_flags & IRQ_GC_INIT_MASK_CACHE) {
> + raw_spin_lock_irqsave(&gc->lock, flags);
> + gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
> + raw_spin_unlock_irqrestore(&gc->lock, flags);
> + }
This looks a little weird to me - it seems that it'll re-read this
each time any irq is mapped in the domain, which is probably not
wanted.
^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 7/8] genirq: generic chip: Add linear irq domain support
2013-05-03 22:23 ` Russell King - ARM Linux
@ 2013-05-03 22:38 ` Thomas Gleixner
0 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 22:38 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 3 May 2013, Russell King - ARM Linux wrote:
> On Fri, May 03, 2013 at 09:50:53PM -0000, Thomas Gleixner wrote:
> > + /* Init mask cache ? */
> > + if (dgc->gc_flags & IRQ_GC_INIT_MASK_CACHE) {
> > + raw_spin_lock_irqsave(&gc->lock, flags);
> > + gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
> > + raw_spin_unlock_irqrestore(&gc->lock, flags);
> > + }
>
> This looks a little weird to me - it seems that it'll re-read this
> each time any irq is mapped in the domain, which is probably not
> wanted.
Yes, it's sloppy in two aspects.
1) It does not respect the per irq type mask cache, which got
introduced in the same series
2) It rereads the mask cache for each mapping, but thats harmless
because it's proper serialized. We can avoid that by clearing the
IRQ_GC_INIT_MASK_CACHE bit when the first irq of that chip is
mapped.
Congrats, you found a bug and as I said:
WARNING: It's compile tested only. So if you find bugs you can keep
them and fix them yourself :)
Thanks,
tglx
^ permalink raw reply [flat|nested] 74+ messages in thread
* [RFC patch 7/8] genirq: generic chip: Add linear irq domain support
2013-05-03 21:50 ` [RFC patch 7/8] genirq: generic chip: Add linear irq domain support Thomas Gleixner
2013-05-03 22:23 ` Russell King - ARM Linux
@ 2013-05-04 2:30 ` Sebastian Hesselbarth
2013-05-04 8:04 ` Thomas Gleixner
2013-05-06 12:32 ` [RFC patch 7/8] fixup 1/2: " Sebastian Hesselbarth
2 siblings, 1 reply; 74+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-04 2:30 UTC (permalink / raw)
To: linux-arm-kernel
On 05/03/2013 11:50 PM, Thomas Gleixner wrote:
> Provide infrastructure for irq chip implementations which work on
> linear irq domains.
Thomas,
I am happy that I put you into rant mode. It took me little more
than an hour to read through your patches, prepare orion irqchip
driver on top of them and finally got it working.
Anyway, I found some more issues.
> Index: linux-2.6/kernel/irq/generic-chip.c
> ===================================================================
> --- linux-2.6.orig/kernel/irq/generic-chip.c
> +++ linux-2.6/kernel/irq/generic-chip.c
> @@ -7,6 +7,7 @@
[...]
> +int irq_alloc_domain_generic_chips(struct irq_domain *d, int
irqs_per_chip,
> + int num_ct, const char *name,
> + irq_flow_handler_t handler,
> + unsigned int clr, unsigned int set,
> + enum irq_gc_flags gcflags)
> +{
> + struct irq_domain_chip_generic *dgc;
> + struct irq_chip_generic *gc;
> + int numchips, sz, i;
> + unsigned long flags;
> +
> + if (d->gc)
> + return -EBUSY;
> +
> + if (d->revmap_type != IRQ_DOMAIN_MAP_LINEAR)
> + return -EINVAL;
> +
> + numchips = d->revmap_data.linear.size / irqs_per_chip;
> + if (!numchips)
> + return -EINVAL;
> +
> + sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
> + sz *= numchips;
> + sz += sizeof(*dgc);
> +
> + dgc = kzalloc(sz, GFP_KERNEL);
> + if (!dgc)
> + return -ENOMEM;
> + dgc->irqs_per_chip = irqs_per_chip;
> + dgc->num_chips = numchips;
> + dgc->irq_flags_to_set = set;
> + dgc->irq_flags_to_clear = clr;
> + dgc->gc_flags = gcflags;
> + gc = dgc->gc;
> +
> + for (i = 0; i < numchips; i++, gc++) {
The memory you allocated for gc, num_ct * ct, and dgc doesn't allow
to increment through gc. gc is struct irq_chip_generic * but next
gc is@sizeof(*gc) + num_ct * sizeof(struct irq_chip_type).
This also affects indexing dgc->gc later.
I chose to fix it by having an index helper but that first maps
dgc-gc to unsigned char * and then adds the correct offset. Not
nice but it works. Maybe having real array of ptr to gc is more
intuitive here even if we will have to have split kzallocs.
> + irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
> + NULL, handler);
irq_init_generic_chip does not take care of initalizing ct
mask_cache ptr. This should be done here.
> + gc->domain = d;
> + raw_spin_lock_irqsave(&gc_lock, flags);
> + list_add_tail(&gc->list, &gc_list);
> + raw_spin_unlock_irqrestore(&gc_lock, flags);
> + }
> + d->gc = dgc;
Moving this assignment above the for loop allows to get
gc by index as indexing helper relies on domain, not domain
generic chip.
You want me to prepare patches for the above? Maybe you can
split your RFC into 1-6 and 7-8. Then you can have 1-6 applied
independently of irq_domain_generic_chip stuff.
Thanks for the RFC again!
Sebastian
^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 7/8] genirq: generic chip: Add linear irq domain support
2013-05-04 2:30 ` Sebastian Hesselbarth
@ 2013-05-04 8:04 ` Thomas Gleixner
0 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-04 8:04 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, 4 May 2013, Sebastian Hesselbarth wrote:
> On 05/03/2013 11:50 PM, Thomas Gleixner wrote:
> > Provide infrastructure for irq chip implementations which work on
> > linear irq domains.
>
> Thomas,
>
> I am happy that I put you into rant mode. It took me little more
> than an hour to read through your patches, prepare orion irqchip
> driver on top of them and finally got it working.
Cool.
> Anyway, I found some more issues.
That was expected. :)
> > + for (i = 0; i < numchips; i++, gc++) {
>
> The memory you allocated for gc, num_ct * ct, and dgc doesn't allow
> to increment through gc. gc is struct irq_chip_generic * but next
> gc is at sizeof(*gc) + num_ct * sizeof(struct irq_chip_type).
> This also affects indexing dgc->gc later.
Indeed.
> I chose to fix it by having an index helper but that first maps
> dgc-gc to unsigned char * and then adds the correct offset. Not
void * is the preferred over uchar *
> nice but it works. Maybe having real array of ptr to gc is more
> intuitive here even if we will have to have split kzallocs.
No, you still can have a single kzalloc. It's just a matter of setting
the pointers correctly.
> > + irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
> > + NULL, handler);
>
> irq_init_generic_chip does not take care of initalizing ct
> mask_cache ptr. This should be done here.
Right.
> > + gc->domain = d;
> > + raw_spin_lock_irqsave(&gc_lock, flags);
> > + list_add_tail(&gc->list, &gc_list);
> > + raw_spin_unlock_irqrestore(&gc_lock, flags);
> > + }
> > + d->gc = dgc;
>
> Moving this assignment above the for loop allows to get
> gc by index as indexing helper relies on domain, not domain
> generic chip.
>
> You want me to prepare patches for the above? Maybe you can
That'd be nice.
> split your RFC into 1-6 and 7-8. Then you can have 1-6 applied
> independently of irq_domain_generic_chip stuff.
> Thanks for the RFC again!
Welcome. Have fun!
tglx
^ permalink raw reply [flat|nested] 74+ messages in thread
* [RFC patch 7/8] fixup 1/2: genirq: generic chip: Add linear irq domain support
2013-05-03 21:50 ` [RFC patch 7/8] genirq: generic chip: Add linear irq domain support Thomas Gleixner
2013-05-03 22:23 ` Russell King - ARM Linux
2013-05-04 2:30 ` Sebastian Hesselbarth
@ 2013-05-06 12:32 ` Sebastian Hesselbarth
2013-05-06 12:32 ` [RFC patch 7/8] fixup 2/2: " Sebastian Hesselbarth
2013-05-06 13:25 ` [RFC patch 7/8] fixup 1/2: " Thomas Gleixner
2 siblings, 2 replies; 74+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-06 12:32 UTC (permalink / raw)
To: linux-arm-kernel
irq_domain_chip_generic is allocating and indexing irq_chip_generic
itself. However, the size of irq_chip_generic varies with number of
irq_chip_types. This fixup moves irq_chip_generic helt by
irq_domain_chip_generic to array of ptr and fixes the pointer arith
used by irq_alloc_domain_generic_chip.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Jean-Francois Moine <moinejf@free.fr>
Cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
include/linux/irq.h | 4 ++--
kernel/irq/generic-chip.c | 20 +++++++++++++-------
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 7315155..fd2d7cb 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -730,7 +730,7 @@ enum irq_gc_flags {
* @irq_flags_to_set: IRQ* flags to set on irq setup
* @irq_flags_to_clear: IRQ* flags to clear on irq setup
* @gc_flags: Generic chip specific setup flags
- * @gc: Array of generic interrupt chips
+ * @gc: Array of pointer to generic interrupt chips
*/
struct irq_domain_chip_generic {
unsigned int irqs_per_chip;
@@ -738,7 +738,7 @@ struct irq_domain_chip_generic {
unsigned int irq_flags_to_clear;
unsigned int irq_flags_to_set;
enum irq_gc_flags gc_flags;
- struct irq_chip_generic gc[0];
+ struct irq_chip_generic *gc[0];
};
/* Generic chip callback functions */
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index e212b26..3dbfe2e 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -247,6 +247,7 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
struct irq_chip_generic *gc;
int numchips, sz, i;
unsigned long flags;
+ void *p;
if (d->gc)
return -EBUSY;
@@ -260,9 +261,9 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
sz *= numchips;
- sz += sizeof(*dgc);
+ sz += sizeof(*dgc) + numchips * sizeof(void *);
- dgc = kzalloc(sz, GFP_KERNEL);
+ p = dgc = kzalloc(sz, GFP_KERNEL);
if (!dgc)
return -ENOMEM;
dgc->irqs_per_chip = irqs_per_chip;
@@ -270,17 +271,22 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
dgc->irq_flags_to_set = set;
dgc->irq_flags_to_clear = clr;
dgc->gc_flags = gcflags;
- gc = dgc->gc;
+ d->gc = dgc;
- for (i = 0; i < numchips; i++, gc++) {
+ p += sizeof(*dgc) + numchips * sizeof(void *);
+ for (i = 0; i < numchips; i++) {
+ gc = (struct irq_chip_generic *)p;
+ dgc->gc[i] = gc;
irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
NULL, handler);
gc->domain = d;
+
raw_spin_lock_irqsave(&gc_lock, flags);
list_add_tail(&gc->list, &gc_list);
raw_spin_unlock_irqrestore(&gc_lock, flags);
+
+ p += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
}
- d->gc = dgc;
return 0;
}
EXPORT_SYMBOL_GPL(irq_alloc_domain_generic_chips);
@@ -301,7 +307,7 @@ irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
idx = hw_irq / dgc->irqs_per_chip;
if (idx >= dgc->num_chips)
return NULL;
- return &dgc->gc[idx];
+ return dgc->gc[idx];
}
EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
@@ -331,7 +337,7 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
idx = hw_irq / dgc->irqs_per_chip;
if (idx >= dgc->num_chips)
return -EINVAL;
- gc = &dgc->gc[idx];
+ gc = dgc->gc[idx];
idx = hw_irq % dgc->irqs_per_chip;
--
1.7.2.5
^ permalink raw reply related [flat|nested] 74+ messages in thread* [RFC patch 7/8] fixup 2/2: genirq: generic chip: Add linear irq domain support
2013-05-06 12:32 ` [RFC patch 7/8] fixup 1/2: " Sebastian Hesselbarth
@ 2013-05-06 12:32 ` Sebastian Hesselbarth
2013-05-06 13:31 ` Thomas Gleixner
2013-05-06 13:25 ` [RFC patch 7/8] fixup 1/2: " Thomas Gleixner
1 sibling, 1 reply; 74+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-06 12:32 UTC (permalink / raw)
To: linux-arm-kernel
mask_cache pointer also needs to be initialized for domain generic
chips.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Jean-Francois Moine <moinejf@free.fr>
Cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
kernel/irq/generic-chip.c | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index 3dbfe2e..3e0312f 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -275,12 +275,22 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
p += sizeof(*dgc) + numchips * sizeof(void *);
for (i = 0; i < numchips; i++) {
+ int k;
+
gc = (struct irq_chip_generic *)p;
dgc->gc[i] = gc;
irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
NULL, handler);
gc->domain = d;
+ for (k = 0; k < gc->num_ct; k++) {
+ struct irq_chip_type *ct = &gc->chip_types[k];
+ if (gcflags & IRQ_GC_MASK_CACHE_PER_TYPE)
+ ct->mask_cache = &ct->mask_cache_priv;
+ else
+ ct->mask_cache = &gc->mask_cache;
+ }
+
raw_spin_lock_irqsave(&gc_lock, flags);
list_add_tail(&gc->list, &gc_list);
raw_spin_unlock_irqrestore(&gc_lock, flags);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 74+ messages in thread* [RFC patch 7/8] fixup 1/2: genirq: generic chip: Add linear irq domain support
2013-05-06 12:32 ` [RFC patch 7/8] fixup 1/2: " Sebastian Hesselbarth
2013-05-06 12:32 ` [RFC patch 7/8] fixup 2/2: " Sebastian Hesselbarth
@ 2013-05-06 13:25 ` Thomas Gleixner
1 sibling, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-06 13:25 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 6 May 2013, Sebastian Hesselbarth wrote:
> irq_domain_chip_generic is allocating and indexing irq_chip_generic
> itself. However, the size of irq_chip_generic varies with number of
> irq_chip_types. This fixup moves irq_chip_generic helt by
> irq_domain_chip_generic to array of ptr and fixes the pointer arith
> used by irq_alloc_domain_generic_chip.
Thanks. I folded it in.
^ permalink raw reply [flat|nested] 74+ messages in thread
* [RFC patch 8/8] irqchip: sun4i: Convert to generic irq chip
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
` (6 preceding siblings ...)
2013-05-03 21:50 ` [RFC patch 7/8] genirq: generic chip: Add linear irq domain support Thomas Gleixner
@ 2013-05-03 21:50 ` Thomas Gleixner
2013-05-04 2:37 ` Sebastian Hesselbarth
2013-05-06 9:48 ` [RFC patch 0/8] genirq: Support for irq domains in " Uwe Kleine-König
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
9 siblings, 1 reply; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-03 21:50 UTC (permalink / raw)
To: linux-arm-kernel
An embedded and charset-unspecified text was scrubbed...
Name: irqchip-convert-sun4i.patch
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130503/4bcdc237/attachment.ksh>
^ permalink raw reply [flat|nested] 74+ messages in thread* [RFC patch 8/8] irqchip: sun4i: Convert to generic irq chip
2013-05-03 21:50 ` [RFC patch 8/8] irqchip: sun4i: Convert to generic irq chip Thomas Gleixner
@ 2013-05-04 2:37 ` Sebastian Hesselbarth
0 siblings, 0 replies; 74+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-04 2:37 UTC (permalink / raw)
To: linux-arm-kernel
On 05/03/2013 11:50 PM, Thomas Gleixner wrote:
> Proof of concept patch to demonstrate the new irqdomain support for
> the generic irq chip. Untested !!
>
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
...
> + gc->reg_base = sun4i_irq_base;
> + gc->chip_types[0].regs.mask = SUN4I_IRQ_ENABLE_REG(i);
> + gc->chip_types[0].regs.ack = SUN4I_IRQ_PENDING_REG(i);
> + gc->chip_types[0].chip.mask = irq_gc_mask_clr_bit;
> + gc->chip_types[0].chip.ack = irq_gc_ack_set_bit;
> + gc->chip_types[0].chip.unmask = irq_gc_mask_set_bit;
To help Maxime debug, the three callbacks must be prepended by irq_,
i.e. chip.irq_mask, ...
Sebastian
^ permalink raw reply [flat|nested] 74+ messages in thread
* [RFC patch 0/8] genirq: Support for irq domains in generic irq chip
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
` (7 preceding siblings ...)
2013-05-03 21:50 ` [RFC patch 8/8] irqchip: sun4i: Convert to generic irq chip Thomas Gleixner
@ 2013-05-06 9:48 ` Uwe Kleine-König
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
9 siblings, 0 replies; 74+ messages in thread
From: Uwe Kleine-König @ 2013-05-06 9:48 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Fri, May 03, 2013 at 09:50:43PM -0000, Thomas Gleixner wrote:
> The ongoing device tree support for ARM is creating new irq chip
> drivers in drivers/irqchip/ in a frenzy. Quite some of them are
> ripping out the generic irq chip implementation from arch/arm/* and
> just creating the same mess of duplicated code again, which was
> cleaned up with the generic irq chip implementation with a lot of
> effort. Sigh!
>
> I already prodded a few people in reviews to tackle that issue with no
> outcome. Even more sigh!
>
> Poor Sebastian triggered me into rant mode, but he ad hoc
> volunteered to give it a try. YAY!
>
> Though he asked for a bit of kickstart help. So I squeezed out a few
> spare cycles and implemented the basics as far as I think that they
> should work.
>
> The following series contains the missing bits and pieces including a
> somehow forgotten and now slightly modified series from Gerlando
> adding support for irq chips which need separate mask caches for
> different chip (control flow) types.
>
> At the moment this supports only linear irq domains, but it could be
> extended to other types as well if the need arises. Though the ARM
> chips are pretty much all about linear domains AFAICT.
Is there a tree/set of patches that have already fixed the issues
pointed out by Russell and Sebastian? I'd like to use it to get forward
with my nvic patch and want to avert double work and merging different
approaches.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 74+ messages in thread* [patch 0/8] genirq: Support for irq domains in generic irq chip - V2
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
` (8 preceding siblings ...)
2013-05-06 9:48 ` [RFC patch 0/8] genirq: Support for irq domains in " Uwe Kleine-König
@ 2013-05-06 14:30 ` Thomas Gleixner
2013-05-06 14:30 ` [patch 1/8] genirq: generic chip: Remove the local cur_regs() function Thomas Gleixner
` (8 more replies)
9 siblings, 9 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-06 14:30 UTC (permalink / raw)
To: linux-arm-kernel
Changes vs. V1:
- Fixed the generic chip pointer thinko (Sebastian Hesselbarth)
- Proper support for mask cache
- Read mask hardware only for the first map of an generic chip
instance
- sun4i prefix irq functions proper
Thanks,
tglx
^ permalink raw reply [flat|nested] 74+ messages in thread* [patch 1/8] genirq: generic chip: Remove the local cur_regs() function
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
@ 2013-05-06 14:30 ` Thomas Gleixner
2013-05-06 14:30 ` [patch 2/8] genirq: generic chip: Add support for per chip type mask cache Thomas Gleixner
` (7 subsequent siblings)
8 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-06 14:30 UTC (permalink / raw)
To: linux-arm-kernel
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^ permalink raw reply [flat|nested] 74+ messages in thread* [patch 2/8] genirq: generic chip: Add support for per chip type mask cache
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
2013-05-06 14:30 ` [patch 1/8] genirq: generic chip: Remove the local cur_regs() function Thomas Gleixner
@ 2013-05-06 14:30 ` Thomas Gleixner
2013-05-06 14:30 ` [patch 3/8] genirq: generic chip: Handle separate mask registers Thomas Gleixner
` (6 subsequent siblings)
8 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-06 14:30 UTC (permalink / raw)
To: linux-arm-kernel
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Name: genirq-add-mask_cache-and-pmask_cache-into-struct-irq_chip_type.patch
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130506/e85bdaa2/attachment.ksh>
^ permalink raw reply [flat|nested] 74+ messages in thread* [patch 3/8] genirq: generic chip: Handle separate mask registers
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
2013-05-06 14:30 ` [patch 1/8] genirq: generic chip: Remove the local cur_regs() function Thomas Gleixner
2013-05-06 14:30 ` [patch 2/8] genirq: generic chip: Add support for per chip type mask cache Thomas Gleixner
@ 2013-05-06 14:30 ` Thomas Gleixner
2013-05-06 14:30 ` [patch 4/8] genirq: generic chip: Cache per irq bit mask Thomas Gleixner
` (5 subsequent siblings)
8 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-06 14:30 UTC (permalink / raw)
To: linux-arm-kernel
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Name: genirq-handle-separate-mask-registers.patch
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130506/5d841737/attachment.ksh>
^ permalink raw reply [flat|nested] 74+ messages in thread* [patch 4/8] genirq: generic chip: Cache per irq bit mask
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
` (2 preceding siblings ...)
2013-05-06 14:30 ` [patch 3/8] genirq: generic chip: Handle separate mask registers Thomas Gleixner
@ 2013-05-06 14:30 ` Thomas Gleixner
2013-05-06 14:30 ` [patch 5/8] genirq: Add a mask calculation function Thomas Gleixner
` (4 subsequent siblings)
8 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-06 14:30 UTC (permalink / raw)
To: linux-arm-kernel
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URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130506/31334bab/attachment.ksh>
^ permalink raw reply [flat|nested] 74+ messages in thread* [patch 5/8] genirq: Add a mask calculation function
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
` (3 preceding siblings ...)
2013-05-06 14:30 ` [patch 4/8] genirq: generic chip: Cache per irq bit mask Thomas Gleixner
@ 2013-05-06 14:30 ` Thomas Gleixner
2013-05-06 14:30 ` [patch 6/8] genirq: Split out code in generic chip Thomas Gleixner
` (3 subsequent siblings)
8 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-06 14:30 UTC (permalink / raw)
To: linux-arm-kernel
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^ permalink raw reply [flat|nested] 74+ messages in thread* [patch 6/8] genirq: Split out code in generic chip
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
` (4 preceding siblings ...)
2013-05-06 14:30 ` [patch 5/8] genirq: Add a mask calculation function Thomas Gleixner
@ 2013-05-06 14:30 ` Thomas Gleixner
2013-05-06 14:30 ` [patch 7/8] genirq: generic chip: Add linear irq domain support Thomas Gleixner
` (2 subsequent siblings)
8 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-06 14:30 UTC (permalink / raw)
To: linux-arm-kernel
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^ permalink raw reply [flat|nested] 74+ messages in thread* [patch 7/8] genirq: generic chip: Add linear irq domain support
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
` (5 preceding siblings ...)
2013-05-06 14:30 ` [patch 6/8] genirq: Split out code in generic chip Thomas Gleixner
@ 2013-05-06 14:30 ` Thomas Gleixner
2013-05-29 2:22 ` Grant Likely
2013-05-06 14:30 ` [patch 8/8] irqchip: sun4i: Convert to generic irq chip Thomas Gleixner
2013-10-01 15:27 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Gerlando Falauto
8 siblings, 1 reply; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-06 14:30 UTC (permalink / raw)
To: linux-arm-kernel
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^ permalink raw reply [flat|nested] 74+ messages in thread* [patch 7/8] genirq: generic chip: Add linear irq domain support
2013-05-06 14:30 ` [patch 7/8] genirq: generic chip: Add linear irq domain support Thomas Gleixner
@ 2013-05-29 2:22 ` Grant Likely
2013-05-29 8:23 ` Thomas Gleixner
0 siblings, 1 reply; 74+ messages in thread
From: Grant Likely @ 2013-05-29 2:22 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 06 May 2013 14:30:27 -0000, Thomas Gleixner <tglx@linutronix.de> wrote:
> Provide infrastructure for irq chip implementations which work on
> linear irq domains.
>
> - Interface to allocate multiple generic chips which are associated to
> the irq domain.
>
> - Interface to get the generic chip pointer for a particular hardware
> interrupt in the domain.
>
> - irq domain mapping function to install the chip for a particular
> interrupt.
>
> Note: This lacks a removal function for now, but this is a draft patch
> the ARM folks to work on.
>
> [ Sebastian Hesselbarth: Mask cache and pointer math fixups ]
>
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Hi Thomas,
Acked-by: Grant Likely <grant.likely@linaro.org>
But I have some comments below...
> ---
> include/linux/irq.h | 30 +++++++
> include/linux/irqdomain.h | 12 ++
> kernel/irq/generic-chip.c | 187 ++++++++++++++++++++++++++++++++++++++++++++--
> kernel/irq/irqdomain.c | 6 -
> 4 files changed, 223 insertions(+), 12 deletions(-)
>
> Index: linux-2.6/include/linux/irq.h
> ===================================================================
> --- linux-2.6.orig/include/linux/irq.h
> +++ linux-2.6/include/linux/irq.h
> @@ -678,6 +678,8 @@ struct irq_chip_type {
> * @wake_active: Interrupt is marked as an wakeup from suspend source
> * @num_ct: Number of available irq_chip_type instances (usually 1)
> * @private: Private data for non generic chip callbacks
> + * @installed: bitfield to denote installed interrupts
> + * @domain: irq domain pointer
> * @list: List head for keeping track of instances
> * @chip_types: Array of interrupt irq_chip_types
> *
> @@ -699,6 +701,8 @@ struct irq_chip_generic {
> u32 wake_active;
> unsigned int num_ct;
> void *private;
> + unsigned long installed;
This is probably something that the irqdomain should be keeping track of
internally, but that's an issue for a separate patch series.
[...]
> +struct irq_domain_ops irq_generic_chip_ops = {
> + .map = irq_map_generic_chip,
> + .xlate = irq_domain_xlate_onecell,
As discussed on IRC, should use onetwocell here for greater
compatibility with existing bindings.
Cheers,
g.
^ permalink raw reply [flat|nested] 74+ messages in thread* [patch 7/8] genirq: generic chip: Add linear irq domain support
2013-05-29 2:22 ` Grant Likely
@ 2013-05-29 8:23 ` Thomas Gleixner
0 siblings, 0 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-29 8:23 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 29 May 2013, Grant Likely wrote:
> > --- linux-2.6.orig/include/linux/irq.h
> > +++ linux-2.6/include/linux/irq.h
> > @@ -678,6 +678,8 @@ struct irq_chip_type {
> > * @wake_active: Interrupt is marked as an wakeup from suspend source
> > * @num_ct: Number of available irq_chip_type instances (usually 1)
> > * @private: Private data for non generic chip callbacks
> > + * @installed: bitfield to denote installed interrupts
> > + * @domain: irq domain pointer
> > * @list: List head for keeping track of instances
> > * @chip_types: Array of interrupt irq_chip_types
> > *
> > @@ -699,6 +701,8 @@ struct irq_chip_generic {
> > u32 wake_active;
> > unsigned int num_ct;
> > void *private;
> > + unsigned long installed;
>
> This is probably something that the irqdomain should be keeping track of
> internally, but that's an issue for a separate patch series.
Ok. I just need access to that information, so I can figure out if
it's the first irq of the chip which gets mapped. I need this for
initializing the mask cache.
> [...]
> > +struct irq_domain_ops irq_generic_chip_ops = {
> > + .map = irq_map_generic_chip,
> > + .xlate = irq_domain_xlate_onecell,
>
> As discussed on IRC, should use onetwocell here for greater
> compatibility with existing bindings.
Changed that.
Thanks,
tglx
^ permalink raw reply [flat|nested] 74+ messages in thread
* [patch 8/8] irqchip: sun4i: Convert to generic irq chip
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
` (6 preceding siblings ...)
2013-05-06 14:30 ` [patch 7/8] genirq: generic chip: Add linear irq domain support Thomas Gleixner
@ 2013-05-06 14:30 ` Thomas Gleixner
2013-05-06 15:18 ` Rob Herring
` (2 more replies)
2013-10-01 15:27 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Gerlando Falauto
8 siblings, 3 replies; 74+ messages in thread
From: Thomas Gleixner @ 2013-05-06 14:30 UTC (permalink / raw)
To: linux-arm-kernel
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^ permalink raw reply [flat|nested] 74+ messages in thread* [patch 8/8] irqchip: sun4i: Convert to generic irq chip
2013-05-06 14:30 ` [patch 8/8] irqchip: sun4i: Convert to generic irq chip Thomas Gleixner
@ 2013-05-06 15:18 ` Rob Herring
2013-05-12 14:05 ` [PATCH] irq-sun4i: Fix trivial build errors Maxime Ripard
2013-05-12 14:08 ` [patch 8/8] irqchip: sun4i: Convert to generic irq chip Maxime Ripard
2 siblings, 0 replies; 74+ messages in thread
From: Rob Herring @ 2013-05-06 15:18 UTC (permalink / raw)
To: linux-arm-kernel
On 05/06/2013 09:30 AM, Thomas Gleixner wrote:
> Proof of concept patch to demonstrate the new irqdomain support for
> the generic irq chip. Untested !!
>
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/irqchip/irq-sun4i.c | 100 ++++++++++++--------------------------------
> 1 file changed, 29 insertions(+), 71 deletions(-)
>
> Index: linux-2.6/drivers/irqchip/irq-sun4i.c
> ===================================================================
> --- linux-2.6.orig/drivers/irqchip/irq-sun4i.c
> +++ linux-2.6/drivers/irqchip/irq-sun4i.c
> @@ -32,70 +32,43 @@
> #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
> #define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
> #define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
> +#define SUN4I_NUM_CHIPS 3
> +#define SUN4I_IRQS_PER_CHIP 32
>
> static void __iomem *sun4i_irq_base;
> static struct irq_domain *sun4i_irq_domain;
>
> static asmlinkage void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
>
> -void sun4i_irq_ack(struct irq_data *irqd)
> +static int __init sun4i_init_domain_chips(void)
> {
> - unsigned int irq = irqd_to_hwirq(irqd);
> - unsigned int irq_off = irq % 32;
> - int reg = irq / 32;
> - u32 val;
> -
> - val = readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
> - writel(val | (1 << irq_off),
> - sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
> -}
> -
> -static void sun4i_irq_mask(struct irq_data *irqd)
> -{
> - unsigned int irq = irqd_to_hwirq(irqd);
> - unsigned int irq_off = irq % 32;
> - int reg = irq / 32;
> - u32 val;
> -
> - val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
> - writel(val & ~(1 << irq_off),
> - sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
> -}
> -
> -static void sun4i_irq_unmask(struct irq_data *irqd)
> -{
> - unsigned int irq = irqd_to_hwirq(irqd);
> - unsigned int irq_off = irq % 32;
> - int reg = irq / 32;
> - u32 val;
> -
> - val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
> - writel(val | (1 << irq_off),
> - sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
> -}
> -
> -static struct irq_chip sun4i_irq_chip = {
> - .name = "sun4i_irq",
> - .irq_ack = sun4i_irq_ack,
> - .irq_mask = sun4i_irq_mask,
> - .irq_unmask = sun4i_irq_unmask,
> -};
> -
> -static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
> - irq_hw_number_t hw)
> -{
> - irq_set_chip_and_handler(virq, &sun4i_irq_chip,
> - handle_level_irq);
> - set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
> -
> + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
> + struct irq_chip_generic *gc;
> + int i, ret, base = 0;
> +
> + ret = irq_alloc_domain_generic_chips(d, SUN4I_IRQS_PER_CHIP, 1,
1 should be SUN4I_NUM_CHIPS.
> + "sun4i_irq", handle_level_irq,
> + clr, 0, IRQ_GC_INIT_MASK_CACHE);
> + if (ret)
> + return ret;
> +
> + for (i = 0; i < SUN4I_NUM_CHIPS; i++, base += SUN4I_IRQS_PER_CHIP) {
> + gc = irq_get_domain_generic_chip(sun4i_irq_domain, base);
Perhaps this could be an iterator macro.
> + gc->reg_base = sun4i_irq_base;
> + gc->chip_types[0].regs.mask = SUN4I_IRQ_ENABLE_REG(i);
> + gc->chip_types[0].regs.ack = SUN4I_IRQ_PENDING_REG(i);
> + gc->chip_types[0].chip.mask = irq_gc_mask_clr_bit;
> + gc->chip_types[0].chip.ack = irq_gc_ack_set_bit;
> + gc->chip_types[0].chip.unmask = irq_gc_mask_set_bit;
> +
> + /* Disable, mask and clear all pending interrupts */
> + writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(i));
> + writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(i));
> + writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(i));
> + }
> return 0;
> }
>
> -static struct irq_domain_ops sun4i_irq_ops = {
> - .map = sun4i_irq_map,
> - .xlate = irq_domain_xlate_onecell,
> -};
> -
> static int __init sun4i_of_init(struct device_node *node,
> struct device_node *parent)
> {
> @@ -104,21 +77,6 @@ static int __init sun4i_of_init(struct d
> panic("%s: unable to map IC registers\n",
> node->full_name);
>
> - /* Disable all interrupts */
> - writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
> - writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
> - writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
> -
> - /* Mask all the interrupts */
> - writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
> - writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
> - writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
> -
> - /* Clear all the pending interrupts */
> - writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
> - writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
> - writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
> -
> /* Enable protection mode */
> writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
>
> @@ -126,8 +84,8 @@ static int __init sun4i_of_init(struct d
> writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
>
> sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
s/3 * 32/SUN4I_NUM_CHIPS * SUN4I_IRQS_PER_CHIP/
> - &sun4i_irq_ops, NULL);
> - if (!sun4i_irq_domain)
> + &irq_generic_chip_ops, NULL);
> + if (!sun4i_irq_domain || sun4i_init_domain_chips())
> panic("%s: unable to create IRQ domain\n", node->full_name);
>
> set_handle_irq(sun4i_handle_irq);
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH] irq-sun4i: Fix trivial build errors
2013-05-06 14:30 ` [patch 8/8] irqchip: sun4i: Convert to generic irq chip Thomas Gleixner
2013-05-06 15:18 ` Rob Herring
@ 2013-05-12 14:05 ` Maxime Ripard
2013-05-12 14:08 ` [patch 8/8] irqchip: sun4i: Convert to generic irq chip Maxime Ripard
2 siblings, 0 replies; 74+ messages in thread
From: Maxime Ripard @ 2013-05-12 14:05 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Jean-Francois Moine <moinejf@free.fr>
Cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/irqchip/irq-sun4i.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c
index 0191f2c..cab36b1 100644
--- a/drivers/irqchip/irq-sun4i.c
+++ b/drivers/irqchip/irq-sun4i.c
@@ -46,7 +46,8 @@ static int __init sun4i_init_domain_chips(void)
struct irq_chip_generic *gc;
int i, ret, base = 0;
- ret = irq_alloc_domain_generic_chips(d, SUN4I_IRQS_PER_CHIP, 1,
+ ret = irq_alloc_domain_generic_chips(sun4i_irq_domain,
+ SUN4I_IRQS_PER_CHIP, 1,
"sun4i_irq", handle_level_irq,
clr, 0, IRQ_GC_INIT_MASK_CACHE);
if (ret)
@@ -57,9 +58,9 @@ static int __init sun4i_init_domain_chips(void)
gc->reg_base = sun4i_irq_base;
gc->chip_types[0].regs.mask = SUN4I_IRQ_ENABLE_REG(i);
gc->chip_types[0].regs.ack = SUN4I_IRQ_PENDING_REG(i);
- gc->chip_types[0].chip.mask = irq_gc_mask_clr_bit;
- gc->chip_types[0].chip.ack = irq_gc_ack_set_bit;
- gc->chip_types[0].chip.unmask = irq_gc_mask_set_bit;
+ gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
+ gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
+ gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
/* Disable, mask and clear all pending interrupts */
writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(i));
--
1.8.1.2
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [patch 8/8] irqchip: sun4i: Convert to generic irq chip
2013-05-06 14:30 ` [patch 8/8] irqchip: sun4i: Convert to generic irq chip Thomas Gleixner
2013-05-06 15:18 ` Rob Herring
2013-05-12 14:05 ` [PATCH] irq-sun4i: Fix trivial build errors Maxime Ripard
@ 2013-05-12 14:08 ` Maxime Ripard
2013-05-12 14:14 ` Maxime Ripard
2 siblings, 1 reply; 74+ messages in thread
From: Maxime Ripard @ 2013-05-12 14:08 UTC (permalink / raw)
To: linux-arm-kernel
Hi Thomas,
Le 06/05/2013 16:30, Thomas Gleixner a ?crit :
> Proof of concept patch to demonstrate the new irqdomain support for
> the generic irq chip. Untested !!
>
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
I just tested it, and with the minor patch I sent, it's working fine.
You can add my
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 74+ messages in thread
* [patch 8/8] irqchip: sun4i: Convert to generic irq chip
2013-05-12 14:08 ` [patch 8/8] irqchip: sun4i: Convert to generic irq chip Maxime Ripard
@ 2013-05-12 14:14 ` Maxime Ripard
0 siblings, 0 replies; 74+ messages in thread
From: Maxime Ripard @ 2013-05-12 14:14 UTC (permalink / raw)
To: linux-arm-kernel
Le 12/05/2013 16:08, Maxime Ripard a ?crit :
> Hi Thomas,
>
> Le 06/05/2013 16:30, Thomas Gleixner a ?crit :
>> Proof of concept patch to demonstrate the new irqdomain support for
>> the generic irq chip. Untested !!
>>
>> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> I just tested it, and with the minor patch I sent, it's working fine.
>
> You can add my
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
After addressing the comments RobH already made that is.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 74+ messages in thread
* [patch 0/8] genirq: Support for irq domains in generic irq chip - V2
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
` (7 preceding siblings ...)
2013-05-06 14:30 ` [patch 8/8] irqchip: sun4i: Convert to generic irq chip Thomas Gleixner
@ 2013-10-01 15:27 ` Gerlando Falauto
8 siblings, 0 replies; 74+ messages in thread
From: Gerlando Falauto @ 2013-10-01 15:27 UTC (permalink / raw)
To: linux-arm-kernel
Hi Thomas, Sebastian,
I see these changes made it to 3.11.
AFAICT though, 3.10.9 still has the original bug (the one that got me to
write the patch for handling separate mask registers) and I am bit
confused as to how to integrate that back into 3.10 (or any previous
affected kernels, as they deserve a fix as well!).
The way I understand it, any mainstream patch would be based on this
work, which is not available on previous kernels. And I guess
backporting the whole thing would be overkill.
So I believe the only way to fix it on older kernels would be to write
one (or more) minimal version-specific patch series.
But then I wonder: would that be acceptable material for linux-stable?
Please correct me if I'm totally wrong here. I'm willing to help & test
but I need directions.
Thanks,
Gerlando
On 05/06/2013 04:30 PM, Thomas Gleixner wrote:
> Changes vs. V1:
>
> - Fixed the generic chip pointer thinko (Sebastian Hesselbarth)
>
> - Proper support for mask cache
>
> - Read mask hardware only for the first map of an generic chip
> instance
>
> - sun4i prefix irq functions proper
>
> Thanks,
>
> tglx
>
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth
2013-05-02 23:48 ` [PATCH v2 0/5] ARM: orion: add orion irqchip driver Sebastian Hesselbarth
2013-05-02 23:48 ` [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs Sebastian Hesselbarth
@ 2013-05-02 23:48 ` Sebastian Hesselbarth
2013-05-03 5:06 ` Andrew Lunn
2013-05-02 23:48 ` [PATCH v2 3/5] ARM: dove: add DT parsing for legacy timer Sebastian Hesselbarth
` (2 subsequent siblings)
4 siblings, 1 reply; 74+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-02 23:48 UTC (permalink / raw)
To: linux-arm-kernel
To allow to move to orion irqchip driver, existing legacy devices
have to map their irqs. This patch adds init code to map the
corresponding irqs. It will vanish as soon as there is true device tree
support for mv643xx_eth.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- split off DT changes (Suggested by Jason Cooper)
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Jean-Francois Moine <moinejf@free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
arch/arm/mach-dove/board-dt.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index fbde1dd..9df6dd7 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -12,6 +12,7 @@
#include <linux/clk-provider.h>
#include <linux/clk/mvebu.h>
#include <linux/of.h>
+#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <asm/hardware/cache-tauros2.h>
@@ -57,6 +58,34 @@ static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
};
+#define DOVE_GE00_PHYS_BASE 0xf1070000
+
+static void __init dove_legacy_ge00_init(void)
+{
+ struct device_node *np = of_find_compatible_node(NULL, NULL,
+ "marvell,mv643xx-eth-block");
+ int irq_sum, irq_err;
+
+ if (!np)
+ return;
+
+ irq_sum = irq_of_parse_and_map(np, 0);
+ if (!irq_sum) {
+ pr_err("%s: missing sum irq\n", np->full_name);
+ return;
+ }
+
+ irq_err = irq_of_parse_and_map(np, 1);
+ if (!irq_err) {
+ pr_err("%s: missing err irq\n", np->full_name);
+ return;
+ }
+
+ /* legacy ge00_init wants phys base */
+ orion_ge00_init(&dove_dt_ge00_data, DOVE_GE00_PHYS_BASE,
+ irq_sum, irq_err, 1600);
+}
+
static void __init dove_dt_init(void)
{
pr_info("Dove 88AP510 SoC\n");
@@ -70,7 +99,7 @@ static void __init dove_dt_init(void)
dove_of_clk_init();
/* Internal devices not ported to DT yet */
- dove_ge00_init(&dove_dt_ge00_data);
+ dove_legacy_ge00_init();
dove_pcie_init(1, 1);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 74+ messages in thread* [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth
2013-05-02 23:48 ` [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth Sebastian Hesselbarth
@ 2013-05-03 5:06 ` Andrew Lunn
2013-05-03 9:58 ` Sebastian Hesselbarth
2013-05-04 18:29 ` Jason Cooper
0 siblings, 2 replies; 74+ messages in thread
From: Andrew Lunn @ 2013-05-03 5:06 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 03, 2013 at 01:48:36AM +0200, Sebastian Hesselbarth wrote:
> To allow to move to orion irqchip driver, existing legacy devices
> have to map their irqs. This patch adds init code to map the
> corresponding irqs. It will vanish as soon as there is true device tree
> support for mv643xx_eth.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Changelog:
> v1->v2:
> - split off DT changes (Suggested by Jason Cooper)
>
> Cc: Grant Likely <grant.likely@linaro.org>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Rob Landley <rob@landley.net>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> Cc: Jean-Francois Moine <moinejf@free.fr>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: linux-doc at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
> arch/arm/mach-dove/board-dt.c | 31 ++++++++++++++++++++++++++++++-
> 1 file changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
> index fbde1dd..9df6dd7 100644
> --- a/arch/arm/mach-dove/board-dt.c
> +++ b/arch/arm/mach-dove/board-dt.c
> @@ -12,6 +12,7 @@
> #include <linux/clk-provider.h>
> #include <linux/clk/mvebu.h>
> #include <linux/of.h>
> +#include <linux/of_irq.h>
> #include <linux/of_platform.h>
> #include <linux/platform_data/usb-ehci-orion.h>
> #include <asm/hardware/cache-tauros2.h>
> @@ -57,6 +58,34 @@ static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
> .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
> };
>
> +#define DOVE_GE00_PHYS_BASE 0xf1070000
> +
> +static void __init dove_legacy_ge00_init(void)
> +{
> + struct device_node *np = of_find_compatible_node(NULL, NULL,
> + "marvell,mv643xx-eth-block");
> + int irq_sum, irq_err;
> +
> + if (!np)
> + return;
> +
> + irq_sum = irq_of_parse_and_map(np, 0);
> + if (!irq_sum) {
> + pr_err("%s: missing sum irq\n", np->full_name);
> + return;
> + }
> +
> + irq_err = irq_of_parse_and_map(np, 1);
> + if (!irq_err) {
> + pr_err("%s: missing err irq\n", np->full_name);
> + return;
> + }
> +
> + /* legacy ge00_init wants phys base */
> + orion_ge00_init(&dove_dt_ge00_data, DOVE_GE00_PHYS_BASE,
> + irq_sum, irq_err, 1600);
> +}
Hi Sebastian
I know the above code is throw away, but it might help with getting
Kirkwood, Orion5x, mv78xx00 supported if we refactor this code and
move most of it into plat-orion/common.c. I could imaging a function
orion_ge00_irq_init(struct mv643xx_eth_platform_data *eth_data,
unsigned long mapbase, unsigned int tx_csum_limit)
which does the irq lookup and then calls orion_ge00_init().
Jason: what is the status of the ethernet driver conversion to DT?
Will it get merged this week, or is it material for the next merge
window?
Andrew
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth
2013-05-03 5:06 ` Andrew Lunn
@ 2013-05-03 9:58 ` Sebastian Hesselbarth
2013-05-04 18:29 ` Jason Cooper
1 sibling, 0 replies; 74+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-03 9:58 UTC (permalink / raw)
To: linux-arm-kernel
On 05/03/2013 07:06 AM, Andrew Lunn wrote:
> On Fri, May 03, 2013 at 01:48:36AM +0200, Sebastian Hesselbarth wrote:
>> To allow to move to orion irqchip driver, existing legacy devices
>> have to map their irqs. This patch adds init code to map the
>> corresponding irqs. It will vanish as soon as there is true device tree
>> support for mv643xx_eth.
>>
>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth@gmail.com>
>> ---
>> Changelog:
>> v1->v2:
>> - split off DT changes (Suggested by Jason Cooper)
>>
>> Cc: Grant Likely<grant.likely@linaro.org>
>> Cc: Rob Herring<rob.herring@calxeda.com>
>> Cc: Rob Landley<rob@landley.net>
>> Cc: Thomas Gleixner<tglx@linutronix.de>
>> Cc: Russell King<linux@arm.linux.org.uk>
>> Cc: Arnd Bergmann<arnd@arndb.de>
>> Cc: Jason Cooper<jason@lakedaemon.net>
>> Cc: Andrew Lunn<andrew@lunn.ch>
>> Cc: Jason Gunthorpe<jgunthorpe@obsidianresearch.com>
>> Cc: Thomas Petazzoni<thomas.petazzoni@free-electrons.com>
>> Cc: Gregory Clement<gregory.clement@free-electrons.com>
>> Cc: Ezequiel Garcia<ezequiel.garcia@free-electrons.com>
>> Cc: Jean-Francois Moine<moinejf@free.fr>
>> Cc: devicetree-discuss at lists.ozlabs.org
>> Cc: linux-doc at vger.kernel.org
>> Cc: linux-arm-kernel at lists.infradead.org
>> Cc: linux-kernel at vger.kernel.org
>> ---
>> arch/arm/mach-dove/board-dt.c | 31 ++++++++++++++++++++++++++++++-
>> 1 file changed, 30 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
>> index fbde1dd..9df6dd7 100644
>> --- a/arch/arm/mach-dove/board-dt.c
>> +++ b/arch/arm/mach-dove/board-dt.c
>> @@ -12,6 +12,7 @@
>> #include<linux/clk-provider.h>
>> #include<linux/clk/mvebu.h>
>> #include<linux/of.h>
>> +#include<linux/of_irq.h>
>> #include<linux/of_platform.h>
>> #include<linux/platform_data/usb-ehci-orion.h>
>> #include<asm/hardware/cache-tauros2.h>
>> @@ -57,6 +58,34 @@ static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
>> .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
>> };
>>
>> +#define DOVE_GE00_PHYS_BASE 0xf1070000
>> +
>> +static void __init dove_legacy_ge00_init(void)
>> +{
>> + struct device_node *np = of_find_compatible_node(NULL, NULL,
>> + "marvell,mv643xx-eth-block");
>> + int irq_sum, irq_err;
>> +
>> + if (!np)
>> + return;
>> +
>> + irq_sum = irq_of_parse_and_map(np, 0);
>> + if (!irq_sum) {
>> + pr_err("%s: missing sum irq\n", np->full_name);
>> + return;
>> + }
>> +
>> + irq_err = irq_of_parse_and_map(np, 1);
>> + if (!irq_err) {
>> + pr_err("%s: missing err irq\n", np->full_name);
>> + return;
>> + }
>> +
>> + /* legacy ge00_init wants phys base */
>> + orion_ge00_init(&dove_dt_ge00_data, DOVE_GE00_PHYS_BASE,
>> + irq_sum, irq_err, 1600);
>> +}
>
> Hi Sebastian
>
> I know the above code is throw away, but it might help with getting
> Kirkwood, Orion5x, mv78xx00 supported if we refactor this code and
> move most of it into plat-orion/common.c. I could imaging a function
>
> orion_ge00_irq_init(struct mv643xx_eth_platform_data *eth_data,
> unsigned long mapbase, unsigned int tx_csum_limit)
>
> which does the irq lookup and then calls orion_ge00_init().
Andrew,
sure. Feel free to move legacy code to where all SoCs can use it.
> Jason: what is the status of the ethernet driver conversion to DT?
> Will it get merged this week, or is it material for the next merge
> window?
What I remember from Florian's work it was close to be released. I
never saw Florian sending an update to his patches, maybe he ran out
of time?
I guess DT timer will be a quick patch when we have all SoCs running
on DT irqchip and maybe Florian can update his patches even before we
sort out Thomas request. Then we could also merge DT timer within this
patch set and get rid of legacy helpers before we even introduce them.
Sebastian
^ permalink raw reply [flat|nested] 74+ messages in thread* [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth
2013-05-03 5:06 ` Andrew Lunn
2013-05-03 9:58 ` Sebastian Hesselbarth
@ 2013-05-04 18:29 ` Jason Cooper
1 sibling, 0 replies; 74+ messages in thread
From: Jason Cooper @ 2013-05-04 18:29 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 03, 2013 at 07:06:32AM +0200, Andrew Lunn wrote:
> Jason: what is the status of the ethernet driver conversion to DT?
> Will it get merged this week, or is it material for the next merge
> window?
You'd have to ask Florian/David Miller. I'm not sure wether David was
able to pull that in for v3.10 or not. He was pretty responsive to all
of the other changes Florian posted.
thx,
Jason.
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v2 3/5] ARM: dove: add DT parsing for legacy timer
2013-05-02 23:48 ` [PATCH v2 0/5] ARM: orion: add orion irqchip driver Sebastian Hesselbarth
2013-05-02 23:48 ` [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs Sebastian Hesselbarth
2013-05-02 23:48 ` [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth Sebastian Hesselbarth
@ 2013-05-02 23:48 ` Sebastian Hesselbarth
2013-05-02 23:48 ` [PATCH v2 4/5] ARM: dove: move DT boards to orion irqchip driver Sebastian Hesselbarth
2013-05-02 23:48 ` [PATCH v2 5/5] ARM: dove: add DT nodes for irqchip conversion Sebastian Hesselbarth
4 siblings, 0 replies; 74+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-02 23:48 UTC (permalink / raw)
To: linux-arm-kernel
To allow to move to orion irqchip driver, existing legacy devices
have to map their irqs. This patch adds init code to map the
corresponding irqs. It will vanish as soon as there is true device tree
support for orion timer.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- split off DT changes (Suggested by Jason Cooper)
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Jean-Francois Moine <moinejf@free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
arch/arm/mach-dove/board-dt.c | 42 +++++++++++++++++++++++++++++++++++------
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index 9df6dd7..cea65b7 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -12,6 +12,7 @@
#include <linux/clk-provider.h>
#include <linux/clk/mvebu.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_data/usb-ehci-orion.h>
@@ -20,6 +21,7 @@
#include <mach/pm.h>
#include <plat/common.h>
#include <plat/irq.h>
+#include <plat/time.h>
#include "common.h"
/*
@@ -48,10 +50,42 @@ static void __init dove_legacy_clk_init(void)
of_clk_get_from_provider(&clkspec));
}
-static void __init dove_of_clk_init(void)
+#define BRIDGE_INT_TIMER1_CLR (~0x0004)
+
+static void __init dove_legacy_timer_init(void)
{
+ struct device_node *np = of_find_compatible_node(NULL, NULL,
+ "marvell,orion-timer");
+ struct clk *clk;
+ void __iomem *base;
+ unsigned int tclk, irq;
+
+ /* Setup root of clk tree */
mvebu_clocks_init();
dove_legacy_clk_init();
+
+ if (!np)
+ panic("missing timer node\n");
+
+ base = of_iomap(np, 0);
+ if (!base)
+ panic("%s: missing reg base for timer\n", np->full_name);
+
+ irq = irq_of_parse_and_map(np, 0);
+ if (!irq)
+ panic("%s: missing irq for timer\n", np->full_name);
+
+ clk = of_clk_get(np, 0);
+ if (IS_ERR(clk))
+ panic("%s: missing clock for timer\n", np->full_name);
+
+ clk_prepare_enable(clk);
+ tclk = clk_get_rate(clk);
+ clk_put(clk);
+
+ orion_time_set_base(base);
+ /* legacy timer init gets bridge reg base */
+ orion_time_init(base - 0x300, BRIDGE_INT_TIMER1_CLR, irq, tclk);
}
static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
@@ -95,9 +129,6 @@ static void __init dove_dt_init(void)
#endif
dove_setup_cpu_mbus();
- /* Setup root of clk tree */
- dove_of_clk_init();
-
/* Internal devices not ported to DT yet */
dove_legacy_ge00_init();
dove_pcie_init(1, 1);
@@ -112,9 +143,8 @@ static const char * const dove_dt_board_compat[] = {
DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
.map_io = dove_map_io,
- .init_early = dove_init_early,
.init_irq = orion_dt_init_irq,
- .init_time = dove_timer_init,
+ .init_time = dove_legacy_timer_init,
.init_machine = dove_dt_init,
.restart = dove_restart,
.dt_compat = dove_dt_board_compat,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 74+ messages in thread* [PATCH v2 4/5] ARM: dove: move DT boards to orion irqchip driver
2013-05-02 23:48 ` [PATCH v2 0/5] ARM: orion: add orion irqchip driver Sebastian Hesselbarth
` (2 preceding siblings ...)
2013-05-02 23:48 ` [PATCH v2 3/5] ARM: dove: add DT parsing for legacy timer Sebastian Hesselbarth
@ 2013-05-02 23:48 ` Sebastian Hesselbarth
2013-05-02 23:48 ` [PATCH v2 5/5] ARM: dove: add DT nodes for irqchip conversion Sebastian Hesselbarth
4 siblings, 0 replies; 74+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-02 23:48 UTC (permalink / raw)
To: linux-arm-kernel
With legacy devices mapping their irqs, we can now switch DT enabled
boards to orion irqchip driver.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- split off DT changes (Suggested by Jason Cooper)
- use irqchip_init (Suggested by Jason Gunthorpe)
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Jean-Francois Moine <moinejf@free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
arch/arm/mach-dove/Kconfig | 1 +
arch/arm/mach-dove/Makefile | 4 ++--
arch/arm/mach-dove/board-dt.c | 4 ++--
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 36469d8..60d72b4 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -22,6 +22,7 @@ config MACH_CM_A510
config MACH_DOVE_DT
bool "Marvell Dove Flattened Device Tree"
+ select IRQCHIP_ORION
select MVEBU_CLK_CORE
select MVEBU_CLK_GATING
select REGULATOR
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 3f0a858..4780f78 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,5 +1,5 @@
-obj-y += common.o addr-map.o irq.o
-obj-$(CONFIG_DOVE_LEGACY) += mpp.o
+obj-y += common.o addr-map.o
+obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o
obj-$(CONFIG_PCI) += pcie.o
obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
obj-$(CONFIG_MACH_DOVE_DT) += board-dt.o
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index cea65b7..404c993 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/clk/mvebu.h>
+#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@@ -20,7 +21,6 @@
#include <asm/mach/arch.h>
#include <mach/pm.h>
#include <plat/common.h>
-#include <plat/irq.h>
#include <plat/time.h>
#include "common.h"
@@ -143,7 +143,7 @@ static const char * const dove_dt_board_compat[] = {
DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
.map_io = dove_map_io,
- .init_irq = orion_dt_init_irq,
+ .init_irq = irqchip_init,
.init_time = dove_legacy_timer_init,
.init_machine = dove_dt_init,
.restart = dove_restart,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 74+ messages in thread* [PATCH v2 5/5] ARM: dove: add DT nodes for irqchip conversion
2013-05-02 23:48 ` [PATCH v2 0/5] ARM: orion: add orion irqchip driver Sebastian Hesselbarth
` (3 preceding siblings ...)
2013-05-02 23:48 ` [PATCH v2 4/5] ARM: dove: move DT boards to orion irqchip driver Sebastian Hesselbarth
@ 2013-05-02 23:48 ` Sebastian Hesselbarth
4 siblings, 0 replies; 74+ messages in thread
From: Sebastian Hesselbarth @ 2013-05-02 23:48 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds required device tree nodes for irqchip conversion
on Dove. The nodes are named and layed out to allow seamless migration
to true DT enabled drivers as soon as they are available.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- merge DT changes into this patch (Suggested by Jason Cooper)
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Jean-Francois Moine <moinejf@free.fr>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
arch/arm/boot/dts/dove.dtsi | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 6cab468..afb719a 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -30,11 +30,18 @@
marvell,tauros2-cache-features = <0>;
};
+ timer: timer {
+ compatible = "marvell,orion-timer";
+ reg = <0x20300 0x20>;
+ interrupts = <0>;
+ clocks = <&core_clk 0>;
+ };
+
intc: interrupt-controller {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
- reg = <0x20204 0x04>, <0x20214 0x04>;
+ reg = <0x20200 0x10>, <0x20210 0x10>;
};
core_clk: core-clocks at d0214 {
@@ -202,6 +209,13 @@
status = "disabled";
};
+ gbe: ethernet-controller {
+ compatible = "marvell,mv643xx-eth-block";
+ reg = <0x72000 0x4000>;
+ interrupts = <29>, <30>;
+ status = "disabled";
+ };
+
rtc at d8500 {
compatible = "marvell,orion-rtc";
reg = <0xd8500 0x20>;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 74+ messages in thread