From: cdall@cs.columbia.edu (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building page tables
Date: Sun, 12 May 2013 22:17:37 -0700 [thread overview]
Message-ID: <20130513051737.GB64337@ubuntu> (raw)
In-Reply-To: <20130502151753.GB25022@mudshark.cambridge.arm.com>
On Thu, May 02, 2013 at 04:17:53PM +0100, Will Deacon wrote:
> On Thu, May 02, 2013 at 04:15:05PM +0100, Christoffer Dall wrote:
> > On Thu, May 2, 2013 at 8:03 AM, Will Deacon <will.deacon@arm.com> wrote:
> > > On Thu, May 02, 2013 at 03:39:00PM +0100, Marc Zyngier wrote:
> > >> Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
> > >> introduced code that flushes page tables to the point of coherency.
> > >> This is overkill (point of unification is enough and already done),
> > >> and actually not required if running on a SMP capable platform
> > >> (the HW PTW can snoop other cpus' L1).
> > >>
> > >> Remove this code and let ae8a8b9553bd (ARM: 7691/1: mm: kill unused
> > >> TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead) turn it into
> > >> a no-op for SMP ARMv7.
> > >>
> > >> Reported-by: Catalin Marinas <catalin.marinas@arm.com>
> > >> Cc: Will Deacon <will.deacon@arm.com>
> > >> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> > >> ---
> > >> arch/arm/kvm/mmu.c | 3 ---
> > >> 1 file changed, 3 deletions(-)
> > >>
> > >> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> > >> index 4a838db..d79b594 100644
> > >> --- a/arch/arm/kvm/mmu.c
> > >> +++ b/arch/arm/kvm/mmu.c
> > >> @@ -234,7 +234,6 @@ static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
> > >> pte = pte_offset_kernel(pmd, addr);
> > >> kvm_set_pte(pte, pfn_pte(pfn, prot));
> > >> get_page(virt_to_page(pte));
> > >> - kvm_flush_dcache_to_poc(pte, sizeof(*pte));
> > >> pfn++;
> > >> } while (addr += PAGE_SIZE, addr != end);
> > >
> > > Could you remove the flushing code out of kvm_set_pte, then flush the range
> > > after the loop? Then you get one flush and one barrier for the whole range.
> > >
> > that would be different from how it's done in the rest of the kernel
> > where you're expecting set_pte to do the necessary flushing for you,
> > no?
>
> Correct, but since kvm_set_pte seems only to be called from this file, I'm
> not sure you need to match thes rest of the kernel.
>
> > instead, if this optimization is worth it, the code could just use
> > pte_val(pte) = XX;
>
> or just *pte = XX;
>
That won't work with STRICT_M_TYPECHECKS though will it?
-Christoffer
next prev parent reply other threads:[~2013-05-13 5:17 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-02 14:38 [PATCH v2 0/5] ARM: KVM: various mmu related fixes for 3.10 Marc Zyngier
2013-05-02 14:38 ` [PATCH v2 1/5] ARM: KVM: be more thorough when invalidating TLBs Marc Zyngier
2013-05-02 15:13 ` Catalin Marinas
2013-05-08 10:46 ` Marc Zyngier
2013-05-02 14:38 ` [PATCH v2 2/5] ARM: KVM: remove dead prototype for __kvm_tlb_flush_vmid Marc Zyngier
2013-05-02 14:39 ` [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building page tables Marc Zyngier
2013-05-02 15:00 ` Catalin Marinas
2013-05-02 15:03 ` Will Deacon
2013-05-02 15:15 ` Christoffer Dall
2013-05-02 15:17 ` Will Deacon
2013-05-13 5:17 ` Christoffer Dall [this message]
2013-05-13 8:58 ` Will Deacon
2013-05-14 17:05 ` Christoffer Dall
2013-05-02 14:39 ` [PATCH v2 4/5] ARM: KVM: get rid of S2_PGD_SIZE Marc Zyngier
2013-05-02 14:39 ` [PATCH v2 5/5] ARM: KVM: use phys_addr_t instead of unsigned long long for HYP PGDs Marc Zyngier
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