From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic ldrd/strd instructions
Date: Wed, 22 May 2013 09:43:28 +0100 [thread overview]
Message-ID: <20130522084328.GC14322@arm.com> (raw)
In-Reply-To: <20130521180201.GB26251@mudshark.cambridge.arm.com>
On Tue, May 21, 2013 at 07:02:01PM +0100, Will Deacon wrote:
> On Mon, May 20, 2013 at 06:13:52PM +0100, Catalin Marinas wrote:
> > On Mon, May 20, 2013 at 05:04:07PM +0100, Will Deacon wrote:
> > > On Mon, May 20, 2013 at 04:11:58PM +0100, Catalin Marinas wrote:
> > > > Given that the ARM ARM isn't clear (though this is the case on the
> > > > actual implementations), user space may not necessarily assume that
> > > > LPAE==atomic doubles. That's why I think reporting the actual atomic
> > > > feature is better.
> > >
> > > The ARM ARM isn't too bad: it's just avoiding mandating 64-bit-wide paths
> > > around the entire SoC (and I've checked this with the architects). The only
> > > way we can probe this feature is using the MMFR0 and checking if LPAE is
> > > supported, and that's exactly what userspace will need to rely on.
> >
> > Well, LPAE implies atomic doubles but I wouldn't say that's the "only"
> > way, it can always be a feature of the CPU. Now, would the user
> > developers fully understand the implications of LPAE?
>
> I don't think it *can* be a feature of the CPU, because it depends on
> system-wide support. It could be a feature of an SoC, but per-SoC hwcaps
> isn't something we currently support. As I said, the only reason we can even
> probe this is because the architecture helps us out.
LPAE is also a feature of the CPU, not the SoC.
--
Catalin
next prev parent reply other threads:[~2013-05-22 8:43 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-17 17:07 [PATCH 00/14] Random LPAE-related patches Will Deacon
2013-05-17 17:07 ` [PATCH 01/14] ARM: LPAE: use signed arithmetic for mask definitions Will Deacon
2013-05-17 17:07 ` [PATCH 02/14] ARM: LPAE: use phys_addr_t in alloc_init_pud() Will Deacon
2013-05-17 17:07 ` [PATCH 03/14] ARM: LPAE: use phys_addr_t in free_memmap() Will Deacon
2013-05-17 17:07 ` [PATCH 04/14] ARM: LPAE: use phys_addr_t for initrd location Will Deacon
2013-05-17 17:07 ` [PATCH 05/14] ARM: LPAE: use phys_addr_t in switch_mm() Will Deacon
2013-05-17 17:07 ` [PATCH 06/14] ARM: LPAE: use 64-bit accessors for TTBR registers Will Deacon
2013-05-17 17:07 ` [PATCH 07/14] ARM: LPAE: factor out T1SZ and TTBR1 computations Will Deacon
2013-05-17 17:07 ` [PATCH 08/14] ARM: LPAE: accomodate >32-bit addresses for page table base Will Deacon
2013-05-17 17:07 ` [PATCH 09/14] ARM: mm: use physical addresses in highmem sanity checks Will Deacon
2013-05-17 17:07 ` [PATCH 10/14] ARM: fix type of PHYS_PFN_OFFSET to unsigned long Will Deacon
2013-05-17 17:07 ` [PATCH 11/14] ARM: mm: cleanup checks for membank overlap with vmalloc area Will Deacon
2013-05-17 17:07 ` [PATCH 12/14] ARM: mm: clean up membank size limit checks Will Deacon
2013-05-17 17:07 ` [PATCH 13/14] ARM: lpae: fix definition of PTE_HWTABLE_PTRS Will Deacon
2013-05-17 17:07 ` [PATCH 14/14] ARM: elf: add new hwcap for identifying atomic ldrd/strd instructions Will Deacon
2013-05-20 14:18 ` Catalin Marinas
2013-05-20 14:24 ` Will Deacon
2013-05-20 15:11 ` Catalin Marinas
2013-05-20 16:04 ` Will Deacon
2013-05-20 17:13 ` Catalin Marinas
2013-05-21 18:02 ` Will Deacon
2013-05-22 8:43 ` Catalin Marinas [this message]
2013-05-21 18:48 ` Rob Herring
2013-05-22 8:47 ` Catalin Marinas
2013-05-22 18:09 ` Will Deacon
2013-05-23 8:50 ` Catalin Marinas
2013-05-17 18:23 ` [PATCH 00/14] Random LPAE-related patches Santosh Shilimkar
2013-05-30 13:31 ` Subash Patel
2013-05-30 15:03 ` Will Deacon
2013-05-31 0:38 ` Kukjin Kim
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