From mboxrd@z Thu Jan  1 00:00:00 1970
From: jgunthorpe@obsidianresearch.com (Jason Gunthorpe)
Date: Thu, 23 May 2013 11:27:54 -0600
Subject: [PATCH 0/9] Switch internal registers address to 0xF1 on Armada
 370/XP
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To: linux-arm-kernel@lists.infradead.org
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On Thu, May 23, 2013 at 11:53:21AM +0200, Thomas Petazzoni wrote:

> This is not a problem, because the MBus Bridge Window {Base,Control}
> Register tell the CPU that memory accesses between addresses X and Y
> are for MBus windows, and the other accesses are for the DRAM.

Okay, I see, you are minimizing the size of the memory hole, sounds
good.

> > You can combine this idea with the CP15 signalling mechanism. Check
> > CP15 and use it to alter the DTB, similar to how ATAGs are used to
> > fixup the DTB. Don't relocate the registers.
> 
> Where would the code doing this would sit? Remember, this is a
> temporary solution that we want to get rid of after some time. So I've
> been very careful in this proposal to only touch mvebu-specific code.

Well, there are three elements here:
 1) Remove ARMADA_370_XP_REGS_PHYS_BASE and related (looks nearly done now)
 2) Adjust the FDT/DT before it is used based on CP15
 3) Support early printk

#1 looks like it is done when the mbus driver is merged, ie
   we will soon have full dynamic support for the internal regs base
#2 can be done in the machine's init_early, nothing will touch
   internal regs prior to init_early
#3 is for expert use, so the rules can be a bit different:
   - Patch the XP/370 specific early printk code to look in CP15
     to compute the base address
   - .. or rely on a CONFIG_XXX to set the serial base address
   - .. or parse the FDT to find the serial port, requiring
     that the developer has made the FDT match the bootloader.

So, I'm not sure what common code would need to be touched, do you see
something else?

Jason