* [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4
@ 2013-06-05 15:29 Aida Mynzhasova
2013-06-05 15:29 ` [PATCH 1/5] ARM: OMAP: DM81xx: multiple renames for DM81xx platform Aida Mynzhasova
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Aida Mynzhasova @ 2013-06-05 15:29 UTC (permalink / raw)
To: linux-arm-kernel
Not so long ago I tried to boot Linux 3.10-rc4 kernel on DM816x EVM
board. Unfortunately, my attempts were failed by reason of poor
support of DM81xx-based devices in new kernels.
Actually, on Linux 3.10-rc4 kernel early initialization of board
is failed when it tries to initialize power domains:
[ 0.000000] Unhandled fault: external abort on non-linefetch (0x1028)
at 0xfa17f8e4
[ 0.000000] Internal error: : 1028 [#1] SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted
3.10.0-rc3-00001-g0e5443c-dirty #12
[ 0.000000] task: c076fc50 ti: c0764000 task.ti: c0764000
[ 0.000000] PC is at omap2_pwrdm_wait_transition+0x1c/0xac
[ 0.000000] LR is at pwrdm_register_pwrdms+0x15c/0x1ac
[ 0.000000] pc : [<c0031698>] lr : [<c0036010>] psr: 60000193
[ 0.000000] sp : c0765f28 ip : c07bebe0 fp : 00000001
[ 0.000000] r10: c07e6a90 r9 : 00000000 r8 : c07e6944
[ 0.000000] r7 : c0754a50 r6 : c064f264 r5 : c0775298 r4 : c0773e9c
[ 0.000000] r3 : fffff8e4 r2 : fa17f8e4 r1 : 00000004 r0 : c0775298
[ 0.000000] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM
Segment kernel
[ 0.000000] Control: 10c5387d Table: 80004019 DAC: 00000017
[ 0.000000] Process swapper (pid: 0, stack limit = 0xc0764240)
[ 0.000000] Stack: (0xc0765f28 to 0xc0766000)
[ 0.000000] 5f20: c0773e9c c0775298 c064f264
c0754a50 c0773ee4 c0036010
[ 0.000000] 5f40: 35170034 81600134 c05125a8 fa180000 80000200
c0771348 c07b1b48 c07475ac
[ 0.000000] 5f60: c0771348 c07191fc c0647c40 c0711598 16c00000
c0d24fb4 c06450ac c070c148
[ 0.000000] 5f80: c0765f98 c0765f90 c0771134 c0765fdc 00000000
00000000 00000000 00000000
[ 0.000000] 5fa0: c0643878 00000001 00000000 c0748774 c0771134
c076c880 413fc082 00000000
[ 0.000000] 5fc0: 00000000 c07086fc 00000000 00000000 00000000
00000000 00000000 c0748778
[ 0.000000] 5fe0: 10c53c7d c076c910 c0748774 c0771134 80004059
80008074 00000000 00000000
[ 0.000000] [<c0031698>] (omap2_pwrdm_wait_transition+0x1c/0xac) from
[<c0036010>] (pwrdm_register_pwrdms+0x15c/0x1ac)
[ 0.000000] [<c0036010>] (pwrdm_register_pwrdms+0x15c/0x1ac) from
[<c07191fc>] (omap3xxx_powerdomains_init+0x50/0x144)
[ 0.000000] [<c07191fc>] (omap3xxx_powerdomains_init+0x50/0x144) from
[<c0711598>] (ti81xx_init_early+0xcc/0x178)
[ 0.000000] [<c0711598>] (ti81xx_init_early+0xcc/0x178) from
[<c070c148>] (setup_arch+0x5ac/0x800)
[ 0.000000] [<c070c148>] (setup_arch+0x5ac/0x800) from [<c07086fc>]
(start_kernel+0x7c/0x330)
[ 0.000000] [<c07086fc>] (start_kernel+0x7c/0x330) from [<80008074>]
(0x80008074)
[ 0.000000] Code: e1d030f8 e5982000 e28330e4 e0822003 (e5921000)
[ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
So, I suggest you this patch series, which fixes that kernel crush and
adds new functions/structures, required for early initialization on
DM816x (power and clock domains, hwmods). After applying these patches
the kernel is able to successfully continue booting till clock
initialization (will be added later).
Thanks,
Aida
Aida Mynzhasova (5):
ARM: OMAP: DM81xx: multiple renames for DM81xx platform
ARM: OMAP: AM33xx: multiple renames for early initialization
ARM: OMAP: DM816x: add powerdomains for DM816x
ARM: OMAP: DM816x: add clock domain support for DM816x
ARM: OMAP: DM816x: add hwmod support for DM81xx
arch/arm/Kconfig.debug | 12 +-
arch/arm/include/debug/omap2plus.S | 20 +-
arch/arm/mach-omap2/Kconfig | 16 +-
arch/arm/mach-omap2/Makefile | 22 +-
arch/arm/mach-omap2/am33xx-restart.c | 4 +-
arch/arm/mach-omap2/board-dm816x-evm.c | 62 +
arch/arm/mach-omap2/board-ti8168evm.c | 62 -
arch/arm/mach-omap2/cclock33xx_data.c | 990 ------
arch/arm/mach-omap2/cclock3xxx_data.c | 6 +-
arch/arm/mach-omap2/cclock_am33xx_data.c | 990 ++++++
arch/arm/mach-omap2/clock.h | 4 +-
arch/arm/mach-omap2/clockdomain.h | 3 +
arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 10 +
arch/arm/mach-omap2/clockdomains33xx_data.c | 196 --
arch/arm/mach-omap2/clockdomains_am33xx_data.c | 196 ++
arch/arm/mach-omap2/clockdomains_dm81xx_data.c | 213 ++
arch/arm/mach-omap2/cm-regbits-33xx.h | 817 -----
arch/arm/mach-omap2/cm-regbits-am33xx.h | 817 +++++
arch/arm/mach-omap2/cm-regbits-dm81xx.h | 22 +
arch/arm/mach-omap2/cm33xx.c | 364 ---
arch/arm/mach-omap2/cm33xx.h | 417 ---
arch/arm/mach-omap2/cm_am33xx.c | 364 +++
arch/arm/mach-omap2/cm_am33xx.h | 417 +++
arch/arm/mach-omap2/cm_dm81xx.h | 81 +
arch/arm/mach-omap2/common.h | 8 +-
arch/arm/mach-omap2/control.h | 8 +-
arch/arm/mach-omap2/dm81xx.h | 62 +
arch/arm/mach-omap2/dma.h | 12 +
arch/arm/mach-omap2/id.c | 20 +-
arch/arm/mach-omap2/include/mach/serial.h | 8 +-
arch/arm/mach-omap2/io.c | 32 +-
arch/arm/mach-omap2/irq.c | 4 +-
arch/arm/mach-omap2/omap_hwmod.c | 4 +-
arch/arm/mach-omap2/omap_hwmod.h | 1 +
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 3609 ----------------------
arch/arm/mach-omap2/omap_hwmod_am33xx_data.c | 3609 ++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_dm81xx_data.c | 1209 ++++++++
arch/arm/mach-omap2/omap_phy_internal.c | 18 +-
arch/arm/mach-omap2/powerdomain.h | 4 +
arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c | 43 +
arch/arm/mach-omap2/powerdomains33xx_data.c | 185 --
arch/arm/mach-omap2/powerdomains3xxx_data.c | 43 -
arch/arm/mach-omap2/powerdomains_am33xx_data.c | 185 ++
arch/arm/mach-omap2/powerdomains_dm81xx_data.c | 115 +
arch/arm/mach-omap2/prm-regbits-33xx.h | 357 ---
arch/arm/mach-omap2/prm-regbits-am33xx.h | 357 +++
arch/arm/mach-omap2/prm-regbits-dm81xx.h | 24 +
arch/arm/mach-omap2/prm33xx.c | 338 --
arch/arm/mach-omap2/prm33xx.h | 131 -
arch/arm/mach-omap2/prm_am33xx.c | 338 ++
arch/arm/mach-omap2/prm_am33xx.h | 131 +
arch/arm/mach-omap2/prm_dm81xx.c | 79 +
arch/arm/mach-omap2/prm_dm81xx.h | 44 +
arch/arm/mach-omap2/soc.h | 54 +-
arch/arm/mach-omap2/ti81xx.h | 36 -
arch/arm/mach-omap2/usb-musb.c | 4 +-
arch/arm/mach-omap2/usb.h | 12 +-
arch/arm/mach-omap2/voltagedomains33xx_data.c | 43 -
arch/arm/mach-omap2/voltagedomains_am33xx_data.c | 43 +
arch/arm/plat-omap/include/plat/dmtimer.h | 6 +
arch/arm/plat-omap/include/plat/irqs-dm81xx.h | 43 +
arch/arm/tools/mach-types | 4 +-
drivers/pci/quirks.c | 6 +-
drivers/usb/musb/musb_dsps.c | 12 +-
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 2 +-
include/linux/platform_data/davinci_asp.h | 2 +-
66 files changed, 9624 insertions(+), 7726 deletions(-)
create mode 100644 arch/arm/mach-omap2/board-dm816x-evm.c
delete mode 100644 arch/arm/mach-omap2/board-ti8168evm.c
delete mode 100644 arch/arm/mach-omap2/cclock33xx_data.c
create mode 100644 arch/arm/mach-omap2/cclock_am33xx_data.c
delete mode 100644 arch/arm/mach-omap2/clockdomains33xx_data.c
create mode 100644 arch/arm/mach-omap2/clockdomains_am33xx_data.c
create mode 100644 arch/arm/mach-omap2/clockdomains_dm81xx_data.c
delete mode 100644 arch/arm/mach-omap2/cm-regbits-33xx.h
create mode 100644 arch/arm/mach-omap2/cm-regbits-am33xx.h
create mode 100644 arch/arm/mach-omap2/cm-regbits-dm81xx.h
delete mode 100644 arch/arm/mach-omap2/cm33xx.c
delete mode 100644 arch/arm/mach-omap2/cm33xx.h
create mode 100644 arch/arm/mach-omap2/cm_am33xx.c
create mode 100644 arch/arm/mach-omap2/cm_am33xx.h
create mode 100644 arch/arm/mach-omap2/cm_dm81xx.h
create mode 100644 arch/arm/mach-omap2/dm81xx.h
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c
create mode 100644 arch/arm/mach-omap2/omap_hwmod_am33xx_data.c
create mode 100644 arch/arm/mach-omap2/omap_hwmod_dm81xx_data.c
delete mode 100644 arch/arm/mach-omap2/powerdomains33xx_data.c
create mode 100644 arch/arm/mach-omap2/powerdomains_am33xx_data.c
create mode 100644 arch/arm/mach-omap2/powerdomains_dm81xx_data.c
delete mode 100644 arch/arm/mach-omap2/prm-regbits-33xx.h
create mode 100644 arch/arm/mach-omap2/prm-regbits-am33xx.h
create mode 100644 arch/arm/mach-omap2/prm-regbits-dm81xx.h
delete mode 100644 arch/arm/mach-omap2/prm33xx.c
delete mode 100644 arch/arm/mach-omap2/prm33xx.h
create mode 100644 arch/arm/mach-omap2/prm_am33xx.c
create mode 100644 arch/arm/mach-omap2/prm_am33xx.h
create mode 100644 arch/arm/mach-omap2/prm_dm81xx.c
create mode 100644 arch/arm/mach-omap2/prm_dm81xx.h
delete mode 100644 arch/arm/mach-omap2/ti81xx.h
delete mode 100644 arch/arm/mach-omap2/voltagedomains33xx_data.c
create mode 100644 arch/arm/mach-omap2/voltagedomains_am33xx_data.c
create mode 100644 arch/arm/plat-omap/include/plat/irqs-dm81xx.h
--
1.7.10.4
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/5] ARM: OMAP: DM81xx: multiple renames for DM81xx platform
2013-06-05 15:29 [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4 Aida Mynzhasova
@ 2013-06-05 15:29 ` Aida Mynzhasova
2013-06-05 15:29 ` [PATCH 3/5] ARM: OMAP: DM816x: add powerdomains for DM816x Aida Mynzhasova
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Aida Mynzhasova @ 2013-06-05 15:29 UTC (permalink / raw)
To: linux-arm-kernel
This patch renames all DM81xx platform related structures, variables,
files, and functions. Previously names with "ti81" prefixes were used,
which are inconsistent, because actual name of the platform is DM81xx.
Also, for the same reason DM816x EVM was renamed from board-ti8168evm
to board-dm816x-evm.
Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
---
arch/arm/Kconfig.debug | 12 +++---
arch/arm/include/debug/omap2plus.S | 20 +++++-----
arch/arm/mach-omap2/Kconfig | 16 ++++----
arch/arm/mach-omap2/Makefile | 4 +-
arch/arm/mach-omap2/board-dm816x-evm.c | 62 +++++++++++++++++++++++++++++
arch/arm/mach-omap2/board-ti8168evm.c | 62 -----------------------------
arch/arm/mach-omap2/cclock3xxx_data.c | 6 +--
arch/arm/mach-omap2/clock.h | 4 +-
arch/arm/mach-omap2/common.h | 8 ++--
arch/arm/mach-omap2/control.h | 8 ++--
arch/arm/mach-omap2/dm81xx.h | 36 +++++++++++++++++
arch/arm/mach-omap2/id.c | 20 +++++-----
arch/arm/mach-omap2/include/mach/serial.h | 8 ++--
arch/arm/mach-omap2/io.c | 26 ++++++------
arch/arm/mach-omap2/irq.c | 4 +-
arch/arm/mach-omap2/omap_phy_internal.c | 18 ++++-----
arch/arm/mach-omap2/soc.h | 54 ++++++++++++-------------
arch/arm/mach-omap2/ti81xx.h | 36 -----------------
arch/arm/mach-omap2/usb-musb.c | 4 +-
arch/arm/mach-omap2/usb.h | 12 +++---
arch/arm/tools/mach-types | 4 +-
drivers/pci/quirks.c | 6 +--
drivers/usb/musb/musb_dsps.c | 12 +++---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 2 +-
include/linux/platform_data/davinci_asp.h | 2 +-
25 files changed, 223 insertions(+), 223 deletions(-)
create mode 100644 arch/arm/mach-omap2/board-dm816x-evm.c
delete mode 100644 arch/arm/mach-omap2/board-ti8168evm.c
create mode 100644 arch/arm/mach-omap2/dm81xx.h
delete mode 100644 arch/arm/mach-omap2/ti81xx.h
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1d41908..55e18d6 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -571,14 +571,14 @@ choice
config DEBUG_OMAP4UART4
bool "OMAP4/5 UART4"
- config DEBUG_TI81XXUART1
- bool "TI81XX UART1 (ti8148evm)"
+ config DEBUG_DM81XXUART1
+ bool "DM81XX UART1 (DM8148evm)"
- config DEBUG_TI81XXUART2
- bool "TI81XX UART2"
+ config DEBUG_DM81XXUART2
+ bool "DM81XX UART2"
- config DEBUG_TI81XXUART3
- bool "TI81XX UART3 (ti8168evm)"
+ config DEBUG_DM81XXUART3
+ bool "DM81XX UART3 (DM8168evm)"
config DEBUG_AM33XXUART1
bool "AM33XX UART1"
diff --git a/arch/arm/include/debug/omap2plus.S b/arch/arm/include/debug/omap2plus.S
index 6d867ae..76d643b 100644
--- a/arch/arm/include/debug/omap2plus.S
+++ b/arch/arm/include/debug/omap2plus.S
@@ -30,10 +30,10 @@
#define OMAP4_UART3_BASE 0x48020000
#define OMAP4_UART4_BASE 0x4806e000
-/* TI81XX serial ports */
-#define TI81XX_UART1_BASE 0x48020000
-#define TI81XX_UART2_BASE 0x48022000
-#define TI81XX_UART3_BASE 0x48024000
+/* DM81XX serial ports */
+#define DM81XX_UART1_BASE 0x48020000
+#define DM81XX_UART2_BASE 0x48022000
+#define DM81XX_UART3_BASE 0x48024000
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
@@ -111,16 +111,16 @@ omap_uart_lsr: .word 0
mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
b 98f
#endif
-#ifdef CONFIG_DEBUG_TI81XXUART1
- mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
+#ifdef CONFIG_DEBUG_DM81XXUART1
+ mov \rp, #UART_OFFSET(DM81XX_UART1_BASE)
b 98f
#endif
-#ifdef CONFIG_DEBUG_TI81XXUART2
- mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
+#ifdef CONFIG_DEBUG_DM81XXUART2
+ mov \rp, #UART_OFFSET(DM81XX_UART2_BASE)
b 98f
#endif
-#ifdef CONFIG_DEBUG_TI81XXUART3
- mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
+#ifdef CONFIG_DEBUG_DM81XXUART3
+ mov \rp, #UART_OFFSET(DM81XX_UART3_BASE)
b 98f
#endif
#ifdef CONFIG_DEBUG_AM33XXUART1
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51..376600b 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -135,8 +135,8 @@ config SOC_OMAP3430
default y
select SOC_HAS_OMAP2_SDRC
-config SOC_TI81XX
- bool "TI81XX support"
+config SOC_DM81XX
+ bool "DM81xx support"
depends on ARCH_OMAP3
default y
@@ -368,14 +368,14 @@ config MACH_OMAP_3630SDP
default y
select OMAP_PACKAGE_CBP
-config MACH_TI8168EVM
- bool "TI8168 Evaluation Module"
- depends on SOC_TI81XX
+config MACH_DM816X_EVM
+ bool "DM816x Evaluation Module"
+ depends on SOC_DM81XX
default y
-config MACH_TI8148EVM
- bool "TI8148 Evaluation Module"
- depends on SOC_TI81XX
+config MACH_DM814X_EVM
+ bool "DM814x Evaluation Module"
+ depends on SOC_DM81XX
default y
config MACH_OMAP_4430SDP
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d67..abbd043 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -259,8 +259,8 @@ obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o
-obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
-obj-$(CONFIG_MACH_TI8148EVM) += board-ti8168evm.o
+obj-$(CONFIG_MACH_DM816X_EVM) += board-dm816x-evm.o
+obj-$(CONFIG_MACH_DM814X_EVM) += board-dm816x-evm.o
# Platform specific device init code
diff --git a/arch/arm/mach-omap2/board-dm816x-evm.c b/arch/arm/mach-omap2/board-dm816x-evm.c
new file mode 100644
index 0000000..05a958b
--- /dev/null
+++ b/arch/arm/mach-omap2/board-dm816x-evm.c
@@ -0,0 +1,62 @@
+/*
+ * Code for DM816x/DM814x EVM.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/usb/musb.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "common.h"
+
+static struct omap_musb_board_data musb_board_data = {
+ .set_phy_power = dm81xx_musb_phy_power,
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 500,
+};
+
+static void __init dm81xx_evm_init(void)
+{
+ omap_serial_init();
+ omap_sdrc_init(NULL, NULL);
+ usb_musb_init(&musb_board_data);
+}
+
+MACHINE_START(DM816X_EVM, "dm816x_evm")
+ /* Maintainer: Texas Instruments */
+ .atag_offset = 0x100,
+ .map_io = dm81xx_map_io,
+ .init_early = dm81xx_init_early,
+ .init_irq = dm81xx_init_irq,
+ .init_time = omap3_sync32k_timer_init,
+ .init_machine = dm81xx_evm_init,
+ .init_late = dm81xx_init_late,
+ .restart = omap44xx_restart,
+MACHINE_END
+
+MACHINE_START(DM814X_EVM, "dm814x_evm")
+ /* Maintainer: Texas Instruments */
+ .atag_offset = 0x100,
+ .map_io = dm81xx_map_io,
+ .init_early = dm81xx_init_early,
+ .init_irq = dm81xx_init_irq,
+ .init_time = omap3_sync32k_timer_init,
+ .init_machine = dm81xx_evm_init,
+ .init_late = dm81xx_init_late,
+ .restart = omap44xx_restart,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
deleted file mode 100644
index 6273c28..0000000
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Code for TI8168/TI8148 EVM.
- *
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/usb/musb.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-
-static struct omap_musb_board_data musb_board_data = {
- .set_phy_power = ti81xx_musb_phy_power,
- .interface_type = MUSB_INTERFACE_ULPI,
- .mode = MUSB_OTG,
- .power = 500,
-};
-
-static void __init ti81xx_evm_init(void)
-{
- omap_serial_init();
- omap_sdrc_init(NULL, NULL);
- usb_musb_init(&musb_board_data);
-}
-
-MACHINE_START(TI8168EVM, "ti8168evm")
- /* Maintainer: Texas Instruments */
- .atag_offset = 0x100,
- .map_io = ti81xx_map_io,
- .init_early = ti81xx_init_early,
- .init_irq = ti81xx_init_irq,
- .init_time = omap3_sync32k_timer_init,
- .init_machine = ti81xx_evm_init,
- .init_late = ti81xx_init_late,
- .restart = omap44xx_restart,
-MACHINE_END
-
-MACHINE_START(TI8148EVM, "ti8148evm")
- /* Maintainer: Texas Instruments */
- .atag_offset = 0x100,
- .map_io = ti81xx_map_io,
- .init_early = ti81xx_init_early,
- .init_irq = ti81xx_init_irq,
- .init_time = omap3_sync32k_timer_init,
- .init_machine = ti81xx_evm_init,
- .init_late = ti81xx_init_late,
- .restart = omap44xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 45cd264..8df75b3 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3596,8 +3596,8 @@ int __init omap3xxx_clk_init(void)
omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
} else if (soc_is_am33xx()) {
cpu_mask = RATE_IN_AM33XX;
- } else if (cpu_is_ti814x()) {
- cpu_mask = RATE_IN_TI814X;
+ } else if (cpu_is_dm814x()) {
+ cpu_mask = RATE_IN_DM814X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
@@ -3641,7 +3641,7 @@ int __init omap3xxx_clk_init(void)
* Lock DPLL5 -- here only until other device init code can
* handle this
*/
- if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
+ if (!cpu_is_dm81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd..6187196 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -133,10 +133,10 @@ struct clockdomain;
#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
#define RATE_IN_36XX (1 << 4)
#define RATE_IN_4430 (1 << 5)
-#define RATE_IN_TI816X (1 << 6)
+#define RATE_IN_DM816X (1 << 6)
#define RATE_IN_4460 (1 << 7)
#define RATE_IN_AM33XX (1 << 8)
-#define RATE_IN_TI814X (1 << 9)
+#define RATE_IN_DM814X (1 << 9)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2..5cc3132 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -94,7 +94,7 @@ void omap3630_init_early(void);
void omap3_init_early(void); /* Do not use this one */
void am33xx_init_early(void);
void am35xx_init_early(void);
-void ti81xx_init_early(void);
+void dm81xx_init_early(void);
void am33xx_init_early(void);
void omap4430_init_early(void);
void omap5_init_early(void);
@@ -106,7 +106,7 @@ void omap3430_init_late(void);
void omap35xx_init_late(void);
void omap3630_init_late(void);
void am35xx_init_late(void);
-void ti81xx_init_late(void);
+void dm81xx_init_late(void);
int omap2_common_pm_late_init(void);
#ifdef CONFIG_SOC_BUS
@@ -158,7 +158,7 @@ void __init omap3_map_io(void);
void __init am33xx_map_io(void);
void __init omap4_map_io(void);
void __init omap5_map_io(void);
-void __init ti81xx_map_io(void);
+void __init dm81xx_map_io(void);
/* omap_barriers_init() is OMAP4 only */
void omap_barriers_init(void);
@@ -190,7 +190,7 @@ extern struct device *omap4_get_dsp_device(void);
void omap2_init_irq(void);
void omap3_init_irq(void);
-void ti81xx_init_irq(void);
+void dm81xx_init_irq(void);
extern int omap_irq_pending(void);
void omap_intc_save_context(void);
void omap_intc_restore_context(void);
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index e6c3281..03d4166 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -57,8 +57,8 @@
#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
-/* TI81XX spefic control submodules */
-#define TI81XX_CONTROL_DEVCONF 0x600
+/* DM81XX spefic control submodules */
+#define DM81XX_CONTROL_DEVCONF 0x600
/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
@@ -251,8 +251,8 @@
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
-/* TI81XX CONTROL_DEVCONF register offsets */
-#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
+/* DM81XX CONTROL_DEVCONF register offsets */
+#define DM81XX_CONTROL_DEVICE_ID (DM81XX_CONTROL_DEVCONF + 0x000)
/* OMAP54XX CONTROL STATUS register */
#define OMAP5XXX_CONTROL_STATUS 0x134
diff --git a/arch/arm/mach-omap2/dm81xx.h b/arch/arm/mach-omap2/dm81xx.h
new file mode 100644
index 0000000..a0b18a6
--- /dev/null
+++ b/arch/arm/mach-omap2/dm81xx.h
@@ -0,0 +1,36 @@
+/*
+ * This file contains the address data for various DM81xx modules.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_DM81XX_H
+#define __ASM_ARCH_DM81XX_H
+
+#define L4_SLOW_DM81XX_BASE 0x48000000
+
+#define DM81XX_SCM_BASE 0x48140000
+#define DM81XX_CTRL_BASE DM81XX_SCM_BASE
+#define DM81XX_PRCM_BASE 0x48180000
+
+/*
+ * Adjust TAP register base such that omap3_check_revision accesses the correct
+ * DM81XX register for checking device ID (it adds 0x204 to tap base while
+ * DM81XX DEVICE ID register is@offset 0x600 from control base).
+ */
+#define DM81XX_TAP_BASE (DM81XX_CTRL_BASE + \
+ DM81XX_CONTROL_DEVICE_ID - 0x204)
+
+
+#define DM81XX_ARM_INTC_BASE 0x48200000
+
+#endif /* __ASM_ARCH_DM81XX_H */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1272c41..91f1f2f 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -205,12 +205,12 @@ static void __init omap3_cpuinfo(void)
cpu_name = "OMAP3630";
} else if (soc_is_am35xx()) {
cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
- } else if (cpu_is_ti816x()) {
- cpu_name = "TI816X";
+ } else if (cpu_is_dm816x()) {
+ cpu_name = "DM816X";
} else if (soc_is_am335x()) {
cpu_name = "AM335X";
- } else if (cpu_is_ti814x()) {
- cpu_name = "TI814X";
+ } else if (cpu_is_dm814x()) {
+ cpu_name = "DM814X";
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
cpu_name = "OMAP3430/3530";
@@ -296,7 +296,7 @@ void __init omap4xxx_check_features(void)
omap_features = OMAP4_HAS_PERF_SILICON;
}
-void __init ti81xx_check_features(void)
+void __init dm81xx_check_features(void)
{
omap_features = OMAP3_HAS_NEON;
omap3_cpuinfo();
@@ -401,13 +401,13 @@ void __init omap3xxx_check_revision(void)
case 0xb81e:
switch (rev) {
case 0:
- omap_revision = TI8168_REV_ES1_0;
+ omap_revision = DM8168_REV_ES1_0;
cpu_rev = "1.0";
break;
case 1:
/* FALLTHROUGH */
default:
- omap_revision = TI8168_REV_ES1_1;
+ omap_revision = DM8168_REV_ES1_1;
cpu_rev = "1.1";
break;
}
@@ -435,17 +435,17 @@ void __init omap3xxx_check_revision(void)
case 0:
/* FALLTHROUGH */
case 1:
- omap_revision = TI8148_REV_ES1_0;
+ omap_revision = DM8148_REV_ES1_0;
cpu_rev = "1.0";
break;
case 2:
- omap_revision = TI8148_REV_ES2_0;
+ omap_revision = DM8148_REV_ES2_0;
cpu_rev = "2.0";
break;
case 3:
/* FALLTHROUGH */
default:
- omap_revision = TI8148_REV_ES2_1;
+ omap_revision = DM8148_REV_ES2_1;
cpu_rev = "2.1";
break;
}
diff --git a/arch/arm/mach-omap2/include/mach/serial.h b/arch/arm/mach-omap2/include/mach/serial.h
index 7ca1fcf..c648773 100644
--- a/arch/arm/mach-omap2/include/mach/serial.h
+++ b/arch/arm/mach-omap2/include/mach/serial.h
@@ -26,10 +26,10 @@
#define OMAP4_UART3_BASE 0x48020000
#define OMAP4_UART4_BASE 0x4806e000
-/* TI81XX serial ports */
-#define TI81XX_UART1_BASE 0x48020000
-#define TI81XX_UART2_BASE 0x48022000
-#define TI81XX_UART3_BASE 0x48024000
+/* DM81XX serial ports */
+#define DM81XX_UART1_BASE 0x48020000
+#define DM81XX_UART2_BASE 0x48022000
+#define DM81XX_UART3_BASE 0x48024000
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99..3deba6e 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -191,8 +191,8 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
};
#endif
-#ifdef CONFIG_SOC_TI81XX
-static struct map_desc omapti81xx_io_desc[] __initdata = {
+#ifdef CONFIG_SOC_DM81XX
+static struct map_desc omapdm81xx_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
@@ -311,10 +311,10 @@ void __init omap3_map_io(void)
}
#endif
-#ifdef CONFIG_SOC_TI81XX
-void __init ti81xx_map_io(void)
+#ifdef CONFIG_SOC_DM81XX
+void __init dm81xx_map_io(void)
{
- iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
+ iotable_init(omapdm81xx_io_desc, ARRAY_SIZE(omapdm81xx_io_desc));
}
#endif
@@ -505,16 +505,16 @@ void __init am35xx_init_early(void)
omap3_init_early();
}
-void __init ti81xx_init_early(void)
+void __init dm81xx_init_early(void)
{
omap2_set_globals_tap(OMAP343X_CLASS,
- OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
- omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
+ OMAP2_L4_IO_ADDRESS(DM81XX_TAP_BASE));
+ omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(DM81XX_CTRL_BASE),
NULL);
- omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
- omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
+ omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(DM81XX_PRCM_BASE));
+ omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DM81XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
- ti81xx_check_features();
+ dm81xx_check_features();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap3xxx_clockdomains_init();
@@ -558,7 +558,7 @@ void __init am35xx_init_late(void)
omap2_clk_enable_autoidle_all();
}
-void __init ti81xx_init_late(void)
+void __init dm81xx_init_late(void)
{
omap_common_late_init();
omap3_pm_init();
@@ -576,7 +576,7 @@ void __init am33xx_init_early(void)
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
- ti81xx_check_features();
+ dm81xx_check_features();
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 3926f37..6001cf6 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -214,7 +214,7 @@ void __init omap3_init_irq(void)
omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
}
-void __init ti81xx_init_irq(void)
+void __init dm81xx_init_irq(void)
{
omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
}
@@ -233,7 +233,7 @@ static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs
goto out;
irqnr = readl_relaxed(base_addr + 0xd8);
-#ifdef CONFIG_SOC_TI81XX
+#ifdef CONFIG_SOC_DM81XX
if (irqnr)
goto out;
irqnr = readl_relaxed(base_addr + 0xf8);
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index eb8a25d..400d6a0 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -151,12 +151,12 @@ void am35x_set_mode(u8 musb_mode)
omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
}
-void ti81xx_musb_phy_power(u8 on)
+void dm81xx_musb_phy_power(u8 on)
{
void __iomem *scm_base = NULL;
u32 usbphycfg;
- scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K);
+ scm_base = ioremap(DM81XX_SCM_BASE, SZ_2K);
if (!scm_base) {
pr_err("system control module ioremap failed\n");
return;
@@ -165,19 +165,19 @@ void ti81xx_musb_phy_power(u8 on)
usbphycfg = __raw_readl(scm_base + USBCTRL0);
if (on) {
- if (cpu_is_ti816x()) {
- usbphycfg |= TI816X_USBPHY0_NORMAL_MODE;
- usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC;
- } else if (cpu_is_ti814x()) {
+ if (cpu_is_dm816x()) {
+ usbphycfg |= DM816X_USBPHY0_NORMAL_MODE;
+ usbphycfg &= ~DM816X_USBPHY_REFCLK_OSC;
+ } else if (cpu_is_dm814x()) {
usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN
| USBPHY_DPINPUT | USBPHY_DMINPUT);
usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN
| USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL);
}
} else {
- if (cpu_is_ti816x())
- usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE;
- else if (cpu_is_ti814x())
+ if (cpu_is_dm816x())
+ usbphycfg &= ~DM816X_USBPHY0_NORMAL_MODE;
+ else if (cpu_is_dm814x())
usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
}
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 197cc16..066ce57 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -28,7 +28,7 @@
#include "omap24xx.h"
#include "omap34xx.h"
#include "omap44xx.h"
-#include "ti81xx.h"
+#include "dm81xx.h"
#include "am33xx.h"
#include "omap54xx.h"
@@ -153,12 +153,12 @@ static inline int is_am ##class (void) \
return (GET_AM_CLASS == (id)) ? 1 : 0; \
}
-#define GET_TI_CLASS ((omap_rev() >> 24) & 0xff)
+#define GET_DM_CLASS ((omap_rev() >> 24) & 0xff)
-#define IS_TI_CLASS(class, id) \
-static inline int is_ti ##class (void) \
+#define IS_DM_CLASS(class, id) \
+static inline int is_dm ##class (void) \
{ \
- return (GET_TI_CLASS == (id)) ? 1 : 0; \
+ return (GET_DM_CLASS == (id)) ? 1 : 0; \
}
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
@@ -169,8 +169,8 @@ static inline int is_omap ##subclass (void) \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
-#define IS_TI_SUBCLASS(subclass, id) \
-static inline int is_ti ##subclass (void) \
+#define IS_DM_SUBCLASS(subclass, id) \
+static inline int is_dm ##subclass (void) \
{ \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
@@ -188,7 +188,7 @@ IS_AM_CLASS(35xx, 0x35)
IS_OMAP_CLASS(54xx, 0x54)
IS_AM_CLASS(33xx, 0x33)
-IS_TI_CLASS(81xx, 0x81)
+IS_DM_CLASS(81xx, 0x81)
IS_OMAP_SUBCLASS(242x, 0x242)
IS_OMAP_SUBCLASS(243x, 0x243)
@@ -199,8 +199,8 @@ IS_OMAP_SUBCLASS(446x, 0x446)
IS_OMAP_SUBCLASS(447x, 0x447)
IS_OMAP_SUBCLASS(543x, 0x543)
-IS_TI_SUBCLASS(816x, 0x816)
-IS_TI_SUBCLASS(814x, 0x814)
+IS_DM_SUBCLASS(816x, 0x816)
+IS_DM_SUBCLASS(814x, 0x814)
IS_AM_SUBCLASS(335x, 0x335)
#define cpu_is_omap24xx() 0
@@ -208,9 +208,9 @@ IS_AM_SUBCLASS(335x, 0x335)
#define cpu_is_omap243x() 0
#define cpu_is_omap34xx() 0
#define cpu_is_omap343x() 0
-#define cpu_is_ti81xx() 0
-#define cpu_is_ti816x() 0
-#define cpu_is_ti814x() 0
+#define cpu_is_dm81xx() 0
+#define cpu_is_dm816x() 0
+#define cpu_is_dm814x() 0
#define soc_is_am35xx() 0
#define soc_is_am33xx() 0
#define soc_is_am335x() 0
@@ -321,16 +321,16 @@ IS_OMAP_TYPE(3430, 0x3430)
#if defined(CONFIG_ARCH_OMAP3)
# undef cpu_is_omap3430
-# undef cpu_is_ti81xx
-# undef cpu_is_ti816x
-# undef cpu_is_ti814x
+# undef cpu_is_dm81xx
+# undef cpu_is_dm816x
+# undef cpu_is_dm814x
# undef soc_is_am35xx
# define cpu_is_omap3430() is_omap3430()
# undef cpu_is_omap3630
# define cpu_is_omap3630() is_omap363x()
-# define cpu_is_ti81xx() is_ti81xx()
-# define cpu_is_ti816x() is_ti816x()
-# define cpu_is_ti814x() is_ti814x()
+# define cpu_is_dm81xx() is_dm81xx()
+# define cpu_is_dm816x() is_dm816x()
+# define cpu_is_dm814x() is_dm814x()
# define soc_is_am35xx() is_am35xx()
#endif
@@ -380,14 +380,14 @@ IS_OMAP_TYPE(3430, 0x3430)
#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8))
#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8))
-#define TI816X_CLASS 0x81600034
-#define TI8168_REV_ES1_0 TI816X_CLASS
-#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
+#define DM816X_CLASS 0x81600034
+#define DM8168_REV_ES1_0 DM816X_CLASS
+#define DM8168_REV_ES1_1 (DM816X_CLASS | (0x1 << 8))
-#define TI814X_CLASS 0x81400034
-#define TI8148_REV_ES1_0 TI814X_CLASS
-#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8))
-#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8))
+#define DM814X_CLASS 0x81400034
+#define DM8148_REV_ES1_0 DM814X_CLASS
+#define DM8148_REV_ES2_0 (DM814X_CLASS | (0x1 << 8))
+#define DM8148_REV_ES2_1 (DM814X_CLASS | (0x2 << 8))
#define AM35XX_CLASS 0x35170034
#define AM35XX_REV_ES1_0 AM35XX_CLASS
@@ -423,7 +423,7 @@ void omap3xxx_check_revision(void);
void omap4xxx_check_revision(void);
void omap5xxx_check_revision(void);
void omap3xxx_check_features(void);
-void ti81xx_check_features(void);
+void dm81xx_check_features(void);
void omap4xxx_check_features(void);
/*
diff --git a/arch/arm/mach-omap2/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h
deleted file mode 100644
index a1e6caf..0000000
--- a/arch/arm/mach-omap2/ti81xx.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file contains the address data for various TI81XX modules.
- *
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_TI81XX_H
-#define __ASM_ARCH_TI81XX_H
-
-#define L4_SLOW_TI81XX_BASE 0x48000000
-
-#define TI81XX_SCM_BASE 0x48140000
-#define TI81XX_CTRL_BASE TI81XX_SCM_BASE
-#define TI81XX_PRCM_BASE 0x48180000
-
-/*
- * Adjust TAP register base such that omap3_check_revision accesses the correct
- * TI81XX register for checking device ID (it adds 0x204 to tap base while
- * TI81XX DEVICE ID register is@offset 0x600 from control base).
- */
-#define TI81XX_TAP_BASE (TI81XX_CTRL_BASE + \
- TI81XX_CONTROL_DEVICE_ID - 0x204)
-
-
-#define TI81XX_ARM_INTC_BASE 0x48200000
-
-#endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 3242a55..d16ebc6 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -91,9 +91,9 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
if (soc_is_am35xx()) {
oh_name = "am35x_otg_hs";
name = "musb-am35x";
- } else if (cpu_is_ti81xx()) {
+ } else if (cpu_is_dm81xx()) {
oh_name = "usb_otg_hs";
- name = "musb-ti81xx";
+ name = "musb-dm81xx";
} else {
oh_name = "usb_otg_hs";
name = "musb-omap2430";
diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h
index e7261eb..e1c0ae4 100644
--- a/arch/arm/mach-omap2/usb.h
+++ b/arch/arm/mach-omap2/usb.h
@@ -22,15 +22,15 @@
#define CONF2_OTGPWRDN (1 << 2)
#define CONF2_DATPOL (1 << 1)
-/* TI81XX specific definitions */
+/* DM81XX specific definitions */
#define USBCTRL0 0x620
#define USBSTAT0 0x624
-/* TI816X PHY controls bits */
-#define TI816X_USBPHY0_NORMAL_MODE (1 << 0)
-#define TI816X_USBPHY_REFCLK_OSC (1 << 8)
+/* DM816X PHY controls bits */
+#define DM816X_USBPHY0_NORMAL_MODE (1 << 0)
+#define DM816X_USBPHY_REFCLK_OSC (1 << 8)
-/* TI814X PHY controls bits */
+/* DM814X PHY controls bits */
#define USBPHY_CM_PWRDN (1 << 0)
#define USBPHY_OTG_PWRDN (1 << 1)
#define USBPHY_CHGDET_DIS (1 << 2)
@@ -69,5 +69,5 @@ extern void am35x_musb_reset(void);
extern void am35x_musb_phy_power(u8 on);
extern void am35x_musb_clear_irq(void);
extern void am35x_set_mode(u8 musb_mode);
-extern void ti81xx_musb_phy_power(u8 on);
+extern void dm81xx_musb_phy_power(u8 on);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index a10297d..90619dd 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -481,7 +481,7 @@ msm8x60_sim MACH_MSM8X60_SIM MSM8X60_SIM 2756
tcc8000_sdk MACH_TCC8000_SDK TCC8000_SDK 2758
cns3420vb MACH_CNS3420VB CNS3420VB 2776
omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791
-ti8168evm MACH_TI8168EVM TI8168EVM 2800
+dm816x_evm MACH_DM816X_EVM DM816X_EVM 2800
teton_bga MACH_TETON_BGA TETON_BGA 2816
eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25SD EUKREA_CPUIMX25SD 2820
eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35SD EUKREA_CPUIMX35SD 2821
@@ -508,7 +508,7 @@ mx50_rdp MACH_MX50_RDP MX50_RDP 2988
universal_c210 MACH_UNIVERSAL_C210 UNIVERSAL_C210 2989
real6410 MACH_REAL6410 REAL6410 2990
dockstar MACH_DOCKSTAR DOCKSTAR 2998
-ti8148evm MACH_TI8148EVM TI8148EVM 3004
+dm814x_evm MACH_DM814X_EVM DM814X_EVM 3004
seaboard MACH_SEABOARD SEABOARD 3005
mx53_ard MACH_MX53_ARD MX53_ARD 3010
mx53_smd MACH_MX53_SMD MX53_SMD 3011
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 7d68aee..bfaa05b 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2772,14 +2772,14 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
#endif
-static void fixup_ti816x_class(struct pci_dev *dev)
+static void fixup_dm816x_class(struct pci_dev *dev)
{
- /* TI 816x devices do not have class code set when in PCIe boot mode */
+ /* DM 816x devices do not have class code set when in PCIe boot mode */
dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
- PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
+ PCI_CLASS_NOT_DEFINED, 0, fixup_dm816x_class);
/* Some PCIe devices do not work reliably with the claimed maximum
* payload size supported.
diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c
index e1b661d..e82b039 100644
--- a/drivers/usb/musb/musb_dsps.c
+++ b/drivers/usb/musb/musb_dsps.c
@@ -24,8 +24,8 @@
* Suite 330, Boston, MA 02111-1307 USA
*
* musb_dsps.c will be a common file for all the TI DSPS platforms
- * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
- * For now only ti81x is using this and in future davinci.c, am35x.c
+ * such as dm64x, dm36x, dm35x, da8x, am35x and dm81x.
+ * For now only dm81x is using this and in future davinci.c, am35x.c
* da8xx.c would be merged to this file after testing.
*/
@@ -719,7 +719,7 @@ static int dsps_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
-static const struct dsps_musb_wrapper ti81xx_driver_data = {
+static const struct dsps_musb_wrapper dm81xx_driver_data = {
.revision = 0x00,
.control = 0x14,
.status = 0x18,
@@ -752,8 +752,8 @@ static const struct dsps_musb_wrapper ti81xx_driver_data = {
static const struct platform_device_id musb_dsps_id_table[] = {
{
- .name = "musb-ti81xx",
- .driver_data = (kernel_ulong_t) &ti81xx_driver_data,
+ .name = "musb-dm81xx",
+ .driver_data = (kernel_ulong_t) &dm81xx_driver_data,
},
{ }, /* Terminating Entry */
};
@@ -762,7 +762,7 @@ MODULE_DEVICE_TABLE(platform, musb_dsps_id_table);
#ifdef CONFIG_OF
static const struct of_device_id musb_dsps_of_match[] = {
{ .compatible = "ti,musb-am33xx",
- .data = (void *) &ti81xx_driver_data, },
+ .data = (void *) &dm81xx_driver_data, },
{ },
};
MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index e18b222..a61e9d1 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -1,7 +1,7 @@
/*
* ti_hdmi_4xxx_ip.c
*
- * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
+ * HDMI DM81xx, TI38xx, TI OMAP4 etc IP driver Library
* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
* Authors: Yong Zhi
* Mythri pk <mythripk@ti.com>
diff --git a/include/linux/platform_data/davinci_asp.h b/include/linux/platform_data/davinci_asp.h
index 8db5ae0..693b7d6 100644
--- a/include/linux/platform_data/davinci_asp.h
+++ b/include/linux/platform_data/davinci_asp.h
@@ -89,7 +89,7 @@ struct snd_platform_data {
enum {
MCASP_VERSION_1 = 0, /* DM646x */
MCASP_VERSION_2, /* DA8xx/OMAPL1x */
- MCASP_VERSION_3, /* TI81xx/AM33xx */
+ MCASP_VERSION_3, /* DM81xx/AM33xx */
};
enum mcbsp_clk_input_pin {
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/5] ARM: OMAP: DM816x: add powerdomains for DM816x
2013-06-05 15:29 [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4 Aida Mynzhasova
2013-06-05 15:29 ` [PATCH 1/5] ARM: OMAP: DM81xx: multiple renames for DM81xx platform Aida Mynzhasova
@ 2013-06-05 15:29 ` Aida Mynzhasova
2013-06-05 15:29 ` [PATCH 4/5] ARM: OMAP: DM816x: add clock domain support " Aida Mynzhasova
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Aida Mynzhasova @ 2013-06-05 15:29 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds required structures for powerdomain initialization on
the DM816x. It is impossible to use OMAP3430 structures in order to
initialize powerdomains on DM816x, because there are big differences
between PRCM module base address offsets on these CPUs.
Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
---
arch/arm/mach-omap2/Makefile | 3 +
arch/arm/mach-omap2/io.c | 2 +-
arch/arm/mach-omap2/powerdomain.h | 4 +
arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c | 43 ++++++++
arch/arm/mach-omap2/powerdomains3xxx_data.c | 43 --------
arch/arm/mach-omap2/powerdomains_dm81xx_data.c | 115 ++++++++++++++++++++++
arch/arm/mach-omap2/prm-regbits-dm81xx.h | 24 +++++
arch/arm/mach-omap2/prm_dm81xx.c | 79 +++++++++++++++
arch/arm/mach-omap2/prm_dm81xx.h | 44 +++++++++
9 files changed, 313 insertions(+), 44 deletions(-)
create mode 100644 arch/arm/mach-omap2/powerdomains_dm81xx_data.c
create mode 100644 arch/arm/mach-omap2/prm-regbits-dm81xx.h
create mode 100644 arch/arm/mach-omap2/prm_dm81xx.c
create mode 100644 arch/arm/mach-omap2/prm_dm81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 607a2bf..03121cc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -113,6 +113,7 @@ obj-$(CONFIG_SOC_AM33XX) += prm_am33xx.o cm_am33xx.o
omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
prcm_mpu44xx.o prminst44xx.o \
vc44xx_data.o vp44xx_data.o
+obj-$(CONFIG_SOC_DM81XX) += prm_dm81xx.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
@@ -140,6 +141,8 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_AM33XX) += powerdomains_am33xx_data.o
+obj-$(CONFIG_SOC_DM81XX) += $(powerdomain-common)
+obj-$(CONFIG_SOC_DM81XX) += powerdomains_dm81xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
# PRCM clockdomain control
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3deba6e..2a9e5b3 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -516,7 +516,7 @@ void __init dm81xx_init_early(void)
omap3xxx_check_revision();
dm81xx_check_features();
omap3xxx_voltagedomains_init();
- omap3xxx_powerdomains_init();
+ dm81xx_powerdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 140c360..6d78990 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -252,11 +252,13 @@ extern void omap242x_powerdomains_init(void);
extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void);
+extern void dm81xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
extern struct pwrdm_ops am33xx_pwrdm_operations;
+extern struct pwrdm_ops dm81xx_pwrdm_operations;
extern struct pwrdm_ops omap4_pwrdm_operations;
/* Common Internal functions used across OMAP rev's */
@@ -266,6 +268,8 @@ extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
extern struct powerdomain wkup_omap2_pwrdm;
extern struct powerdomain gfx_omap2_pwrdm;
+extern struct powerdomain mpu_3xxx_pwrdm;
+extern struct powerdomain core_3xxx_pre_es3_1_pwrdm;
extern void pwrdm_lock(struct powerdomain *pwrdm);
extern void pwrdm_unlock(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 7b946f1..2c2b630 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -63,3 +63,46 @@ struct powerdomain wkup_omap2_pwrdm = {
.pwrsts = PWRSTS_ON,
.voltdm = { .name = "wakeup" },
};
+
+struct powerdomain mpu_3xxx_pwrdm = {
+ .name = "mpu_pwrdm",
+ .prcm_offs = MPU_MOD,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .flags = PWRDM_HAS_MPU_QUIRK,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET,
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_ON,
+ },
+ .voltdm = { .name = "mpu_iva" },
+};
+
+/*
+ * The USBTLL Save-and-Restore mechanism is broken on
+ * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
+ * needs to be disabled on these chips.
+ * Refer: 3430 errata ID i459 and 3630 errata ID i579
+ *
+ * Note: setting the SAR flag could help for errata ID i478
+ * which applies to 3430 <= ES3.1, but since the SAR feature
+ * is broken, do not use it.
+ */
+struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
+ .name = "core_pwrdm",
+ .prcm_offs = CORE_MOD,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
+ [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
+ [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
+ },
+ .voltdm = { .name = "core" },
+};
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index f0e14e9..6c3261b 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -53,22 +53,6 @@ static struct powerdomain iva2_pwrdm = {
.voltdm = { .name = "mpu_iva" },
};
-static struct powerdomain mpu_3xxx_pwrdm = {
- .name = "mpu_pwrdm",
- .prcm_offs = MPU_MOD,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
- .flags = PWRDM_HAS_MPU_QUIRK,
- .banks = 1,
- .pwrsts_mem_ret = {
- [0] = PWRSTS_OFF_RET,
- },
- .pwrsts_mem_on = {
- [0] = PWRSTS_OFF_ON,
- },
- .voltdm = { .name = "mpu_iva" },
-};
-
static struct powerdomain mpu_am35x_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = MPU_MOD,
@@ -85,33 +69,6 @@ static struct powerdomain mpu_am35x_pwrdm = {
.voltdm = { .name = "mpu_iva" },
};
-/*
- * The USBTLL Save-and-Restore mechanism is broken on
- * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
- * needs to be disabled on these chips.
- * Refer: 3430 errata ID i459 and 3630 errata ID i579
- *
- * Note: setting the SAR flag could help for errata ID i478
- * which applies to 3430 <= ES3.1, but since the SAR feature
- * is broken, do not use it.
- */
-static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
- .name = "core_pwrdm",
- .prcm_offs = CORE_MOD,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
- .banks = 2,
- .pwrsts_mem_ret = {
- [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
- [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
- },
- .pwrsts_mem_on = {
- [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
- [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
- },
- .voltdm = { .name = "core" },
-};
-
static struct powerdomain core_3xxx_es3_1_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
diff --git a/arch/arm/mach-omap2/powerdomains_dm81xx_data.c b/arch/arm/mach-omap2/powerdomains_dm81xx_data.c
new file mode 100644
index 0000000..878ca7d
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains_dm81xx_data.c
@@ -0,0 +1,115 @@
+/*
+ * DM816X Power Domain data.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS_DM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS_DM81XX_H
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+
+#include "prcm-common.h"
+#include "prcm44xx.h"
+#include "prm-regbits-44xx.h"
+#include "prm44xx.h"
+#include "prcm_mpu44xx.h"
+#include "prm_dm81xx.h"
+
+
+#ifdef CONFIG_SOC_DM81XX
+
+/*
+ * DM81XX common
+ */
+
+static struct powerdomain alwon_dm81xx_pwrdm = {
+ .name = "alwon_pwrdm",
+ .prcm_offs = DM81XX_PRM_ALWON_MOD,
+ .voltdm = { .name = "core" },
+};
+
+/*
+ * DM816X only
+ */
+
+static struct powerdomain active_dm816x_pwrdm = {
+ .name = "active_pwrdm",
+ .prcm_offs = DM816X_PRM_ACTIVE_MOD,
+ .pwrsts = PWRSTS_OFF_ON,
+ .voltdm = { .name = "core" },
+};
+
+static struct powerdomain default_dm816x_pwrdm = {
+ .name = "default_pwrdm",
+ .prcm_offs = DM81XX_PRM_DEFAULT_MOD,
+ .pwrsts = PWRSTS_OFF_ON,
+ .voltdm = { .name = "core" },
+};
+
+static struct powerdomain ivahd0_dm816x_pwrdm = {
+ .name = "ivahd0_pwrdm",
+ .prcm_offs = DM816X_PRM_IVAHD0_MOD,
+ .pwrsts = PWRSTS_OFF_ON,
+ .voltdm = { .name = "mpu_iva" },
+};
+
+static struct powerdomain ivahd1_dm816x_pwrdm = {
+ .name = "ivahd1_pwrdm",
+ .prcm_offs = DM816X_PRM_IVAHD1_MOD,
+ .pwrsts = PWRSTS_OFF_ON,
+ .voltdm = { .name = "mpu_iva" },
+};
+
+static struct powerdomain ivahd2_dm816x_pwrdm = {
+ .name = "ivahd2_pwrdm",
+ .prcm_offs = DM816X_PRM_IVAHD2_MOD,
+ .pwrsts = PWRSTS_OFF_ON,
+ .voltdm = { .name = "mpu_iva" },
+};
+
+static struct powerdomain sgx_dm816x_pwrdm = {
+ .name = "sgx_pwrdm",
+ .prcm_offs = DM816X_PRM_SGX_MOD,
+ .pwrsts = PWRSTS_OFF_ON,
+ .voltdm = { .name = "core" },
+};
+
+static struct powerdomain *powerdomains_dm81xx[] __initdata = {
+ &wkup_omap2_pwrdm,
+ &mpu_3xxx_pwrdm,
+ &core_3xxx_pre_es3_1_pwrdm,
+
+ &alwon_dm81xx_pwrdm,
+ &active_dm816x_pwrdm,
+ &default_dm816x_pwrdm,
+ &ivahd0_dm816x_pwrdm,
+ &ivahd1_dm816x_pwrdm,
+ &ivahd2_dm816x_pwrdm,
+ &sgx_dm816x_pwrdm,
+ NULL
+};
+
+void __init dm81xx_powerdomains_init(void)
+{
+ pwrdm_register_platform_funcs(&dm81xx_pwrdm_operations);
+ pwrdm_register_pwrdms(powerdomains_dm81xx);
+ pwrdm_complete_init();
+}
+
+
+#endif /* CONFIG_SOC_DM81XX */
+
+#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-dm81xx.h b/arch/arm/mach-omap2/prm-regbits-dm81xx.h
new file mode 100644
index 0000000..adcf6cb
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-dm81xx.h
@@ -0,0 +1,24 @@
+/*
+ * DM81XX PRM_XXX register bits
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_DM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_DM81XX_H
+
+#include "prm.h"
+
+#define DM81XX_PM_PWSTCTRL 0x0000
+#define DM81XX_PM_PWSTST 0x0004
+
+#endif
diff --git a/arch/arm/mach-omap2/prm_dm81xx.c b/arch/arm/mach-omap2/prm_dm81xx.c
new file mode 100644
index 0000000..70185f3
--- /dev/null
+++ b/arch/arm/mach-omap2/prm_dm81xx.c
@@ -0,0 +1,79 @@
+/*
+ * DM81XX powerdomain control
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include "powerdomain.h"
+#include "prm_dm81xx.h"
+#include "prm-regbits-dm81xx.h"
+#include "prm-regbits-34xx.h"
+
+int dm81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+ omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
+ (pwrst << OMAP_POWERSTATE_SHIFT),
+ pwrdm->prcm_offs, DM81XX_PM_PWSTCTRL);
+ return 0;
+}
+
+int dm81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+ return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+ DM81XX_PM_PWSTCTRL,
+ OMAP_POWERSTATE_MASK);
+}
+
+int dm81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+ return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+ DM81XX_PM_PWSTST,
+ OMAP_POWERSTATEST_MASK);
+}
+
+int dm81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+ /* Hack to fix GFX pwstst and rstctrl reg offsets to be removed */
+ return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+ DM81XX_PM_PWSTST,
+ OMAP3430_LOGICSTATEST_MASK);
+}
+
+int dm81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+ u32 c = 0;
+
+ /*
+ * REVISIT: pwrdm_wait_transition() may be better implemented
+ * via a callback and a periodic timer check -- how long do we expect
+ * powerdomain transitions to take?
+ */
+
+ /* XXX Is this udelay() value meaningful? */
+ /* Hack to fix GFX pwstst and rstctrl reg offsets to be removed */
+ while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs,
+ DM81XX_PM_PWSTST) &
+ OMAP_INTRANSITION_MASK) &&
+ (c++ < PWRDM_TRANSITION_BAILOUT))
+ udelay(1);
+
+ if (c > PWRDM_TRANSITION_BAILOUT) {
+ printk(KERN_ERR "powerdomain: waited too long for "
+ "powerdomain %s to complete transition\n", pwrdm->name);
+ return -EAGAIN;
+ }
+
+ pr_debug("powerdomain: completed transition in %d loops\n", c);
+
+ return 0;
+}
+
+struct pwrdm_ops dm81xx_pwrdm_operations = {
+ .pwrdm_set_next_pwrst = dm81xx_pwrdm_set_next_pwrst,
+ .pwrdm_read_next_pwrst = dm81xx_pwrdm_read_next_pwrst,
+ .pwrdm_read_pwrst = dm81xx_pwrdm_read_pwrst,
+ .pwrdm_read_logic_pwrst = dm81xx_pwrdm_read_logic_pwrst,
+ .pwrdm_wait_transition = dm81xx_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/prm_dm81xx.h b/arch/arm/mach-omap2/prm_dm81xx.h
new file mode 100644
index 0000000..4a43ce5
--- /dev/null
+++ b/arch/arm/mach-omap2/prm_dm81xx.h
@@ -0,0 +1,44 @@
+/*
+ * DM33XX PRM instance offset macros
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_DM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_DM81XX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+
+/* DM81XX common PRM module offsets */
+
+#define DM81XX_PRM_DEVICE_MOD 0x0000
+#define DM81XX_PRM_ALWON_MOD 0x1800
+#define DM81XX_PRM_DEFAULT_MOD 0x0b00
+
+/* DM816X PRM module offsets */
+
+#define DM816X_PRM_OCP_SOCKET_MOD 0x0200
+#define DM816X_PRM_ACTIVE_MOD 0x0a00
+#define DM816X_PRM_IVAHD0_MOD 0x0c00
+#define DM816X_PRM_IVAHD1_MOD 0x0d00
+#define DM816X_PRM_IVAHD2_MOD 0x0e00
+#define DM816X_PRM_SGX_MOD 0x0f00
+
+#ifndef __ASSEMBLER__
+int dm81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
+int dm81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
+int dm81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm);
+int dm81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
+int dm81xx_pwrdm_wait_transition(struct powerdomain *pwrdm);
+#endif /* ASSEMBLER */
+#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/5] ARM: OMAP: DM816x: add clock domain support for DM816x
2013-06-05 15:29 [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4 Aida Mynzhasova
2013-06-05 15:29 ` [PATCH 1/5] ARM: OMAP: DM81xx: multiple renames for DM81xx platform Aida Mynzhasova
2013-06-05 15:29 ` [PATCH 3/5] ARM: OMAP: DM816x: add powerdomains for DM816x Aida Mynzhasova
@ 2013-06-05 15:29 ` Aida Mynzhasova
2013-06-05 15:29 ` [PATCH 5/5] ARM: OMAP: DM816x: add hwmod support for DM81xx Aida Mynzhasova
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Aida Mynzhasova @ 2013-06-05 15:29 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds required definitions and structures for clockdomain
initialization:
1. register offsets for DM81xx and DM816x clock domain modules;
2. clock domain register bits;
3. additional OMAP2/3 common clock domains: prm_clkdm and cm_clkdm;
4. clockdomain structure definitions for DM816x.
Also, omap3xxx_clockdomains_init() was substituted by new
dm81xx_clockdomains_init().
Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
---
arch/arm/mach-omap2/Makefile | 2 +
arch/arm/mach-omap2/clockdomain.h | 3 +
arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 10 +
arch/arm/mach-omap2/clockdomains_dm81xx_data.c | 213 ++++++++++++++++++++++
arch/arm/mach-omap2/cm-regbits-dm81xx.h | 22 +++
arch/arm/mach-omap2/cm_dm81xx.h | 61 +++++++
arch/arm/mach-omap2/io.c | 2 +-
7 files changed, 312 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-omap2/clockdomains_dm81xx_data.c
create mode 100644 arch/arm/mach-omap2/cm-regbits-dm81xx.h
create mode 100644 arch/arm/mach-omap2/cm_dm81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 03121cc..132a1e2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -158,6 +158,8 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM33XX) += clockdomains_am33xx_data.o
+obj-$(CONFIG_SOC_DM81XX) += $(clockdomain-common)
+obj-$(CONFIG_SOC_DM81XX) += clockdomains_dm81xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
# Clock framework
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 2da3765..0a9d4fc 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -215,6 +215,7 @@ extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
+extern void __init dm81xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
@@ -228,5 +229,7 @@ extern struct clkdm_ops am33xx_clkdm_operations;
extern struct clkdm_dep gfx_24xx_wkdeps[];
extern struct clkdm_dep dsp_24xx_wkdeps[];
extern struct clockdomain wkup_common_clkdm;
+extern struct clockdomain cm_common_clkdm;
+extern struct clockdomain prm_common_clkdm;
#endif
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 49722196..8a62c7f 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -90,3 +90,13 @@ struct clockdomain wkup_common_clkdm = {
.dep_bit = OMAP_EN_WKUP_SHIFT,
.flags = CLKDM_ACTIVE_WITH_MPU,
};
+
+struct clockdomain prm_common_clkdm = {
+ .name = "prm_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+};
+
+struct clockdomain cm_common_clkdm = {
+ .name = "cm_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+};
diff --git a/arch/arm/mach-omap2/clockdomains_dm81xx_data.c b/arch/arm/mach-omap2/clockdomains_dm81xx_data.c
new file mode 100644
index 0000000..daf390f
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains_dm81xx_data.c
@@ -0,0 +1,213 @@
+/*
+ * DM81XX Clock Domain data.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_DM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_DM81XX_H
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+
+#include "cm_dm81xx.h"
+#include "cm-regbits-dm81xx.h"
+
+/*
+ * TODO:
+ * - Add other domains as required
+ * - Fill up associated powerdomans (especially ALWON powerdomains are NULL at
+ * the moment
+ * - Consider dependencies across domains (probably not applicable till now)
+ */
+
+/* Common DM81XX */
+static struct clockdomain alwon_l3_slow_dm81xx_clkdm = {
+ .name = "alwon_l3_slow_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = DM81XX_CM_ALWON_MOD,
+ .clkdm_offs = DM81XX_CM_ALWON_L3_SLOW_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_l3_med_dm81xx_clkdm = {
+ .name = "alwon_l3_med_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = DM81XX_CM_ALWON_MOD,
+ .clkdm_offs = DM81XX_CM_ALWON_L3_MED_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_l3_fast_dm81xx_clkdm = {
+ .name = "alwon_l3_fast_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = DM81XX_CM_ALWON_MOD,
+ .clkdm_offs = DM81XX_CM_ALWON_L3_FAST_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_ethernet_dm81xx_clkdm = {
+ .name = "alwon_ethernet_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = DM81XX_CM_ALWON_MOD,
+ .clkdm_offs = DM81XX_CM_ETHERNET_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+/* OCMC clock domain */
+static struct clockdomain mmu_dm81xx_clkdm = {
+ .name = "mmu_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = DM81XX_CM_ALWON_MOD,
+ .clkdm_offs = DM81XX_CM_MMU_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mmu_cfg_dm81xx_clkdm = {
+ .name = "mmu_cfg_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = DM81XX_CM_ALWON_MOD,
+ .clkdm_offs = DM81XX_CM_MMUCFG_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+/* DM816X only */
+static struct clockdomain alwon_mpu_dm816x_clkdm = {
+ .name = "alwon_mpu_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = DM81XX_CM_ALWON_MOD,
+ .clkdm_offs = DM81XX_CM_ALWON_MPU_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain active_gem_dm816x_clkdm = {
+ .name = "active_gem_clkdm",
+ .pwrdm = { .name = "active_pwrdm" },
+ .cm_inst = DM816X_CM_ACTIVE_MOD,
+ .clkdm_offs = DM816X_CM_ACTIVE_GEM_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain ivahd0_dm816x_clkdm = {
+ .name = "ivahd0_clkdm",
+ .pwrdm = { .name = "ivahd0_pwrdm" },
+ .cm_inst = DM816X_CM_IVAHD0_MOD,
+ .clkdm_offs = DM816X_CM_IVAHD0_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain ivahd1_dm816x_clkdm = {
+ .name = "ivahd1_clkdm",
+ .pwrdm = { .name = "ivahd1_pwrdm" },
+ .cm_inst = DM816X_CM_IVAHD1_MOD,
+ .clkdm_offs = DM816X_CM_IVAHD1_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain ivahd2_dm816x_clkdm = {
+ .name = "ivahd2_clkdm",
+ .pwrdm = { .name = "ivahd2_pwrdm" },
+ .cm_inst = DM816X_CM_IVAHD2_MOD,
+ .clkdm_offs = DM816X_CM_IVAHD2_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain sgx_dm816x_clkdm = {
+ .name = "sgx_clkdm",
+ .pwrdm = { .name = "sgx_pwrdm" },
+ .cm_inst = DM816X_CM_SGX_MOD,
+ .clkdm_offs = DM816X_CM_SGX_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_l3_med_dm816x_clkdm = {
+ .name = "default_l3_med_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = DM816X_CM_DEFAULT_MOD,
+ .clkdm_offs = DM816X_CM_DEFAULT_L3_MED_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_ducati_dm816x_clkdm = {
+ .name = "default_ducati_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = DM816X_CM_DEFAULT_MOD,
+ .clkdm_offs = DM816X_CM_DEFAULT_DUCATI_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_pcie_dm816x_clkdm = {
+ .name = "default_pcie_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = DM816X_CM_DEFAULT_MOD,
+ .clkdm_offs = DM816X_CM_DEFAULT_PCI_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_usb_dm816x_clkdm = {
+ .name = "default_usb_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = DM816X_CM_DEFAULT_MOD,
+ .clkdm_offs = DM816X_CM_DEFAULT_L3_SLOW_CLKDM,
+ .clktrctrl_mask = DM81XX_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain *clockdomains_dm81xx[] __initdata = {
+ &wkup_common_clkdm,
+ &cm_common_clkdm,
+ &prm_common_clkdm,
+
+ &alwon_mpu_dm816x_clkdm,
+ &alwon_l3_slow_dm81xx_clkdm,
+ &alwon_l3_med_dm81xx_clkdm,
+ &alwon_l3_fast_dm81xx_clkdm,
+ &alwon_ethernet_dm81xx_clkdm,
+ &mmu_dm81xx_clkdm,
+ &mmu_cfg_dm81xx_clkdm,
+ &active_gem_dm816x_clkdm,
+ &ivahd0_dm816x_clkdm,
+ &ivahd1_dm816x_clkdm,
+ &ivahd2_dm816x_clkdm,
+ &sgx_dm816x_clkdm,
+ &default_l3_med_dm816x_clkdm,
+ &default_ducati_dm816x_clkdm,
+ &default_pcie_dm816x_clkdm,
+ &default_usb_dm816x_clkdm,
+ NULL,
+};
+
+void __init dm81xx_clockdomains_init(void)
+{
+ clkdm_register_platform_funcs(&omap3_clkdm_operations);
+ clkdm_register_clkdms(clockdomains_dm81xx);
+ clkdm_complete_init();
+}
+#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-dm81xx.h b/arch/arm/mach-omap2/cm-regbits-dm81xx.h
new file mode 100644
index 0000000..536e19a
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-dm81xx.h
@@ -0,0 +1,22 @@
+/*
+ * Clock Domain register bits for DM81xx.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_DM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_DM81XX_H
+
+#define DM81XX_CLKTRCTRL_MASK (3 << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/cm_dm81xx.h b/arch/arm/mach-omap2/cm_dm81xx.h
new file mode 100644
index 0000000..f8988da
--- /dev/null
+++ b/arch/arm/mach-omap2/cm_dm81xx.h
@@ -0,0 +1,61 @@
+/*
+ * Clock domain register offsets for DM81xx.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_DM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_DM81XX_H
+
+/* DM81XX common CM module offsets */
+#define DM81XX_CM_ALWON_MOD 0x1400 /* 1KB */
+
+/* DM816X CM module offsets */
+#define DM816X_CM_ACTIVE_MOD 0x0400 /* 256B */
+#define DM816X_CM_DEFAULT_MOD 0x0500 /* 256B */
+#define DM816X_CM_IVAHD0_MOD 0x0600 /* 256B */
+#define DM816X_CM_IVAHD1_MOD 0x0700 /* 256B */
+#define DM816X_CM_IVAHD2_MOD 0x0800 /* 256B */
+#define DM816X_CM_SGX_MOD 0x0900 /* 256B */
+
+/* ALWON */
+#define DM81XX_CM_ALWON_MPU_CLKDM 0x001C
+#define DM81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
+#define DM81XX_CM_ALWON_L3_MED_CLKDM 0x0004
+#define DM81XX_CM_ALWON_L3_FAST_CLKDM 0x0030
+#define DM81XX_CM_ETHERNET_CLKDM 0x0004
+#define DM81XX_CM_MMU_CLKDM 0x000C
+#define DM81XX_CM_MMUCFG_CLKDM 0x0010
+
+/* ACTIVE */
+#define DM816X_CM_ACTIVE_GEM_CLKDM 0x0000
+
+/* IVAHD0 */
+#define DM816X_CM_IVAHD0_CLKDM 0x0000
+
+/* IVAHD1 */
+#define DM816X_CM_IVAHD1_CLKDM 0x0000
+
+/* IVAHD2 */
+#define DM816X_CM_IVAHD2_CLKDM 0x0000
+
+/* SGX */
+#define DM816X_CM_SGX_CLKDM 0x0000
+
+/* DEFAULT */
+#define DM816X_CM_DEFAULT_L3_MED_CLKDM 0x0004
+#define DM816X_CM_DEFAULT_DUCATI_CLKDM 0x0018
+#define DM816X_CM_DEFAULT_PCI_CLKDM 0x0010
+#define DM816X_CM_DEFAULT_L3_SLOW_CLKDM 0x0014
+
+#endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 2a9e5b3..f3808ce 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -517,7 +517,7 @@ void __init dm81xx_init_early(void)
dm81xx_check_features();
omap3xxx_voltagedomains_init();
dm81xx_powerdomains_init();
- omap3xxx_clockdomains_init();
+ dm81xx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_init = omap3xxx_clk_init;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/5] ARM: OMAP: DM816x: add hwmod support for DM81xx
2013-06-05 15:29 [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4 Aida Mynzhasova
` (2 preceding siblings ...)
2013-06-05 15:29 ` [PATCH 4/5] ARM: OMAP: DM816x: add clock domain support " Aida Mynzhasova
@ 2013-06-05 15:29 ` Aida Mynzhasova
2013-06-06 3:54 ` [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4 Paul Walmsley
2013-06-06 4:16 ` Paul Walmsley
5 siblings, 0 replies; 9+ messages in thread
From: Aida Mynzhasova @ 2013-06-05 15:29 UTC (permalink / raw)
To: linux-arm-kernel
OCP interface data structures were added in order to achieve
successful initialization of hwmods on DM816x.
Required DM81xx family IRQ definitions, offsets of the PRCM clock
control registers and additional OMAP2PLUS DMA channel definitions
were added as they are needed during the hwmod registration.
omap3xxx_hwmod_init() call was substituted by dm81xx_hwmod_init().
Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
---
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/cm_dm81xx.h | 20 +
arch/arm/mach-omap2/dm81xx.h | 28 +-
arch/arm/mach-omap2/dma.h | 12 +
arch/arm/mach-omap2/io.c | 2 +-
arch/arm/mach-omap2/omap_hwmod.h | 1 +
arch/arm/mach-omap2/omap_hwmod_dm81xx_data.c | 1209 +++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/dmtimer.h | 6 +
arch/arm/plat-omap/include/plat/irqs-dm81xx.h | 43 +
9 files changed, 1320 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-omap2/omap_hwmod_dm81xx_data.c
create mode 100644 arch/arm/plat-omap/include/plat/irqs-dm81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 132a1e2..3b5cc8b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -202,6 +202,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_am33xx_data.o
+obj-$(CONFIG_SOC_DM81XX) += omap_hwmod_dm81xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
# EMU peripherals
diff --git a/arch/arm/mach-omap2/cm_dm81xx.h b/arch/arm/mach-omap2/cm_dm81xx.h
index f8988da..d8268cd 100644
--- a/arch/arm/mach-omap2/cm_dm81xx.h
+++ b/arch/arm/mach-omap2/cm_dm81xx.h
@@ -58,4 +58,24 @@
#define DM816X_CM_DEFAULT_PCI_CLKDM 0x0010
#define DM816X_CM_DEFAULT_L3_SLOW_CLKDM 0x0014
+#define DM81XX_CM_ALWON_UART_0_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0150)
+#define DM81XX_CM_ALWON_UART_1_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0154)
+#define DM81XX_CM_ALWON_UART_2_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0158)
+#define DM81XX_CM_ALWON_GPIO_0_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x015C)
+#define DM81XX_CM_ALWON_GPIO_1_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0160)
+#define DM81XX_CM_ALWON_WDTIMER_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x018C)
+#define DM81XX_CM_ALWON_SPI_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0190)
+#define DM816X_CM_ALWON_I2C_0_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0164)
+#define DM816X_CM_ALWON_I2C_1_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0168)
+#define DM816X_CM_DEFAULT_USB_CLKCTRL_OFF (DM816X_CM_DEFAULT_MOD + 0x0058)
+#define DM816X_CM_ALWON_TIMER_0_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x016C)
+#define DM816X_CM_ALWON_TIMER_1_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0170)
+#define DM816X_CM_ALWON_TIMER_2_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0174)
+#define DM816X_CM_ALWON_TIMER_3_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0178)
+#define DM816X_CM_ALWON_TIMER_4_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x017C)
+#define DM816X_CM_ALWON_TIMER_5_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0180)
+#define DM816X_CM_ALWON_TIMER_6_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0184)
+#define DM816X_CM_ALWON_TIMER_7_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0188)
+#define DM816X_CM_ALWON_SDIO_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x15B0)
+#define DM81XX_CM_ALWON_SPI_CLKCTRL_OFF (DM81XX_CM_ALWON_MOD + 0x0190)
#endif
diff --git a/arch/arm/mach-omap2/dm81xx.h b/arch/arm/mach-omap2/dm81xx.h
index a0b18a6..e92a2d2 100644
--- a/arch/arm/mach-omap2/dm81xx.h
+++ b/arch/arm/mach-omap2/dm81xx.h
@@ -30,7 +30,33 @@
#define DM81XX_TAP_BASE (DM81XX_CTRL_BASE + \
DM81XX_CONTROL_DEVICE_ID - 0x204)
+#define DM81XX_MAILBOX_BASE 0x480C8000
-#define DM81XX_ARM_INTC_BASE 0x48200000
+#define DM816X_WDTIMER1_BASE 0x480C2000
+
+#define DM816X_I2C0_BASE 0x48028000
+#define DM816X_I2C1_BASE 0x4802A000
+
+#define DM81XX_ELM_BASE 0x48080000
+
+#define DM81XX_GPIO0_BASE 0x48032000
+#define DM81XX_GPIO1_BASE 0x4804C000
+
+#define DM81XX_USBSS_BASE 0x47400000
+
+#define DM81XX_USB0_BASE 0x47401000
+#define DM81XX_USB1_BASE 0x47401800
+
+#define DM816X_TIMER0_BASE 0x4802E000
+#define DM816X_TIMER1_BASE 0x48040000
+#define DM816X_TIMER2_BASE 0x48042000
+#define DM816X_TIMER3_BASE 0x48044000
+#define DM816X_TIMER4_BASE 0x48046000
+#define DM816X_TIMER5_BASE 0x48048000
+#define DM816X_TIMER6_BASE 0x4804A000
+
+#define DM816X_MMC0_BASE 0x48060000
+
+#define DM816X_SPI0_BASE 0x48030000
#endif /* __ASM_ARCH_DM81XX_H */
diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h
index 65f80ca..6bd28ee 100644
--- a/arch/arm/mach-omap2/dma.h
+++ b/arch/arm/mach-omap2/dma.h
@@ -36,6 +36,18 @@
#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
+
+#ifdef CONFIG_MACH_DM816X_EVM
+#define OMAP24XX_DMA_SPI1_TX0 16 /* E_DMA_16 */
+#define OMAP24XX_DMA_SPI1_RX0 17 /* E_DMA_17 */
+#define OMAP24XX_DMA_SPI1_TX1 18 /* E_DMA_18 */
+#define OMAP24XX_DMA_SPI1_RX1 19 /* E_DMA_19 */
+#define OMAP24XX_DMA_SPI1_TX2 20 /* E_DMA_20 */
+#define OMAP24XX_DMA_SPI1_RX2 21 /* E_DMA_21 */
+#define OMAP24XX_DMA_SPI1_TX3 22 /* E_DMA_22 */
+#define OMAP24XX_DMA_SPI1_RX3 23 /* E_DMA_23 */
+#endif
+
#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index f3808ce..6c6e27f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -518,7 +518,7 @@ void __init dm81xx_init_early(void)
omap3xxx_voltagedomains_init();
dm81xx_powerdomains_init();
dm81xx_clockdomains_init();
- omap3xxx_hwmod_init();
+ dm81xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_init = omap3xxx_clk_init;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0c898f5..f05d98d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -700,6 +700,7 @@ extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
extern int am33xx_hwmod_init(void);
+extern int dm81xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_dm81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_dm81xx_data.c
new file mode 100644
index 0000000..a428402
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_dm81xx_data.c
@@ -0,0 +1,1209 @@
+/*
+ * DM81xx hwmod data.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <plat/dmtimer.h>
+#include <plat/irqs-dm81xx.h>
+
+#include "dma.h"
+#include "mmc.h"
+#include "omap_hwmod_common_data.h"
+#include "cm_dm81xx.h"
+#include "dm81xx.h"
+
+/*
+ * DM816X hardware modules integration data
+ *
+ * Note: This is incomplete and at present, not generated from h/w database.
+ *
+ * TODO: Add EDMA in the 'user' field wherever applicable.
+ */
+
+static struct omap_hwmod dm816x_mpu_hwmod;
+static struct omap_hwmod dm816x_l3_slow_hwmod;
+static struct omap_hwmod dm816x_l4_slow_hwmod;
+
+/* L3 SLOW -> L4_SLOW Peripheral interface */
+static struct omap_hwmod_ocp_if dm816x_l3_slow__l4_slow = {
+ .master = &dm816x_l3_slow_hwmod,
+ .slave = &dm816x_l4_slow_hwmod,
+ .user = OCP_USER_MPU,
+};
+
+/* MPU -> L3 SLOW interface */
+static struct omap_hwmod_ocp_if dm816x_mpu__l3_slow = {
+ .master = &dm816x_mpu_hwmod,
+ .slave = &dm816x_l3_slow_hwmod,
+ .user = OCP_USER_MPU,
+};
+
+/* L3 SLOW */
+static struct omap_hwmod dm816x_l3_slow_hwmod = {
+ .name = "l3_main",
+ .class = &l3_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
+};
+
+static struct omap_hwmod dm816x_uart1_hwmod;
+static struct omap_hwmod dm816x_uart2_hwmod;
+static struct omap_hwmod dm816x_uart3_hwmod;
+static struct omap_hwmod dm816x_wd_timer2_hwmod;
+static struct omap_hwmod dm81xx_i2c1_hwmod;
+static struct omap_hwmod dm816x_i2c2_hwmod;
+static struct omap_hwmod dm81xx_gpio1_hwmod;
+static struct omap_hwmod dm81xx_gpio2_hwmod;
+static struct omap_hwmod dm81xx_usbss_hwmod;
+static struct omap_hwmod dm81xx_elm_hwmod;
+static struct omap_hwmod dm816x_mmc1_hwmod;
+static struct omap_hwmod dm816x_iva_hwmod;
+static struct omap_hwmod dm816x_mcspi1_hwmod;
+static struct omap_hwmod dm816x_mailbox_hwmod;
+
+static struct omap_hwmod_ocp_if dm816x_l4_slow__uart1;
+static struct omap_hwmod_ocp_if dm816x_l4_slow__uart2;
+static struct omap_hwmod_ocp_if dm816x_l4_slow__uart3;
+static struct omap_hwmod_ocp_if dm816x_l4_slow__wd_timer2;
+static struct omap_hwmod_ocp_if dm816x_l4_slow__i2c1;
+static struct omap_hwmod_ocp_if dm816x_l4_slow__i2c2;
+static struct omap_hwmod_ocp_if dm81xx_l4_slow__gpio1;
+static struct omap_hwmod_ocp_if dm81xx_l4_slow__gpio2;
+static struct omap_hwmod_ocp_if dm81xx_l4_slow__elm;
+static struct omap_hwmod_ocp_if dm816x_l4_slow__mmc1;
+static struct omap_hwmod_ocp_if dm816x_l3__iva;
+
+/* L4 SLOW */
+static struct omap_hwmod dm816x_l4_slow_hwmod = {
+ .name = "l4_slow",
+ .class = &l4_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
+};
+
+/* MPU */
+static struct omap_hwmod dm816x_mpu_hwmod = {
+ .name = "mpu",
+ .class = &mpu_hwmod_class,
+ .main_clk = "arm_fck",
+};
+
+/* UART common */
+
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+ .rev_offs = 0x50,
+ .sysc_offs = 0x54,
+ .syss_offs = 0x58,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+ .name = "uart",
+ .sysc = &uart_sysc,
+};
+
+/* UART1 */
+
+/* L4 SLOW -> UART1 interface */
+static struct omap_hwmod_addr_space dm816x_uart1_addr_space[] = {
+ {
+ .pa_start = DM81XX_UART1_BASE,
+ .pa_end = DM81XX_UART1_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if dm816x_l4_slow__uart1 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_uart1_hwmod,
+ .clk = "uart1_ick",
+ .addr = dm816x_uart1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_UART0, },
+ { .irq = -1 }
+};
+
+/*
+ * There is no SDMA on DM81XX, instead we have EDMA. Presently using dummy
+ * channel numbers as the omap UART driver (drivers/serial/omap-serial.c)
+ * requires these values to be filled in even if we don't have DMA enabled. Same
+ * applies for other UARTs below.
+ */
+static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dm816x_uart1_hwmod = {
+ .name = "uart1",
+ .mpu_irqs = uart1_mpu_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "uart1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL_OFF,
+ },
+ },
+ .class = &uart_class,
+};
+
+/* UART2 */
+
+/* L4 SLOW -> UART2 interface */
+static struct omap_hwmod_addr_space dm816x_uart2_addr_space[] = {
+ {
+ .pa_start = DM81XX_UART2_BASE,
+ .pa_end = DM81XX_UART2_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if dm816x_l4_slow__uart2 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_uart2_hwmod,
+ .clk = "uart2_ick",
+ .addr = dm816x_uart2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_UART1, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dm816x_uart2_hwmod = {
+ .name = "uart2",
+ .mpu_irqs = uart2_mpu_irqs,
+ .sdma_reqs = uart2_edma_reqs,
+ .main_clk = "uart2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL_OFF,
+ },
+ },
+ .class = &uart_class,
+};
+
+/* UART3 */
+
+/* L4 SLOW -> UART3 interface */
+static struct omap_hwmod_addr_space dm816x_uart3_addr_space[] = {
+ {
+ .pa_start = DM81XX_UART3_BASE,
+ .pa_end = DM81XX_UART3_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if dm816x_l4_slow__uart3 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_uart3_hwmod,
+ .clk = "uart3_ick",
+ .addr = dm816x_uart3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_UART2, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dm816x_uart3_hwmod = {
+ .name = "uart3",
+ .mpu_irqs = uart3_mpu_irqs,
+ .sdma_reqs = uart3_edma_reqs,
+ .main_clk = "uart3_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL_OFF,
+ },
+ },
+ .class = &uart_class,
+};
+
+/* Watchdog */
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class wd_timer_class = {
+ .name = "wd_timer",
+ .sysc = &wd_timer_sysc,
+};
+
+/* L4 SLOW -> Watchdog */
+static struct omap_hwmod_addr_space dm816x_wd_timer2_addrs[] = {
+ {
+ .pa_start = DM816X_WDTIMER1_BASE,
+ .pa_end = DM816X_WDTIMER1_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if dm816x_l4_slow__wd_timer2 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_wd_timer2_hwmod,
+ .clk = "wdt2_ick",
+ .addr = dm816x_wd_timer2_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod dm816x_wd_timer2_hwmod = {
+ .name = "wd_timer2",
+ .main_clk = "wdt2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL_OFF,
+ },
+ },
+ .class = &wd_timer_class,
+ .flags = HWMOD_INIT_NO_RESET,
+};
+
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x90,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &i2c_sysc,
+};
+
+/* I2C1 */
+
+/* L4 SLOW -> I2C1 */
+static struct omap_hwmod_addr_space dm816x_i2c1_addr_space[] = {
+ {
+ .pa_start = DM816X_I2C0_BASE,
+ .pa_end = DM816X_I2C0_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if dm816x_l4_slow__i2c1 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm81xx_i2c1_hwmod,
+ .clk = "i2c1_ick",
+ .addr = dm816x_i2c1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_I2C0, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dm81xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_edma_reqs,
+ .main_clk = "i2c1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM816X_CM_ALWON_I2C_0_CLKCTRL_OFF,
+ },
+ },
+ .class = &i2c_class,
+};
+
+/* I2C2 */
+
+/* L4 SLOW -> I2C2 */
+static struct omap_hwmod_addr_space dm816x_i2c2_addr_space[] = {
+ {
+ .pa_start = DM816X_I2C1_BASE,
+ .pa_end = DM816X_I2C1_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if dm816x_l4_slow__i2c2 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_i2c2_hwmod,
+ .clk = "i2c2_ick",
+ .addr = dm816x_i2c2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_I2C1, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dm816x_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_edma_reqs,
+ .main_clk = "i2c2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM816X_CM_ALWON_I2C_1_CLKCTRL_OFF,
+ },
+ },
+ .class = &i2c_class,
+};
+
+/* ELM */
+static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+/* 'elm' class */
+static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
+ .name = "elm",
+ .sysc = &dm81xx_elm_sysc,
+};
+
+static struct omap_hwmod_irq_info dm81xx_elm_irqs[] = {
+ { .irq = DM81XX_IRQ_ELM },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_addr_space dm81xx_elm_addr_space[] = {
+ {
+ .pa_start = DM81XX_ELM_BASE,
+ .pa_end = DM81XX_ELM_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_slow__elm = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm81xx_elm_hwmod,
+ .addr = dm81xx_elm_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* elm */
+static struct omap_hwmod dm81xx_elm_hwmod = {
+ .name = "elm",
+ .class = &dm81xx_elm_hwmod_class,
+ .main_clk = "elm_fck",
+ .mpu_irqs = dm81xx_elm_irqs,
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &dm81xx_gpio_sysc,
+ .rev = 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* GPIO1 DM81XX */
+
+/* L4 SLOW -> GPIO1 */
+static struct omap_hwmod_addr_space dm81xx_gpio1_addrs[] = {
+ {
+ .pa_start = DM81XX_GPIO0_BASE,
+ .pa_end = DM81XX_GPIO0_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_slow__gpio1 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm81xx_gpio1_hwmod,
+ .addr = dm81xx_gpio1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_irq_info dm81xx_gpio1_irqs[] = {
+ { .irq = DM81XX_IRQ_GPIO_0A },
+ { .irq = DM81XX_IRQ_GPIO_0B },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbck" },
+};
+
+static struct omap_hwmod dm81xx_gpio1_hwmod = {
+ .name = "gpio1",
+ .class = &dm81xx_gpio_hwmod_class,
+ .mpu_irqs = dm81xx_gpio1_irqs,
+ .main_clk = "gpio1_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL_OFF,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* GPIO2 DM81XX*/
+
+/* L4 SLOW -> GPIO2 */
+static struct omap_hwmod_addr_space dm81xx_gpio2_addrs[] = {
+ {
+ .pa_start = DM81XX_GPIO1_BASE,
+ .pa_end = DM81XX_GPIO1_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_slow__gpio2 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm81xx_gpio2_hwmod,
+ .addr = dm81xx_gpio2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_irq_info dm81xx_gpio2_irqs[] = {
+ { .irq = DM81XX_IRQ_GPIO_1A },
+ { .irq = DM81XX_IRQ_GPIO_1B },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbck" },
+};
+
+static struct omap_hwmod dm81xx_gpio2_hwmod = {
+ .name = "gpio2",
+ .class = &dm81xx_gpio_hwmod_class,
+ .mpu_irqs = dm81xx_gpio2_irqs,
+ .main_clk = "gpio2_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL_OFF,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* L3 SLOW -> USBSS interface */
+static struct omap_hwmod_addr_space dm81xx_usbss_addr_space[] = {
+ {
+ .name = "usbss",
+ .pa_start = DM81XX_USBSS_BASE,
+ .pa_end = DM81XX_USBSS_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb0",
+ .pa_start = DM81XX_USB0_BASE,
+ .pa_end = DM81XX_USB0_BASE + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb1",
+ .pa_start = DM81XX_USB1_BASE,
+ .pa_end = DM81XX_USB1_BASE + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+};
+
+static struct omap_hwmod_class dm81xx_usbotg_class = {
+ .name = "usbotg",
+ .sysc = &dm81xx_usbhsotg_sysc,
+};
+
+static struct omap_hwmod_irq_info dm81xx_usbss_mpu_irqs[] = {
+ { .name = "usbss-irq", .irq = DM81XX_IRQ_USBSS, },
+ { .name = "musb0-irq", .irq = DM81XX_IRQ_USB0, },
+ { .name = "musb1-irq", .irq = DM81XX_IRQ_USB1, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l3_slow__usbss = {
+ .master = &dm816x_l3_slow_hwmod,
+ .slave = &dm81xx_usbss_hwmod,
+ .clk = "usb_ick",
+ .addr = dm81xx_usbss_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod dm81xx_usbss_hwmod = {
+ .name = "usb_otg_hs",
+ .mpu_irqs = dm81xx_usbss_mpu_irqs,
+ .main_clk = "usb_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL_OFF,
+ },
+ },
+ .class = &dm81xx_usbotg_class,
+};
+
+/* timer class */
+static struct omap_hwmod_class_sysconfig dm816x_timer_1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dm816x_timer_1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &dm816x_timer_1ms_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dm816x_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &dm816x_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+ .timer_capability = OMAP_TIMER_ALWON,
+};
+
+/* timer1 */
+static struct omap_hwmod dm816x_timer1_hwmod;
+
+static struct omap_hwmod_addr_space dm816x_timer1_addrs[] = {
+ {
+ .pa_start = DM816X_TIMER0_BASE,
+ .pa_end = DM816X_TIMER0_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_irq_info dm816x_timer1_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_GPT1, },
+ { .irq = -1 }
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if dm816x_l4_wkup__timer1 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_timer1_hwmod,
+ .clk = "gpt1_ick",
+ .addr = dm816x_timer1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod dm816x_timer1_hwmod = {
+ .name = "timer1",
+ .mpu_irqs = dm816x_timer1_mpu_irqs,
+ .main_clk = "gpt1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM816X_CM_ALWON_TIMER_0_CLKCTRL_OFF,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &dm816x_timer_1ms_hwmod_class,
+};
+
+/* timer2 */
+static struct omap_hwmod dm816x_timer2_hwmod;
+
+static struct omap_hwmod_addr_space dm816x_timer2_addrs[] = {
+ {
+ .pa_start = DM816X_TIMER1_BASE,
+ .pa_end = DM816X_TIMER1_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_irq_info dm816x_timer2_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_GPT2, },
+ { .irq = -1 }
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if dm816x_l4_per__timer2 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_timer2_hwmod,
+ .clk = "gpt2_ick",
+ .addr = dm816x_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod dm816x_timer2_hwmod = {
+ .name = "timer2",
+ .mpu_irqs = dm816x_timer2_mpu_irqs,
+ .main_clk = "gpt2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL_OFF,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &dm816x_timer_1ms_hwmod_class,
+};
+
+/* timer3 */
+static struct omap_hwmod dm816x_timer3_hwmod;
+
+static struct omap_hwmod_addr_space dm816x_timer3_addrs[] = {
+ {
+ .pa_start = DM816X_TIMER2_BASE,
+ .pa_end = DM816X_TIMER2_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_irq_info dm816x_timer3_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_GPT3, },
+ { .irq = -1 }
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if dm816x_l4_per__timer3 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_timer3_hwmod,
+ .clk = "gpt3_ick",
+ .addr = dm816x_timer3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod dm816x_timer3_hwmod = {
+ .name = "timer3",
+ .mpu_irqs = dm816x_timer3_mpu_irqs,
+ .main_clk = "gpt3_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL_OFF,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &dm816x_timer_hwmod_class,
+};
+
+/* timer4 */
+static struct omap_hwmod dm816x_timer4_hwmod;
+
+static struct omap_hwmod_addr_space dm816x_timer4_addrs[] = {
+ {
+ .pa_start = DM816X_TIMER3_BASE,
+ .pa_end = DM816X_TIMER3_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_irq_info dm816x_timer4_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_GPT4, },
+ { .irq = -1 }
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if dm816x_l4_per__timer4 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_timer4_hwmod,
+ .clk = "gpt4_ick",
+ .addr = dm816x_timer4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod dm816x_timer4_hwmod = {
+ .name = "timer4",
+ .mpu_irqs = dm816x_timer4_mpu_irqs,
+ .main_clk = "gpt4_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL_OFF,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &dm816x_timer_hwmod_class,
+};
+
+/* timer5 */
+static struct omap_hwmod dm816x_timer5_hwmod;
+
+static struct omap_hwmod_addr_space dm816x_timer5_addrs[] = {
+ {
+ .pa_start = DM816X_TIMER4_BASE,
+ .pa_end = DM816X_TIMER4_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_irq_info dm816x_timer5_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_GPT5, },
+ { .irq = -1 }
+};
+
+/* l4_per -> timer5 */
+static struct omap_hwmod_ocp_if dm816x_l4_per__timer5 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_timer5_hwmod,
+ .clk = "gpt5_ick",
+ .addr = dm816x_timer5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod dm816x_timer5_hwmod = {
+ .name = "timer5",
+ .mpu_irqs = dm816x_timer5_mpu_irqs,
+ .main_clk = "gpt5_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL_OFF,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &dm816x_timer_hwmod_class,
+};
+
+/* timer6 */
+static struct omap_hwmod dm816x_timer6_hwmod;
+
+static struct omap_hwmod_addr_space dm816x_timer6_addrs[] = {
+ {
+ .pa_start = DM816X_TIMER5_BASE,
+ .pa_end = DM816X_TIMER5_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_irq_info dm816x_timer6_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_GPT6, },
+ { .irq = -1 }
+};
+
+/* l4_per -> timer6 */
+static struct omap_hwmod_ocp_if dm816x_l4_per__timer6 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_timer6_hwmod,
+ .clk = "gpt6_ick",
+ .addr = dm816x_timer6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod dm816x_timer6_hwmod = {
+ .name = "timer6",
+ .mpu_irqs = dm816x_timer6_mpu_irqs,
+ .main_clk = "gpt6_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL_OFF,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &dm816x_timer_hwmod_class,
+};
+
+/* timer7 */
+static struct omap_hwmod dm816x_timer7_hwmod;
+
+static struct omap_hwmod_addr_space dm816x_timer7_addrs[] = {
+ {
+ .pa_start = DM816X_TIMER6_BASE,
+ .pa_end = DM816X_TIMER6_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_irq_info dm816x_timer7_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_GPT7, },
+ { .irq = -1 }
+};
+
+/* l4_per -> timer7 */
+static struct omap_hwmod_ocp_if dm816x_l4_per__timer7 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_timer7_hwmod,
+ .clk = "gpt7_ick",
+ .addr = dm816x_timer7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod dm816x_timer7_hwmod = {
+ .name = "timer7",
+ .mpu_irqs = dm816x_timer7_mpu_irqs,
+ .main_clk = "gpt7_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL_OFF,
+ },
+ },
+ .dev_attr = &capability_alwon_dev_attr,
+ .class = &dm816x_timer_hwmod_class,
+};
+
+/* MMC/SD/SDIO common */
+
+static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x110,
+ .syss_offs = 0x114,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dm816x_mmc_class = {
+ .name = "mmc",
+ .sysc = &dm816x_mmc_sysc,
+};
+
+/* MMC/SD/SDIO1 */
+
+static struct omap_hwmod_irq_info dm816x_mmc1_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_SD, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dm816x_mmc1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_MMC1_TX, },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_MMC1_RX, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks[] = {
+ { .role = "dbck", .clk = "sys_32k_ck", },
+};
+
+struct omap_hwmod_addr_space dm816x_mmc1_addr_space[] = {
+ {
+ .pa_start = DM816X_MMC0_BASE,
+ .pa_end = DM816X_MMC0_BASE + SZ_64K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if dm816x_l4_slow__mmc1 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_mmc1_hwmod,
+ .clk = "mmchs1_ick",
+ .addr = dm816x_mmc1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .flags = OMAP_FIREWALL_L4
+};
+
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod dm816x_mmc1_hwmod = {
+ .name = "mmc1",
+ .mpu_irqs = dm816x_mmc1_mpu_irqs,
+ .sdma_reqs = dm816x_mmc1_sdma_reqs,
+ .opt_clks = dm816x_mmc1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dm816x_mmc1_opt_clks),
+ .main_clk = "mmchs1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL_OFF,
+ },
+ },
+ .dev_attr = &mmc1_dev_attr,
+ .class = &dm816x_mmc_class,
+};
+
+/*
+ * IVA2_2 interface data
+ */
+
+/* IVA2 <- L3 interface */
+static struct omap_hwmod_ocp_if dm816x_l3__iva = {
+ .master = &dm816x_l3_slow_hwmod,
+ .slave = &dm816x_iva_hwmod,
+ .clk = "iva2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* IVA2 (IVA2) */
+
+static struct omap_hwmod dm816x_iva_hwmod = {
+ .name = "iva",
+ .class = &iva_hwmod_class,
+};
+
+/* MCSPI */
+
+struct omap_hwmod_addr_space dm816x_mcspi1_addr_space[] = {
+ {
+ .pa_start = DM816X_SPI0_BASE + 0x100,
+ .pa_end = DM816X_SPI0_BASE - 0x100 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+/* l4 core -> mcspi1 interface */
+static struct omap_hwmod_ocp_if dm816x_l4_core__mcspi1 = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_mcspi1_hwmod,
+ .clk = "mcspi1_ick",
+ .addr = dm816x_mcspi1_addr_space,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dm816x_mcspi_class = {
+ .name = "mcspi",
+ .sysc = &dm816x_mcspi_sysc,
+ .rev = OMAP3_MCSPI_REV,
+};
+
+static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
+ .num_chipselect = 4,
+};
+
+struct omap_hwmod_irq_info dm816x_mcspi1_mpu_irqs[] = {
+ { .irq = DM81XX_IRQ_SPI },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_dma_info dm816x_mcspi1_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = OMAP24XX_DMA_SPI1_TX0 },
+ { .name = "rx0", .dma_req = OMAP24XX_DMA_SPI1_RX0 },
+ { .name = "tx1", .dma_req = OMAP24XX_DMA_SPI1_TX1 },
+ { .name = "rx1", .dma_req = OMAP24XX_DMA_SPI1_RX1 },
+ { .name = "tx2", .dma_req = OMAP24XX_DMA_SPI1_TX2 },
+ { .name = "rx2", .dma_req = OMAP24XX_DMA_SPI1_RX2 },
+ { .name = "tx3", .dma_req = OMAP24XX_DMA_SPI1_TX3 },
+ { .name = "rx3", .dma_req = OMAP24XX_DMA_SPI1_RX3 },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dm816x_mcspi1_hwmod = {
+ .name = "mcspi1",
+ .mpu_irqs = dm816x_mcspi1_mpu_irqs,
+ .sdma_reqs = dm816x_mcspi1_sdma_reqs,
+ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL_OFF,
+ },
+ },
+ .class = &dm816x_mcspi_class,
+ .dev_attr = &dm816x_mcspi1_dev_attr,
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig dm816x_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dm816x_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &dm816x_mailbox_sysc,
+};
+
+static struct omap_hwmod_irq_info dm816x_mailbox_irqs[] = {
+ { .irq = DM81XX_IRQ_MBOX },
+ { .irq = -1 }
+};
+
+#define DM81XX_MBOX_REG_SIZE 0x144
+static struct omap_hwmod_addr_space dm816x_mailbox_addrs[] = {
+ {
+ .pa_start = DM81XX_MAILBOX_BASE,
+ .pa_end = DM81XX_MAILBOX_BASE + DM81XX_MBOX_REG_SIZE - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if dm816x_l4_core__mailbox = {
+ .master = &dm816x_l4_slow_hwmod,
+ .slave = &dm816x_mailbox_hwmod,
+ .addr = dm816x_mailbox_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod dm816x_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &dm816x_mailbox_hwmod_class,
+ .mpu_irqs = dm816x_mailbox_irqs,
+ .main_clk = "mailbox_ick",
+ .prcm = {
+ .omap4 = {
+ },
+ },
+};
+
+static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
+ &dm816x_mpu__l3_slow,
+ &dm816x_l3_slow__l4_slow,
+ &dm816x_l4_slow__uart1,
+ &dm816x_l4_slow__uart2,
+ &dm816x_l4_slow__uart3,
+ &dm816x_l4_slow__wd_timer2,
+ &dm816x_l4_slow__i2c1,
+ &dm816x_l4_slow__i2c2,
+ &dm81xx_l4_slow__gpio1,
+ &dm81xx_l4_slow__gpio2,
+ &dm81xx_l4_slow__elm,
+ &dm816x_l4_slow__mmc1,
+ &dm81xx_l3_slow__usbss,
+ &dm816x_l4_wkup__timer1,
+ &dm816x_l4_per__timer2,
+ &dm816x_l4_per__timer3,
+ &dm816x_l4_per__timer4,
+ &dm816x_l4_per__timer5,
+ &dm816x_l4_per__timer6,
+ &dm816x_l4_per__timer7,
+ &dm816x_l4_core__mcspi1,
+ &dm816x_l4_core__mailbox,
+ &dm816x_l3__iva,
+ NULL,
+};
+
+int __init dm81xx_hwmod_init(void)
+{
+ omap_hwmod_init();
+ return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index fb92abb..dd66663 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -58,6 +58,12 @@
#define OMAP_TIMER_NONPOSTED 0x00
#define OMAP_TIMER_POSTED 0x01
+/*
+ * IP revision identifier so that Highlander IP
+ * in OMAP4 can be distinguished.
+ */
+#define OMAP_TIMER_IP_VERSION_1 0x1
+
/* timer capabilities used in hwmod database */
#define OMAP_TIMER_SECURE 0x80000000
#define OMAP_TIMER_ALWON 0x40000000
diff --git a/arch/arm/plat-omap/include/plat/irqs-dm81xx.h b/arch/arm/plat-omap/include/plat/irqs-dm81xx.h
new file mode 100644
index 0000000..2a44864
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/irqs-dm81xx.h
@@ -0,0 +1,43 @@
+/*
+ * DM81xx family interrupts.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_DM81XX_IRQS_H
+#define __ARCH_ARM_MACH_OMAP2_DM81XX_IRQS_H
+
+#define DM81XX_IRQ_ELM 4
+#define DM81XX_IRQ_USBSS 17
+#define DM81XX_IRQ_USB0 18
+#define DM81XX_IRQ_USB1 19
+#define DM81XX_IRQ_SD 64
+#define DM81XX_IRQ_SPI 65
+#define DM81XX_IRQ_GPT1 67
+#define DM81XX_IRQ_GPT2 68
+#define DM81XX_IRQ_GPT3 69
+#define DM81XX_IRQ_I2C0 70
+#define DM81XX_IRQ_I2C1 71
+#define DM81XX_IRQ_UART0 72
+#define DM81XX_IRQ_UART1 73
+#define DM81XX_IRQ_UART2 74
+#define DM81XX_IRQ_MBOX 77
+#define DM81XX_IRQ_GPT4 92
+#define DM81XX_IRQ_GPT5 93
+#define DM81XX_IRQ_GPT6 94
+#define DM81XX_IRQ_GPT7 95
+#define DM81XX_IRQ_GPIO_0A 96
+#define DM81XX_IRQ_GPIO_0B 97
+#define DM81XX_IRQ_GPIO_1A 98
+#define DM81XX_IRQ_GPIO_1B 99
+#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4
2013-06-05 15:29 [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4 Aida Mynzhasova
` (3 preceding siblings ...)
2013-06-05 15:29 ` [PATCH 5/5] ARM: OMAP: DM816x: add hwmod support for DM81xx Aida Mynzhasova
@ 2013-06-06 3:54 ` Paul Walmsley
2013-06-06 6:03 ` Aida Mynzhasova
2013-06-06 4:16 ` Paul Walmsley
5 siblings, 1 reply; 9+ messages in thread
From: Paul Walmsley @ 2013-06-06 3:54 UTC (permalink / raw)
To: linux-arm-kernel
????????????,
On Wed, 5 Jun 2013, Aida Mynzhasova wrote:
> Not so long ago I tried to boot Linux 3.10-rc4 kernel on DM816x EVM
> board. Unfortunately, my attempts were failed by reason of poor
> support of DM81xx-based devices in new kernels.
Yeah, TI pretty much gave up on trying to get support for that chip
upstream a few years ago. Same for DM814x.
> So, I suggest you this patch series, which fixes that kernel crush and
> adds new functions/structures, required for early initialization on
> DM816x (power and clock domains, hwmods). After applying these patches
> the kernel is able to successfully continue booting till clock
> initialization (will be added later).
OK, it will be great to get my DM8168EVM booting on mainline. But there
are a few preliminary issues with the patches:
1. All new chip and board support needs to be DT-only. So, no new board
files. Also, all the hwmod data shouldn't have IRQ, DMA, etc. data - that
should come from DT. See for example the recently posted patch "[PATCH
13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up"
2. Looks like patch 2 is missing from the list. If it's too big for the
list, please break it down into smaller patches.
3. Did you write this code and data, hwmods, etc., or did it come from a
TI kernel? Please note this clearly in the patch descriptions.
- Paul
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4
2013-06-05 15:29 [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4 Aida Mynzhasova
` (4 preceding siblings ...)
2013-06-06 3:54 ` [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4 Paul Walmsley
@ 2013-06-06 4:16 ` Paul Walmsley
2013-06-06 15:55 ` Tony Lindgren
5 siblings, 1 reply; 9+ messages in thread
From: Paul Walmsley @ 2013-06-06 4:16 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
also,
On Wed, 5 Jun 2013, Aida Mynzhasova wrote:
> Aida Mynzhasova (5):
> ARM: OMAP: AM33xx: multiple renames for early initialization
If this patch is what's responsible for all the file renaming, please drop
it. Looks from the change summary that it's just useless churn (although
I haven't seen the patch here since it never made it to the lists)
- Paul
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4
2013-06-06 3:54 ` [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4 Paul Walmsley
@ 2013-06-06 6:03 ` Aida Mynzhasova
0 siblings, 0 replies; 9+ messages in thread
From: Aida Mynzhasova @ 2013-06-06 6:03 UTC (permalink / raw)
To: linux-arm-kernel
On 06.06.2013 07:54, Paul Walmsley wrote:
> ????????????,
>
> On Wed, 5 Jun 2013, Aida Mynzhasova wrote:
>
>> Not so long ago I tried to boot Linux 3.10-rc4 kernel on DM816x EVM
>> board. Unfortunately, my attempts were failed by reason of poor
>> support of DM81xx-based devices in new kernels.
>
> Yeah, TI pretty much gave up on trying to get support for that chip
> upstream a few years ago. Same for DM814x.
>
>> So, I suggest you this patch series, which fixes that kernel crush and
>> adds new functions/structures, required for early initialization on
>> DM816x (power and clock domains, hwmods). After applying these patches
>> the kernel is able to successfully continue booting till clock
>> initialization (will be added later).
>
> OK, it will be great to get my DM8168EVM booting on mainline. But there
> are a few preliminary issues with the patches:
>
> 1. All new chip and board support needs to be DT-only. So, no new board
> files. Also, all the hwmod data shouldn't have IRQ, DMA, etc. data - that
> should come from DT. See for example the recently posted patch "[PATCH
> 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up"
>
> 2. Looks like patch 2 is missing from the list. If it's too big for the
> list, please break it down into smaller patches.
>
> 3. Did you write this code and data, hwmods, etc., or did it come from a
> TI kernel? Please note this clearly in the patch descriptions.
>
>
> - Paul
>
Hi!
Thanks for reply!
ok, I'll rewrite code by means of DT and add some additional notes to
patch description.
Aida.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4
2013-06-06 4:16 ` Paul Walmsley
@ 2013-06-06 15:55 ` Tony Lindgren
0 siblings, 0 replies; 9+ messages in thread
From: Tony Lindgren @ 2013-06-06 15:55 UTC (permalink / raw)
To: linux-arm-kernel
* Paul Walmsley <paul@pwsan.com> [130605 21:22]:
> Hi,
>
> also,
>
> On Wed, 5 Jun 2013, Aida Mynzhasova wrote:
>
> > Aida Mynzhasova (5):
> > ARM: OMAP: AM33xx: multiple renames for early initialization
>
> If this patch is what's responsible for all the file renaming, please drop
> it. Looks from the change summary that it's just useless churn (although
> I haven't seen the patch here since it never made it to the lists)
Yes no reason for all the renaming, marketing names can be
whatever. For example, we have am/dm37xx too which is really
omap36xx.
Regards,
Tony
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2013-06-06 15:55 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-06-05 15:29 [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4 Aida Mynzhasova
2013-06-05 15:29 ` [PATCH 1/5] ARM: OMAP: DM81xx: multiple renames for DM81xx platform Aida Mynzhasova
2013-06-05 15:29 ` [PATCH 3/5] ARM: OMAP: DM816x: add powerdomains for DM816x Aida Mynzhasova
2013-06-05 15:29 ` [PATCH 4/5] ARM: OMAP: DM816x: add clock domain support " Aida Mynzhasova
2013-06-05 15:29 ` [PATCH 5/5] ARM: OMAP: DM816x: add hwmod support for DM81xx Aida Mynzhasova
2013-06-06 3:54 ` [PATCH 0/5] Broken DM816x support in Linux 3.10-rc4 Paul Walmsley
2013-06-06 6:03 ` Aida Mynzhasova
2013-06-06 4:16 ` Paul Walmsley
2013-06-06 15:55 ` Tony Lindgren
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