* [PATCH 0/4] clk, mfd: u8540 clock tree definition
@ 2013-05-27 12:41 Philippe Begnic
2013-05-27 12:41 ` [PATCH 1/4] clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 Philippe Begnic
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Philippe Begnic @ 2013-05-27 12:41 UTC (permalink / raw)
To: linux-arm-kernel
From: Philippe Begnic <philippe.begnic@st.com>
Create U8540 clock tree definitions for common clock framework
Philippe Begnic (4):
clk: ux500: Pass clock base adresses in initcall for u8540 and u9540
mfd: db8500: Update register definition for u8540 clock
mfd: db8500: Update BML clock register for db8580
clk: ux500: Clocks definition for u8540
arch/arm/mach-ux500/cpu.c | 6 +-
drivers/clk/ux500/u8540_clk.c | 564 ++++++++++++++++++++++++++++-
drivers/clk/ux500/u9540_clk.c | 4 +-
drivers/mfd/db8500-prcmu.c | 1 +
drivers/mfd/dbx500-prcmu-regs.h | 1 +
include/linux/mfd/abx500/ab8500-sysctrl.h | 4 +-
include/linux/mfd/dbx500-prcmu.h | 12 +
include/linux/platform_data/clk-ux500.h | 6 +-
8 files changed, 587 insertions(+), 11 deletions(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 1/4] clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 2013-05-27 12:41 [PATCH 0/4] clk, mfd: u8540 clock tree definition Philippe Begnic @ 2013-05-27 12:41 ` Philippe Begnic 2013-05-27 12:49 ` Ulf Hansson 2013-05-27 12:41 ` [PATCH 2/4] mfd: db8500: Update register definition for u8540 clock Philippe Begnic ` (3 subsequent siblings) 4 siblings, 1 reply; 11+ messages in thread From: Philippe Begnic @ 2013-05-27 12:41 UTC (permalink / raw) To: linux-arm-kernel From: Philippe Begnic <philippe.begnic@st.com> Align on u8500 version, pass clock base address in clk_init functions for u8540 and u9540. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Philippe Begnic <philippe.begnic@st.com> --- arch/arm/mach-ux500/cpu.c | 6 ++++-- drivers/clk/ux500/u8540_clk.c | 4 ++-- drivers/clk/ux500/u9540_clk.c | 4 ++-- include/linux/platform_data/clk-ux500.h | 6 ++++-- 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index b6145ea..e6fb023 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -76,13 +76,15 @@ void __init ux500_init_irq(void) } else if (cpu_is_u9540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); - u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, + u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, U8500_CLKRST6_BASE); } else if (cpu_is_u8540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); - u8540_clk_init(); + u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, + U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, + U8500_CLKRST6_BASE); } } diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c index 10adfd2..90f3c88 100644 --- a/drivers/clk/ux500/u8540_clk.c +++ b/drivers/clk/ux500/u8540_clk.c @@ -12,10 +12,10 @@ #include <linux/clk-provider.h> #include <linux/mfd/dbx500-prcmu.h> #include <linux/platform_data/clk-ux500.h> - #include "clk.h" -void u8540_clk_init(void) +void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, + u32 clkrst5_base, u32 clkrst6_base) { /* register clocks here */ } diff --git a/drivers/clk/ux500/u9540_clk.c b/drivers/clk/ux500/u9540_clk.c index dbc0191..4479478 100644 --- a/drivers/clk/ux500/u9540_clk.c +++ b/drivers/clk/ux500/u9540_clk.c @@ -12,10 +12,10 @@ #include <linux/clk-provider.h> #include <linux/mfd/dbx500-prcmu.h> #include <linux/platform_data/clk-ux500.h> - #include "clk.h" -void u9540_clk_init(void) +void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, + u32 clkrst5_base, u32 clkrst6_base) { /* register clocks here */ } diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h index 320d9c3..9d98f3a 100644 --- a/include/linux/platform_data/clk-ux500.h +++ b/include/linux/platform_data/clk-ux500.h @@ -12,7 +12,9 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, u32 clkrst5_base, u32 clkrst6_base); -void u9540_clk_init(void); -void u8540_clk_init(void); +void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, + u32 clkrst5_base, u32 clkrst6_base); +void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, + u32 clkrst5_base, u32 clkrst6_base); #endif /* __CLK_UX500_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 1/4] clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 2013-05-27 12:41 ` [PATCH 1/4] clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 Philippe Begnic @ 2013-05-27 12:49 ` Ulf Hansson 0 siblings, 0 replies; 11+ messages in thread From: Ulf Hansson @ 2013-05-27 12:49 UTC (permalink / raw) To: linux-arm-kernel On 27 May 2013 14:41, Philippe Begnic <philippe.begnic.st@gmail.com> wrote: > From: Philippe Begnic <philippe.begnic@st.com> > > Align on u8500 version, pass clock base address in clk_init functions > for u8540 and u9540. > > Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> > Signed-off-by: Philippe Begnic <philippe.begnic@st.com> > --- > arch/arm/mach-ux500/cpu.c | 6 ++++-- > drivers/clk/ux500/u8540_clk.c | 4 ++-- > drivers/clk/ux500/u9540_clk.c | 4 ++-- > include/linux/platform_data/clk-ux500.h | 6 ++++-- > 4 files changed, 12 insertions(+), 8 deletions(-) > > diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c > index b6145ea..e6fb023 100644 > --- a/arch/arm/mach-ux500/cpu.c > +++ b/arch/arm/mach-ux500/cpu.c > @@ -76,13 +76,15 @@ void __init ux500_init_irq(void) > } else if (cpu_is_u9540()) { > prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); > ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); > - u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, > + u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, > U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, > U8500_CLKRST6_BASE); > } else if (cpu_is_u8540()) { > prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); > ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); > - u8540_clk_init(); > + u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, > + U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, > + U8500_CLKRST6_BASE); > } > } > > diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c > index 10adfd2..90f3c88 100644 > --- a/drivers/clk/ux500/u8540_clk.c > +++ b/drivers/clk/ux500/u8540_clk.c > @@ -12,10 +12,10 @@ > #include <linux/clk-provider.h> > #include <linux/mfd/dbx500-prcmu.h> > #include <linux/platform_data/clk-ux500.h> > - > #include "clk.h" > > -void u8540_clk_init(void) > +void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, > + u32 clkrst5_base, u32 clkrst6_base) > { > /* register clocks here */ > } > diff --git a/drivers/clk/ux500/u9540_clk.c b/drivers/clk/ux500/u9540_clk.c > index dbc0191..4479478 100644 > --- a/drivers/clk/ux500/u9540_clk.c > +++ b/drivers/clk/ux500/u9540_clk.c > @@ -12,10 +12,10 @@ > #include <linux/clk-provider.h> > #include <linux/mfd/dbx500-prcmu.h> > #include <linux/platform_data/clk-ux500.h> > - > #include "clk.h" > > -void u9540_clk_init(void) > +void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, > + u32 clkrst5_base, u32 clkrst6_base) > { > /* register clocks here */ > } > diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h > index 320d9c3..9d98f3a 100644 > --- a/include/linux/platform_data/clk-ux500.h > +++ b/include/linux/platform_data/clk-ux500.h > @@ -12,7 +12,9 @@ > > void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, > u32 clkrst5_base, u32 clkrst6_base); > -void u9540_clk_init(void); > -void u8540_clk_init(void); > +void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, > + u32 clkrst5_base, u32 clkrst6_base); > +void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, > + u32 clkrst5_base, u32 clkrst6_base); > > #endif /* __CLK_UX500_H */ > -- > 1.7.9.5 > Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/4] mfd: db8500: Update register definition for u8540 clock 2013-05-27 12:41 [PATCH 0/4] clk, mfd: u8540 clock tree definition Philippe Begnic 2013-05-27 12:41 ` [PATCH 1/4] clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 Philippe Begnic @ 2013-05-27 12:41 ` Philippe Begnic 2013-05-27 12:41 ` [PATCH 3/4] mfd: db8500: Update BML clock register for db8580 Philippe Begnic ` (2 subsequent siblings) 4 siblings, 0 replies; 11+ messages in thread From: Philippe Begnic @ 2013-05-27 12:41 UTC (permalink / raw) To: linux-arm-kernel From: Philippe Begnic <philippe.begnic@st.com> PRCMU and ab8500 registers updated for u8540 Signed-off-by: Philippe Begnic <philippe.begnic@st.com> --- include/linux/mfd/abx500/ab8500-sysctrl.h | 4 ++-- include/linux/mfd/dbx500-prcmu.h | 11 +++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h index 990bc93..adba89d 100644 --- a/include/linux/mfd/abx500/ab8500-sysctrl.h +++ b/include/linux/mfd/abx500/ab8500-sysctrl.h @@ -278,8 +278,8 @@ struct ab8500_sysctrl_platform_data { #define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0) #define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1) -#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C -#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2 +#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0 BIT(2) +#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1 BIT(3) #define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4) #define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5) #define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6) diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index 689e6a0..d0ba355 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -134,6 +134,10 @@ enum prcmu_clock { PRCMU_SIACLK, PRCMU_SVACLK, PRCMU_ACLK, + PRCMU_HVACLK, /* Ux540 only */ + PRCMU_G1CLK, /* Ux540 only */ + PRCMU_SDMMCHCLK, + PRCMU_CAMCLK, PRCMU_NUM_REG_CLOCKS, PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, PRCMU_CDCLK, @@ -148,6 +152,13 @@ enum prcmu_clock { PRCMU_DSI0ESCCLK, PRCMU_DSI1ESCCLK, PRCMU_DSI2ESCCLK, + /* LCD DSI PLL - Ux540 only */ + PRCMU_PLLDSI_LCD, + PRCMU_DSI0CLK_LCD, + PRCMU_DSI1CLK_LCD, + PRCMU_DSI0ESCCLK_LCD, + PRCMU_DSI1ESCCLK_LCD, + PRCMU_DSI2ESCCLK_LCD, }; /** -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/4] mfd: db8500: Update BML clock register for db8580 2013-05-27 12:41 [PATCH 0/4] clk, mfd: u8540 clock tree definition Philippe Begnic 2013-05-27 12:41 ` [PATCH 1/4] clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 Philippe Begnic 2013-05-27 12:41 ` [PATCH 2/4] mfd: db8500: Update register definition for u8540 clock Philippe Begnic @ 2013-05-27 12:41 ` Philippe Begnic 2013-05-27 12:41 ` [PATCH 4/4] clk: ux500: Clocks definition for u8540 Philippe Begnic 2013-05-31 1:25 ` [PATCH 0/4] clk, mfd: u8540 clock tree definition Mike Turquette 4 siblings, 0 replies; 11+ messages in thread From: Philippe Begnic @ 2013-05-27 12:41 UTC (permalink / raw) To: linux-arm-kernel From: Philippe Begnic <philippe.begnic@st.com> BML clock register address in DB8580 has changed.Defined a new address under different name for DB8580. Signed-off-by: Philippe Begnic <philippe.begnic@st.com> --- drivers/mfd/db8500-prcmu.c | 1 + drivers/mfd/dbx500-prcmu-regs.h | 1 + include/linux/mfd/dbx500-prcmu.h | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 66f8097..a292a1d 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -480,6 +480,7 @@ struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), + CLK_MGT_ENTRY(BML8580CLK, PLL_DIV, true), CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h index d14836e..ca355dd 100644 --- a/drivers/mfd/dbx500-prcmu-regs.h +++ b/drivers/mfd/dbx500-prcmu-regs.h @@ -32,6 +32,7 @@ #define PRCM_PER7CLK_MGT (0x040) #define PRCM_LCDCLK_MGT (0x044) #define PRCM_BMLCLK_MGT (0x04C) +#define PRCM_BML8580CLK_MGT (0x108) #define PRCM_HSITXCLK_MGT (0x050) #define PRCM_HSIRXCLK_MGT (0x054) #define PRCM_HDMICLK_MGT (0x058) diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index d0ba355..ca0790f 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -138,6 +138,7 @@ enum prcmu_clock { PRCMU_G1CLK, /* Ux540 only */ PRCMU_SDMMCHCLK, PRCMU_CAMCLK, + PRCMU_BML8580CLK, PRCMU_NUM_REG_CLOCKS, PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, PRCMU_CDCLK, -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/4] clk: ux500: Clocks definition for u8540 2013-05-27 12:41 [PATCH 0/4] clk, mfd: u8540 clock tree definition Philippe Begnic ` (2 preceding siblings ...) 2013-05-27 12:41 ` [PATCH 3/4] mfd: db8500: Update BML clock register for db8580 Philippe Begnic @ 2013-05-27 12:41 ` Philippe Begnic 2013-05-31 1:25 ` [PATCH 0/4] clk, mfd: u8540 clock tree definition Mike Turquette 4 siblings, 0 replies; 11+ messages in thread From: Philippe Begnic @ 2013-05-27 12:41 UTC (permalink / raw) To: linux-arm-kernel From: Philippe Begnic <philippe.begnic@st.com> First clocks definition version of PRCMU and PRCC clocks for u8540 platform Signed-off-by: Philippe Begnic <philippe.begnic@st.com> --- drivers/clk/ux500/u8540_clk.c | 560 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 559 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c index 90f3c88..f262588 100644 --- a/drivers/clk/ux500/u8540_clk.c +++ b/drivers/clk/ux500/u8540_clk.c @@ -17,5 +17,563 @@ void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, u32 clkrst5_base, u32 clkrst6_base) { - /* register clocks here */ + struct clk *clk; + + /* Clock sources. */ + /* Fixed ClockGen */ + clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, + CLK_IS_ROOT|CLK_IGNORE_UNUSED); + clk_register_clkdev(clk, "soc0_pll", NULL); + + clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, + CLK_IS_ROOT|CLK_IGNORE_UNUSED); + clk_register_clkdev(clk, "soc1_pll", NULL); + + clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, + CLK_IS_ROOT|CLK_IGNORE_UNUSED); + clk_register_clkdev(clk, "ddr_pll", NULL); + + clk = clk_register_fixed_rate(NULL, "rtc32k", NULL, + CLK_IS_ROOT|CLK_IGNORE_UNUSED, + 32768); + clk_register_clkdev(clk, "clk32k", NULL); + clk_register_clkdev(clk, "apb_pclk", "rtc-pl031"); + + clk = clk_register_fixed_rate(NULL, "ulp38m4", NULL, + CLK_IS_ROOT|CLK_IGNORE_UNUSED, + 38400000); + + clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "UART"); + + /* msp02clk needs a abx500 clk as parent. Handle by abx500 clk driver */ + clk = clk_reg_prcmu_gate("msp02clk", "ab9540_sysclk12_b1", + PRCMU_MSP02CLK, 0); + clk_register_clkdev(clk, NULL, "MSP02"); + + clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "MSP1"); + + clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "I2C"); + + clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "slim"); + + clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "PERIPH1"); + + clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "PERIPH2"); + + clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "PERIPH3"); + + clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "PERIPH5"); + + clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "PERIPH6"); + + clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "PERIPH7"); + + clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "lcd"); + clk_register_clkdev(clk, "lcd", "mcde"); + + clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BML8580CLK, + CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "bml"); + + clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + + clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + + clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "hdmi"); + clk_register_clkdev(clk, "hdmi", "mcde"); + + clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "apeat"); + + clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, + CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "apetrace"); + + clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "mcde"); + clk_register_clkdev(clk, "mcde", "mcde"); + clk_register_clkdev(clk, NULL, "dsilink.0"); + clk_register_clkdev(clk, NULL, "dsilink.1"); + clk_register_clkdev(clk, NULL, "dsilink.2"); + + clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, + CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "ipi2"); + + clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, + CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "dsialt"); + + clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "dma40.0"); + + clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "b2r2"); + clk_register_clkdev(clk, NULL, "b2r2_core"); + clk_register_clkdev(clk, NULL, "U8500-B2R2.0"); + clk_register_clkdev(clk, NULL, "b2r2_1_core"); + + clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "tv"); + clk_register_clkdev(clk, "tv", "mcde"); + + clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "SSP"); + + clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "rngclk"); + + clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "uicc"); + + clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "mtu0"); + clk_register_clkdev(clk, NULL, "mtu1"); + + clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, + PRCMU_SDMMCCLK, 100000000, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "sdmmc"); + + clk = clk_reg_prcmu_opp_volt_scalable("sdmmchclk", NULL, + PRCMU_SDMMCHCLK, 400000000, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "sdmmchclk"); + + clk = clk_reg_prcmu_gate("hvaclk", NULL, PRCMU_HVACLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "hva"); + + clk = clk_reg_prcmu_gate("g1clk", NULL, PRCMU_G1CLK, CLK_IS_ROOT); + clk_register_clkdev(clk, NULL, "g1"); + + clk = clk_reg_prcmu_scalable("spare1clk", NULL, PRCMU_SPARE1CLK, 0, + CLK_IS_ROOT|CLK_SET_RATE_GATE); + clk_register_clkdev(clk, "dsilcd", "mcde"); + + clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", + PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); + clk_register_clkdev(clk, "dsihs2", "mcde"); + clk_register_clkdev(clk, "hs_clk", "dsilink.2"); + + clk = clk_reg_prcmu_scalable("dsilcd_pll", "spare1clk", + PRCMU_PLLDSI_LCD, 0, CLK_SET_RATE_GATE); + clk_register_clkdev(clk, "dsilcd_pll", "mcde"); + + clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", + PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); + clk_register_clkdev(clk, "dsihs0", "mcde"); + + clk = clk_reg_prcmu_scalable("dsi0lcdclk", "dsilcd_pll", + PRCMU_DSI0CLK_LCD, 0, CLK_SET_RATE_GATE); + clk_register_clkdev(clk, "dsihs0", "mcde"); + clk_register_clkdev(clk, "hs_clk", "dsilink.0"); + + clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", + PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); + clk_register_clkdev(clk, "dsihs1", "mcde"); + + clk = clk_reg_prcmu_scalable("dsi1lcdclk", "dsilcd_pll", + PRCMU_DSI1CLK_LCD, 0, CLK_SET_RATE_GATE); + clk_register_clkdev(clk, "dsihs1", "mcde"); + clk_register_clkdev(clk, "hs_clk", "dsilink.1"); + + clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", + PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); + clk_register_clkdev(clk, "lp_clk", "dsilink.0"); + clk_register_clkdev(clk, "dsilp0", "mcde"); + + clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", + PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE); + clk_register_clkdev(clk, "lp_clk", "dsilink.1"); + clk_register_clkdev(clk, "dsilp1", "mcde"); + + clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", + PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE); + clk_register_clkdev(clk, "lp_clk", "dsilink.2"); + clk_register_clkdev(clk, "dsilp2", "mcde"); + + clk = clk_reg_prcmu_scalable_rate("armss", NULL, + PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED); + clk_register_clkdev(clk, "armss", NULL); + + clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", + CLK_IGNORE_UNUSED, 1, 2); + clk_register_clkdev(clk, NULL, "smp_twd"); + + /* PRCC P-clocks */ + /* Peripheral 1 : PRCC P-clocks */ + clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base, + BIT(0), 0); + clk_register_clkdev(clk, "apb_pclk", "uart0"); + + clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base, + BIT(1), 0); + clk_register_clkdev(clk, "apb_pclk", "uart1"); + + clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base, + BIT(2), 0); + clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1"); + + clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base, + BIT(3), 0); + clk_register_clkdev(clk, "apb_pclk", "msp0"); + clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.0"); + + clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base, + BIT(4), 0); + clk_register_clkdev(clk, "apb_pclk", "msp1"); + clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.1"); + + clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base, + BIT(5), 0); + clk_register_clkdev(clk, "apb_pclk", "sdi0"); + + clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base, + BIT(6), 0); + clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2"); + + clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base, + BIT(7), 0); + clk_register_clkdev(clk, NULL, "spi3"); + + clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base, + BIT(8), 0); + clk_register_clkdev(clk, "apb_pclk", "slimbus0"); + + clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base, + BIT(9), 0); + clk_register_clkdev(clk, NULL, "gpio.0"); + clk_register_clkdev(clk, NULL, "gpio.1"); + clk_register_clkdev(clk, NULL, "gpioblock0"); + clk_register_clkdev(clk, "apb_pclk", "ab85xx-codec.0"); + + clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base, + BIT(10), 0); + clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4"); + + clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base, + BIT(11), 0); + clk_register_clkdev(clk, "apb_pclk", "msp3"); + clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.3"); + + /* Peripheral 2 : PRCC P-clocks */ + clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base, + BIT(0), 0); + clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3"); + + clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base, + BIT(1), 0); + clk_register_clkdev(clk, NULL, "spi2"); + + clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base, + BIT(2), 0); + clk_register_clkdev(clk, NULL, "spi1"); + + clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base, + BIT(3), 0); + clk_register_clkdev(clk, NULL, "pwl"); + + clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base, + BIT(4), 0); + clk_register_clkdev(clk, "apb_pclk", "sdi4"); + + clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base, + BIT(5), 0); + clk_register_clkdev(clk, "apb_pclk", "msp2"); + clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.2"); + + clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base, + BIT(6), 0); + clk_register_clkdev(clk, "apb_pclk", "sdi1"); + + clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base, + BIT(7), 0); + clk_register_clkdev(clk, "apb_pclk", "sdi3"); + + clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base, + BIT(8), 0); + clk_register_clkdev(clk, NULL, "spi0"); + + clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base, + BIT(9), 0); + clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0"); + + clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base, + BIT(10), 0); + clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0"); + + clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base, + BIT(11), 0); + clk_register_clkdev(clk, NULL, "gpio.6"); + clk_register_clkdev(clk, NULL, "gpio.7"); + clk_register_clkdev(clk, NULL, "gpioblock1"); + + clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base, + BIT(12), 0); + clk_register_clkdev(clk, "msp4-pclk", "ab85xx-codec.0"); + + /* Peripheral 3 : PRCC P-clocks */ + clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, + BIT(0), 0); + clk_register_clkdev(clk, NULL, "fsmc"); + + clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, + BIT(1), 0); + clk_register_clkdev(clk, "apb_pclk", "ssp0"); + + clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base, + BIT(2), 0); + clk_register_clkdev(clk, "apb_pclk", "ssp1"); + + clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base, + BIT(3), 0); + clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0"); + + clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base, + BIT(4), 0); + clk_register_clkdev(clk, "apb_pclk", "sdi2"); + + clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base, + BIT(5), 0); + clk_register_clkdev(clk, "apb_pclk", "ske"); + clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad"); + + clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base, + BIT(6), 0); + clk_register_clkdev(clk, "apb_pclk", "uart2"); + + clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base, + BIT(7), 0); + clk_register_clkdev(clk, "apb_pclk", "sdi5"); + + clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base, + BIT(8), 0); + clk_register_clkdev(clk, NULL, "gpio.2"); + clk_register_clkdev(clk, NULL, "gpio.3"); + clk_register_clkdev(clk, NULL, "gpio.4"); + clk_register_clkdev(clk, NULL, "gpio.5"); + clk_register_clkdev(clk, NULL, "gpioblock2"); + + clk = clk_reg_prcc_pclk("p3_pclk9", "per3clk", clkrst3_base, + BIT(9), 0); + clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.5"); + + clk = clk_reg_prcc_pclk("p3_pclk10", "per3clk", clkrst3_base, + BIT(10), 0); + clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.6"); + + clk = clk_reg_prcc_pclk("p3_pclk11", "per3clk", clkrst3_base, + BIT(11), 0); + clk_register_clkdev(clk, "apb_pclk", "uart3"); + + clk = clk_reg_prcc_pclk("p3_pclk12", "per3clk", clkrst3_base, + BIT(12), 0); + clk_register_clkdev(clk, "apb_pclk", "uart4"); + + /* Peripheral 5 : PRCC P-clocks */ + clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base, + BIT(0), 0); + clk_register_clkdev(clk, "usb", "musb-ux500.0"); + clk_register_clkdev(clk, "usbclk", "ab-iddet.0"); + + clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base, + BIT(1), 0); + clk_register_clkdev(clk, NULL, "gpio.8"); + clk_register_clkdev(clk, NULL, "gpioblock3"); + + /* Peripheral 6 : PRCC P-clocks */ + clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base, + BIT(0), 0); + clk_register_clkdev(clk, "apb_pclk", "rng"); + + clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base, + BIT(1), 0); + clk_register_clkdev(clk, NULL, "cryp0"); + clk_register_clkdev(clk, NULL, "cryp1"); + + clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base, + BIT(2), 0); + clk_register_clkdev(clk, NULL, "hash0"); + + clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base, + BIT(3), 0); + clk_register_clkdev(clk, NULL, "pka"); + + clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base, + BIT(4), 0); + clk_register_clkdev(clk, NULL, "db8540-hash1"); + + clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base, + BIT(5), 0); + clk_register_clkdev(clk, NULL, "cfgreg"); + + clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base, + BIT(6), 0); + clk_register_clkdev(clk, "apb_pclk", "mtu0"); + + clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base, + BIT(7), 0); + clk_register_clkdev(clk, "apb_pclk", "mtu1"); + + /* + * PRCC K-clocks ==> see table PRCC_PCKEN/PRCC_KCKEN + * This differs from the internal implementation: + * We don't use the PERPIH[n| clock as parent, since those _should_ + * only be used as parents for the P-clocks. + * TODO: "parentjoin" with corresponding P-clocks for all K-clocks. + */ + + /* Peripheral 1 : PRCC K-clocks */ + clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", + clkrst1_base, BIT(0), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "uart0"); + + clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", + clkrst1_base, BIT(1), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "uart1"); + + clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", + clkrst1_base, BIT(2), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "nmk-i2c.1"); + + clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", + clkrst1_base, BIT(3), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "msp0"); + clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.0"); + + clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", + clkrst1_base, BIT(4), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "msp1"); + clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.1"); + + clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmchclk", + clkrst1_base, BIT(5), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "sdi0"); + + clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", + clkrst1_base, BIT(6), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "nmk-i2c.2"); + + clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", + clkrst1_base, BIT(8), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "slimbus0"); + + clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", + clkrst1_base, BIT(9), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "nmk-i2c.4"); + + clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", + clkrst1_base, BIT(10), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "msp3"); + clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.3"); + + /* Peripheral 2 : PRCC K-clocks */ + clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", + clkrst2_base, BIT(0), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "nmk-i2c.3"); + + clk = clk_reg_prcc_kclk("p2_pwl_kclk", "rtc32k", + clkrst2_base, BIT(1), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "pwl"); + + clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmchclk", + clkrst2_base, BIT(2), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "sdi4"); + + clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", + clkrst2_base, BIT(3), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "msp2"); + clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.2"); + + clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmchclk", + clkrst2_base, BIT(4), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "sdi1"); + + clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", + clkrst2_base, BIT(5), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "sdi3"); + + clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", + clkrst2_base, BIT(6), + CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); + clk_register_clkdev(clk, "hsir_hsirxclk", "ste_hsi.0"); + + clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", + clkrst2_base, BIT(7), + CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); + clk_register_clkdev(clk, "hsit_hsitxclk", "ste_hsi.0"); + + /* Should only be 9540, but might be added for 85xx as well */ + clk = clk_reg_prcc_kclk("p2_msp4_kclk", "msp02clk", + clkrst2_base, BIT(9), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "msp4"); + clk_register_clkdev(clk, "msp4", "ab85xx-codec.0"); + + /* Peripheral 3 : PRCC K-clocks */ + clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", + clkrst3_base, BIT(1), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "ssp0"); + + clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", + clkrst3_base, BIT(2), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "ssp1"); + + clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", + clkrst3_base, BIT(3), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "nmk-i2c.0"); + + clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmchclk", + clkrst3_base, BIT(4), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "sdi2"); + + clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", + clkrst3_base, BIT(5), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "ske"); + clk_register_clkdev(clk, NULL, "nmk-ske-keypad"); + + clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", + clkrst3_base, BIT(6), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "uart2"); + + clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", + clkrst3_base, BIT(7), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "sdi5"); + + clk = clk_reg_prcc_kclk("p3_i2c5_kclk", "i2cclk", + clkrst3_base, BIT(8), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "nmk-i2c.5"); + + clk = clk_reg_prcc_kclk("p3_i2c6_kclk", "i2cclk", + clkrst3_base, BIT(9), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "nmk-i2c.6"); + + clk = clk_reg_prcc_kclk("p3_uart3_kclk", "uartclk", + clkrst3_base, BIT(10), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "uart3"); + + clk = clk_reg_prcc_kclk("p3_uart4_kclk", "uartclk", + clkrst3_base, BIT(11), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "uart4"); + + /* Peripheral 6 : PRCC K-clocks */ + clk = clk_reg_prcc_kclk("p6_rng_kclk", "rngclk", + clkrst6_base, BIT(0), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "rng"); } -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 0/4] clk, mfd: u8540 clock tree definition 2013-05-27 12:41 [PATCH 0/4] clk, mfd: u8540 clock tree definition Philippe Begnic ` (3 preceding siblings ...) 2013-05-27 12:41 ` [PATCH 4/4] clk: ux500: Clocks definition for u8540 Philippe Begnic @ 2013-05-31 1:25 ` Mike Turquette 2013-05-31 6:55 ` Lee Jones 4 siblings, 1 reply; 11+ messages in thread From: Mike Turquette @ 2013-05-31 1:25 UTC (permalink / raw) To: linux-arm-kernel Quoting Philippe Begnic (2013-05-27 05:41:28) > From: Philippe Begnic <philippe.begnic@st.com> > > Create U8540 clock tree definitions for common clock framework > The clock changes look good to me. How did you want to merge the patches? Regards, Mike > Philippe Begnic (4): > clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 > mfd: db8500: Update register definition for u8540 clock > mfd: db8500: Update BML clock register for db8580 > clk: ux500: Clocks definition for u8540 > > arch/arm/mach-ux500/cpu.c | 6 +- > drivers/clk/ux500/u8540_clk.c | 564 ++++++++++++++++++++++++++++- > drivers/clk/ux500/u9540_clk.c | 4 +- > drivers/mfd/db8500-prcmu.c | 1 + > drivers/mfd/dbx500-prcmu-regs.h | 1 + > include/linux/mfd/abx500/ab8500-sysctrl.h | 4 +- > include/linux/mfd/dbx500-prcmu.h | 12 + > include/linux/platform_data/clk-ux500.h | 6 +- > 8 files changed, 587 insertions(+), 11 deletions(-) > > -- > 1.7.9.5 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 0/4] clk, mfd: u8540 clock tree definition 2013-05-31 1:25 ` [PATCH 0/4] clk, mfd: u8540 clock tree definition Mike Turquette @ 2013-05-31 6:55 ` Lee Jones 2013-05-31 19:14 ` Mike Turquette 0 siblings, 1 reply; 11+ messages in thread From: Lee Jones @ 2013-05-31 6:55 UTC (permalink / raw) To: linux-arm-kernel On Thu, 30 May 2013, Mike Turquette wrote: > Quoting Philippe Begnic (2013-05-27 05:41:28) > > From: Philippe Begnic <philippe.begnic@st.com> > > > > Create U8540 clock tree definitions for common clock framework > > > > The clock changes look good to me. How did you want to merge the > patches? You may as well take them through your tree Mike. > > Philippe Begnic (4): > > clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 > > mfd: db8500: Update register definition for u8540 clock > > mfd: db8500: Update BML clock register for db8580 > > clk: ux500: Clocks definition for u8540 > > > > arch/arm/mach-ux500/cpu.c | 6 +- > > drivers/clk/ux500/u8540_clk.c | 564 ++++++++++++++++++++++++++++- > > drivers/clk/ux500/u9540_clk.c | 4 +- > > drivers/mfd/db8500-prcmu.c | 1 + > > drivers/mfd/dbx500-prcmu-regs.h | 1 + > > include/linux/mfd/abx500/ab8500-sysctrl.h | 4 +- > > include/linux/mfd/dbx500-prcmu.h | 12 + > > include/linux/platform_data/clk-ux500.h | 6 +- > > 8 files changed, 587 insertions(+), 11 deletions(-) > > -- Lee Jones Linaro ST-Ericsson Landing Team Lead Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 0/4] clk, mfd: u8540 clock tree definition 2013-05-31 6:55 ` Lee Jones @ 2013-05-31 19:14 ` Mike Turquette 2013-06-03 8:15 ` Lee Jones 0 siblings, 1 reply; 11+ messages in thread From: Mike Turquette @ 2013-05-31 19:14 UTC (permalink / raw) To: linux-arm-kernel Quoting Lee Jones (2013-05-30 23:55:32) > On Thu, 30 May 2013, Mike Turquette wrote: > > > Quoting Philippe Begnic (2013-05-27 05:41:28) > > > From: Philippe Begnic <philippe.begnic@st.com> > > > > > > Create U8540 clock tree definitions for common clock framework > > > > > > > The clock changes look good to me. How did you want to merge the > > patches? > > You may as well take them through your tree Mike. > Sure I can take them but it would be best to wait for an Ack from Samuel for the MFD parts, if only so that we are coordinated. Regards, Mike > > > Philippe Begnic (4): > > > clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 > > > mfd: db8500: Update register definition for u8540 clock > > > mfd: db8500: Update BML clock register for db8580 > > > clk: ux500: Clocks definition for u8540 > > > > > > arch/arm/mach-ux500/cpu.c | 6 +- > > > drivers/clk/ux500/u8540_clk.c | 564 ++++++++++++++++++++++++++++- > > > drivers/clk/ux500/u9540_clk.c | 4 +- > > > drivers/mfd/db8500-prcmu.c | 1 + > > > drivers/mfd/dbx500-prcmu-regs.h | 1 + > > > include/linux/mfd/abx500/ab8500-sysctrl.h | 4 +- > > > include/linux/mfd/dbx500-prcmu.h | 12 + > > > include/linux/platform_data/clk-ux500.h | 6 +- > > > 8 files changed, 587 insertions(+), 11 deletions(-) > > > > > -- > Lee Jones > Linaro ST-Ericsson Landing Team Lead > Linaro.org ? Open source software for ARM SoCs > Follow Linaro: Facebook | Twitter | Blog ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 0/4] clk, mfd: u8540 clock tree definition 2013-05-31 19:14 ` Mike Turquette @ 2013-06-03 8:15 ` Lee Jones 2013-06-07 1:19 ` Mike Turquette 0 siblings, 1 reply; 11+ messages in thread From: Lee Jones @ 2013-06-03 8:15 UTC (permalink / raw) To: linux-arm-kernel On Fri, 31 May 2013, Mike Turquette wrote: > Quoting Lee Jones (2013-05-30 23:55:32) > > On Thu, 30 May 2013, Mike Turquette wrote: > > > > > Quoting Philippe Begnic (2013-05-27 05:41:28) > > > > From: Philippe Begnic <philippe.begnic@st.com> > > > > > > > > Create U8540 clock tree definitions for common clock framework > > > > > > > > > > The clock changes look good to me. How did you want to merge the > > > patches? > > > > You may as well take them through your tree Mike. > > > > Sure I can take them but it would be best to wait for an Ack from Samuel > for the MFD parts, if only so that we are coordinated. You don't need it. Apply with mine instead: Acked-by: Lee Jones <lee.jones@linaro.org> > > > > Philippe Begnic (4): > > > > clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 > > > > mfd: db8500: Update register definition for u8540 clock > > > > mfd: db8500: Update BML clock register for db8580 > > > > clk: ux500: Clocks definition for u8540 > > > > > > > > arch/arm/mach-ux500/cpu.c | 6 +- > > > > drivers/clk/ux500/u8540_clk.c | 564 ++++++++++++++++++++++++++++- > > > > drivers/clk/ux500/u9540_clk.c | 4 +- > > > > drivers/mfd/db8500-prcmu.c | 1 + > > > > drivers/mfd/dbx500-prcmu-regs.h | 1 + > > > > include/linux/mfd/abx500/ab8500-sysctrl.h | 4 +- > > > > include/linux/mfd/dbx500-prcmu.h | 12 + > > > > include/linux/platform_data/clk-ux500.h | 6 +- > > > > 8 files changed, 587 insertions(+), 11 deletions(-) > > > > > > -- Lee Jones Linaro ST-Ericsson Landing Team Lead Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 0/4] clk, mfd: u8540 clock tree definition 2013-06-03 8:15 ` Lee Jones @ 2013-06-07 1:19 ` Mike Turquette 0 siblings, 0 replies; 11+ messages in thread From: Mike Turquette @ 2013-06-07 1:19 UTC (permalink / raw) To: linux-arm-kernel Quoting Lee Jones (2013-06-03 01:15:04) > On Fri, 31 May 2013, Mike Turquette wrote: > > > Quoting Lee Jones (2013-05-30 23:55:32) > > > On Thu, 30 May 2013, Mike Turquette wrote: > > > > > > > Quoting Philippe Begnic (2013-05-27 05:41:28) > > > > > From: Philippe Begnic <philippe.begnic@st.com> > > > > > > > > > > Create U8540 clock tree definitions for common clock framework > > > > > > > > > > > > > The clock changes look good to me. How did you want to merge the > > > > patches? > > > > > > You may as well take them through your tree Mike. > > > > > > > Sure I can take them but it would be best to wait for an Ack from Samuel > > for the MFD parts, if only so that we are coordinated. > > You don't need it. Apply with mine instead: > > Acked-by: Lee Jones <lee.jones@linaro.org> > Done. Taken into clk-next. Thanks, Mike > > > > > Philippe Begnic (4): > > > > > clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 > > > > > mfd: db8500: Update register definition for u8540 clock > > > > > mfd: db8500: Update BML clock register for db8580 > > > > > clk: ux500: Clocks definition for u8540 > > > > > > > > > > arch/arm/mach-ux500/cpu.c | 6 +- > > > > > drivers/clk/ux500/u8540_clk.c | 564 ++++++++++++++++++++++++++++- > > > > > drivers/clk/ux500/u9540_clk.c | 4 +- > > > > > drivers/mfd/db8500-prcmu.c | 1 + > > > > > drivers/mfd/dbx500-prcmu-regs.h | 1 + > > > > > include/linux/mfd/abx500/ab8500-sysctrl.h | 4 +- > > > > > include/linux/mfd/dbx500-prcmu.h | 12 + > > > > > include/linux/platform_data/clk-ux500.h | 6 +- > > > > > 8 files changed, 587 insertions(+), 11 deletions(-) > > > > > > > > > > -- > Lee Jones > Linaro ST-Ericsson Landing Team Lead > Linaro.org ? Open source software for ARM SoCs > Follow Linaro: Facebook | Twitter | Blog ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2013-06-07 1:19 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-05-27 12:41 [PATCH 0/4] clk, mfd: u8540 clock tree definition Philippe Begnic 2013-05-27 12:41 ` [PATCH 1/4] clk: ux500: Pass clock base adresses in initcall for u8540 and u9540 Philippe Begnic 2013-05-27 12:49 ` Ulf Hansson 2013-05-27 12:41 ` [PATCH 2/4] mfd: db8500: Update register definition for u8540 clock Philippe Begnic 2013-05-27 12:41 ` [PATCH 3/4] mfd: db8500: Update BML clock register for db8580 Philippe Begnic 2013-05-27 12:41 ` [PATCH 4/4] clk: ux500: Clocks definition for u8540 Philippe Begnic 2013-05-31 1:25 ` [PATCH 0/4] clk, mfd: u8540 clock tree definition Mike Turquette 2013-05-31 6:55 ` Lee Jones 2013-05-31 19:14 ` Mike Turquette 2013-06-03 8:15 ` Lee Jones 2013-06-07 1:19 ` Mike Turquette
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).