From: thierry.reding@gmail.com (Thierry Reding)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] memory: tegra20-mc: Fix hang in IRQ handler.
Date: Mon, 10 Jun 2013 22:36:42 +0200 [thread overview]
Message-ID: <20130610203641.GA26036@mithrandir> (raw)
In-Reply-To: <1370855624-30564-2-git-send-email-ttynkkynen@nvidia.com>
On Mon, Jun 10, 2013 at 12:13:43PM +0300, Tuomas Tynkkynen wrote:
> In Tegra20 memory controller any MC interrupt would cause an
> infinite loop in the IRQ handler.
>
> Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
> ---
> drivers/memory/tegra20-mc.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/memory/tegra20-mc.c b/drivers/memory/tegra20-mc.c
> index 2ca5f28..bd5a553 100644
> --- a/drivers/memory/tegra20-mc.c
> +++ b/drivers/memory/tegra20-mc.c
> @@ -193,8 +193,11 @@ static irqreturn_t tegra20_mc_isr(int irq, void *data)
> mask &= stat;
> if (!mask)
> return IRQ_NONE;
> - while ((bit = ffs(mask)) != 0)
> + while ((bit = ffs(mask)) != 0) {
> tegra20_mc_decode(mc, bit - 1);
> + mask &= BIT(bit);
Shouldn't this be "mask &= ~BIT(bit);"? The intent of the code is to
clear the bit which was handled by the loop body, right? The above
clears all other bits instead.
Thierry
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next prev parent reply other threads:[~2013-06-10 20:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-10 9:13 [PATCH 0/2] Bugfixes for Tegra memory controllers Tuomas Tynkkynen
2013-06-10 9:13 ` [PATCH 1/2] memory: tegra20-mc: Fix hang in IRQ handler Tuomas Tynkkynen
2013-06-10 20:36 ` Thierry Reding [this message]
2013-06-11 10:09 ` Tuomas Tynkkynen
2013-06-10 9:13 ` [PATCH 2/2] memory: tegra30-mc: Fix IRQ handler bugs Tuomas Tynkkynen
2013-06-10 20:37 ` Thierry Reding
-- strict thread matches above, loose matches on Subject: below --
2013-06-11 10:11 [PATCH 0/2 v2] Bugfixes for Tegra memory controllers Tuomas Tynkkynen
2013-06-11 10:11 ` [PATCH 1/2] memory: tegra20-mc: Fix hang in IRQ handler Tuomas Tynkkynen
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