[PATCH 0/2 v2] Bugfixes for Tegra memory controllers.

[PATCH 0/2 v2] Bugfixes for Tegra memory controllers.

[Tuomas Tynkkynen]

Hi,

Here's two simple bugfixes for the Tegra memory controllers.

v2: Fix a dumb bug in the bit masking.

Tuomas Tynkkynen (2):
  memory: tegra20-mc: Fix hang in IRQ handler.
  memory: tegra30-mc: Fix IRQ handler.

 drivers/memory/tegra20-mc.c | 5 ++++-
 drivers/memory/tegra30-mc.c | 9 ++++++---
 2 files changed, 10 insertions(+), 4 deletions(-)

-- 
1.8.1.5

[PATCH 1/2] memory: tegra20-mc: Fix hang in IRQ handler.

[Tuomas Tynkkynen]

In Tegra20 any memory controller interrupt would cause an
infinite loop in the IRQ handler.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
---
 drivers/memory/tegra20-mc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/memory/tegra20-mc.c b/drivers/memory/tegra20-mc.c
index 2ca5f28..0548eea 100644
--- a/drivers/memory/tegra20-mc.c
+++ b/drivers/memory/tegra20-mc.c
@@ -193,8 +193,11 @@ static irqreturn_t tegra20_mc_isr(int irq, void *data)
 	mask &= stat;
 	if (!mask)
 		return IRQ_NONE;
-	while ((bit = ffs(mask)) != 0)
+	while ((bit = ffs(mask)) != 0) {
 		tegra20_mc_decode(mc, bit - 1);
+		mask &= ~BIT(bit - 1);
+	}
+
 	mc_writel(mc, stat, MC_INTSTATUS);
 	return IRQ_HANDLED;
 }
-- 
1.8.1.5

[PATCH 2/2] memory: tegra30-mc: Fix IRQ handler.

[Tuomas Tynkkynen]

In Tegra30 any memory controller interrupt would cause an infinite loop in the
IRQ handler. Additionally, a garbage pointer was used to read the MC
status registers, which causes wrong values to be printed if a MC error
occurred.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
---
 drivers/memory/tegra30-mc.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/memory/tegra30-mc.c b/drivers/memory/tegra30-mc.c
index f4ae074..58d2979 100644
--- a/drivers/memory/tegra30-mc.c
+++ b/drivers/memory/tegra30-mc.c
@@ -218,7 +218,7 @@ static void tegra30_mc_decode(struct tegra30_mc *mc, int n)
 		return;
 	}
 
-	err = readl(mc + MC_ERR_STATUS);
+	err = mc_readl(mc, MC_ERR_STATUS);
 
 	type = (err & MC_ERR_TYPE_MASK) >> MC_ERR_TYPE_SHIFT;
 	perm = (err & MC_ERR_INVALID_SMMU_PAGE_MASK) >>
@@ -235,7 +235,7 @@ static void tegra30_mc_decode(struct tegra30_mc *mc, int n)
 	if (cid < ARRAY_SIZE(tegra30_mc_client))
 		client = tegra30_mc_client[cid];
 
-	addr = readl(mc + MC_ERR_ADR);
+	addr = mc_readl(mc, MC_ERR_ADR);
 
 	dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s %s %s)\n",
 			   mc_int_err[idx], err, addr, client,
@@ -313,8 +313,11 @@ static irqreturn_t tegra30_mc_isr(int irq, void *data)
 	mask &= stat;
 	if (!mask)
 		return IRQ_NONE;
-	while ((bit = ffs(mask)) != 0)
+	while ((bit = ffs(mask)) != 0) {
 		tegra30_mc_decode(mc, bit - 1);
+		mask &= ~BIT(bit - 1);
+	}
+
 	mc_writel(mc, stat, MC_INTSTATUS);
 	return IRQ_HANDLED;
 }
-- 
1.8.1.5

[PATCH 0/2 v2] Bugfixes for Tegra memory controllers.

[Thierry Reding]

On Tue, Jun 11, 2013 at 01:11:17PM +0300, Tuomas Tynkkynen wrote:
> Hi,
> 
> Here's two simple bugfixes for the Tegra memory controllers.
> 
> v2: Fix a dumb bug in the bit masking.
> 
> Tuomas Tynkkynen (2):
>   memory: tegra20-mc: Fix hang in IRQ handler.
>   memory: tegra30-mc: Fix IRQ handler.
> 
>  drivers/memory/tegra20-mc.c | 5 ++++-
>  drivers/memory/tegra30-mc.c | 9 ++++++---
>  2 files changed, 10 insertions(+), 4 deletions(-)

Both patches:

Reviewed-by: Thierry Reding <thierry.reding@gmail.com>

On a side-note, the subject format looks a bit strange and my guess is
you had to manually edit it to insert "v2". git can do it for you when
you generate the patch series using:

	git format-patch --subject-prefix='PATCH v2'

That'll also automatically add the v2 to all individual patches instead
of just the cover-letter.

Thierry
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[PATCH 0/2 v2] Bugfixes for Tegra memory controllers.

[Stephen Warren]

On 06/11/2013 04:11 AM, Tuomas Tynkkynen wrote:
> Hi,
> 
> Here's two simple bugfixes for the Tegra memory controllers.
> 
> v2: Fix a dumb bug in the bit masking.

The series,
Reviewed-by: Stephen Warren <swarren@nvidia.com>