From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: BUG: commit "ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on pre-ARMv6 CPUs" breaks armv5 with CONFIG_PREEMPT
Date: Thu, 20 Jun 2013 11:28:56 +0100 [thread overview]
Message-ID: <20130620102856.GC18536@arm.com> (raw)
In-Reply-To: <51C2D5EF.3040803@pengutronix.de>
On Thu, Jun 20, 2013 at 11:14:07AM +0100, Marc Kleine-Budde wrote:
> On 06/20/2013 11:57 AM, Catalin Marinas wrote:
> >>> :040000 040000 034899bdcbc9aa59b5455a85a9d78b646b4cf784 ecc23e33a4ca807d4153f87fbea85a9437ff2928 M arch
> >>
> >> The problem can be reproduced on several mx28 and an at91sam9263 and
> >> only occurs of CONFIG_PREEMPT (Preemptible Kernel (Low-Latency Desktop))
> >> is enabled.
> >>
> >> I have the gut feeling that the "if (irqs_disabled())" check in the
> >> above patch is not correct for CONFIG_PREEMPT.
> >
> > The check is there to avoid long interrupt latencies (flushing the whole
> > cache with interrupts disabled during context switch). You can drop the
> > check and always call cpu_switch_mm() to confirm that it fixes the
> > faults.
> >
> > finish_task_switch() calls finish_arch_post_lock_switch() after the
> > interrupts have been enabled so that the CPU can actually switch the mm.
> > I wonder whether we could actually be preempted after
> > finish_lock_switch() but before we actually switched the MMU.
> >
> > Here's an untested patch (trying to keep it in the arch/arm code):
>
> [...]
>
> When stating userspace I get this reproducible:
>
> init started: BusyBox v1.18.5 (2013-04-04 18:31:36 CEST)
> starting pid 50, tty '/dev/console': '/etc/init.d/rcS'
> [ 7.000828] ------------[ cut here ]------------
> [ 7.005560] WARNING: at kernel/sched/core.c:2809 finish_task_switch.constprop.84+0xf8/0x164()
> [ 7.014650] DEBUG_LOCKS_WARN_ON(val > preempt_count())
We may need to place the preempt disable/enable at a higher level in the
scheduler. My theory is that we have a context switch from prev to next.
We get preempted just before finish_arch_post_lock_switch(), so the MMU
hasn't been switched yet. The new switch during preemption happens to a
thread with the same next mm, so the scheduler no longer switch_mm() and
the TIF_SWITCH_MM isn't set for the new thread.
I'll come back with another patch shortly.
--
Catalin
next prev parent reply other threads:[~2013-06-20 10:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-20 8:43 BUG: commit "ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on pre-ARMv6 CPUs" breaks armv5 with CONFIG_PREEMPT Marc Kleine-Budde
2013-06-20 9:25 ` Will Deacon
2013-06-20 9:51 ` Marc Kleine-Budde
2013-06-20 9:57 ` Catalin Marinas
2013-06-20 10:08 ` Marc Kleine-Budde
2013-06-20 10:14 ` Marc Kleine-Budde
2013-06-20 10:28 ` Catalin Marinas [this message]
2013-06-20 11:12 ` Catalin Marinas
2013-06-20 11:35 ` Marc Kleine-Budde
2013-06-20 11:39 ` Marc Kleine-Budde
2013-06-20 11:47 ` Marc Kleine-Budde
2013-06-20 12:48 ` Marc Kleine-Budde
2013-06-20 13:01 ` Catalin Marinas
2013-06-20 13:05 ` Marc Kleine-Budde
2013-06-21 10:28 ` Marc Kleine-Budde
2013-06-21 13:52 ` Catalin Marinas
2013-07-17 8:41 ` Marc Kleine-Budde
2013-07-17 8:51 ` Russell King - ARM Linux
2013-07-17 11:48 ` Marc Kleine-Budde
2013-07-17 19:41 ` Catalin Marinas
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