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From: christoffer.dall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/5] ARM: KVM: make sure maintainance operation complete before world switch
Date: Thu, 20 Jun 2013 11:50:36 -0700	[thread overview]
Message-ID: <20130620185036.GH4563@lvm> (raw)
In-Reply-To: <20130620183818.GD25734@mudshark.cambridge.arm.com>

On Thu, Jun 20, 2013 at 07:38:18PM +0100, Will Deacon wrote:
> On Thu, Jun 20, 2013 at 07:28:47PM +0100, Christoffer Dall wrote:
> > On Thu, Jun 20, 2013 at 07:15:25PM +0100, Will Deacon wrote:
> > > On Thu, Jun 20, 2013 at 06:14:09PM +0100, Christoffer Dall wrote:
> > > > ok, I was trying to think about how it would break, and if a guest needs
> > > > a TLB invalidation to be visisble by other CPUs it would have to have a
> > > > dsb/isb itself after the operation, and that would eventually be
> > > > executed once the VCPU was rescheduled, but potentially on another CPU,
> > > > but then I wonder if the PCPU migration on the host wouldn't take care
> > > > of it?
> > > 
> > > Actually, it's worse than both of you think :)
> > > 
> > > The dsb *must* be executed on the same physical CPU as the TLB invalidation.
> > > The same virtual CPU isn't enough, which is all that is guaranteed by the
> > > guest. If you don't have a dsb on your vcpu migration path, then you need
> > > something here.
> > > 
> > > The same thing applies to cache maintenance operations.
> > > 
> > But are we not sure that a dsb will happen anywhere in the kernel if a
> > process is migrated to a different core?
> 
> Yes, we have a dsb when we unlock the runqueue for a CPU. That's why Linux
> doesn't crash and burn usually. If vcpu migration always goes through the
> usual scheduling paths, then you don't have a problem.
> 
Right, a vcpu is simply a thread, a process, so it gets migrated on the
host as any other process.

I gather this means we don't need these, except maybe for the VMID
rollover case, which I honestly didn't fully understand, but maybe it
can be added for that specific case instead?

-Christoffer

  reply	other threads:[~2013-06-20 18:50 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-06-19 13:20 [PATCH 0/5] A handful of KVM/ARM fixes Marc Zyngier
2013-06-19 13:20 ` [PATCH 1/5] ARM: KVM: perform save/restore of PAR Marc Zyngier
2013-06-19 13:20 ` [PATCH 2/5] ARM: KVM: add missing dsb before invalidating Stage-2 TLBs Marc Zyngier
2013-06-20  0:05   ` Christoffer Dall
2013-06-20  0:08     ` Christoffer Dall
2013-06-20 10:47   ` Will Deacon
2013-06-19 13:20 ` [PATCH 3/5] ARM: KVM: make sure maintainance operation complete before world switch Marc Zyngier
2013-06-20  0:18   ` Christoffer Dall
2013-06-20  8:13     ` Marc Zyngier
2013-06-20 17:14       ` Christoffer Dall
2013-06-20 17:29         ` Marc Zyngier
2013-06-20 18:15         ` Will Deacon
2013-06-20 18:28           ` Christoffer Dall
2013-06-20 18:38             ` Will Deacon
2013-06-20 18:50               ` Christoffer Dall [this message]
2013-06-20 10:48   ` Will Deacon
2013-06-19 13:20 ` [PATCH 4/5] ARM: KVM: clear exclusive monitor on all exception returns Marc Zyngier
2013-06-20  0:27   ` Christoffer Dall
2013-06-20  8:29     ` Marc Zyngier
2013-06-19 13:20 ` [PATCH 5/5] ARM: KVM: issue a DSB after cache maintainance operations Marc Zyngier
2013-06-20 10:46   ` Will Deacon
2013-06-20 18:33 ` [PATCH 0/5] A handful of KVM/ARM fixes Christoffer Dall
2013-06-20 18:41   ` Marc Zyngier
2013-06-20 18:48     ` Christoffer Dall

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