[PATCHv2 00/11] ARM: OMAP4 clock data conversion to DT

[PATCHv2 00/11] ARM: OMAP4 clock data conversion to DT

[Tero Kristo]

Hi,

This set converts the OMAP4 clock data to device tree format.
This set also fixes a couple of problems detected in the basic clock
devicetree code (patches 2 & 3), and adds some generic support functions
for the transition phase when all the drivers are not fully devicetree
compliant (see patches 1 & 7.) OMAP4 clock data was converted from
cclock44xx_data.c file with a custom perl script, which can probably
be applied for other SoCs with some modifications also.

Version one for this work was done by Mike Turquette:
   http://comments.gmane.org/gmane.linux.ports.arm.omap/98741

This set needs the basic devicetree support code from Mike:
   http://comments.gmane.org/gmane.linux.kernel/1509300

Testing done with omap4-panda board, booted up to console and tested
that suspend / resume works with 3.10-rc6.

I have also provided a working branch here:
   git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
   branch:  mainline-3.10-rc6-omap4-dt-clks-v2

This branch contains the pre-req set from Mike, and a couple of additional
hacks you can ignore.

Any comments / testing feedback welcome.

-Tero

[PATCHv2 01/11] CLK: clkdev: add support for looking up clocks from DT

[Tero Kristo]

clk_get_sys / clk_get can now find clocks from device-tree. If a DT clock
is found, an entry is added to the clk_lookup list also for subsequent
searches.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clkdev.c |   32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 442a313..e39f082 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -93,6 +93,18 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
 EXPORT_SYMBOL(of_clk_get_by_name);
 #endif
 
+/**
+ * clkdev_add_nolock - add lookup entry for a clock
+ * @cl: pointer to new clock lookup entry
+ *
+ * Non-locking version, used internally by clk_find() to add DT based
+ * clock lookup entries.
+ */
+static void clkdev_add_nolock(struct clk_lookup *cl)
+{
+	list_add_tail(&cl->node, &clocks);
+}
+
 /*
  * Find the correct struct clk for the device and connection ID.
  * We do slightly fuzzy matching here:
@@ -106,6 +118,9 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
 {
 	struct clk_lookup *p, *cl = NULL;
 	int match, best_found = 0, best_possible = 0;
+	struct device_node *node;
+	struct clk *clk;
+	struct of_phandle_args clkspec;
 
 	if (dev_id)
 		best_possible += 2;
@@ -133,6 +148,23 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
 				break;
 		}
 	}
+
+	if (cl)
+		return cl;
+
+	/* If clock was not found, attempt to look-up from DT */
+	node = of_find_node_by_name(NULL, con_id);
+
+	clkspec.np = node;
+
+	clk = of_clk_get_from_provider(&clkspec);
+
+	if (!IS_ERR(clk)) {
+		/* We found a clock, add node to clkdev */
+		cl = clkdev_alloc(clk, con_id, dev_id);
+		clkdev_add_nolock(cl);
+	}
+
 	return cl;
 }
 
-- 
1.7.9.5

[PATCHv2 02/11] CLK: use of_property_read_u32 instead of read_u8

[Tero Kristo]

of_property_read_u8 does not work properly because of endianess problem
with its current implementation, and this causes it to always return
0 with little endian architectures. Instead, use property_read_u32
until this is fixed.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk-divider.c |    4 ++--
 drivers/clk/clk-gate.c    |    4 ++--
 drivers/clk/clk-mux.c     |    4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 17ea475..3413602 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -361,7 +361,7 @@ void of_divider_clk_setup(struct device_node *node)
 	const char *parent_name;
 	u8 clk_divider_flags = 0;
 	u32 mask = 0;
-	u8 shift = 0;
+	u32 shift = 0;
 	struct clk_div_table *table;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
@@ -375,7 +375,7 @@ void of_divider_clk_setup(struct device_node *node)
 		return;
 	}
 
-	if (of_property_read_u8(node, "bit-shift", &shift)) {
+	if (of_property_read_u32(node, "bit-shift", &shift)) {
 		shift = __ffs(mask);
 		pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
 				__func__, shift, node->name);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 72cf99d..61b4dc1 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -162,7 +162,7 @@ void of_gate_clk_setup(struct device_node *node)
 	void __iomem *reg;
 	const char *parent_name;
 	u8 clk_gate_flags = 0;
-	u8 bit_idx = 0;
+	u32 bit_idx = 0;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -170,7 +170,7 @@ void of_gate_clk_setup(struct device_node *node)
 
 	reg = of_iomap(node, 0);
 
-	if (of_property_read_u8(node, "bit-shift", &bit_idx)) {
+	if (of_property_read_u32(node, "bit-shift", &bit_idx)) {
 		pr_err("%s: missing bit-shift property for %s\n",
 				__func__, node->name);
 		return;
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index c9f9f32..e63dd1b 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -170,7 +170,7 @@ void of_mux_clk_setup(struct device_node *node)
 	int i;
 	u8 clk_mux_flags = 0;
 	u32 mask = 0;
-	u8 shift = 0;
+	u32 shift = 0;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -194,7 +194,7 @@ void of_mux_clk_setup(struct device_node *node)
 		return;
 	}
 
-	if (of_property_read_u8(node, "bit-shift", &shift)) {
+	if (of_property_read_u32(node, "bit-shift", &shift)) {
 		shift = __ffs(mask);
 		pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
 				__func__, shift, node->name);
-- 
1.7.9.5

[PATCHv2 02/11] CLK: use of_property_read_u32 instead of read_u8

[Mike Turquette]

On Wed, Jun 19, 2013 at 6:18 AM, Tero Kristo <t-kristo@ti.com> wrote:
> of_property_read_u8 does not work properly because of endianess problem
> with its current implementation, and this causes it to always return
> 0 with little endian architectures. Instead, use property_read_u32
> until this is fixed.

Tero,

Thanks for the fix. Heiko Stubner pointed out to me that in order to
read a u8 value the DT node needs to specify "/bits/ 8" before the
values. From the of_property_read_u8_array kerneldoc:

"
/**
...
 * dts entry of array should be like:
 *      property = /bits/ 8 <0x50 0x60 0x70>;
 *
 * The out_value is modified only if a valid u8 value can be decoded.
 */
"

Still I think it is a bit silly to have to do this in all of the
bindings, so I'm going to roll this patch into my next version of the
series if only for the sake of readability. Not only that but it is
slightly more future proof for the binding to use a u32 value. The
fact that the implementation in Linux uses a u8 is of little
consequence to the binding.  I'll also add a cast like the following
to your patch:

clk = clk_register_gate(NULL, clk_name, parent_name, 0, reg, (u8) bit_idx,
                clk_gate_flags, NULL);

Thanks,
Mike

>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  drivers/clk/clk-divider.c |    4 ++--
>  drivers/clk/clk-gate.c    |    4 ++--
>  drivers/clk/clk-mux.c     |    4 ++--
>  3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 17ea475..3413602 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -361,7 +361,7 @@ void of_divider_clk_setup(struct device_node *node)
>         const char *parent_name;
>         u8 clk_divider_flags = 0;
>         u32 mask = 0;
> -       u8 shift = 0;
> +       u32 shift = 0;
>         struct clk_div_table *table;
>
>         of_property_read_string(node, "clock-output-names", &clk_name);
> @@ -375,7 +375,7 @@ void of_divider_clk_setup(struct device_node *node)
>                 return;
>         }
>
> -       if (of_property_read_u8(node, "bit-shift", &shift)) {
> +       if (of_property_read_u32(node, "bit-shift", &shift)) {
>                 shift = __ffs(mask);
>                 pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
>                                 __func__, shift, node->name);
> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> index 72cf99d..61b4dc1 100644
> --- a/drivers/clk/clk-gate.c
> +++ b/drivers/clk/clk-gate.c
> @@ -162,7 +162,7 @@ void of_gate_clk_setup(struct device_node *node)
>         void __iomem *reg;
>         const char *parent_name;
>         u8 clk_gate_flags = 0;
> -       u8 bit_idx = 0;
> +       u32 bit_idx = 0;
>
>         of_property_read_string(node, "clock-output-names", &clk_name);
>
> @@ -170,7 +170,7 @@ void of_gate_clk_setup(struct device_node *node)
>
>         reg = of_iomap(node, 0);
>
> -       if (of_property_read_u8(node, "bit-shift", &bit_idx)) {
> +       if (of_property_read_u32(node, "bit-shift", &bit_idx)) {
>                 pr_err("%s: missing bit-shift property for %s\n",
>                                 __func__, node->name);
>                 return;
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index c9f9f32..e63dd1b 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -170,7 +170,7 @@ void of_mux_clk_setup(struct device_node *node)
>         int i;
>         u8 clk_mux_flags = 0;
>         u32 mask = 0;
> -       u8 shift = 0;
> +       u32 shift = 0;
>
>         of_property_read_string(node, "clock-output-names", &clk_name);
>
> @@ -194,7 +194,7 @@ void of_mux_clk_setup(struct device_node *node)
>                 return;
>         }
>
> -       if (of_property_read_u8(node, "bit-shift", &shift)) {
> +       if (of_property_read_u32(node, "bit-shift", &shift)) {
>                 shift = __ffs(mask);
>                 pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
>                                 __func__, shift, node->name);
> --
> 1.7.9.5
>

[PATCHv2 02/11] CLK: use of_property_read_u32 instead of read_u8

[Nishanth Menon]

On 17:57-20130620, Mike Turquette wrote:
> On Wed, Jun 19, 2013 at 6:18 AM, Tero Kristo <t-kristo@ti.com> wrote:
> > of_property_read_u8 does not work properly because of endianess problem
> > with its current implementation, and this causes it to always return
> > 0 with little endian architectures. Instead, use property_read_u32
> > until this is fixed.
> 
> Tero,
> 
> Thanks for the fix. Heiko Stubner pointed out to me that in order to
> read a u8 value the DT node needs to specify "/bits/ 8" before the
> values. From the of_property_read_u8_array kerneldoc:
> 
> "
> /**
> ...
>  * dts entry of array should be like:
>  *      property = /bits/ 8 <0x50 0x60 0x70>;
>  *
>  * The out_value is modified only if a valid u8 value can be decoded.
>  */
> "
> 
> Still I think it is a bit silly to have to do this in all of the
> bindings, so I'm going to roll this patch into my next version of the
> series if only for the sake of readability. Not only that but it is
> slightly more future proof for the binding to use a u32 value. The
> fact that the implementation in Linux uses a u8 is of little
> consequence to the binding.  I'll also add a cast like the following
> to your patch:
> 
> clk = clk_register_gate(NULL, clk_name, parent_name, 0, reg, (u8) bit_idx,
>                 clk_gate_flags, NULL);
> 
Given that dtb size could be directly impacted, could we consider
something like a preprocessor macro to make it readable, yet not too
huge dts size?
> 
> >
> > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> > ---
> >  drivers/clk/clk-divider.c |    4 ++--
> >  drivers/clk/clk-gate.c    |    4 ++--
> >  drivers/clk/clk-mux.c     |    4 ++--
> >  3 files changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > index 17ea475..3413602 100644
> > --- a/drivers/clk/clk-divider.c
> > +++ b/drivers/clk/clk-divider.c
> > @@ -361,7 +361,7 @@ void of_divider_clk_setup(struct device_node *node)
> >         const char *parent_name;
> >         u8 clk_divider_flags = 0;
> >         u32 mask = 0;
> > -       u8 shift = 0;
> > +       u32 shift = 0;
> >         struct clk_div_table *table;
> >
> >         of_property_read_string(node, "clock-output-names", &clk_name);
> > @@ -375,7 +375,7 @@ void of_divider_clk_setup(struct device_node *node)
> >                 return;
> >         }
> >
> > -       if (of_property_read_u8(node, "bit-shift", &shift)) {
> > +       if (of_property_read_u32(node, "bit-shift", &shift)) {
> >                 shift = __ffs(mask);
> >                 pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
> >                                 __func__, shift, node->name);
> > diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> > index 72cf99d..61b4dc1 100644
> > --- a/drivers/clk/clk-gate.c
> > +++ b/drivers/clk/clk-gate.c
> > @@ -162,7 +162,7 @@ void of_gate_clk_setup(struct device_node *node)
> >         void __iomem *reg;
> >         const char *parent_name;
> >         u8 clk_gate_flags = 0;
> > -       u8 bit_idx = 0;
> > +       u32 bit_idx = 0;
> >
> >         of_property_read_string(node, "clock-output-names", &clk_name);
> >
> > @@ -170,7 +170,7 @@ void of_gate_clk_setup(struct device_node *node)
> >
> >         reg = of_iomap(node, 0);
> >
> > -       if (of_property_read_u8(node, "bit-shift", &bit_idx)) {
> > +       if (of_property_read_u32(node, "bit-shift", &bit_idx)) {
> >                 pr_err("%s: missing bit-shift property for %s\n",
> >                                 __func__, node->name);
> >                 return;
> > diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> > index c9f9f32..e63dd1b 100644
> > --- a/drivers/clk/clk-mux.c
> > +++ b/drivers/clk/clk-mux.c
> > @@ -170,7 +170,7 @@ void of_mux_clk_setup(struct device_node *node)
> >         int i;
> >         u8 clk_mux_flags = 0;
> >         u32 mask = 0;
> > -       u8 shift = 0;
> > +       u32 shift = 0;
> >
> >         of_property_read_string(node, "clock-output-names", &clk_name);
> >
> > @@ -194,7 +194,7 @@ void of_mux_clk_setup(struct device_node *node)
> >                 return;
> >         }
> >
> > -       if (of_property_read_u8(node, "bit-shift", &shift)) {
> > +       if (of_property_read_u32(node, "bit-shift", &shift)) {
> >                 shift = __ffs(mask);
> >                 pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
> >                                 __func__, shift, node->name);
> > --
> > 1.7.9.5
> >

-- 
Regards,
Nishanth Menon

[PATCHv2 02/11] CLK: use of_property_read_u32 instead of read_u8

[Mike Turquette]

Quoting Nishanth Menon (2013-06-21 05:45:58)
> On 17:57-20130620, Mike Turquette wrote:
> > On Wed, Jun 19, 2013 at 6:18 AM, Tero Kristo <t-kristo@ti.com> wrote:
> > > of_property_read_u8 does not work properly because of endianess problem
> > > with its current implementation, and this causes it to always return
> > > 0 with little endian architectures. Instead, use property_read_u32
> > > until this is fixed.
> > 
> > Tero,
> > 
> > Thanks for the fix. Heiko Stubner pointed out to me that in order to
> > read a u8 value the DT node needs to specify "/bits/ 8" before the
> > values. From the of_property_read_u8_array kerneldoc:
> > 
> > "
> > /**
> > ...
> >  * dts entry of array should be like:
> >  *      property = /bits/ 8 <0x50 0x60 0x70>;
> >  *
> >  * The out_value is modified only if a valid u8 value can be decoded.
> >  */
> > "
> > 
> > Still I think it is a bit silly to have to do this in all of the
> > bindings, so I'm going to roll this patch into my next version of the
> > series if only for the sake of readability. Not only that but it is
> > slightly more future proof for the binding to use a u32 value. The
> > fact that the implementation in Linux uses a u8 is of little
> > consequence to the binding.  I'll also add a cast like the following
> > to your patch:
> > 
> > clk = clk_register_gate(NULL, clk_name, parent_name, 0, reg, (u8) bit_idx,
> >                 clk_gate_flags, NULL);
> > 
> Given that dtb size could be directly impacted, could we consider
> something like a preprocessor macro to make it readable, yet not too
> huge dts size?

bit-shift is an optional property and you don't need it at all. It is
mostly there for legacy reasons and also it is useful to the Rockchip
and Hisilicon drivers.

The OMAP DT clock data could simply use a 32-bit mask that covers the
whole register and not provide bit-shift at all, if you're worried about
the extra 24 bits.

Regards,
Mike

> > 
> > >
> > > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> > > ---
> > >  drivers/clk/clk-divider.c |    4 ++--
> > >  drivers/clk/clk-gate.c    |    4 ++--
> > >  drivers/clk/clk-mux.c     |    4 ++--
> > >  3 files changed, 6 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > > index 17ea475..3413602 100644
> > > --- a/drivers/clk/clk-divider.c
> > > +++ b/drivers/clk/clk-divider.c
> > > @@ -361,7 +361,7 @@ void of_divider_clk_setup(struct device_node *node)
> > >         const char *parent_name;
> > >         u8 clk_divider_flags = 0;
> > >         u32 mask = 0;
> > > -       u8 shift = 0;
> > > +       u32 shift = 0;
> > >         struct clk_div_table *table;
> > >
> > >         of_property_read_string(node, "clock-output-names", &clk_name);
> > > @@ -375,7 +375,7 @@ void of_divider_clk_setup(struct device_node *node)
> > >                 return;
> > >         }
> > >
> > > -       if (of_property_read_u8(node, "bit-shift", &shift)) {
> > > +       if (of_property_read_u32(node, "bit-shift", &shift)) {
> > >                 shift = __ffs(mask);
> > >                 pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
> > >                                 __func__, shift, node->name);
> > > diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> > > index 72cf99d..61b4dc1 100644
> > > --- a/drivers/clk/clk-gate.c
> > > +++ b/drivers/clk/clk-gate.c
> > > @@ -162,7 +162,7 @@ void of_gate_clk_setup(struct device_node *node)
> > >         void __iomem *reg;
> > >         const char *parent_name;
> > >         u8 clk_gate_flags = 0;
> > > -       u8 bit_idx = 0;
> > > +       u32 bit_idx = 0;
> > >
> > >         of_property_read_string(node, "clock-output-names", &clk_name);
> > >
> > > @@ -170,7 +170,7 @@ void of_gate_clk_setup(struct device_node *node)
> > >
> > >         reg = of_iomap(node, 0);
> > >
> > > -       if (of_property_read_u8(node, "bit-shift", &bit_idx)) {
> > > +       if (of_property_read_u32(node, "bit-shift", &bit_idx)) {
> > >                 pr_err("%s: missing bit-shift property for %s\n",
> > >                                 __func__, node->name);
> > >                 return;
> > > diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> > > index c9f9f32..e63dd1b 100644
> > > --- a/drivers/clk/clk-mux.c
> > > +++ b/drivers/clk/clk-mux.c
> > > @@ -170,7 +170,7 @@ void of_mux_clk_setup(struct device_node *node)
> > >         int i;
> > >         u8 clk_mux_flags = 0;
> > >         u32 mask = 0;
> > > -       u8 shift = 0;
> > > +       u32 shift = 0;
> > >
> > >         of_property_read_string(node, "clock-output-names", &clk_name);
> > >
> > > @@ -194,7 +194,7 @@ void of_mux_clk_setup(struct device_node *node)
> > >                 return;
> > >         }
> > >
> > > -       if (of_property_read_u8(node, "bit-shift", &shift)) {
> > > +       if (of_property_read_u32(node, "bit-shift", &shift)) {
> > >                 shift = __ffs(mask);
> > >                 pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
> > >                                 __func__, shift, node->name);
> > > --
> > > 1.7.9.5
> > >
> 
> -- 
> Regards,
> Nishanth Menon

[PATCHv2 03/11] CLK: divider: fix table parsing logic for DT

[Tero Kristo]

The existing implementation had a couple of bugs:

1) table_size was attempted to read improperly, it has to be calculated
   from the 'len' parameter of a property
2) Reading the integer entries from the table was reading only first
   two entries of the DT data

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk-divider.c |   19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 3413602..2fa7932 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -325,15 +325,18 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
 struct clk_div_table *of_clk_get_div_table(struct device_node *node)
 {
 	int i;
-	int table_size = 0;
+	u32 table_size;
 	struct clk_div_table *table;
-	u32 pair[2];
+	const __be32 *tablespec;
+	u32 val;
 
-	table_size = of_count_phandle_with_args(node, "table", "#clock-cells");
+	tablespec = of_get_property(node, "table", &table_size);
 
-	if (table_size < 1)
+	if (!tablespec)
 		return NULL;
 
+	table_size /= sizeof(struct clk_div_table);
+
 	table = kzalloc(sizeof(struct clk_div_table) * table_size, GFP_KERNEL);
 	if (!table) {
 		pr_err("%s: unable to allocate memory for %s table\n", __func__, node->name);
@@ -341,10 +344,10 @@ struct clk_div_table *of_clk_get_div_table(struct device_node *node)
 	}
 
 	for (i = 0; i < table_size; i++) {
-		if (!of_property_read_u32_array(node, "table", pair, ARRAY_SIZE(pair))) {
-			table[i].val = pair[0];
-			table[i].div = pair[1];
-		}
+		of_property_read_u32_index(node, "table", i * 2, &val);
+		table[i].div = val;
+		of_property_read_u32_index(node, "table", i * 2 + 1, &val);
+		table[i].val = val;
 	}
 
 	return table;
-- 
1.7.9.5

[PATCHv2 04/11] clk: omap: introduce clock driver

[Tero Kristo]

Parses OMAP clock data from DT and registers those clocks with the clock
framework.  dt_omap_clk_init must be called early during boot for timer
initialization so it is exported and called from the existing clock code
instead of probing like a real driver. Based on initial work done by
Mike Turquette.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
---
 drivers/clk/Makefile      |    1 +
 drivers/clk/omap/Makefile |    1 +
 drivers/clk/omap/clk.c    |   44 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/omap.h  |   24 ++++++++++++++++++++++++
 4 files changed, 70 insertions(+)
 create mode 100644 drivers/clk/omap/Makefile
 create mode 100644 drivers/clk/omap/clk.c
 create mode 100644 include/linux/clk/omap.h

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 137d3e7..1d5a2ec 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
 obj-$(CONFIG_ARCH_ZYNQ)		+= clk-zynq.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
+obj-$(CONFIG_ARCH_OMAP)		+= omap/
 
 obj-$(CONFIG_X86)		+= x86/
 
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
new file mode 100644
index 0000000..8195931
--- /dev/null
+++ b/drivers/clk/omap/Makefile
@@ -0,0 +1 @@
+obj-y					+= clk.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
new file mode 100644
index 0000000..b4533ed
--- /dev/null
+++ b/drivers/clk/omap/clk.c
@@ -0,0 +1,44 @@
+/*
+ * OMAP PRCM clock driver
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *     Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk/omap.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+/* FIXME - should the OMAP PRCM clock driver match generic types? */
+static const struct of_device_id clk_match[] = {
+	{.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
+	{.compatible = "mux-clock", .data = of_mux_clk_setup, },
+	{.compatible = "fixed-factor-clock",
+		.data = of_fixed_factor_clk_setup, },
+	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
+	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
+	{},
+};
+
+/* FIXME - need to initialize early; skip real driver registration & probe */
+int __init dt_omap_clk_init(void)
+{
+	of_clk_init(clk_match);
+	return 0;
+}
+
+MODULE_DESCRIPTION("OMAP Clock driver");
+MODULE_AUTHOR("Texas Instruments Inc.");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
new file mode 100644
index 0000000..504e838
--- /dev/null
+++ b/include/linux/clk/omap.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_CLK_OMAP_H_
+#define __LINUX_CLK_OMAP_H_
+
+int __init dt_omap_clk_init(void);
+
+#endif
-- 
1.7.9.5

[PATCHv2 05/11] CLK: OMAP4: Add DPLL clock support

[Tero Kristo]

The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile |    2 +-
 drivers/clk/omap/clk.c    |    1 +
 drivers/clk/omap/dpll.c   |  307 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 309 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/dpll.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 8195931..4cad480 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1 +1 @@
-obj-y					+= clk.o
+obj-y					+= clk.o dpll.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index b4533ed..c2a3f8f 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
 		.data = of_fixed_factor_clk_setup, },
 	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
+	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
 	{},
 };
 
diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
new file mode 100644
index 0000000..183ec60
--- /dev/null
+++ b/drivers/clk/omap/dpll.c
@@ -0,0 +1,307 @@
+/*
+ * OMAP DPLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/omap.h>
+
+/*
+ * DOC: basic adjustable divider clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is adjustable.  clk->rate = parent->rate / divisor
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+#define div_mask(d)	((1 << ((d)->width)) - 1)
+
+static const struct clk_ops dpll_m4xen_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
+	.round_rate	= &omap4_dpll_regm4xen_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.get_parent	= &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops dpll_core_ck_ops = {
+	.recalc_rate	= &omap3_dpll_recalc,
+	.get_parent	= &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops dpll_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.round_rate	= &omap2_dpll_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.get_parent	= &omap2_init_dpll_parent,
+	.init		= &omap2_init_clk_clkdm,
+};
+
+static const struct clk_ops dpll_x2_ck_ops = {
+	.recalc_rate	= &omap3_clkoutx2_recalc,
+};
+
+struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
+		const char **parent_names, int num_parents, unsigned long flags,
+		struct dpll_data *dpll_data, const char *clkdm_name,
+		const struct clk_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+
+	/* allocate the divider */
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk_hw->dpll_data = dpll_data;
+	clk_hw->ops = &clkhwops_omap3_dpll;
+	clk_hw->clkdm_name = clkdm_name;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.flags = flags;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	/* register the clock */
+	clk = clk_register(dev, &clk_hw->hw);
+
+	if (IS_ERR(clk))
+		kfree(clk_hw);
+	else
+		omap2_init_clk_hw_omap_clocks(clk);
+
+	return clk;
+}
+
+struct clk *omap_clk_register_dpll_x2(struct device *dev, const char *name,
+		const char *parent_name, void __iomem *reg,
+		const struct clk_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+
+	if (!parent_name) {
+		pr_err("%s: dpll_x2 must have parent\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk_hw->ops = &clkhwops_omap4_dpllmx;
+	clk_hw->clksel_reg = reg;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	/* register the clock */
+	clk = clk_register(dev, &clk_hw->hw);
+
+	if (IS_ERR(clk))
+		kfree(clk_hw);
+	else
+		omap2_init_clk_hw_omap_clocks(clk);
+
+	return clk;
+}
+
+#ifdef CONFIG_OF
+
+/**
+ * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
+ */
+static void __init of_omap_dpll_setup(struct device_node *node,
+					const struct clk_ops *ops)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names;
+	const char *clkdm_name = NULL;
+	struct of_phandle_args clkspec;
+	u8 dpll_flags = 0;
+	struct dpll_data *dd;
+	u32 idlest_mask = 0x1;
+	u32 enable_mask = 0x7;
+	u32 autoidle_mask = 0x7;
+	u32 mult_mask = 0x7ff << 8;
+	u32 div1_mask = 0x7f;
+	u32 max_multiplier = 2047;
+	u32 max_divider = 128;
+	u32 min_divider = 1;
+	int i;
+
+	dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
+	if (!dd) {
+		pr_err("%s: could not allocate dpll_data\n", __func__);
+		return;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap dpll %s must have parent(s)\n",
+			__func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	of_property_read_u32(node, "ti,idlest-mask", &idlest_mask);
+
+	of_property_read_u32(node, "ti,enable-mask", &enable_mask);
+
+	of_property_read_u32(node, "ti,autoidle-mask", &autoidle_mask);
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
+	dd->clk_ref = of_clk_get_from_provider(&clkspec);
+	if (!dd->clk_ref) {
+		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+			clk_name);
+		goto cleanup;
+	}
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
+	dd->clk_bypass = of_clk_get_from_provider(&clkspec);
+	if (!dd->clk_bypass) {
+		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+			clk_name);
+		goto cleanup;
+	}
+
+	of_property_read_string(node, "ti,clkdm-name", &clkdm_name);
+
+	dd->control_reg = of_iomap(node, 0);
+	dd->idlest_reg = of_iomap(node, 1);
+	dd->autoidle_reg = of_iomap(node, 2);
+	dd->mult_div1_reg = of_iomap(node, 3);
+
+	dd->idlest_mask = idlest_mask;
+	dd->enable_mask = enable_mask;
+	dd->autoidle_mask = autoidle_mask;
+
+	if (of_property_read_bool(node, "ti,dpll-j-type")) {
+		dd->sddiv_mask = 0xff000000;
+		mult_mask = 0xfff << 8;
+		div1_mask = 0xff;
+		max_multiplier = 4095;
+		max_divider = 256;
+	}
+
+	if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
+		dd->m4xen_mask = 0x800;
+		dd->lpmode_mask = 1 << 10;
+	}
+
+	dd->mult_mask = mult_mask;
+	dd->div1_mask = div1_mask;
+	dd->max_multiplier = max_multiplier;
+	dd->max_divider = max_divider;
+	dd->min_divider = min_divider;
+
+	clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
+				num_parents, dpll_flags, dd,
+				clkdm_name, ops);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	return;
+
+cleanup:
+	kfree(dd);
+	return;
+}
+
+static void __init of_omap_dpll_x2_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	const char *parent_name;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	reg = of_iomap(node, 0);
+
+	clk = omap_clk_register_dpll_x2(NULL, clk_name, parent_name,
+				reg, &dpll_x2_ck_ops);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+
+__init void of_omap3_dpll_setup(struct device_node *node)
+{
+	/* XXX: to be done */
+}
+EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
+CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
+
+__init void of_omap4_dpll_setup(struct device_node *node)
+{
+	const struct clk_ops *ops;
+
+	ops = &dpll_ck_ops;
+
+	if (of_property_read_bool(node, "ti,dpll-regm4xen"))
+		ops = &dpll_m4xen_ck_ops;
+
+	if (of_property_read_bool(node, "ti,dpll-core"))
+		ops = &dpll_core_ck_ops;
+
+	if (of_property_read_bool(node, "ti,dpll-clk-x2")) {
+		of_omap_dpll_x2_setup(node);
+		return;
+	}
+
+	of_omap_dpll_setup(node, ops);
+}
+EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
+CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
+#endif
-- 
1.7.9.5

[PATCHv2 06/11] CLK: omap: move part of the machine specific clock header contents to driver

[Tero Kristo]

Some of the clock.h contents are needed by the new OMAP clock driver,
including dpll_data and clk_hw_omap. Thus, move these to the generic
omap header file which can be accessed by the driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.h |  150 +----------------------------------------
 include/linux/clk/omap.h    |  155 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 155 insertions(+), 150 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd..3238c57 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
+#include <linux/clk/omap.h>
 
 struct omap_clk {
 	u16				cpu;
@@ -178,83 +179,6 @@ struct clksel {
 	const struct clksel_rate *rates;
 };
 
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @last_rounded_m4xen: cache of the last M4X result of
- *			omap4_dpll_regm4xen_round_rate()
- * @last_rounded_lpmode: cache of the last lpmode result of
- *			 omap4_dpll_lpmode_recalc()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
- * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
-	void __iomem		*mult_div1_reg;
-	u32			mult_mask;
-	u32			div1_mask;
-	struct clk		*clk_bypass;
-	struct clk		*clk_ref;
-	void __iomem		*control_reg;
-	u32			enable_mask;
-	unsigned long		last_rounded_rate;
-	u16			last_rounded_m;
-	u8			last_rounded_m4xen;
-	u8			last_rounded_lpmode;
-	u16			max_multiplier;
-	u8			last_rounded_n;
-	u8			min_divider;
-	u16			max_divider;
-	u8			modes;
-	void __iomem		*autoidle_reg;
-	void __iomem		*idlest_reg;
-	u32			autoidle_mask;
-	u32			freqsel_mask;
-	u32			idlest_mask;
-	u32			dco_mask;
-	u32			sddiv_mask;
-	u32			lpmode_mask;
-	u32			m4xen_mask;
-	u8			auto_recal_bit;
-	u8			recal_en_bit;
-	u8			recal_st_bit;
-	u8			flags;
-};
-
 /*
  * struct clk.flags possibilities
  *
@@ -274,56 +198,6 @@ struct dpll_data {
 #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
 #define CLOCK_CLKOUTX2		(1 << 5)
 
-/**
- * struct clk_hw_omap - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- */
-
-struct clk_hw_omap_ops;
-
-struct clk_hw_omap {
-	struct clk_hw		hw;
-	struct list_head	node;
-	unsigned long		fixed_rate;
-	u8			fixed_div;
-	void __iomem		*enable_reg;
-	u8			enable_bit;
-	u8			flags;
-	void __iomem		*clksel_reg;
-	u32			clksel_mask;
-	const struct clksel	*clksel;
-	struct dpll_data	*dpll_data;
-	const char		*clkdm_name;
-	struct clockdomain	*clkdm;
-	const struct clk_hw_omap_ops	*ops;
-};
-
-struct clk_hw_omap_ops {
-	void			(*find_idlest)(struct clk_hw_omap *oclk,
-					void __iomem **idlest_reg,
-					u8 *idlest_bit, u8 *idlest_val);
-	void			(*find_companion)(struct clk_hw_omap *oclk,
-					void __iomem **other_reg,
-					u8 *other_bit);
-	void			(*allow_idle)(struct clk_hw_omap *oclk);
-	void			(*deny_idle)(struct clk_hw_omap *oclk);
-};
-
 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 					unsigned long parent_rate);
 
@@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 /* DPLL Type and DCO Selection Flags */
 #define DPLL_J_TYPE		0x1
 
-long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
-			unsigned long *parent_rate);
-unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
-int omap3_noncore_dpll_enable(struct clk_hw *hw);
-void omap3_noncore_dpll_disable(struct clk_hw *hw);
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
-				unsigned long parent_rate);
 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
 void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
 void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
-unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
-				    unsigned long parent_rate);
 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
-unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
-				unsigned long parent_rate);
-long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
-				    unsigned long target_rate,
-				    unsigned long *parent_rate);
 
-void omap2_init_clk_clkdm(struct clk_hw *clk);
 void __init omap2_clk_disable_clkdm_control(void);
 
 /* clkt_clksel.c public functions */
@@ -396,7 +255,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
 
-u8 omap2_init_dpll_parent(struct clk_hw *hw);
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
 int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -408,7 +266,6 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 				void __iomem **idlest_reg,
 				u8 *idlest_bit, u8 *idlest_val);
-void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap2_clk_enable_autoidle_all(void);
 int omap2_clk_disable_autoidle_all(void);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
@@ -431,10 +288,8 @@ extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 extern struct clk dummy_ck;
 
-extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
 extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
@@ -460,8 +315,5 @@ extern const struct clksel_rate div31_1to31_rates[];
 
 extern int am33xx_clk_init(void);
 
-extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
-extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
-
 extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
 #endif
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 504e838..2d24641 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -19,6 +19,159 @@
 #ifndef __LINUX_CLK_OMAP_H_
 #define __LINUX_CLK_OMAP_H_
 
-int __init dt_omap_clk_init(void);
+/**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @last_rounded_m4xen: cache of the last M4X result of
+ *                     omap4_dpll_regm4xen_round_rate()
+ * @last_rounded_lpmode: cache of the last lpmode result of
+ *                      omap4_dpll_lpmode_recalc()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
+ * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ *
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a different structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+struct dpll_data {
+	void __iomem		*mult_div1_reg;
+	u32			mult_mask;
+	u32			div1_mask;
+	struct clk		*clk_bypass;
+	struct clk		*clk_ref;
+	void __iomem		*control_reg;
+	u32			enable_mask;
+	unsigned long		last_rounded_rate;
+	u16			last_rounded_m;
+	u8			last_rounded_m4xen;
+	u8			last_rounded_lpmode;
+	u16			max_multiplier;
+	u8			last_rounded_n;
+	u8			min_divider;
+	u16			max_divider;
+	u8			modes;
+	void __iomem		*autoidle_reg;
+	void __iomem		*idlest_reg;
+	u32			autoidle_mask;
+	u32			freqsel_mask;
+	u32			idlest_mask;
+	u32			dco_mask;
+	u32			sddiv_mask;
+	u32			lpmode_mask;
+	u32			m4xen_mask;
+	u8			auto_recal_bit;
+	u8			recal_en_bit;
+	u8			recal_st_bit;
+	u8			flags;
+};
+
+/**
+ * struct clk_hw_omap - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @flags: see "struct clk.flags possibilities" above
+ * @clksel_reg: for clksel clks, register va containing src/divisor select
+ * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ * @clksel: for clksel clks, pointer to struct clksel for this clock
+ * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ * @clkdm_name: clockdomain name that this clock is contained in
+ * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name@runtime
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ */
+
+struct clk_hw_omap_ops;
+
+struct clk_hw_omap {
+	struct clk_hw		hw;
+	struct list_head	node;
+	unsigned long		fixed_rate;
+	u8			fixed_div;
+	void __iomem		*enable_reg;
+	u8			enable_bit;
+	u8			flags;
+	void __iomem		*clksel_reg;
+	u32			clksel_mask;
+	const struct clksel	*clksel;
+	struct dpll_data	*dpll_data;
+	const char		*clkdm_name;
+	struct clockdomain	*clkdm;
+	const struct clk_hw_omap_ops	*ops;
+};
+
+struct clk_hw_omap_ops {
+	void			(*find_idlest)(struct clk_hw_omap *oclk,
+					void __iomem **idlest_reg,
+					u8 *idlest_bit, u8 *idlest_val);
+	void			(*find_companion)(struct clk_hw_omap *oclk,
+					void __iomem **other_reg,
+					u8 *other_bit);
+	void			(*allow_idle)(struct clk_hw_omap *oclk);
+	void			(*deny_idle)(struct clk_hw_omap *oclk);
+};
+
+void omap2_init_clk_hw_omap_clocks(struct clk *clk);
+int omap3_noncore_dpll_enable(struct clk_hw *hw);
+void omap3_noncore_dpll_disable(struct clk_hw *hw);
+int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate);
+unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
+				unsigned long parent_rate);
+long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
+				    unsigned long target_rate,
+				    unsigned long *parent_rate);
+u8 omap2_init_dpll_parent(struct clk_hw *hw);
+unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
+long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+			unsigned long *parent_rate);
+void omap2_init_clk_clkdm(struct clk_hw *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
+				    unsigned long parent_rate);
+
+int omap2_clkops_enable_clkdm(struct clk_hw *hw);
+void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+
+extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
+extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+
+/* DT functions */
+int dt_omap_clk_init(void);
+void of_omap4_dpll_setup(struct device_node *node);
 
 #endif
-- 
1.7.9.5

[PATCHv2 06/11] CLK: omap: move part of the machine specific clock header contents to driver

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [130619 06:25]:
> Some of the clock.h contents are needed by the new OMAP clock driver,
> including dpll_data and clk_hw_omap. Thus, move these to the generic
> omap header file which can be accessed by the driver.

Do you mean "are only needed by the new OMAP clock driver"?

Otherwise it sounds like this will break things for other
omaps that don't yet have clocks configured in DT..

Regards,

Tony

[PATCHv2 06/11] CLK: omap: move part of the machine specific clock header contents to driver

[Tero Kristo]

On 06/21/2013 10:32 AM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [130619 06:25]:
>> Some of the clock.h contents are needed by the new OMAP clock driver,
>> including dpll_data and clk_hw_omap. Thus, move these to the generic
>> omap header file which can be accessed by the driver.
>
> Do you mean "are only needed by the new OMAP clock driver"?

Not only, it is needed by both driver and mach-omap2.

> Otherwise it sounds like this will break things for other
> omaps that don't yet have clocks configured in DT..

No it doesn't, as you can probably see, the new include/linux/clk/omap.h 
is included from clock.h also.

-Tero

>
> Regards,
>
> Tony
>

[PATCHv2 07/11] ARM: OMAP: clock: add DT duplicate clock registration mechanism

[Tero Kristo]

Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific clock names.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.c |   39 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/clock.h |   16 ++++++++++++++++
 2 files changed, 55 insertions(+)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca9..6fe14b5 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -584,6 +584,45 @@ void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
 }
 
 /**
+ * omap_dt_clocks_register - register DT duplicate clocks during boot
+ * @oclks: list of clocks to register
+ * @cnt: number of clocks
+ *
+ * Register duplicate or non-standard DT clock entries during boot. By
+ * default, DT clocks are found based on their node name. If any
+ * additional con-id / dev-id -> clock mapping is required, use this
+ * function to list these.
+ */
+void __init omap_dt_clocks_register(struct omap_dt_clk oclks[], int cnt)
+{
+	struct omap_dt_clk *c;
+	struct device_node *n;
+	struct clk *clk;
+	struct of_phandle_args clkspec;
+
+	for (c = oclks; c < oclks + cnt; c++) {
+		n = of_find_node_by_name(NULL, c->node_name);
+
+		if (!n) {
+			pr_err("%s: %s not found!\n", __func__, c->node_name);
+			continue;
+		}
+
+		clkspec.np = n;
+
+		clk = of_clk_get_from_provider(&clkspec);
+
+		if (!clk) {
+			pr_err("%s: %s has no clock!\n", __func__,
+				c->node_name);
+			continue;
+		}
+		c->lk.clk = clk;
+		clkdev_add(&c->lk);
+	}
+}
+
+/**
  * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
  * @mpurate_ck_name: clk name of the clock to change rate
  *
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 3238c57..1c1fbe4 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -37,6 +37,21 @@ struct omap_clk {
 		},			\
 	}
 
+struct omap_dt_clk {
+	u16				cpu;
+	struct clk_lookup		lk;
+	const char			*node_name;
+};
+
+#define DT_CLK(dev, con, name)		\
+	{				\
+		.lk = {			\
+			.dev_id = dev,	\
+			.con_id = con,	\
+		},			\
+		.node_name = name,	\
+	}
+
 struct clockdomain;
 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
@@ -316,4 +331,5 @@ extern const struct clksel_rate div31_1to31_rates[];
 extern int am33xx_clk_init(void);
 
 extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
+extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
 #endif
-- 
1.7.9.5

[PATCHv2 08/11] CLK: omap: add autoidle support

[Tero Kristo]

OMAP clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.c |    6 ++
 drivers/clk/omap/Makefile   |    2 +-
 drivers/clk/omap/autoidle.c |  130 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/omap/clk.c      |    4 +-
 include/linux/clk/omap.h    |    4 ++
 5 files changed, 143 insertions(+), 3 deletions(-)
 create mode 100644 drivers/clk/omap/autoidle.c

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 6fe14b5..9bd66b4 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
 		if (c->ops && c->ops->allow_idle)
 			c->ops->allow_idle(c);
+
+	of_omap_clk_allow_autoidle_all();
+
 	return 0;
 }
 
@@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
 		if (c->ops && c->ops->deny_idle)
 			c->ops->deny_idle(c);
+
+	of_omap_clk_deny_autoidle_all();
+
 	return 0;
 }
 
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 4cad480..ca56700 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1 +1 @@
-obj-y					+= clk.o dpll.o
+obj-y					+= clk.o dpll.o autoidle.o
diff --git a/drivers/clk/omap/autoidle.c b/drivers/clk/omap/autoidle.c
new file mode 100644
index 0000000..6424cb2
--- /dev/null
+++ b/drivers/clk/omap/autoidle.c
@@ -0,0 +1,130 @@
+/*
+ * OMAP clock autoidle support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#ifdef CONFIG_OF
+struct clk_omap_autoidle {
+	void __iomem		*reg;
+	u8			shift;
+	u8			flags;
+	const char		*name;
+	struct list_head	node;
+};
+
+#define AUTOIDLE_LOW		0x1
+
+static LIST_HEAD(autoidle_clks);
+
+static void omap_allow_autoidle(struct clk_omap_autoidle *clk)
+{
+	u32 val;
+
+	val = readl(clk->reg);
+
+	if (clk->flags & AUTOIDLE_LOW)
+		val &= ~(1 << clk->shift);
+	else
+		val |= (1 << clk->shift);
+
+	writel(val, clk->reg);
+}
+
+static void omap_deny_autoidle(struct clk_omap_autoidle *clk)
+{
+	u32 val;
+
+	val = readl(clk->reg);
+
+	if (clk->flags & AUTOIDLE_LOW)
+		val |= (1 << clk->shift);
+	else
+		val &= ~(1 << clk->shift);
+
+	writel(val, clk->reg);
+}
+
+void of_omap_clk_allow_autoidle_all(void)
+{
+	struct clk_omap_autoidle *c;
+
+	list_for_each_entry(c, &autoidle_clks, node)
+		omap_allow_autoidle(c);
+}
+
+void of_omap_clk_deny_autoidle_all(void)
+{
+	struct clk_omap_autoidle *c;
+
+	list_for_each_entry(c, &autoidle_clks, node)
+		omap_deny_autoidle(c);
+}
+
+static __init void of_omap_autoidle_setup(struct device_node *node)
+{
+	u32 shift;
+	void __iomem *reg;
+	struct clk_omap_autoidle *clk;
+
+	if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
+		return;
+
+	reg = of_iomap(node, 0);
+
+	clk = kzalloc(sizeof(struct clk_omap_autoidle), GFP_KERNEL);
+
+	if (!clk) {
+		pr_err("%s: kzalloc failed\n", __func__);
+		return;
+	}
+
+	clk->shift = shift;
+	clk->name = node->name;
+	clk->reg = reg;
+
+	if (of_property_read_bool(node, "ti,autoidle-low"))
+		clk->flags |= AUTOIDLE_LOW;
+
+	list_add(&clk->node, &autoidle_clks);
+}
+
+void __init of_omap_divider_setup(struct device_node *node)
+{
+	of_divider_clk_setup(node);
+	of_omap_autoidle_setup(node);
+}
+EXPORT_SYMBOL_GPL(of_omap_divider_setup);
+CLK_OF_DECLARE(omap_autoidle_clock, "divider-clock", of_omap_divider_setup);
+
+void __init of_omap_fixed_factor_setup(struct device_node *node)
+{
+	of_fixed_factor_clk_setup(node);
+	of_omap_autoidle_setup(node);
+}
+EXPORT_SYMBOL_GPL(of_omap_fixed_factor_setup);
+CLK_OF_DECLARE(omap_fixed_factor_clock, "fixed-factor-clock",
+	of_omap_fixed_factor_setup);
+
+#endif
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index c2a3f8f..181795f 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -26,8 +26,8 @@ static const struct of_device_id clk_match[] = {
 	{.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
 	{.compatible = "mux-clock", .data = of_mux_clk_setup, },
 	{.compatible = "fixed-factor-clock",
-		.data = of_fixed_factor_clk_setup, },
-	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
+		.data = of_omap_fixed_factor_setup, },
+	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
 	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
 	{},
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 2d24641..003e374 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -173,5 +173,9 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 /* DT functions */
 int dt_omap_clk_init(void);
 void of_omap4_dpll_setup(struct device_node *node);
+void of_omap_fixed_factor_setup(struct device_node *node);
+void of_omap_divider_setup(struct device_node *node);
+void of_omap_clk_allow_autoidle_all(void);
+void of_omap_clk_deny_autoidle_all(void);
 
 #endif
-- 
1.7.9.5

[PATCHv2 09/11] CLK: omap: add support for OMAP gate clock

[Tero Kristo]

This node adds support for a clock node which allows control to the
clockdomain enable / disable.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile |    2 +-
 drivers/clk/omap/clk.c    |    1 +
 drivers/clk/omap/gate.c   |   88 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/omap.h  |    1 +
 4 files changed, 91 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/gate.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index ca56700..3d3ca30f 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1 +1 @@
-obj-y					+= clk.o dpll.o autoidle.o
+obj-y					+= clk.o dpll.o autoidle.o gate.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index 181795f..20643a2 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -30,6 +30,7 @@ static const struct of_device_id clk_match[] = {
 	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
 	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
+	{.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
 	{},
 };
 
diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
new file mode 100644
index 0000000..7186bb2
--- /dev/null
+++ b/drivers/clk/omap/gate.c
@@ -0,0 +1,88 @@
+/*
+ * OMAP gate clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/omap.h>
+
+#ifdef CONFIG_OF
+
+static const struct clk_ops omap_gate_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_clkops_enable_clkdm,
+	.disable	= &omap2_clkops_disable_clkdm,
+};
+
+void __init of_omap_gate_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names;
+	int i;
+
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return;
+	}
+
+	clk_hw->hw.init = &init;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
+
+	init.name = clk_name;
+	init.ops = &omap_gate_clk_ops;
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap trace_clk %s must have parent(s)\n",
+			__func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	init.num_parents = num_parents;
+	init.parent_names = parent_names;
+
+	clk = clk_register(NULL, &clk_hw->hw);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		return;
+	}
+
+cleanup:
+	kfree(clk_hw);
+}
+EXPORT_SYMBOL(of_omap_gate_clk_setup);
+CLK_OF_DECLARE(omap_gate_clk, "ti,omap-gate-clock", of_omap_gate_clk_setup);
+#endif
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 003e374..17757d3 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -175,6 +175,7 @@ int dt_omap_clk_init(void);
 void of_omap4_dpll_setup(struct device_node *node);
 void of_omap_fixed_factor_setup(struct device_node *node);
 void of_omap_divider_setup(struct device_node *node);
+void of_omap_gate_clk_setup(struct device_node *node);
 void of_omap_clk_allow_autoidle_all(void);
 void of_omap_clk_deny_autoidle_all(void);
 
-- 
1.7.9.5

[PATCHv2 10/11] ARM: dts: omap4 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap4-clocks.dtsi | 1704 +++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi        |    2 +
 2 files changed, 1706 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap4-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap4-clocks.dtsi b/arch/arm/boot/dts/omap4-clocks.dtsi
new file mode 100644
index 0000000..b420d8a
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-clocks.dtsi
@@ -0,0 +1,1704 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* Root clocks */
+extalt_clkin_ck: extalt_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <59000000>;
+};
+
+pad_clks_src_ck: pad_clks_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck at 4a004108 {
+	compatible = "gate-clock";
+	reg = <0x4a004108 0x4>;
+	bit-shift = <8>;
+	clocks = <&pad_clks_src_ck>;
+	#clock-cells = <0>;
+};
+
+pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk at 4a004108 {
+	compatible = "gate-clock";
+	reg = <0x4a004108 0x4>;
+	bit-shift = <10>;
+	clocks = <&slimbus_src_clk>;
+	#clock-cells = <0>;
+};
+
+sys_32k_ck: sys_32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+sys_clkin_ck: sys_clkin_ck at 4a306110 {
+	compatible = "mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a306110 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+tie_low_clock_ck: tie_low_clock_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60motg_ck: xclk60motg_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+/* Module clocks and DPLL outputs */
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a306108 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+};
+
+abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck at 4a30610c {
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30610c 0x4>;
+	bit-mask = <0x1>;
+};
+
+/* DPLL_ABE */
+dpll_abe_ck: dpll_abe_ck {
+	clocks = <&abe_dpll_refclk_mux_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+	ti,clk-bypass = <&abe_dpll_bypass_clk_mux_ck>;
+	ti,clk-ref = <&abe_dpll_refclk_mux_ck>;
+	compatible = "ti,omap4-dpll-clock";
+	ti,dpll-regm4xen;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+	clocks = <&dpll_abe_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0041f0 0x4>;
+	compatible = "ti,omap4-dpll-clock";
+	ti,dpll-clk-x2;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0041f0 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	#clock-cells = <0>;
+	clock-div = <8>;
+	clock-mult = <1>;
+};
+
+abe_clk: abe_clk at 4a004108 {
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a004108 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+aess_fclk: aess_fclk at 4a004528 {
+	compatible = "divider-clock";
+	clocks = <&abe_clk>;
+	#clock-cells = <0>;
+	reg = <0x4a004528 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0041f4 {
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0041f4 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck at 4a00412c {
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a00412c 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <23>;
+};
+
+/* DPLL_CORE */
+dpll_core_ck: dpll_core_ck {
+	clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+	ti,clk-bypass = <&core_hsd_byp_clk_mux_ck>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	compatible = "ti,omap4-dpll-clock";
+	ti,dpll-core;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	clocks = <&dpll_core_ck>;
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	ti,dpll-clk-x2;
+};
+
+dpll_core_m6x2_ck: dpll_core_m6x2_ck at 4a004140 {
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a004140 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck at 4a004130 {
+	compatible = "divider-clock";
+	clocks = <&dpll_core_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a004130 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+ddrphy_ck: ddrphy_ck {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m2_ck>;
+	#clock-cells = <0>;
+	clock-div = <2>;
+	clock-mult = <1>;
+};
+
+dpll_core_m5x2_ck: dpll_core_m5x2_ck at 4a00413c {
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a00413c 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+div_core_ck: div_core_ck at 4a004100 {
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+};
+
+div_iva_hs_clk: div_iva_hs_clk at 4a0041dc {
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0041dc 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+div_mpu_hs_clk: div_mpu_hs_clk at 4a00419c {
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a00419c 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+dpll_core_m4x2_ck: dpll_core_m4x2_ck at 4a004138 {
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a004138 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+dll_clk_div_ck: dll_clk_div_ck {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4x2_ck>;
+	#clock-cells = <0>;
+	clock-div = <2>;
+	clock-mult = <1>;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck at 4a0041f0 {
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0041f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+/* XXX Missing round_rate, set_rate in ops */
+dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck at 4a004134 {
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a004134 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck at 4a004134 {
+	compatible = "gate-clock";
+	#clock-cells = <0>;
+	reg = <0x4a004134 0x4>;
+	bit-shift = <8>;
+	clocks = <&dpll_core_m3x2_div_ck>;
+};
+
+dpll_core_m7x2_ck: dpll_core_m7x2_ck at 4a004144 {
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a004144 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck at 4a0041ac {
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+	#clock-cells = <0>;
+	reg = <0x4a0041ac 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <23>;
+};
+
+/* DPLL_IVA */
+dpll_iva_ck: dpll_iva_ck {
+	clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+	ti,clk-bypass = <&iva_hsd_byp_clk_mux_ck>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	compatible = "ti,omap4-dpll-clock";
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+	clocks = <&dpll_iva_ck>;
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	ti,dpll-clk-x2;
+};
+
+dpll_iva_m4x2_ck: dpll_iva_m4x2_ck at 4a0041b8 {
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0041b8 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+dpll_iva_m5x2_ck: dpll_iva_m5x2_ck at 4a0041bc {
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0041bc 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+/* DPLL_MPU */
+dpll_mpu_ck: dpll_mpu_ck {
+	clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+	#clock-cells = <0>;
+	reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+	ti,clk-bypass = <&div_mpu_hs_clk>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	compatible = "ti,omap4-dpll-clock";
+};
+
+mpu_periphclk: mpu_periphclk {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_mpu_ck>;
+	#clock-cells = <0>;
+	clock-div = <2>;
+	clock-mult = <1>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a004170 {
+	compatible = "divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a004170 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+per_hs_clk_div_ck: per_hs_clk_div_ck {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	#clock-cells = <0>;
+	clock-div = <2>;
+	clock-mult = <1>;
+};
+
+per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck at 4a00814c {
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a00814c 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <23>;
+};
+
+/* DPLL_PER */
+dpll_per_ck: dpll_per_ck {
+	clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+	ti,clk-bypass = <&per_hsd_byp_clk_mux_ck>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	compatible = "ti,omap4-dpll-clock";
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+	clocks = <&dpll_per_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008150 0x4>;
+	compatible = "ti,omap4-dpll-clock";
+	ti,dpll-clk-x2;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+/* XXX Missing round_rate, set_rate in ops */
+dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck at 4a008154 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008154 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck at 4a008154 {
+	compatible = "gate-clock";
+	#clock-cells = <0>;
+	reg = <0x4a008154 0x4>;
+	bit-shift = <8>;
+	clocks = <&dpll_per_m3x2_div_ck>;
+};
+
+dpll_per_m4x2_ck: dpll_per_m4x2_ck at 4a008158 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008158 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+dpll_per_m5x2_ck: dpll_per_m5x2_ck at 4a00815c {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a00815c 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+dpll_per_m6x2_ck: dpll_per_m6x2_ck at 4a008160 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008160 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+dpll_per_m7x2_ck: dpll_per_m7x2_ck at 4a008164 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008164 0x4>;
+	bit-mask = <0x1f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	#clock-cells = <0>;
+	clock-div = <3>;
+	clock-mult = <1>;
+};
+
+/* DPLL_USB */
+dpll_usb_ck: dpll_usb_ck {
+	clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+	ti,clk-bypass = <&usb_hs_clk_div_ck>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clkdm-name = "l3_init_clkdm";
+	compatible = "ti,omap4-dpll-clock";
+	ti,dpll-j-type;
+};
+
+dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_usb_ck>;
+	#clock-cells = <0>;
+	clock-mult = <1>;
+	clock-div = <1>;
+	reg = <0x4a0081b4 0x4>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008190 0x4>;
+	bit-mask = <0x7f>;
+	ti,autoidle-shift = <8>;
+	ti,autoidle-low;
+	index-starts-at-one;
+};
+
+ducati_clk_mux_ck: ducati_clk_mux_ck at 4a008100 {
+	compatible = "mux-clock";
+	clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008100 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_12m_fclk: func_12m_fclk {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	#clock-cells = <0>;
+	clock-div = <16>;
+	clock-mult = <1>;
+};
+
+func_24m_clk: func_24m_clk {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	#clock-cells = <0>;
+	clock-div = <4>;
+	clock-mult = <1>;
+};
+
+func_24mc_fclk: func_24mc_fclk {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	#clock-cells = <0>;
+	clock-div = <8>;
+	clock-mult = <1>;
+};
+
+func_48m_fclk: func_48m_fclk at 4a008108 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008108 0x4>;
+	bit-mask = <0x1>;
+	table = < 4 0 >, < 8 1 >;
+};
+
+func_48mc_fclk: func_48mc_fclk {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	#clock-cells = <0>;
+	clock-div = <4>;
+	clock-mult = <1>;
+};
+
+func_64m_fclk: func_64m_fclk at 4a008108 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008108 0x4>;
+	bit-mask = <0x1>;
+	table = < 2 0 >, < 4 1 >;
+};
+
+func_96m_fclk: func_96m_fclk at 4a008108 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008108 0x4>;
+	bit-mask = <0x1>;
+	table = < 2 0 >, < 4 1 >;
+};
+
+init_60m_fclk: init_60m_fclk at 4a008104 {
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008104 0x4>;
+	bit-mask = <0x1>;
+	table = < 1 0 >, < 8 1 >;
+};
+
+l3_div_ck: l3_div_ck at 4a004100 {
+	compatible = "divider-clock";
+	clocks = <&div_core_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <4>;
+};
+
+l4_div_ck: l4_div_ck at 4a004100 {
+	compatible = "divider-clock";
+	clocks = <&l3_div_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <8>;
+};
+
+lp_clk_div_ck: lp_clk_div_ck {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	#clock-cells = <0>;
+	clock-div = <16>;
+	clock-mult = <1>;
+};
+
+l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck at 4a306108 {
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a306108 0x4>;
+	bit-mask = <0x1>;
+};
+
+ocp_abe_iclk: ocp_abe_iclk at 4a004528 {
+	compatible = "divider-clock";
+	clocks = <&aess_fclk>;
+	#clock-cells = <0>;
+	reg = <0x4a004528 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	table = < 2 0 >, < 1 1 >;
+};
+
+per_abe_24m_fclk: per_abe_24m_fclk {
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	#clock-cells = <0>;
+	clock-div = <4>;
+	clock-mult = <1>;
+};
+
+per_abe_nc_fclk: per_abe_nc_fclk at 4a008108 {
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a008108 0x4>;
+	bit-mask = <0x1>;
+};
+
+syc_clk_div_ck: syc_clk_div_ck at 4a306100 {
+	compatible = "divider-clock";
+	clocks = <&sys_clkin_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a306100 0x4>;
+	bit-mask = <0x1>;
+};
+
+dbgclk_mux_ck: dbgclk_mux_ck {
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	#clock-cells = <0>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+/* Leaf clocks controlled by modules */
+aes1_fck: aes1_fck at 4a0095a0 {
+	compatible = "gate-clock";
+	reg = <0x4a0095a0 0x4>;
+	bit-shift = <1>;
+	clocks = <&l3_div_ck>;
+	#clock-cells = <0>;
+};
+
+aes2_fck: aes2_fck at 4a0095a8 {
+	compatible = "gate-clock";
+	reg = <0x4a0095a8 0x4>;
+	bit-shift = <1>;
+	clocks = <&l3_div_ck>;
+	#clock-cells = <0>;
+};
+
+bandgap_fclk: bandgap_fclk at 4a307888 {
+	compatible = "gate-clock";
+	reg = <0x4a307888 0x4>;
+	bit-shift = <8>;
+	clocks = <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+div_ts_ck: div_ts_ck at 4a307888 {
+	compatible = "divider-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a307888 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <24>;
+	table = < 8 0 >, < 16 1 >, < 32 2 >;
+};
+
+bandgap_ts_fclk: bandgap_ts_fclk at 4a307888 {
+	compatible = "gate-clock";
+	reg = <0x4a307888 0x4>;
+	bit-shift = <8>;
+	clocks = <&div_ts_ck>;
+	#clock-cells = <0>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck at 4a004538 {
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	#clock-cells = <0>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <25>;
+};
+
+func_dmic_abe_gfclk: func_dmic_abe_gfclk at 4a004538 {
+	compatible = "mux-clock";
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <24>;
+	clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	#clock-cells = <0>;
+};
+
+dss_sys_clk: dss_sys_clk at 4a009120 {
+	compatible = "gate-clock";
+	reg = <0x4a009120 0x4>;
+	bit-shift = <10>;
+	clocks = <&syc_clk_div_ck>;
+	#clock-cells = <0>;
+};
+
+dss_tv_clk: dss_tv_clk at 4a009120 {
+	compatible = "gate-clock";
+	reg = <0x4a009120 0x4>;
+	bit-shift = <11>;
+	clocks = <&extalt_clkin_ck>;
+	#clock-cells = <0>;
+};
+
+dss_dss_clk: dss_dss_clk at 4a009120 {
+	compatible = "gate-clock";
+	reg = <0x4a009120 0x4>;
+	bit-shift = <8>;
+	clocks = <&dpll_per_m5x2_ck>;
+	#clock-cells = <0>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk at 4a009120 {
+	compatible = "gate-clock";
+	reg = <0x4a009120 0x4>;
+	bit-shift = <9>;
+	clocks = <&func_48mc_fclk>;
+	#clock-cells = <0>;
+};
+
+dss_fck: dss_fck at 4a009120 {
+	compatible = "gate-clock";
+	reg = <0x4a009120 0x4>;
+	bit-shift = <1>;
+	clocks = <&l3_div_ck>;
+	#clock-cells = <0>;
+};
+
+fdif_fck: fdif_fck at 4a009028 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a009028 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <24>;
+	index-power-of-two;
+};
+
+gpio1_dbclk: gpio1_dbclk at 4a307838 {
+	compatible = "gate-clock";
+	reg = <0x4a307838 0x4>;
+	bit-shift = <8>;
+	clocks = <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 4a009460 {
+	compatible = "gate-clock";
+	reg = <0x4a009460 0x4>;
+	bit-shift = <8>;
+	clocks = <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 4a009468 {
+	compatible = "gate-clock";
+	reg = <0x4a009468 0x4>;
+	bit-shift = <8>;
+	clocks = <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 4a009470 {
+	compatible = "gate-clock";
+	reg = <0x4a009470 0x4>;
+	bit-shift = <8>;
+	clocks = <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 4a009478 {
+	compatible = "gate-clock";
+	reg = <0x4a009478 0x4>;
+	bit-shift = <8>;
+	clocks = <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+gpio6_dbclk: gpio6_dbclk at 4a009480 {
+	compatible = "gate-clock";
+	reg = <0x4a009480 0x4>;
+	bit-shift = <8>;
+	clocks = <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+sgx_clk_mux: sgx_clk_mux at 4a009220 {
+	compatible = "mux-clock";
+	reg = <0x4a009220 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+	#clock-cells = <0>;
+};
+
+hsi_fck: hsi_fck at 4a009338 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a009338 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <24>;
+	index-power-of-two;
+};
+
+iss_ctrlclk: iss_ctrlclk at 4a009020 {
+	compatible = "gate-clock";
+	reg = <0x4a009020 0x4>;
+	bit-shift = <8>;
+	clocks = <&func_96m_fclk>;
+	#clock-cells = <0>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck at 4a004540 {
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	#clock-cells = <0>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <25>;
+};
+
+func_mcasp_abe_gfclk: func_mcasp_abe_gfclk at 4a004540 {
+	compatible = "mux-clock";
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <24>;
+	clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	#clock-cells = <0>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck at 4a004548 {
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	#clock-cells = <0>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <25>;
+};
+
+func_mcbsp1_gfclk: func_mcbsp1_gfclk at 4a004548 {
+	compatible = "mux-clock";
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <24>;
+	clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	#clock-cells = <0>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 4a004550 {
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	#clock-cells = <0>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <25>;
+};
+
+func_mcbsp2_gfclk: func_mcbsp2_gfclk at 4a004550 {
+	compatible = "mux-clock";
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <24>;
+	clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	#clock-cells = <0>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 4a004558 {
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	#clock-cells = <0>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <25>;
+};
+
+func_mcbsp3_gfclk: func_mcbsp3_gfclk at 4a004558 {
+	compatible = "mux-clock";
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <24>;
+	clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	#clock-cells = <0>;
+};
+
+mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck at 4a0094e0 {
+	compatible = "mux-clock";
+	clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+	#clock-cells = <0>;
+	reg = <0x4a0094e0 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <25>;
+};
+
+per_mcbsp4_gfclk: per_mcbsp4_gfclk at 4a0094e0 {
+	compatible = "mux-clock";
+	reg = <0x4a0094e0 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+	#clock-cells = <0>;
+};
+
+hsmmc1_fclk: hsmmc1_fclk at 4a009328 {
+	compatible = "mux-clock";
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+	#clock-cells = <0>;
+};
+
+hsmmc2_fclk: hsmmc2_fclk at 4a009330 {
+	compatible = "mux-clock";
+	reg = <0x4a009330 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+	#clock-cells = <0>;
+};
+
+ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m at 4a0093e0 {
+	compatible = "gate-clock";
+	reg = <0x4a0093e0 0x4>;
+	bit-shift = <8>;
+	clocks = <&func_48m_fclk>;
+	#clock-cells = <0>;
+};
+
+sha2md5_fck: sha2md5_fck at 4a0095c8 {
+	compatible = "gate-clock";
+	reg = <0x4a0095c8 0x4>;
+	bit-shift = <1>;
+	clocks = <&l3_div_ck>;
+	#clock-cells = <0>;
+};
+
+slimbus1_fclk_1: slimbus1_fclk_1 at 4a004560 {
+	compatible = "gate-clock";
+	reg = <0x4a004560 0x4>;
+	bit-shift = <9>;
+	clocks = <&func_24m_clk>;
+	#clock-cells = <0>;
+};
+
+slimbus1_fclk_0: slimbus1_fclk_0 at 4a004560 {
+	compatible = "gate-clock";
+	reg = <0x4a004560 0x4>;
+	bit-shift = <8>;
+	clocks = <&abe_24m_fclk>;
+	#clock-cells = <0>;
+};
+
+slimbus1_fclk_2: slimbus1_fclk_2 at 4a004560 {
+	compatible = "gate-clock";
+	reg = <0x4a004560 0x4>;
+	bit-shift = <10>;
+	clocks = <&pad_clks_ck>;
+	#clock-cells = <0>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk at 4a004560 {
+	compatible = "gate-clock";
+	reg = <0x4a004560 0x4>;
+	bit-shift = <11>;
+	clocks = <&slimbus_clk>;
+	#clock-cells = <0>;
+};
+
+slimbus2_fclk_1: slimbus2_fclk_1 at 4a009538 {
+	compatible = "gate-clock";
+	reg = <0x4a009538 0x4>;
+	bit-shift = <9>;
+	clocks = <&per_abe_24m_fclk>;
+	#clock-cells = <0>;
+};
+
+slimbus2_fclk_0: slimbus2_fclk_0 at 4a009538 {
+	compatible = "gate-clock";
+	reg = <0x4a009538 0x4>;
+	bit-shift = <8>;
+	clocks = <&func_24mc_fclk>;
+	#clock-cells = <0>;
+};
+
+slimbus2_slimbus_clk: slimbus2_slimbus_clk at 4a009538 {
+	compatible = "gate-clock";
+	reg = <0x4a009538 0x4>;
+	bit-shift = <10>;
+	clocks = <&pad_slimbus_core_clks_ck>;
+	#clock-cells = <0>;
+};
+
+smartreflex_core_fck: smartreflex_core_fck at 4a008638 {
+	compatible = "gate-clock";
+	reg = <0x4a008638 0x4>;
+	bit-shift = <1>;
+	clocks = <&l4_wkup_clk_mux_ck>;
+	#clock-cells = <0>;
+};
+
+smartreflex_iva_fck: smartreflex_iva_fck at 4a008630 {
+	compatible = "gate-clock";
+	reg = <0x4a008630 0x4>;
+	bit-shift = <1>;
+	clocks = <&l4_wkup_clk_mux_ck>;
+	#clock-cells = <0>;
+};
+
+smartreflex_mpu_fck: smartreflex_mpu_fck at 4a008628 {
+	compatible = "gate-clock";
+	reg = <0x4a008628 0x4>;
+	bit-shift = <1>;
+	clocks = <&l4_wkup_clk_mux_ck>;
+	#clock-cells = <0>;
+};
+
+dmt1_clk_mux: dmt1_clk_mux at 4a307840 {
+	compatible = "mux-clock";
+	reg = <0x4a307840 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+cm2_dm10_mux: cm2_dm10_mux at 4a009428 {
+	compatible = "mux-clock";
+	reg = <0x4a009428 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+cm2_dm11_mux: cm2_dm11_mux at 4a009430 {
+	compatible = "mux-clock";
+	reg = <0x4a009430 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+cm2_dm2_mux: cm2_dm2_mux at 4a009438 {
+	compatible = "mux-clock";
+	reg = <0x4a009438 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+cm2_dm3_mux: cm2_dm3_mux at 4a009440 {
+	compatible = "mux-clock";
+	reg = <0x4a009440 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+cm2_dm4_mux: cm2_dm4_mux at 4a009448 {
+	compatible = "mux-clock";
+	reg = <0x4a009448 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+timer5_sync_mux: timer5_sync_mux at 4a004568 {
+	compatible = "mux-clock";
+	reg = <0x4a004568 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+timer6_sync_mux: timer6_sync_mux at 4a004570 {
+	compatible = "mux-clock";
+	reg = <0x4a004570 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+timer7_sync_mux: timer7_sync_mux at 4a004578 {
+	compatible = "mux-clock";
+	reg = <0x4a004578 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+timer8_sync_mux: timer8_sync_mux at 4a004580 {
+	compatible = "mux-clock";
+	reg = <0x4a004580 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+cm2_dm9_mux: cm2_dm9_mux at 4a009450 {
+	compatible = "mux-clock";
+	reg = <0x4a009450 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+usb_host_fs_fck: usb_host_fs_fck {
+	clocks = <&func_48mc_fclk>;
+	#clock-cells = <0>;
+	bit-shift = <1>;
+	reg = <0x4a0093d0 0x4>;
+	compatible = "gate-clock";
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk at 4a009358 {
+	compatible = "mux-clock";
+	clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a009358 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk at 4a009358 {
+	compatible = "gate-clock";
+	reg = <0x4a009358 0x4>;
+	bit-shift = <8>;
+	clocks = <&utmi_p1_gfclk>;
+	#clock-cells = <0>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk at 4a009358 {
+	compatible = "mux-clock";
+	clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a009358 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <25>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk at 4a009358 {
+	compatible = "gate-clock";
+	reg = <0x4a009358 0x4>;
+	bit-shift = <9>;
+	clocks = <&utmi_p2_gfclk>;
+	#clock-cells = <0>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk at 4a009358 {
+	compatible = "gate-clock";
+	reg = <0x4a009358 0x4>;
+	bit-shift = <10>;
+	clocks = <&init_60m_fclk>;
+	#clock-cells = <0>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 4a009358 {
+	compatible = "gate-clock";
+	reg = <0x4a009358 0x4>;
+	bit-shift = <13>;
+	clocks = <&dpll_usb_m2_ck>;
+	#clock-cells = <0>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk at 4a009358 {
+	compatible = "gate-clock";
+	reg = <0x4a009358 0x4>;
+	bit-shift = <11>;
+	clocks = <&init_60m_fclk>;
+	#clock-cells = <0>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk at 4a009358 {
+	compatible = "gate-clock";
+	reg = <0x4a009358 0x4>;
+	bit-shift = <12>;
+	clocks = <&init_60m_fclk>;
+	#clock-cells = <0>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk at 4a009358 {
+	compatible = "gate-clock";
+	reg = <0x4a009358 0x4>;
+	bit-shift = <14>;
+	clocks = <&dpll_usb_m2_ck>;
+	#clock-cells = <0>;
+};
+
+usb_host_hs_func48mclk: usb_host_hs_func48mclk at 4a009358 {
+	compatible = "gate-clock";
+	reg = <0x4a009358 0x4>;
+	bit-shift = <15>;
+	clocks = <&func_48mc_fclk>;
+	#clock-cells = <0>;
+};
+
+usb_host_hs_fck: usb_host_hs_fck at 4a009358 {
+	compatible = "gate-clock";
+	reg = <0x4a009358 0x4>;
+	bit-shift = <1>;
+	clocks = <&init_60m_fclk>;
+	#clock-cells = <0>;
+};
+
+otg_60m_gfclk: otg_60m_gfclk at 4a009360 {
+	compatible = "mux-clock";
+	clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a009360 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+};
+
+usb_otg_hs_xclk: usb_otg_hs_xclk at 4a009360 {
+	compatible = "gate-clock";
+	reg = <0x4a009360 0x4>;
+	bit-shift = <8>;
+	clocks = <&otg_60m_gfclk>;
+	#clock-cells = <0>;
+};
+
+usb_otg_hs_ick: usb_otg_hs_ick at 4a009360 {
+	compatible = "gate-clock";
+	reg = <0x4a009360 0x4>;
+	bit-shift = <0>;
+	clocks = <&l3_div_ck>;
+	#clock-cells = <0>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k at 4a008640 {
+	compatible = "gate-clock";
+	reg = <0x4a008640 0x4>;
+	bit-shift = <8>;
+	clocks = <&sys_32k_ck>;
+	#clock-cells = <0>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 4a009368 {
+	compatible = "gate-clock";
+	reg = <0x4a009368 0x4>;
+	bit-shift = <10>;
+	clocks = <&init_60m_fclk>;
+	#clock-cells = <0>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 4a009368 {
+	compatible = "gate-clock";
+	reg = <0x4a009368 0x4>;
+	bit-shift = <8>;
+	clocks = <&init_60m_fclk>;
+	#clock-cells = <0>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 4a009368 {
+	compatible = "gate-clock";
+	reg = <0x4a009368 0x4>;
+	bit-shift = <9>;
+	clocks = <&init_60m_fclk>;
+	#clock-cells = <0>;
+};
+
+usb_tll_hs_ick: usb_tll_hs_ick at 4a009368 {
+	compatible = "gate-clock";
+	reg = <0x4a009368 0x4>;
+	bit-shift = <0>;
+	clocks = <&l4_div_ck>;
+	#clock-cells = <0>;
+};
+
+usim_ck: usim_ck at 4a307858 {
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a307858 0x4>;
+	bit-mask = <0x1>;
+	bit-shift = <24>;
+	table = < 14 0 >, < 18 1 >;
+};
+
+usim_fclk: usim_fclk at 4a307858 {
+	compatible = "gate-clock";
+	reg = <0x4a307858 0x4>;
+	bit-shift = <8>;
+	clocks = <&usim_ck>;
+	#clock-cells = <0>;
+};
+
+/* Remaining optional clocks */
+pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck at 4a307a20 {
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <20>;
+};
+
+pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck at 4a307a20 {
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <22>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck at 4a307a20 {
+	compatible = "divider-clock";
+	clocks = <&pmd_stm_clock_mux_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x7>;
+	bit-shift = <27>;
+	index-power-of-two;
+};
+
+trace_clk_div_div_ck: trace_clk_div_div_ck at 4a307a20 {
+	compatible = "divider-clock";
+	clocks = <&pmd_trace_clk_mux_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x7>;
+	bit-shift = <24>;
+	index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck {
+	clocks = <&trace_clk_div_div_ck>;
+	#clock-cells = <0>;
+	ti,clkdm-name = "emu_sys_clkdm";
+	compatible = "ti,gate-clock";
+};
+
+/* SCRM aux clk nodes */
+auxclk0_src_mux_ck: auxclk0_src_mux_ck at 4a30a310 {
+	compatible = "mux-clock";
+	reg = <0x4a30a310 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <1>;
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	#clock-cells = <0>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck at 4a30a310 {
+	compatible = "gate-clock";
+	#clock-cells = <0>;
+	reg = <0x4a30a310 0x4>;
+	bit-shift = <8>;
+	clocks = <&auxclk0_src_mux_ck>;
+};
+
+auxclk0_ck: auxclk0_ck at 4a30a310 {
+	compatible = "divider-clock";
+	clocks = <&auxclk0_src_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a310 0x4>;
+	bit-mask = <0xf>;
+	bit-shift = <16>;
+};
+
+auxclk1_src_mux_ck: auxclk1_src_mux_ck at 4a30a314 {
+	compatible = "mux-clock";
+	reg = <0x4a30a314 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <1>;
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	#clock-cells = <0>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck at 4a30a314 {
+	compatible = "gate-clock";
+	#clock-cells = <0>;
+	reg = <0x4a30a314 0x4>;
+	bit-shift = <8>;
+	clocks = <&auxclk1_src_mux_ck>;
+};
+
+auxclk1_ck: auxclk1_ck at 4a30a314 {
+	compatible = "divider-clock";
+	clocks = <&auxclk1_src_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a314 0x4>;
+	bit-mask = <0xf>;
+	bit-shift = <16>;
+};
+
+auxclk2_src_mux_ck: auxclk2_src_mux_ck at 4a30a318 {
+	compatible = "mux-clock";
+	reg = <0x4a30a318 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <1>;
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	#clock-cells = <0>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck at 4a30a318 {
+	compatible = "gate-clock";
+	#clock-cells = <0>;
+	reg = <0x4a30a318 0x4>;
+	bit-shift = <8>;
+	clocks = <&auxclk2_src_mux_ck>;
+};
+
+auxclk2_ck: auxclk2_ck at 4a30a318 {
+	compatible = "divider-clock";
+	clocks = <&auxclk2_src_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a318 0x4>;
+	bit-mask = <0xf>;
+	bit-shift = <16>;
+};
+
+auxclk3_src_mux_ck: auxclk3_src_mux_ck at 4a30a31c {
+	compatible = "mux-clock";
+	reg = <0x4a30a31c 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <1>;
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	#clock-cells = <0>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck at 4a30a31c {
+	compatible = "gate-clock";
+	#clock-cells = <0>;
+	reg = <0x4a30a31c 0x4>;
+	bit-shift = <8>;
+	clocks = <&auxclk3_src_mux_ck>;
+};
+
+auxclk3_ck: auxclk3_ck at 4a30a31c {
+	compatible = "divider-clock";
+	clocks = <&auxclk3_src_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a31c 0x4>;
+	bit-mask = <0xf>;
+	bit-shift = <16>;
+};
+
+auxclk4_src_mux_ck: auxclk4_src_mux_ck at 4a30a320 {
+	compatible = "mux-clock";
+	reg = <0x4a30a320 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <1>;
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	#clock-cells = <0>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck at 4a30a320 {
+	compatible = "gate-clock";
+	#clock-cells = <0>;
+	reg = <0x4a30a320 0x4>;
+	bit-shift = <8>;
+	clocks = <&auxclk4_src_mux_ck>;
+};
+
+auxclk4_ck: auxclk4_ck at 4a30a320 {
+	compatible = "divider-clock";
+	clocks = <&auxclk4_src_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a320 0x4>;
+	bit-mask = <0xf>;
+	bit-shift = <16>;
+};
+
+auxclk5_src_mux_ck: auxclk5_src_mux_ck at 4a30a324 {
+	compatible = "mux-clock";
+	reg = <0x4a30a324 0x4>;
+	bit-mask = <0x3>;
+	bit-shift = <1>;
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	#clock-cells = <0>;
+};
+
+auxclk5_src_ck: auxclk5_src_ck at 4a30a324 {
+	compatible = "gate-clock";
+	#clock-cells = <0>;
+	reg = <0x4a30a324 0x4>;
+	bit-shift = <8>;
+	clocks = <&auxclk5_src_mux_ck>;
+};
+
+auxclk5_ck: auxclk5_ck at 4a30a324 {
+	compatible = "divider-clock";
+	clocks = <&auxclk5_src_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a324 0x4>;
+	bit-mask = <0xf>;
+	bit-shift = <16>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck at 4a30a210 {
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a210 0x4>;
+	bit-mask = <0x7>;
+	bit-shift = <2>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck at 4a30a214 {
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a214 0x4>;
+	bit-mask = <0x7>;
+	bit-shift = <2>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck at 4a30a218 {
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a218 0x4>;
+	bit-mask = <0x7>;
+	bit-shift = <2>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck at 4a30a21c {
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a21c 0x4>;
+	bit-mask = <0x7>;
+	bit-shift = <2>;
+};
+
+auxclkreq4_ck: auxclkreq4_ck at 4a30a220 {
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a220 0x4>;
+	bit-mask = <0x7>;
+	bit-shift = <2>;
+};
+
+auxclkreq5_ck: auxclkreq5_ck at 4a30a224 {
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a30a224 0x4>;
+	bit-mask = <0x7>;
+	bit-shift = <2>;
+};
+
+/*
+ * clocks specific to omap4460
+ */
+/*
+ * clocks specific to omap4430
+ */
+/*
+ * clocks common to omap44xx
+ */
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a56428..70608db 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -106,6 +106,8 @@
 			ti,hwmods = "counter_32k";
 		};
 
+		/include/ "omap4-clocks.dtsi"
+
 		omap4_pmx_core: pinmux at 4a100040 {
 			compatible = "ti,omap4-padconf", "pinctrl-single";
 			reg = <0x4a100040 0x0196>;
-- 
1.7.9.5

[PATCHv2 10/11] ARM: dts: omap4 clock data

[Nishanth Menon]

On 16:19-20130619, Tero Kristo wrote:
<snip>
> diff --git a/arch/arm/boot/dts/omap4-clocks.dtsi b/arch/arm/boot/dts/omap4-clocks.dtsi
> new file mode 100644
> index 0000000..b420d8a
> --- /dev/null
> +++ b/arch/arm/boot/dts/omap4-clocks.dtsi
[...]
> +/* XXX Missing round_rate, set_rate in ops */
could be dropped?
> +dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck at 4a004134 {
> +	compatible = "divider-clock";
> +	clocks = <&dpll_core_x2_ck>;
> +	#clock-cells = <0>;
> +	reg = <0x4a004134 0x4>;
> +	bit-mask = <0x1f>;
> +	index-starts-at-one;
> +};
[..]
> +
> +/* XXX Missing round_rate, set_rate in ops */
could be dropped?
> +dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck at 4a008154 {
> +	compatible = "divider-clock";
> +	clocks = <&dpll_per_x2_ck>;
> +	#clock-cells = <0>;
> +	reg = <0x4a008154 0x4>;
> +	bit-mask = <0x1f>;
> +	index-starts-at-one;
> +};
> +
[...]
> +
> +/*
> + * clocks specific to omap4460
> + */
> +/*
> + * clocks specific to omap4430
> + */
> +/*
> + * clocks common to omap44xx
> + */
could be dropped?

btw, are we differentiating 4430 and 4460?A
Example:
bandgap_fclk in 4430
Vs
div_ts_ck, bandgap_ts_fclk in 4460?


-- 
Regards,
Nishanth Menon

[PATCHv2 10/11] ARM: dts: omap4 clock data

[Tero Kristo]

On 06/19/2013 04:30 PM, Nishanth Menon wrote:
> On 16:19-20130619, Tero Kristo wrote:
> <snip>
>> diff --git a/arch/arm/boot/dts/omap4-clocks.dtsi b/arch/arm/boot/dts/omap4-clocks.dtsi
>> new file mode 100644
>> index 0000000..b420d8a
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/omap4-clocks.dtsi
> [...]
>> +/* XXX Missing round_rate, set_rate in ops */
> could be dropped?
>> +dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck at 4a004134 {
>> +	compatible = "divider-clock";
>> +	clocks = <&dpll_core_x2_ck>;
>> +	#clock-cells = <0>;
>> +	reg = <0x4a004134 0x4>;
>> +	bit-mask = <0x1f>;
>> +	index-starts-at-one;
>> +};
> [..]
>> +
>> +/* XXX Missing round_rate, set_rate in ops */
> could be dropped?

Yeah, I blame my bugged script here. :)

>> +dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck at 4a008154 {
>> +	compatible = "divider-clock";
>> +	clocks = <&dpll_per_x2_ck>;
>> +	#clock-cells = <0>;
>> +	reg = <0x4a008154 0x4>;
>> +	bit-mask = <0x1f>;
>> +	index-starts-at-one;
>> +};
>> +
> [...]
>> +
>> +/*
>> + * clocks specific to omap4460
>> + */
>> +/*
>> + * clocks specific to omap4430
>> + */
>> +/*
>> + * clocks common to omap44xx
>> + */
> could be dropped?

Same.

>
> btw, are we differentiating 4430 and 4460?A
> Example:
> bandgap_fclk in 4430
> Vs
> div_ts_ck, bandgap_ts_fclk in 4460?

Both nodes are available for both SoCs as of now. Driver should 
differentiate which clock node to use though. Added Eduardo for 
commenting this part, maybe we should add a couple of entries to the 
list in cclock44xx_data.c...?

-Tero

[PATCHv2 10/11] ARM: dts: omap4 clock data

[Nishanth Menon]

On 16:49-20130619, Tero Kristo wrote:
> On 06/19/2013 04:30 PM, Nishanth Menon wrote:
> >On 16:19-20130619, Tero Kristo wrote:
> >[...]
> >>+
> >>+/*
> >>+ * clocks specific to omap4460
> >>+ */
> >>+/*
> >>+ * clocks specific to omap4430
> >>+ */
> >>+/*
> >>+ * clocks common to omap44xx
> >>+ */
> >could be dropped?
> 
> Same.
> 
> >
> >btw, are we differentiating 4430 and 4460?A
> >Example:
> >bandgap_fclk in 4430
> >Vs
> >div_ts_ck, bandgap_ts_fclk in 4460?
> 
> Both nodes are available for both SoCs as of now. Driver should
> differentiate which clock node to use though. Added Eduardo for
> commenting this part, maybe we should add a couple of entries to the
> list in cclock44xx_data.c...?
How about this:
we do have 443x.dtsi and 4460.dtsi -> add the corresponding clock nodes
there?

ideally, driver should just do devm_clk_get and should not worry about
what SoC revision it is running on.

-- 
Regards,
Nishanth Menon

[PATCHv2 10/11] ARM: dts: omap4 clock data

[Stephen Boyd]

On 06/19/13 06:19, Tero Kristo wrote:
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 2a56428..70608db 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -106,6 +106,8 @@
>  			ti,hwmods = "counter_32k";
>  		};
>  
> +		/include/ "omap4-clocks.dtsi"
> +

Doesn't this cause one platform device to be allocated for each clock
node defined in omap4-clocks.dtsi? Are you concerned about wasting
memory on things that aren't really devices and that will never be probed?

>  		omap4_pmx_core: pinmux at 4a100040 {
>  			compatible = "ti,omap4-padconf", "pinctrl-single";
>  			reg = <0x4a100040 0x0196>;

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

[PATCHv2 10/11] ARM: dts: omap4 clock data

[Tero Kristo]

On 06/21/2013 04:24 AM, Stephen Boyd wrote:
> On 06/19/13 06:19, Tero Kristo wrote:
>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> index 2a56428..70608db 100644
>> --- a/arch/arm/boot/dts/omap4.dtsi
>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> @@ -106,6 +106,8 @@
>>   			ti,hwmods = "counter_32k";
>>   		};
>>
>> +		/include/ "omap4-clocks.dtsi"
>> +
>
> Doesn't this cause one platform device to be allocated for each clock
> node defined in omap4-clocks.dtsi? Are you concerned about wasting
> memory on things that aren't really devices and that will never be probed?

Hi Stephen,

Sounds like a valid point to me, so should this include just go under 
the root in omap4.dtsi? I am not quite familiar with DT specifics myself 
as of yet.

-Tero

>
>>   		omap4_pmx_core: pinmux at 4a100040 {
>>   			compatible = "ti,omap4-padconf", "pinctrl-single";
>>   			reg = <0x4a100040 0x0196>;
>

[PATCHv2 11/11] ARM: OMAP4: register DT clocks and remove old data

[Tero Kristo]

Now that the OMAP4 PRCM clock data has been converted to device tree
representation, it is no longer needed as static clock data. OMAP4
clock init routine is also changed to register DT clocks first.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/cclock44xx_data.c | 1674 +--------------------------------
 1 file changed, 38 insertions(+), 1636 deletions(-)

diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 88e37a4..fdb63c5 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -27,6 +27,7 @@
 #include <linux/clk-private.h>
 #include <linux/clkdev.h>
 #include <linux/io.h>
+#include <linux/clk/omap.h>
 
 #include "soc.h"
 #include "iomap.h"
@@ -59,1650 +60,47 @@
  */
 #define OMAP4_DPLL_USB_DEFFREQ				960000000
 
-/* Root clocks */
-
-DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
-		OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
-		OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
-
-static const char *sys_clkin_ck_parents[] = {
-	"virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
-	"virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
-	"virt_38400000_ck",
-};
-
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
-	       OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-
-DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
-
-DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
-	       NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
-	       OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-/* DPLL_ABE */
-static struct dpll_data dpll_abe_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_ABE,
-	.clk_bypass	= &abe_dpll_bypass_clk_mux_ck,
-	.clk_ref	= &abe_dpll_refclk_mux_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_ABE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_ABE,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_ABE,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.m4xen_mask	= OMAP4430_DPLL_REGM4XEN_MASK,
-	.lpmode_mask	= OMAP4430_DPLL_LPMODE_EN_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-
-static const char *dpll_abe_ck_parents[] = {
-	"abe_dpll_refclk_mux_ck",
-};
-
-static struct clk dpll_abe_ck;
-
-static const struct clk_ops dpll_abe_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
-	.round_rate	= &omap4_dpll_regm4xen_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_abe_ck_hw = {
-	.hw = {
-		.clk = &dpll_abe_ck,
-	},
-	.dpll_data	= &dpll_abe_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
-
-static const char *dpll_abe_x2_ck_parents[] = {
-	"dpll_abe_ck",
-};
-
-static struct clk dpll_abe_x2_ck;
-
-static const struct clk_ops dpll_abe_x2_ck_ops = {
-	.recalc_rate	= &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_abe_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_abe_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-static const struct clk_ops omap_hsdivider_ops = {
-	.set_rate	= &omap2_clksel_set_rate,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-};
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-			0x0, 1, 8);
-
-DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
-		   OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
-		   OMAP4430_CM1_ABE_AESS_CLKCTRL,
-		   OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-		   OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
-			  OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
-
-static const char *core_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "dpll_abe_m3x2_ck",
-};
-
-DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
-	       OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
-	       0x0, NULL);
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_CORE,
-	.clk_bypass	= &core_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_CORE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_CORE,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_CORE,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-
-static const char *dpll_core_ck_parents[] = {
-	"sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-	.hw = {
-		.clk = &dpll_core_ck,
-	},
-	.dpll_data	= &dpll_core_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-	"dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_core_x2_ck,
-	},
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_CORE,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
-			2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
-		   OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-		   0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
-		   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-		   0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
-		   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
-			0x0, 1, 2);
-
-DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
-		   OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-		   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const struct clk_ops dpll_hsd_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static const struct clk_ops func_dmic_abe_gfclk_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-};
-
-static const char *dpll_core_m3x2_ck_parents[] = {
-	"dpll_core_x2_ck",
-};
-
-static const struct clksel dpll_core_m3x2_div[] = {
-	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
-			 OMAP4430_CM_DIV_M3_DPLL_CORE,
-			 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-			 OMAP4430_CM_DIV_M3_DPLL_CORE,
-			 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-			 dpll_core_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "div_iva_hs_clk",
-};
-
-DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-	       OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_IVA */
-static struct dpll_data dpll_iva_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_IVA,
-	.clk_bypass	= &iva_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_IVA,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_IVA,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_IVA,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_iva_ck_parents[] = {
-	"sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_iva_ck;
-
-static const struct clk_ops dpll_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_iva_ck_hw = {
-	.hw = {
-		.clk = &dpll_iva_ck,
-	},
-	.dpll_data	= &dpll_iva_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
-
-static const char *dpll_iva_x2_ck_parents[] = {
-	"dpll_iva_ck",
-};
-
-static struct clk dpll_iva_x2_ck;
-
-static struct clk_hw_omap dpll_iva_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_iva_x2_ck,
-	},
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_MPU,
-	.clk_bypass	= &div_mpu_hs_clk,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_MPU,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_MPU,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_MPU,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_mpu_ck_parents[] = {
-	"sys_clkin_ck", "div_mpu_hs_clk"
-};
-
-static struct clk dpll_mpu_ck;
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-	.hw = {
-		.clk = &dpll_mpu_ck,
-	},
-	.dpll_data	= &dpll_mpu_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_MPU,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-			&dpll_abe_m3x2_ck, 0x0, 1, 2);
-
-static const char *per_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "per_hs_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-	       OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_PER,
-	.clk_bypass	= &per_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_PER,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_PER,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_PER,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_per_ck_parents[] = {
-	"sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-	.hw = {
-		.clk = &dpll_per_ck,
-	},
-	.dpll_data	= &dpll_per_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		   OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-		   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const char *dpll_per_x2_ck_parents[] = {
-	"dpll_per_ck",
-};
-
-static struct clk dpll_per_x2_ck;
-
-static struct clk_hw_omap dpll_per_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_per_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-static const char *dpll_per_m3x2_ck_parents[] = {
-	"dpll_per_x2_ck",
-};
-
-static const struct clksel dpll_per_m3x2_div[] = {
-	{ .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
-			 OMAP4430_CM_DIV_M3_DPLL_PER,
-			 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-			 OMAP4430_CM_DIV_M3_DPLL_PER,
-			 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-			 dpll_per_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-			&dpll_abe_m3x2_ck, 0x0, 1, 3);
-
-/* DPLL_USB */
-static struct dpll_data dpll_usb_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_USB,
-	.clk_bypass	= &usb_hs_clk_div_ck,
-	.flags		= DPLL_J_TYPE,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_USB,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_USB,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_USB,
-	.mult_mask	= OMAP4430_DPLL_MULT_USB_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_0_7_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.sddiv_mask	= OMAP4430_DPLL_SD_DIV_MASK,
-	.max_multiplier	= 4095,
-	.max_divider	= 256,
-	.min_divider	= 1,
-};
-
-static const char *dpll_usb_ck_parents[] = {
-	"sys_clkin_ck", "usb_hs_clk_div_ck"
-};
-
-static struct clk dpll_usb_ck;
-
-static const struct clk_ops dpll_usb_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap dpll_usb_ck_hw = {
-	.hw = {
-		.clk = &dpll_usb_ck,
-	},
-	.dpll_data	= &dpll_usb_dd,
-	.clkdm_name	= "l3_init_clkdm",
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
-
-static const char *dpll_usb_clkdcoldo_ck_parents[] = {
-	"dpll_usb_ck",
-};
-
-static struct clk dpll_usb_clkdcoldo_ck;
-
-static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
-};
-
-static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
-	.hw = {
-		.clk = &dpll_usb_clkdcoldo_ck,
-	},
-	.clksel_reg	= OMAP4430_CM_CLKDCOLDO_DPLL_USB,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
-		  dpll_usb_clkdcoldo_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_USB,
-			  OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
-
-static const char *ducati_clk_mux_ck_parents[] = {
-	"div_core_ck", "dpll_per_m6x2_ck",
-};
-
-DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 16);
-
-DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
-			1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 8);
-
-static const struct clk_div_table func_48m_fclk_rates[] = {
-	{ .div = 4, .val = 0 },
-	{ .div = 8, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
-			 NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk,	"dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 4);
-
-static const struct clk_div_table func_64m_fclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 4, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
-			 NULL);
-
-static const struct clk_div_table func_96m_fclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 4, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
-			 NULL);
-
-static const struct clk_div_table init_60m_fclk_rates[] = {
-	{ .div = 1, .val = 0 },
-	{ .div = 8, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
-			 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
-			 OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
-			 0x0, init_60m_fclk_rates, NULL);
-
-DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
-		   OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
-		   OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-			0x0, 1, 16);
-
-static const char *l4_wkup_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "lp_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const struct clk_div_table ocp_abe_iclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 1, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
-			 OMAP4430_CM1_ABE_AESS_CLKCTRL,
-			 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-			 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-			 0x0, ocp_abe_iclk_rates, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
-			0x0, 1, 4);
-
-DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
-		   OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-		   OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-		   OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-		   OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const char *dbgclk_mux_ck_parents[] = {
-	"sys_clkin_ck"
-};
-
-static struct clk dbgclk_mux_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
-DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
-		  dpll_usb_clkdcoldo_ck_ops);
-
-/* Leaf clocks controlled by modules */
-
-DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_AES1_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_AES2_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-		OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table div_ts_ck_rates[] = {
-	{ .div = 8, .val = 0 },
-	{ .div = 16, .val = 1 },
-	{ .div = 32, .val = 2 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-			 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-			 OMAP4430_CLKSEL_24_25_SHIFT,
-			 OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
-			 NULL);
-
-DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
-		OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-		OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
-		0x0, NULL);
-
-static const char *dmic_sync_mux_ck_parents[] = {
-	"abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
-};
-
-DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
-	{ .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_dmic_abe_gfclk_parents[] = {
-	"dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
-		    OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-		    func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-		   OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
-		   OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-		OMAP4430_OPTFCLKEN_DBCLK_SHIFT,	0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-		OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-static const struct clksel sgx_clk_mux_sel[] = {
-	{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *sgx_clk_mux_parents[] = {
-	"dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
-		    OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
-		    sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
-		   OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
-		   OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
-		OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
-	{ .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcasp_abe_gfclk_parents[] = {
-	"mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-		    func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
-	{ .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp1_gfclk_parents[] = {
-	"mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
-	{ .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp2_gfclk_parents[] = {
-	"mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
-	{ .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp3_gfclk_parents[] = {
-	"mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const char *mcbsp4_sync_mux_ck_parents[] = {
-	"func_96m_fclk", "per_abe_nc_fclk",
-};
-
-DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
-	{ .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *per_mcbsp4_gfclk_parents[] = {
-	"mcbsp4_sync_mux_ck", "pad_clks_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
-		    OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const struct clksel hsmmc1_fclk_sel[] = {
-	{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
-	{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *hsmmc1_fclk_parents[] = {
-	"func_64m_fclk", "func_96m_fclk",
-};
-
-DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-		    OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-		    OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
-		&pad_slimbus_core_clks_ck, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clksel dmt1_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const struct clksel timer5_sync_mux_sel[] = {
-	{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer5_sync_mux_parents[] = {
-	"syc_clk_div_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static struct clk usb_host_fs_fck;
-
-static const char *usb_host_fs_fck_parent_names[] = {
-	"func_48mc_fclk",
-};
-
-static const struct clk_ops usb_host_fs_fck_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-};
-
-static struct clk_hw_omap usb_host_fs_fck_hw = {
-	.hw = {
-		.clk = &usb_host_fs_fck,
-	},
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-};
-
-DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
-		  usb_host_fs_fck_ops);
-
-static const char *utmi_p1_gfclk_parents[] = {
-	"init_60m_fclk", "xclk60mhsp1_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	       OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
-
-static const char *utmi_p2_gfclk_parents[] = {
-	"init_60m_fclk", "xclk60mhsp2_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	       OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
-		&dpll_usb_m2_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
-		&init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
-		&init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
-		&dpll_usb_m2_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const char *otg_60m_gfclk_parents[] = {
-	"utmi_phy_clkout_ck", "xclk60motg_ck",
-};
-
-DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
-	       OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-		OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-		OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
-		OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table usim_ck_rates[] = {
-	{ .div = 14, .val = 0 },
-	{ .div = 18, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-			 OMAP4430_CM_WKUP_USIM_CLKCTRL,
-			 OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
-			 0x0, usim_ck_rates, NULL);
-
-DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
-		OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
-		0x0, NULL);
-
-/* Remaining optional clocks */
-static const char *pmd_stm_clock_mux_ck_parents[] = {
-	"sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
-};
-
-DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
-	       OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	       OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
-	       OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
-		   &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-		   OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
-		   OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-static const char *trace_clk_div_ck_parents[] = {
-	"pmd_trace_clk_mux_ck",
-};
-
-static const struct clksel trace_clk_div_div[] = {
-	{ .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
-
-static struct clk trace_clk_div_ck;
-
-static const struct clk_ops trace_clk_div_ck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.set_rate	= &omap2_clksel_set_rate,
-	.round_rate	= &omap2_clksel_round_rate,
-	.init		= &omap2_init_clk_clkdm,
-	.enable		= &omap2_clkops_enable_clkdm,
-	.disable	= &omap2_clkops_disable_clkdm,
-};
-
-static struct clk_hw_omap trace_clk_div_ck_hw = {
-	.hw = {
-		.clk = &trace_clk_div_ck,
-	},
-	.clkdm_name	= "emu_sys_clkdm",
-	.clksel		= trace_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
-		  trace_clk_div_ck_ops);
-
-/* SCRM aux clk nodes */
-
-static const struct clksel auxclk_src_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
-	{ .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *auxclk_src_ck_parents[] = {
-	"sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
-};
-
-static const struct clk_ops auxclk_src_ck_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-static const char *auxclkreq_ck_parents[] = {
-	"auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
-	"auxclk5_ck",
-};
-
-DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
 /*
  * clocks specific to omap4460
  */
-static struct omap_clk omap446x_clks[] = {
-	CLK(NULL,	"div_ts_ck",			&div_ts_ck),
-	CLK(NULL,	"bandgap_ts_fclk",		&bandgap_ts_fclk),
-};
-
-/*
- * clocks specific to omap4430
- */
-static struct omap_clk omap443x_clks[] = {
-	CLK(NULL,	"bandgap_fclk",			&bandgap_fclk),
-};
-
-/*
- * clocks common to omap44xx
- */
-static struct omap_clk omap44xx_clks[] = {
-	CLK(NULL,	"extalt_clkin_ck",		&extalt_clkin_ck),
-	CLK(NULL,	"pad_clks_src_ck",		&pad_clks_src_ck),
-	CLK(NULL,	"pad_clks_ck",			&pad_clks_ck),
-	CLK(NULL,	"pad_slimbus_core_clks_ck",	&pad_slimbus_core_clks_ck),
-	CLK(NULL,	"secure_32k_clk_src_ck",	&secure_32k_clk_src_ck),
-	CLK(NULL,	"slimbus_src_clk",		&slimbus_src_clk),
-	CLK(NULL,	"slimbus_clk",			&slimbus_clk),
-	CLK(NULL,	"sys_32k_ck",			&sys_32k_ck),
-	CLK(NULL,	"virt_12000000_ck",		&virt_12000000_ck),
-	CLK(NULL,	"virt_13000000_ck",		&virt_13000000_ck),
-	CLK(NULL,	"virt_16800000_ck",		&virt_16800000_ck),
-	CLK(NULL,	"virt_19200000_ck",		&virt_19200000_ck),
-	CLK(NULL,	"virt_26000000_ck",		&virt_26000000_ck),
-	CLK(NULL,	"virt_27000000_ck",		&virt_27000000_ck),
-	CLK(NULL,	"virt_38400000_ck",		&virt_38400000_ck),
-	CLK(NULL,	"sys_clkin_ck",			&sys_clkin_ck),
-	CLK(NULL,	"tie_low_clock_ck",		&tie_low_clock_ck),
-	CLK(NULL,	"utmi_phy_clkout_ck",		&utmi_phy_clkout_ck),
-	CLK(NULL,	"xclk60mhsp1_ck",		&xclk60mhsp1_ck),
-	CLK(NULL,	"xclk60mhsp2_ck",		&xclk60mhsp2_ck),
-	CLK(NULL,	"xclk60motg_ck",		&xclk60motg_ck),
-	CLK(NULL,	"abe_dpll_bypass_clk_mux_ck",	&abe_dpll_bypass_clk_mux_ck),
-	CLK(NULL,	"abe_dpll_refclk_mux_ck",	&abe_dpll_refclk_mux_ck),
-	CLK(NULL,	"dpll_abe_ck",			&dpll_abe_ck),
-	CLK(NULL,	"dpll_abe_x2_ck",		&dpll_abe_x2_ck),
-	CLK(NULL,	"dpll_abe_m2x2_ck",		&dpll_abe_m2x2_ck),
-	CLK(NULL,	"abe_24m_fclk",			&abe_24m_fclk),
-	CLK(NULL,	"abe_clk",			&abe_clk),
-	CLK(NULL,	"aess_fclk",			&aess_fclk),
-	CLK(NULL,	"dpll_abe_m3x2_ck",		&dpll_abe_m3x2_ck),
-	CLK(NULL,	"core_hsd_byp_clk_mux_ck",	&core_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_core_ck",			&dpll_core_ck),
-	CLK(NULL,	"dpll_core_x2_ck",		&dpll_core_x2_ck),
-	CLK(NULL,	"dpll_core_m6x2_ck",		&dpll_core_m6x2_ck),
-	CLK(NULL,	"dbgclk_mux_ck",		&dbgclk_mux_ck),
-	CLK(NULL,	"dpll_core_m2_ck",		&dpll_core_m2_ck),
-	CLK(NULL,	"ddrphy_ck",			&ddrphy_ck),
-	CLK(NULL,	"dpll_core_m5x2_ck",		&dpll_core_m5x2_ck),
-	CLK(NULL,	"div_core_ck",			&div_core_ck),
-	CLK(NULL,	"div_iva_hs_clk",		&div_iva_hs_clk),
-	CLK(NULL,	"div_mpu_hs_clk",		&div_mpu_hs_clk),
-	CLK(NULL,	"dpll_core_m4x2_ck",		&dpll_core_m4x2_ck),
-	CLK(NULL,	"dll_clk_div_ck",		&dll_clk_div_ck),
-	CLK(NULL,	"dpll_abe_m2_ck",		&dpll_abe_m2_ck),
-	CLK(NULL,	"dpll_core_m3x2_ck",		&dpll_core_m3x2_ck),
-	CLK(NULL,	"dpll_core_m7x2_ck",		&dpll_core_m7x2_ck),
-	CLK(NULL,	"iva_hsd_byp_clk_mux_ck",	&iva_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_iva_ck",			&dpll_iva_ck),
-	CLK(NULL,	"dpll_iva_x2_ck",		&dpll_iva_x2_ck),
-	CLK(NULL,	"dpll_iva_m4x2_ck",		&dpll_iva_m4x2_ck),
-	CLK(NULL,	"dpll_iva_m5x2_ck",		&dpll_iva_m5x2_ck),
-	CLK(NULL,	"dpll_mpu_ck",			&dpll_mpu_ck),
-	CLK(NULL,	"dpll_mpu_m2_ck",		&dpll_mpu_m2_ck),
-	CLK(NULL,	"per_hs_clk_div_ck",		&per_hs_clk_div_ck),
-	CLK(NULL,	"per_hsd_byp_clk_mux_ck",	&per_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_per_ck",			&dpll_per_ck),
-	CLK(NULL,	"dpll_per_m2_ck",		&dpll_per_m2_ck),
-	CLK(NULL,	"dpll_per_x2_ck",		&dpll_per_x2_ck),
-	CLK(NULL,	"dpll_per_m2x2_ck",		&dpll_per_m2x2_ck),
-	CLK(NULL,	"dpll_per_m3x2_ck",		&dpll_per_m3x2_ck),
-	CLK(NULL,	"dpll_per_m4x2_ck",		&dpll_per_m4x2_ck),
-	CLK(NULL,	"dpll_per_m5x2_ck",		&dpll_per_m5x2_ck),
-	CLK(NULL,	"dpll_per_m6x2_ck",		&dpll_per_m6x2_ck),
-	CLK(NULL,	"dpll_per_m7x2_ck",		&dpll_per_m7x2_ck),
-	CLK(NULL,	"usb_hs_clk_div_ck",		&usb_hs_clk_div_ck),
-	CLK(NULL,	"dpll_usb_ck",			&dpll_usb_ck),
-	CLK(NULL,	"dpll_usb_clkdcoldo_ck",	&dpll_usb_clkdcoldo_ck),
-	CLK(NULL,	"dpll_usb_m2_ck",		&dpll_usb_m2_ck),
-	CLK(NULL,	"ducati_clk_mux_ck",		&ducati_clk_mux_ck),
-	CLK(NULL,	"func_12m_fclk",		&func_12m_fclk),
-	CLK(NULL,	"func_24m_clk",			&func_24m_clk),
-	CLK(NULL,	"func_24mc_fclk",		&func_24mc_fclk),
-	CLK(NULL,	"func_48m_fclk",		&func_48m_fclk),
-	CLK(NULL,	"func_48mc_fclk",		&func_48mc_fclk),
-	CLK(NULL,	"func_64m_fclk",		&func_64m_fclk),
-	CLK(NULL,	"func_96m_fclk",		&func_96m_fclk),
-	CLK(NULL,	"init_60m_fclk",		&init_60m_fclk),
-	CLK(NULL,	"l3_div_ck",			&l3_div_ck),
-	CLK(NULL,	"l4_div_ck",			&l4_div_ck),
-	CLK(NULL,	"lp_clk_div_ck",		&lp_clk_div_ck),
-	CLK(NULL,	"l4_wkup_clk_mux_ck",		&l4_wkup_clk_mux_ck),
-	CLK("smp_twd",	NULL,				&mpu_periphclk),
-	CLK(NULL,	"ocp_abe_iclk",			&ocp_abe_iclk),
-	CLK(NULL,	"per_abe_24m_fclk",		&per_abe_24m_fclk),
-	CLK(NULL,	"per_abe_nc_fclk",		&per_abe_nc_fclk),
-	CLK(NULL,	"syc_clk_div_ck",		&syc_clk_div_ck),
-	CLK(NULL,	"aes1_fck",			&aes1_fck),
-	CLK(NULL,	"aes2_fck",			&aes2_fck),
-	CLK(NULL,	"dmic_sync_mux_ck",		&dmic_sync_mux_ck),
-	CLK(NULL,	"func_dmic_abe_gfclk",		&func_dmic_abe_gfclk),
-	CLK(NULL,	"dss_sys_clk",			&dss_sys_clk),
-	CLK(NULL,	"dss_tv_clk",			&dss_tv_clk),
-	CLK(NULL,	"dss_dss_clk",			&dss_dss_clk),
-	CLK(NULL,	"dss_48mhz_clk",		&dss_48mhz_clk),
-	CLK(NULL,	"dss_fck",			&dss_fck),
-	CLK("omapdss_dss",	"ick",			&dss_fck),
-	CLK(NULL,	"fdif_fck",			&fdif_fck),
-	CLK(NULL,	"gpio1_dbclk",			&gpio1_dbclk),
-	CLK(NULL,	"gpio2_dbclk",			&gpio2_dbclk),
-	CLK(NULL,	"gpio3_dbclk",			&gpio3_dbclk),
-	CLK(NULL,	"gpio4_dbclk",			&gpio4_dbclk),
-	CLK(NULL,	"gpio5_dbclk",			&gpio5_dbclk),
-	CLK(NULL,	"gpio6_dbclk",			&gpio6_dbclk),
-	CLK(NULL,	"sgx_clk_mux",			&sgx_clk_mux),
-	CLK(NULL,	"hsi_fck",			&hsi_fck),
-	CLK(NULL,	"iss_ctrlclk",			&iss_ctrlclk),
-	CLK(NULL,	"mcasp_sync_mux_ck",		&mcasp_sync_mux_ck),
-	CLK(NULL,	"func_mcasp_abe_gfclk",		&func_mcasp_abe_gfclk),
-	CLK(NULL,	"mcbsp1_sync_mux_ck",		&mcbsp1_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp1_gfclk",		&func_mcbsp1_gfclk),
-	CLK(NULL,	"mcbsp2_sync_mux_ck",		&mcbsp2_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp2_gfclk",		&func_mcbsp2_gfclk),
-	CLK(NULL,	"mcbsp3_sync_mux_ck",		&mcbsp3_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp3_gfclk",		&func_mcbsp3_gfclk),
-	CLK(NULL,	"mcbsp4_sync_mux_ck",		&mcbsp4_sync_mux_ck),
-	CLK(NULL,	"per_mcbsp4_gfclk",		&per_mcbsp4_gfclk),
-	CLK(NULL,	"hsmmc1_fclk",			&hsmmc1_fclk),
-	CLK(NULL,	"hsmmc2_fclk",			&hsmmc2_fclk),
-	CLK(NULL,	"ocp2scp_usb_phy_phy_48m",	&ocp2scp_usb_phy_phy_48m),
-	CLK(NULL,	"sha2md5_fck",			&sha2md5_fck),
-	CLK(NULL,	"slimbus1_fclk_1",		&slimbus1_fclk_1),
-	CLK(NULL,	"slimbus1_fclk_0",		&slimbus1_fclk_0),
-	CLK(NULL,	"slimbus1_fclk_2",		&slimbus1_fclk_2),
-	CLK(NULL,	"slimbus1_slimbus_clk",		&slimbus1_slimbus_clk),
-	CLK(NULL,	"slimbus2_fclk_1",		&slimbus2_fclk_1),
-	CLK(NULL,	"slimbus2_fclk_0",		&slimbus2_fclk_0),
-	CLK(NULL,	"slimbus2_slimbus_clk",		&slimbus2_slimbus_clk),
-	CLK(NULL,	"smartreflex_core_fck",		&smartreflex_core_fck),
-	CLK(NULL,	"smartreflex_iva_fck",		&smartreflex_iva_fck),
-	CLK(NULL,	"smartreflex_mpu_fck",		&smartreflex_mpu_fck),
-	CLK(NULL,	"dmt1_clk_mux",			&dmt1_clk_mux),
-	CLK(NULL,	"cm2_dm10_mux",			&cm2_dm10_mux),
-	CLK(NULL,	"cm2_dm11_mux",			&cm2_dm11_mux),
-	CLK(NULL,	"cm2_dm2_mux",			&cm2_dm2_mux),
-	CLK(NULL,	"cm2_dm3_mux",			&cm2_dm3_mux),
-	CLK(NULL,	"cm2_dm4_mux",			&cm2_dm4_mux),
-	CLK(NULL,	"timer5_sync_mux",		&timer5_sync_mux),
-	CLK(NULL,	"timer6_sync_mux",		&timer6_sync_mux),
-	CLK(NULL,	"timer7_sync_mux",		&timer7_sync_mux),
-	CLK(NULL,	"timer8_sync_mux",		&timer8_sync_mux),
-	CLK(NULL,	"cm2_dm9_mux",			&cm2_dm9_mux),
-	CLK(NULL,	"usb_host_fs_fck",		&usb_host_fs_fck),
-	CLK("usbhs_omap",	"fs_fck",		&usb_host_fs_fck),
-	CLK(NULL,	"utmi_p1_gfclk",		&utmi_p1_gfclk),
-	CLK(NULL,	"usb_host_hs_utmi_p1_clk",	&usb_host_hs_utmi_p1_clk),
-	CLK(NULL,	"utmi_p2_gfclk",		&utmi_p2_gfclk),
-	CLK(NULL,	"usb_host_hs_utmi_p2_clk",	&usb_host_hs_utmi_p2_clk),
-	CLK(NULL,	"usb_host_hs_utmi_p3_clk",	&usb_host_hs_utmi_p3_clk),
-	CLK(NULL,	"usb_host_hs_hsic480m_p1_clk",	&usb_host_hs_hsic480m_p1_clk),
-	CLK(NULL,	"usb_host_hs_hsic60m_p1_clk",	&usb_host_hs_hsic60m_p1_clk),
-	CLK(NULL,	"usb_host_hs_hsic60m_p2_clk",	&usb_host_hs_hsic60m_p2_clk),
-	CLK(NULL,	"usb_host_hs_hsic480m_p2_clk",	&usb_host_hs_hsic480m_p2_clk),
-	CLK(NULL,	"usb_host_hs_func48mclk",	&usb_host_hs_func48mclk),
-	CLK(NULL,	"usb_host_hs_fck",		&usb_host_hs_fck),
-	CLK("usbhs_omap",	"hs_fck",		&usb_host_hs_fck),
-	CLK(NULL,	"otg_60m_gfclk",		&otg_60m_gfclk),
-	CLK(NULL,	"usb_otg_hs_xclk",		&usb_otg_hs_xclk),
-	CLK(NULL,	"usb_otg_hs_ick",		&usb_otg_hs_ick),
-	CLK("musb-omap2430",	"ick",			&usb_otg_hs_ick),
-	CLK(NULL,	"usb_phy_cm_clk32k",		&usb_phy_cm_clk32k),
-	CLK(NULL,	"usb_tll_hs_usb_ch2_clk",	&usb_tll_hs_usb_ch2_clk),
-	CLK(NULL,	"usb_tll_hs_usb_ch0_clk",	&usb_tll_hs_usb_ch0_clk),
-	CLK(NULL,	"usb_tll_hs_usb_ch1_clk",	&usb_tll_hs_usb_ch1_clk),
-	CLK(NULL,	"usb_tll_hs_ick",		&usb_tll_hs_ick),
-	CLK("usbhs_omap",	"usbtll_ick",		&usb_tll_hs_ick),
-	CLK("usbhs_tll",	"usbtll_ick",		&usb_tll_hs_ick),
-	CLK(NULL,	"usim_ck",			&usim_ck),
-	CLK(NULL,	"usim_fclk",			&usim_fclk),
-	CLK(NULL,	"pmd_stm_clock_mux_ck",		&pmd_stm_clock_mux_ck),
-	CLK(NULL,	"pmd_trace_clk_mux_ck",		&pmd_trace_clk_mux_ck),
-	CLK(NULL,	"stm_clk_div_ck",		&stm_clk_div_ck),
-	CLK(NULL,	"trace_clk_div_ck",		&trace_clk_div_ck),
-	CLK(NULL,	"auxclk0_src_ck",		&auxclk0_src_ck),
-	CLK(NULL,	"auxclk0_ck",			&auxclk0_ck),
-	CLK(NULL,	"auxclkreq0_ck",		&auxclkreq0_ck),
-	CLK(NULL,	"auxclk1_src_ck",		&auxclk1_src_ck),
-	CLK(NULL,	"auxclk1_ck",			&auxclk1_ck),
-	CLK(NULL,	"auxclkreq1_ck",		&auxclkreq1_ck),
-	CLK(NULL,	"auxclk2_src_ck",		&auxclk2_src_ck),
-	CLK(NULL,	"auxclk2_ck",			&auxclk2_ck),
-	CLK(NULL,	"auxclkreq2_ck",		&auxclkreq2_ck),
-	CLK(NULL,	"auxclk3_src_ck",		&auxclk3_src_ck),
-	CLK(NULL,	"auxclk3_ck",			&auxclk3_ck),
-	CLK(NULL,	"auxclkreq3_ck",		&auxclkreq3_ck),
-	CLK(NULL,	"auxclk4_src_ck",		&auxclk4_src_ck),
-	CLK(NULL,	"auxclk4_ck",			&auxclk4_ck),
-	CLK(NULL,	"auxclkreq4_ck",		&auxclkreq4_ck),
-	CLK(NULL,	"auxclk5_src_ck",		&auxclk5_src_ck),
-	CLK(NULL,	"auxclk5_ck",			&auxclk5_ck),
-	CLK(NULL,	"auxclkreq5_ck",		&auxclkreq5_ck),
-	CLK("omap-gpmc",	"fck",			&dummy_ck),
-	CLK("omap_i2c.1",	"ick",			&dummy_ck),
-	CLK("omap_i2c.2",	"ick",			&dummy_ck),
-	CLK("omap_i2c.3",	"ick",			&dummy_ck),
-	CLK("omap_i2c.4",	"ick",			&dummy_ck),
-	CLK(NULL,	"mailboxes_ick",		&dummy_ck),
-	CLK("omap_hsmmc.0",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.1",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.2",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.3",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.4",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.1",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.2",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.3",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.4",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.1",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.2",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.3",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.4",	"ick",			&dummy_ck),
-	CLK(NULL,	"uart1_ick",			&dummy_ck),
-	CLK(NULL,	"uart2_ick",			&dummy_ck),
-	CLK(NULL,	"uart3_ick",			&dummy_ck),
-	CLK(NULL,	"uart4_ick",			&dummy_ck),
-	CLK("usbhs_omap",	"usbhost_ick",		&dummy_ck),
-	CLK("usbhs_omap",	"usbtll_fck",		&dummy_ck),
-	CLK("usbhs_tll",	"usbtll_fck",		&dummy_ck),
-	CLK("omap_wdt",	"ick",				&dummy_ck),
-	CLK(NULL,	"timer_32k_ck",	&sys_32k_ck),
+static struct omap_dt_clk omap44xx_clks[] = {
+	DT_CLK("smp_twd",	NULL,			"mpu_periphclk"),
+	DT_CLK(NULL,	"timer_32k_ck",	"sys_32k_ck"),
 	/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
-	CLK("omap_timer.1",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.2",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.3",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.4",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.9",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.10",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.11",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.5",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.6",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.7",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.8",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4a318000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48032000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48034000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48036000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("4803e000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48086000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48088000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("40138000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013a000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013c000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013e000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK(NULL,	"cpufreq_ck",	&dpll_mpu_ck),
+	DT_CLK("omap_timer.1",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.2",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.3",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.4",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.9",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.10",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.11",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.5",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.6",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.7",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.8",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4a318000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48032000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48034000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48036000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("4803e000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48086000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48088000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("40138000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013a000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013c000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013e000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK(NULL,	"cpufreq_ck",	"dpll_mpu_ck"),
 };
 
 int __init omap4xxx_clk_init(void)
 {
 	int rc;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
 
-	if (cpu_is_omap443x()) {
-		cpu_mask = RATE_IN_4430;
-		omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
-	} else if (cpu_is_omap446x() || cpu_is_omap447x()) {
-		cpu_mask = RATE_IN_4460 | RATE_IN_4430;
-		omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
-		if (cpu_is_omap447x())
-			pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
-	} else {
-		return 0;
-	}
+	/* FIXME register clocks from DT first */
+	dt_omap_clk_init();
 
-	omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
+	omap_dt_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
 
 	omap2_clk_disable_autoidle_all();
 
@@ -1712,9 +110,12 @@ int __init omap4xxx_clk_init(void)
 	 * locking the ABE DPLL on boot.
 	 * Lock the ABE DPLL in any case to avoid issues with audio.
 	 */
-	rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
+	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
+	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
 	if (!rc)
-		rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
+		rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
 	if (rc)
 		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
@@ -1722,7 +123,8 @@ int __init omap4xxx_clk_init(void)
 	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
 	 * domain can transition to retention state when not in use.
 	 */
-	rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
+	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+	rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
 	if (rc)
 		pr_err("%s: failed to configure USB DPLL!\n", __func__);
 
-- 
1.7.9.5

[PATCHv2 11/11] ARM: OMAP4: register DT clocks and remove old data

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [130619 06:25]:
> Now that the OMAP4 PRCM clock data has been converted to device tree
> representation, it is no longer needed as static clock data. OMAP4
> clock init routine is also changed to register DT clocks first.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  arch/arm/mach-omap2/cclock44xx_data.c | 1674 +--------------------------------
>  1 file changed, 38 insertions(+), 1636 deletions(-)

This is nice, thanks for working on this. While at it, can
you also keep your eyes open for the register defines in the
header files we can also drop?

Some of those headers are quite huge.. and should eventually
be private to the related drivers if needed at all with DT.

Regards,

Tony 

[PATCHv2 11/11] ARM: OMAP4: register DT clocks and remove old data

[Tero Kristo]

On 06/21/2013 10:25 AM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [130619 06:25]:
>> Now that the OMAP4 PRCM clock data has been converted to device tree
>> representation, it is no longer needed as static clock data. OMAP4
>> clock init routine is also changed to register DT clocks first.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/mach-omap2/cclock44xx_data.c | 1674 +--------------------------------
>>   1 file changed, 38 insertions(+), 1636 deletions(-)
>
> This is nice, thanks for working on this. While at it, can
> you also keep your eyes open for the register defines in the
> header files we can also drop?
>
> Some of those headers are quite huge.. and should eventually
> be private to the related drivers if needed at all with DT.

Yeah, I can take a look at this after this set is done. It seems like 
large portion of the headers can be dropped completely once this 
exercise is done.

-Tero

[PATCHv2 11/11] ARM: OMAP4: register DT clocks and remove old data

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [130624 00:51]:
> On 06/21/2013 10:25 AM, Tony Lindgren wrote:
> >* Tero Kristo <t-kristo@ti.com> [130619 06:25]:
> >>Now that the OMAP4 PRCM clock data has been converted to device tree
> >>representation, it is no longer needed as static clock data. OMAP4
> >>clock init routine is also changed to register DT clocks first.
> >>
> >>Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >>---
> >>  arch/arm/mach-omap2/cclock44xx_data.c | 1674 +--------------------------------
> >>  1 file changed, 38 insertions(+), 1636 deletions(-)
> >
> >This is nice, thanks for working on this. While at it, can
> >you also keep your eyes open for the register defines in the
> >header files we can also drop?
> >
> >Some of those headers are quite huge.. and should eventually
> >be private to the related drivers if needed at all with DT.
> 
> Yeah, I can take a look at this after this set is done. It seems
> like large portion of the headers can be dropped completely once
> this exercise is done.

OK great, thanks.

Tony