From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 05/12] ARM: barrier: allow options to be passed to memory barrier instructions
Date: Fri, 21 Jun 2013 09:51:02 +0100 [thread overview]
Message-ID: <20130621085102.GC6983@mudshark.cambridge.arm.com> (raw)
In-Reply-To: <CACVXFVPrkc4YY25J9QzbKB9A6uerq9m9VQjTZTMN45DvKbx3SA@mail.gmail.com>
Hello,
On Fri, Jun 21, 2013 at 09:37:14AM +0100, Ming Lei wrote:
> On Thu, Jun 20, 2013 at 10:21 PM, Will Deacon <will.deacon@arm.com> wrote:
> > On ARMv7, the memory barrier instructions take an optional `option'
> > field which can be used to constrain the effects of a memory barrier
> > based on shareability and access type.
> >
> > This patch allows the caller to pass these options if required, and
> > updates the smp_*() barriers to request inner-shareable barriers,
> > affecting only stores for the _wmb variant. wmb() is also changed to
> > use the -st version of dsb.
> >
> > Reported-by: Albin Tonnerre <albin.tonnerre@arm.com>
> > Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> > Signed-off-by: Will Deacon <will.deacon@arm.com>
> > ---
> > arch/arm/include/asm/assembler.h | 4 ++--
> > arch/arm/include/asm/barrier.h | 32 ++++++++++++++++----------------
> > 2 files changed, 18 insertions(+), 18 deletions(-)
[...]
> > @@ -42,7 +42,7 @@
> > #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
> > #define mb() do { dsb(); outer_sync(); } while (0)
> > #define rmb() dsb()
>
> The above two dsb() are missed?
I don't think so. What would you suggest changing them to? Remember: there's
no `load' barrier variant in ARMv7, and the non smp_ barriers may be used to
ensure ordering outside of the inner-shareable domain (for example, in I/O
accessors).
Will
next prev parent reply other threads:[~2013-06-21 8:51 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-20 14:21 [PATCH v2 00/12] Make use of v7 barrier variants in Linux Will Deacon
2013-06-20 14:21 ` [PATCH v2 01/12] ARM: mm: remove redundant dsb() prior to range TLB invalidation Will Deacon
2013-06-20 14:21 ` [PATCH v2 02/12] ARM: tlb: don't perform inner-shareable invalidation for local TLB ops Will Deacon
2013-06-20 14:21 ` [PATCH v2 03/12] ARM: tlb: don't bother with barriers for branch predictor maintenance Will Deacon
2013-06-20 14:21 ` [PATCH v2 04/12] ARM: tlb: don't perform inner-shareable invalidation for local BP ops Will Deacon
2013-06-20 14:21 ` [PATCH v2 05/12] ARM: barrier: allow options to be passed to memory barrier instructions Will Deacon
2013-06-21 8:37 ` Ming Lei
2013-06-21 8:51 ` Will Deacon [this message]
2013-06-21 8:53 ` Ming Lei
2013-06-20 14:21 ` [PATCH v2 06/12] ARM: tlb: reduce scope of barrier domains for TLB invalidation Will Deacon
2013-06-20 14:21 ` [PATCH v2 07/12] ARM: mm: use inner-shareable barriers for TLB and user cache operations Will Deacon
2013-06-20 14:21 ` [PATCH v2 08/12] ARM: spinlock: use inner-shareable dsb variant prior to sev instruction Will Deacon
2013-06-20 14:21 ` [PATCH v2 09/12] ARM: kvm: use inner-shareable barriers after TLB flushing Will Deacon
2013-06-20 14:21 ` [PATCH v2 10/12] ARM: mcpm: use -st dsb option prior to sev instructions Will Deacon
2013-06-20 14:21 ` [PATCH v2 11/12] ARM: l2x0: use -st dsb option for ordering writel_relaxed with unlock Will Deacon
2013-06-20 14:21 ` [PATCH v2 12/12] ARM: cacheflush: use -ishst dsb variant for ensuring flush completion Will Deacon
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