From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH RFC 2/8] clk: sunxi: register factors clocks behind composite
Date: Tue, 23 Jul 2013 11:35:00 +0200 [thread overview]
Message-ID: <20130723093500.GC10389@lukather> (raw)
In-Reply-To: <1374541272-32173-3-git-send-email-emilio@elopez.com.ar>
Hi Emilio,
On Mon, Jul 22, 2013 at 10:01:06PM -0300, Emilio L?pez wrote:
> This commit reworks factors clock registration to be done behind a
> composite clock. This allows us to additionally add a gate, mux or
> divisors, as it will be needed by some future PLLs.
Thanks for this patch, it looks fine.
I'm actually wondering if we could do this as well for the mux/gate/div
that we have?
This way, we would cover all the cases, and could only have one clock
defined per actual hardware clock.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2013-07-23 9:35 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-23 1:01 [PATCH RFC 0/8] sunxi clk: PLL4/5/6 and module 0 support Emilio López
2013-07-23 1:01 ` [PATCH RFC 1/8] clk: sunxi: fix initialization of basic clocks Emilio López
2013-07-23 9:33 ` Maxime Ripard
2013-07-23 1:01 ` [PATCH RFC 2/8] clk: sunxi: register factors clocks behind composite Emilio López
2013-07-23 9:35 ` Maxime Ripard [this message]
2013-07-23 1:01 ` [PATCH RFC 3/8] clk: sunxi: add gating support to PLL1 Emilio López
2013-07-23 13:15 ` Maxime Ripard
2013-07-23 1:01 ` [PATCH RFC 4/8] ARM: sunxi: add PLL4 support Emilio López
2013-07-23 1:01 ` [PATCH RFC 5/8] clk: sunxi: add PLL5 and PLL6 support Emilio López
2013-07-23 13:22 ` Maxime Ripard
2013-07-23 1:01 ` [PATCH RFC 6/8] ARM: " Emilio López
2013-07-23 1:01 ` [PATCH RFC 7/8] clk: sunxi: mod0 support Emilio López
2013-07-23 13:29 ` Maxime Ripard
2013-07-23 1:01 ` [PATCH RFC 8/8] ARM: sun4i: mod0 clocks Emilio López
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