[PATCH 00/11] ARM: tegra114: add support for system suspend

[PATCH 00/11] ARM: tegra114: add support for system suspend

[Joseph Lo]

This series introduce system suspend function for Tegra114 and depend on
the series of "ARM: tegra114: cpuidle: add power down state".

Verified on Seaboard, Cardhu and Dalmore and with THUMB2_KERNEL as well.

Joseph Lo (11):
  ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9 in
    tegra_resume
  ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS
    or ALL
  ARM: tegra114: set up the correct L2 data RAM latency for Cortex-A15
  ARM: tegra114: add low level support code for cluster power down
  ARM: tegra114: shut off the CPU rail when the last CPU in suspend
  ARM: tegra114: hook tegra_tear_down_cpu function
  ARM: tegra114: flowctrl: add support for cpu_suspend_enter/exit
  clk: tegra114: add suspend/resume function for tegar_cpu_car_ops
  ARM: tegar: remove the limitation that Tegra114 can't support suspend
  ARM: dts: tegra114: dalmore: add GPIO power key support
  ARM: dts: tegra114: dalmore: add PM configurations for PMC

 arch/arm/boot/dts/tegra114-dalmore.dts | 18 ++++++++++++++++++
 arch/arm/mach-tegra/flowctrl.c         |  2 ++
 arch/arm/mach-tegra/flowctrl.h         |  7 +++++++
 arch/arm/mach-tegra/hotplug.c          |  2 +-
 arch/arm/mach-tegra/pm.c               |  5 +----
 arch/arm/mach-tegra/pmc.c              | 10 ++++++++++
 arch/arm/mach-tegra/reset-handler.S    |  8 ++++++--
 arch/arm/mach-tegra/sleep-tegra20.S    |  1 +
 arch/arm/mach-tegra/sleep-tegra30.S    |  7 ++++++-
 arch/arm/mach-tegra/sleep.S            | 29 ++++++++++++++++++++++++++++-
 arch/arm/mach-tegra/sleep.h            |  6 +++++-
 drivers/clk/tegra/clk-tegra114.c       | 26 ++++++++++++++++++++++++++
 12 files changed, 111 insertions(+), 10 deletions(-)

-- 
1.8.3.1

[PATCH 01/11] ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9 in tegra_resume

[Joseph Lo]

The v7_invalidate_l1 was used for the L1 cache that come out from reset
in a undefined state. This is no need for Cortex-A15. We do it for A9
only.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/reset-handler.S | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 39dc9e7..75285a3 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -40,9 +40,11 @@
  *	  re-enabling sdram.
  *
  *	r6: SoC ID
+ *	r8: CPU part number
  */
 ENTRY(tegra_resume)
-	bl	v7_invalidate_l1
+	check_cpu_part_num 0xc09, r8, r9
+	bleq	v7_invalidate_l1
 
 	cpu_id	r0
 	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
@@ -70,7 +72,8 @@ no_cpu0_chk:
 	str	r1, [r2]
 1:
 
-	check_cpu_part_num 0xc09, r8, r9
+	mov32	r9, 0xc09
+	cmp	r8, r9
 	bne	not_ca9
 #ifdef CONFIG_HAVE_ARM_SCU
 	/* enable SCU */
-- 
1.8.3.1

[PATCH 02/11] ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS or ALL

[Joseph Lo]

Adding a flag for tegra_disable_clean_inv_dcache to flush cache as LoUIS
or ALL. After this patch, the v7_flush_dcache_louis is used for CPU hotplug
and CPU suspend in CPU power down (e.g. CPU idle power-down mode) case. And
the v7_flush_dcache_all is used for CPU cluster power down (e.g. suspend to
LP2 mode).

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/hotplug.c       | 2 +-
 arch/arm/mach-tegra/sleep-tegra20.S | 1 +
 arch/arm/mach-tegra/sleep-tegra30.S | 1 +
 arch/arm/mach-tegra/sleep.S         | 7 ++++++-
 arch/arm/mach-tegra/sleep.h         | 6 +++++-
 5 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index a52c10e..4687ec0 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -37,7 +37,7 @@ int tegra_cpu_kill(unsigned cpu)
 void __ref tegra_cpu_die(unsigned int cpu)
 {
 	/* Clean L1 data cache */
-	tegra_disable_clean_inv_dcache();
+	tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS);
 
 	/* Shut down the current CPU. */
 	tegra_hotplug_shutdown();
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index e3f2417..f87721d 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -191,6 +191,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
 	mrc	p15, 0, r11, c1, c0, 1  @ save actlr before exiting coherency
 
 	/* Flush and disable the L1 data cache */
+	mov	r0, #TEGRA_FLUSH_CACHE_LOUIS
 	bl	tegra_disable_clean_inv_dcache
 
 	mov32	r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 5877f26..6744161 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -137,6 +137,7 @@ ENTRY(tegra30_sleep_cpu_secondary_finish)
 	mov	r7, lr
 
 	/* Flush and disable the L1 data cache */
+	mov 	r0, #TEGRA_FLUSH_CACHE_LOUIS
 	bl	tegra_disable_clean_inv_dcache
 
 	/* Powergate this CPU. */
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 9daaef2..6d6600d 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -56,7 +56,9 @@ ENTRY(tegra_disable_clean_inv_dcache)
 	isb
 
 	/* Flush the D-cache */
-	bl	v7_flush_dcache_louis
+	cmp	r0, #TEGRA_FLUSH_CACHE_ALL
+	blne	v7_flush_dcache_louis
+	bleq	v7_flush_dcache_all
 
 	/* Trun off coherency */
 	exit_smp r4, r5
@@ -73,9 +75,12 @@ ENDPROC(tegra_disable_clean_inv_dcache)
  * tegra?_tear_down_cpu
  */
 ENTRY(tegra_sleep_cpu_finish)
+	mov	r4, r0
 	/* Flush and disable the L1 data cache */
+	mov	r0, #TEGRA_FLUSH_CACHE_ALL
 	bl	tegra_disable_clean_inv_dcache
 
+	mov	r0, r4
 	mov32	r6, tegra_tear_down_cpu
 	ldr	r1, [r6]
 	add	r1, r1, r0
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 98b7da6..f0df3a4 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -41,6 +41,10 @@
 #define CPU_NOT_RESETTABLE	0
 #endif
 
+/* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
+#define TEGRA_FLUSH_CACHE_LOUIS	0x10
+#define TEGRA_FLUSH_CACHE_ALL	0x20
+
 #ifdef __ASSEMBLY__
 /* returns the offset of the flow controller halt register for a cpu */
 .macro cpu_to_halt_reg rd, rcpu
@@ -144,7 +148,7 @@ void tegra_pen_lock(void);
 void tegra_pen_unlock(void);
 void tegra_resume(void);
 int tegra_sleep_cpu_finish(unsigned long);
-void tegra_disable_clean_inv_dcache(void);
+void tegra_disable_clean_inv_dcache(u32 flag);
 
 #ifdef CONFIG_HOTPLUG_CPU
 void tegra20_hotplug_shutdown(void);
-- 
1.8.3.1

[PATCH 03/11] ARM: tegra114: set up the correct L2 data RAM latency for Cortex-A15

[Joseph Lo]

When there is a cluster power down cycle in suspend, we need to set up
the correct L2 RAM data RAM latency to make L2 cache work correctly. This
is only needed for cluster 0 and needs to be done in tegra_resume before
the cache is enabled.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/reset-handler.S |  1 +
 arch/arm/mach-tegra/sleep.S         | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 75285a3..34614bd 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -45,6 +45,7 @@
 ENTRY(tegra_resume)
 	check_cpu_part_num 0xc09, r8, r9
 	bleq	v7_invalidate_l1
+	blne	tegra_init_l2_for_a15
 
 	cpu_id	r0
 	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 6d6600d..8388113 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -69,6 +69,28 @@ ENDPROC(tegra_disable_clean_inv_dcache)
 
 #ifdef CONFIG_PM_SLEEP
 /*
+ * tegra_init_l2_for_a15
+ *
+ * set up the correct L2 cache data RAM latency
+ */
+ENTRY(tegra_init_l2_for_a15)
+	mrc	p15, 0, r0, c0, c0, 5
+	ubfx	r0, r0, #8, #4
+	tst	r0, #1				@ only need for cluster 0
+	bne	_exit_init_l2_a15
+
+	mrc	p15, 0x1, r0, c9, c0, 2
+	and	r0, r0, #7
+	cmp	r0, #2
+	bicne	r0, r0, #7
+	orrne	r0, r0, #2
+	mcrne	p15, 0x1, r0, c9, c0, 2
+_exit_init_l2_a15:
+
+	mov	pc, lr
+ENDPROC(tegra_init_l2_for_a15)
+
+/*
  * tegra_sleep_cpu_finish(unsigned long v2p)
  *
  * enters suspend in LP2 by turning off the mmu and jumping to
-- 
1.8.3.1

[PATCH 04/11] ARM: tegra114: add low level support code for cluster power down

[Joseph Lo]

When the CPU cluster power down, the vGIC is powered down too. The
flow controller needs to monitor the legacy interrupt controller to
wake up CPU. So setting up the appropriate wake up event in flow
controller.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/flowctrl.h      | 2 ++
 arch/arm/mach-tegra/sleep-tegra30.S | 6 +++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index e56a950..de0acb9 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -28,6 +28,8 @@
 #define FLOW_CTRL_SCLK_RESUME		(1 << 27)
 #define FLOW_CTRL_HALT_CPU_IRQ		(1 << 10)
 #define	FLOW_CTRL_HALT_CPU_FIQ		(1 << 8)
+#define FLOW_CTRL_HALT_LIC_IRQ		(1 << 11)
+#define FLOW_CTRL_HALT_LIC_FIQ		(1 << 10)
 #define FLOW_CTRL_HALT_GIC_IRQ		(1 << 9)
 #define FLOW_CTRL_HALT_GIC_FIQ		(1 << 8)
 #define FLOW_CTRL_CPU0_CSR		0x8
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 6744161..ecad4ea 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -175,8 +175,12 @@ tegra30_enter_sleep:
 	orr	r0, r0, #FLOW_CTRL_CSR_ENABLE
 	str	r0, [r6, r2]
 
+	tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
+	cmp	r10, #TEGRA30
 	mov	r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
-	orr	r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
+	orreq	r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
+	orrne   r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
+
 	cpu_to_halt_reg r2, r1
 	str	r0, [r6, r2]
 	dsb
-- 
1.8.3.1

[PATCH 05/11] ARM: tegra114: shut off the CPU rail when the last CPU in suspend

[Joseph Lo]

When the last CPU core in suspend, the CPU power rail can be turned off
by setting flags to flow controller. Then the flow controller will inform
PMC to turn off the CPU rail when the last CPU goes into suspend.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/flowctrl.h |  5 +++++
 arch/arm/mach-tegra/pmc.c      | 10 ++++++++++
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index de0acb9..c89aac6 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -35,6 +35,11 @@
 #define FLOW_CTRL_CPU0_CSR		0x8
 #define	FLOW_CTRL_CSR_INTR_FLAG		(1 << 15)
 #define FLOW_CTRL_CSR_EVENT_FLAG	(1 << 14)
+#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL	(1 << 13)
+#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU	(1 << 12)
+#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
+		FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
+		FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
 #define FLOW_CTRL_CSR_ENABLE		(1 << 0)
 #define FLOW_CTRL_HALT_CPU1_EVENTS	0x14
 #define FLOW_CTRL_CPU1_CSR		0x18
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 32360e5..4c2958f 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -21,6 +21,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
+#include "flowctrl.h"
 #include "fuse.h"
 #include "pm.h"
 #include "pmc.h"
@@ -202,6 +203,15 @@ void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
 	reg |= TEGRA_POWER_CPU_PWRREQ_OE;
 	reg &= ~TEGRA_POWER_EFFECT_LP0;
 
+	/* Turn off CRAIL */
+	if (tegra_chip_id == TEGRA114) {
+		u32 fc_reg;
+		fc_reg = flowctrl_read_cpu_csr(0);
+		fc_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
+		fc_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
+		flowctrl_write_cpu_csr(0, fc_reg);
+	}
+
 	switch (mode) {
 	case TEGRA_SUSPEND_LP2:
 		rate = clk_get_rate(tegra_pclk);
-- 
1.8.3.1

[PATCH 06/11] ARM: tegra114: hook tegra_tear_down_cpu function

[Joseph Lo]

Hooking tegra_tear_down_cpu for Tegra114 for supporting cluster power
down when CPU cluster suspneded in LP2.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/pm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 94e69be..a0668a2 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -52,6 +52,7 @@ static void tegra_tear_down_cpu_init(void)
 			tegra_tear_down_cpu = tegra20_tear_down_cpu;
 		break;
 	case TEGRA30:
+	case TEGRA114:
 		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
 			tegra_tear_down_cpu = tegra30_tear_down_cpu;
 		break;
-- 
1.8.3.1

[PATCH 07/11] ARM: tegra114: flowctrl: add support for cpu_suspend_enter/exit

[Joseph Lo]

The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU goes into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.

For Tegra114, the setting is compatible with Tegra30.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/flowctrl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index b477ef3..5348543 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -86,6 +86,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
 		reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
 		break;
 	case TEGRA30:
+	case TEGRA114:
 		/* clear wfe bitmap */
 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
 		/* clear wfi bitmap */
@@ -123,6 +124,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
 		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
 		break;
 	case TEGRA30:
+	case TEGRA114:
 		/* clear wfe bitmap */
 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
 		/* clear wfi bitmap */
-- 
1.8.3.1

[PATCH 08/11] clk: tegra114: add suspend/resume function for tegar_cpu_car_ops

[Joseph Lo]

Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index dbd0428..cd51d75 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -258,6 +258,12 @@
 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
 
+#ifdef CONFIG_PM_SLEEP
+static struct cpu_clk_suspend_context {
+	u32 clk_csite_src;
+} tegra114_cpu_clk_sctx;
+#endif
+
 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 
 static void __iomem *clk_base;
@@ -2107,9 +2113,29 @@ static void tegra114_disable_cpu_clock(u32 cpu)
 	/* flow controller would take care in the power sequence. */
 }
 
+#ifdef CONFIG_PM_SLEEP
+static void tegra114_cpu_clock_suspend(void)
+{
+	/* switch coresite to clk_m, save off original source */
+	tegra114_cpu_clk_sctx.clk_csite_src =
+				readl(clk_base + CLK_SOURCE_CSITE);
+	writel(3<<30, clk_base + CLK_SOURCE_CSITE);
+}
+
+static void tegra114_cpu_clock_resume(void)
+{
+	writel(tegra114_cpu_clk_sctx.clk_csite_src,
+					clk_base + CLK_SOURCE_CSITE);
+}
+#endif
+
 static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
 	.wait_for_reset	= tegra114_wait_cpu_in_reset,
 	.disable_clock	= tegra114_disable_cpu_clock,
+#ifdef CONFIG_PM_SLEEP
+	.suspend	= tegra114_cpu_clock_suspend,
+	.resume		= tegra114_cpu_clock_resume,
+#endif
 };
 
 static const struct of_device_id pmc_match[] __initconst = {
-- 
1.8.3.1

[PATCH 09/11] ARM: tegar: remove the limitation that Tegra114 can't support suspend

[Joseph Lo]

The Tegra114 can support suspend function now, removing the limitation.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/pm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index a0668a2..94b1ee9 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -172,10 +172,6 @@ void tegra_idle_lp2_last(void)
 enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
 				enum tegra_suspend_mode mode)
 {
-	/* Tegra114 didn't support any suspending mode yet. */
-	if (tegra_chip_id == TEGRA114)
-		return TEGRA_SUSPEND_NONE;
-
 	/*
 	 * The Tegra devices only support suspending to LP2 currently.
 	 */
-- 
1.8.3.1

[PATCH 10/11] ARM: dts: tegra114: dalmore: add GPIO power key support

[Joseph Lo]

Adding the GPIO power key and enabling the wake up function.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/boot/dts/tegra114-dalmore.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index cb640eb..b97a8cc 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -883,6 +883,17 @@
 		};
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+			linux,code = <116>; /* KEY_POWER */
+			gpio-key,wakeup;
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
-- 
1.8.3.1

[PATCH 11/11] ARM: dts: tegra114: dalmore: add PM configurations for PMC

[Joseph Lo]

Adding the PM configurations for PMC to support platform suspend.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/boot/dts/tegra114-dalmore.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index b97a8cc..625bf3a 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -850,6 +850,13 @@
 
 	pmc {
 		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <2>;
+		nvidia,cpu-pwr-good-time = <500>;
+		nvidia,cpu-pwr-off-time = <300>;
+		nvidia,core-pwr-good-time = <641 3845>;
+		nvidia,core-pwr-off-time = <61036>;
+		nvidia,core-power-req-active-high;
+		nvidia,sys-clock-req-active-high;
 	};
 
 	ahub {
-- 
1.8.3.1

[PATCH 09/11] ARM: tegar: remove the limitation that Tegra114 can't support suspend

[Thierry Reding]

There's a typo in the subject, it should be prefixed with "ARM: tegra:".

Thierry
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[PATCH 09/11] ARM: tegar: remove the limitation that Tegra114 can't support suspend

[Joseph Lo]

On Wed, 2013-06-26 at 18:48 +0800, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> There's a typo in the subject, it should be prefixed with "ARM: tegra:".
> 
Thanks for review.

[PATCH 09/11] ARM: tegar: remove the limitation that Tegra114 can't support suspend

[Stephen Warren]

On 06/26/2013 04:48 AM, Thierry Reding wrote:
> There's a typo in the subject, it should be prefixed with "ARM:
> tegra:".

Assuming there are no other issues, I can fix this up when applying.
If the series gets reposted, please do fix it.

[PATCH 02/11] ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS or ALL

[Stephen Warren]

On 06/25/2013 03:27 AM, Joseph Lo wrote:
> Adding a flag for tegra_disable_clean_inv_dcache to flush cache as LoUIS
> or ALL. After this patch, the v7_flush_dcache_louis is used for CPU hotplug
> and CPU suspend in CPU power down (e.g. CPU idle power-down mode) case. And
> the v7_flush_dcache_all is used for CPU cluster power down (e.g. suspend to
> LP2 mode).

> diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h

> +/* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
> +#define TEGRA_FLUSH_CACHE_LOUIS	0x10
> +#define TEGRA_FLUSH_CACHE_ALL	0x20

Is there a reason those two values aren't just 0 and 1; they only seem
to be used internally to switch between two function calls, and not
passed to those calls or written to HW.

[PATCH 05/11] ARM: tegra114: shut off the CPU rail when the last CPU in suspend

[Stephen Warren]

On 06/25/2013 03:27 AM, Joseph Lo wrote:
> When the last CPU core in suspend, the CPU power rail can be turned off
> by setting flags to flow controller. Then the flow controller will inform
> PMC to turn off the CPU rail when the last CPU goes into suspend.

> diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c

> +	/* Turn off CRAIL */
> +	if (tegra_chip_id == TEGRA114) {


Presumably this new code is needed on Tegra114 and chips after it, so
not needing it is the exception? If so, I'd suggest the following
instead, so the code doesn't have to be modified for later chips:

switch (tegra_chip_id) {
case TEGRA20:
case TEGRA30:
	break;
default:
	the code you added
	break;
}

[PATCH 08/11] clk: tegra114: add suspend/resume function for tegar_cpu_car_ops

[Stephen Warren]

On 06/25/2013 03:27 AM, Joseph Lo wrote:
> Adding suspend/resume function for tegra_cpu_car_ops. We only save and
> restore the setting of the clock of CoreSight. Other clocks still need
> to be taken care by clock driver.

Mike, can I get an ack to take this through the Tegra tree with the rest
of this series, for 3.12. Thanks.

(Nit: There's a typo in the patch subject here too.)

> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c

> +#ifdef CONFIG_PM_SLEEP
> +static void tegra114_cpu_clock_suspend(void)
> +{
> +	/* switch coresite to clk_m, save off original source */
> +	tegra114_cpu_clk_sctx.clk_csite_src =
> +				readl(clk_base + CLK_SOURCE_CSITE);
> +	writel(3<<30, clk_base + CLK_SOURCE_CSITE);

Don't you need spaces around the << to satisfy checkpatch/coding style?

[PATCH 09/11] ARM: tegar: remove the limitation that Tegra114 can't support suspend

[Stephen Warren]

On 06/25/2013 03:27 AM, Joseph Lo wrote:
> The Tegra114 can support suspend function now, removing the limitation.

OK, so this is the first point at which system suspend is enabled on
Tegra114. However, some of the changes in earlier patches sounded like
the might affect, or be required by, cpuidle too. Is that the case? If
so, can you assure me that bisectability of Tegra114 cpuidle is
maintained across this whole series?

[PATCH 09/11] ARM: tegar: remove the limitation that Tegra114 can't support suspend

[Joseph Lo]

On Thu, 2013-06-27 at 03:40 +0800, Stephen Warren wrote:
> On 06/25/2013 03:27 AM, Joseph Lo wrote:
> > The Tegra114 can support suspend function now, removing the limitation.
> 
> OK, so this is the first point at which system suspend is enabled on
> Tegra114. However, some of the changes in earlier patches sounded like
> the might affect, or be required by, cpuidle too. Is that the case? If
> so, can you assure me that bisectability of Tegra114 cpuidle is
> maintained across this whole series?

I think you mean one of the patches I changed the init sequence of CPU
idle driver and hook the "tegra_tear_down_cpu" in tegra_init_suspend
(under pm.c). I did that was for fixing the dependence of CPU idle and
suspend driver.

Because we upstreamed the CPU idle "powered-down" support first then
system suspend. So we hook the "tegra_tear_down_cpu" in CPU idle driver.
But it would cause the system suspend function fail when disabling
CPU_IDLE. After reorganizing the sequence, the system suspend is still
working after disabling CPU_IDLE. If the PM is disabled, the CPU idle
driver still supports at least WFI state.

So this series is OK with cpuidle driver. I had tested the previous
series (already merged in the branch for 3.11) is ok for Tegra20/30 as
well.

Thanks for take care.

[PATCH 02/11] ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS or ALL

[Joseph Lo]

On Thu, 2013-06-27 at 03:31 +0800, Stephen Warren wrote:
> On 06/25/2013 03:27 AM, Joseph Lo wrote:
> > Adding a flag for tegra_disable_clean_inv_dcache to flush cache as LoUIS
> > or ALL. After this patch, the v7_flush_dcache_louis is used for CPU hotplug
> > and CPU suspend in CPU power down (e.g. CPU idle power-down mode) case. And
> > the v7_flush_dcache_all is used for CPU cluster power down (e.g. suspend to
> > LP2 mode).
> 
> > diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
> 
> > +/* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
> > +#define TEGRA_FLUSH_CACHE_LOUIS	0x10
> > +#define TEGRA_FLUSH_CACHE_ALL	0x20
> 
> Is there a reason those two values aren't just 0 and 1; they only seem
> to be used internally to switch between two function calls, and not
> passed to those calls or written to HW.

No. Will fix.

[PATCH 05/11] ARM: tegra114: shut off the CPU rail when the last CPU in suspend

[Joseph Lo]

On Thu, 2013-06-27 at 03:36 +0800, Stephen Warren wrote:
> On 06/25/2013 03:27 AM, Joseph Lo wrote:
> > When the last CPU core in suspend, the CPU power rail can be turned off
> > by setting flags to flow controller. Then the flow controller will inform
> > PMC to turn off the CPU rail when the last CPU goes into suspend.
> 
> > diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
> 
> > +	/* Turn off CRAIL */
> > +	if (tegra_chip_id == TEGRA114) {
> 
> 
> Presumably this new code is needed on Tegra114 and chips after it, so
> not needing it is the exception? If so, I'd suggest the following
> instead, so the code doesn't have to be modified for later chips:
> 
> switch (tegra_chip_id) {
> case TEGRA20:
> case TEGRA30:
> 	break;
> default:
> 	the code you added
> 	break;
> }
> 

Indeed. Good idea. Will fix.

Thanks.

[PATCH 08/11] clk: tegra114: add suspend/resume function for tegar_cpu_car_ops

[Joseph Lo]

On Thu, 2013-06-27 at 03:38 +0800, Stephen Warren wrote:
> On 06/25/2013 03:27 AM, Joseph Lo wrote:
> > Adding suspend/resume function for tegra_cpu_car_ops. We only save and
> > restore the setting of the clock of CoreSight. Other clocks still need
> > to be taken care by clock driver.
> 
> Mike, can I get an ack to take this through the Tegra tree with the rest
> of this series, for 3.12. Thanks.
> 
> (Nit: There's a typo in the patch subject here too.)
> 
> > diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> 
> > +#ifdef CONFIG_PM_SLEEP
> > +static void tegra114_cpu_clock_suspend(void)
> > +{
> > +	/* switch coresite to clk_m, save off original source */
> > +	tegra114_cpu_clk_sctx.clk_csite_src =
> > +				readl(clk_base + CLK_SOURCE_CSITE);
> > +	writel(3<<30, clk_base + CLK_SOURCE_CSITE);
> 
> Don't you need spaces around the << to satisfy checkpatch/coding style?

It didn't cause a warning by checkpatch. But I will fix it in next
version.

Thanks.

[PATCH 06/11] ARM: tegra114: hook tegra_tear_down_cpu function

[Thierry Reding]

On Tue, Jun 25, 2013 at 05:27:50PM +0800, Joseph Lo wrote:
> Hooking tegra_tear_down_cpu for Tegra114 for supporting cluster power
> down when CPU cluster suspneded in LP2.
> 
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> ---
>  arch/arm/mach-tegra/pm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
> index 94e69be..a0668a2 100644
> --- a/arch/arm/mach-tegra/pm.c
> +++ b/arch/arm/mach-tegra/pm.c
> @@ -52,6 +52,7 @@ static void tegra_tear_down_cpu_init(void)
>  			tegra_tear_down_cpu = tegra20_tear_down_cpu;
>  		break;
>  	case TEGRA30:
> +	case TEGRA114:
>  		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
>  			tegra_tear_down_cpu = tegra30_tear_down_cpu;

This is getting a little weird. Suppose I want to build a Tegra114 only
kernel. With the above code it means the tegra_tear_down_cpu won't be
hooked because ARCH_TEGRA_3x_SOC isn't selected.

Perhaps tegra30_tear_down_cpu() should be built unconditionally so that
it's always available? I suspect that something similar will need to be
done for future chips too, further complicating matters.

There are other alternatives like adding another Kconfig symbol which
doesn't cover all of Tegra30 but only code shared with Tegra114 (and
possible future chips) or building sleep-tegra30.S if either one of the
ARCH_TEGRA_3x_SOC or ARCH_TEGRA_114_SOC symbols is selected.

Thierry
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[PATCH 06/11] ARM: tegra114: hook tegra_tear_down_cpu function

[Joseph Lo]

On Thu, 2013-06-27 at 18:13 +0800, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Tue, Jun 25, 2013 at 05:27:50PM +0800, Joseph Lo wrote:
> > Hooking tegra_tear_down_cpu for Tegra114 for supporting cluster power
> > down when CPU cluster suspneded in LP2.
> > 
> > Signed-off-by: Joseph Lo <josephl@nvidia.com>
> > ---
> >  arch/arm/mach-tegra/pm.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
> > index 94e69be..a0668a2 100644
> > --- a/arch/arm/mach-tegra/pm.c
> > +++ b/arch/arm/mach-tegra/pm.c
> > @@ -52,6 +52,7 @@ static void tegra_tear_down_cpu_init(void)
> >  			tegra_tear_down_cpu = tegra20_tear_down_cpu;
> >  		break;
> >  	case TEGRA30:
> > +	case TEGRA114:
> >  		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
> >  			tegra_tear_down_cpu = tegra30_tear_down_cpu;
> 
> This is getting a little weird. Suppose I want to build a Tegra114 only
> kernel. With the above code it means the tegra_tear_down_cpu won't be
> hooked because ARCH_TEGRA_3x_SOC isn't selected.
> 
Oops. You are right. Will fix.

> Perhaps tegra30_tear_down_cpu() should be built unconditionally so that
> it's always available?
The tegra30_tear_down_cpu will be built for both Tegra30 or Tegra114.

> 
> There are other alternatives like adding another Kconfig symbol which
> doesn't cover all of Tegra30 but only code shared with Tegra114 (and
> possible future chips) or building sleep-tegra30.S if either one of the
> ARCH_TEGRA_3x_SOC or ARCH_TEGRA_114_SOC symbols is selected.
> 
Yes, we building "sleep-tegra30.S" when either one of the
ARCH_TEGRA_3x_SOC or ARCH_TEGRA_114_SOC symbols is selected.

Thanks,
Joseph

[PATCH 06/11] ARM: tegra114: hook tegra_tear_down_cpu function

[Stephen Warren]

On 06/27/2013 04:13 AM, Thierry Reding wrote:
> On Tue, Jun 25, 2013 at 05:27:50PM +0800, Joseph Lo wrote:
>> Hooking tegra_tear_down_cpu for Tegra114 for supporting cluster
>> power down when CPU cluster suspneded in LP2.
>> 
>> Signed-off-by: Joseph Lo <josephl@nvidia.com> --- 
>> arch/arm/mach-tegra/pm.c | 1 + 1 file changed, 1 insertion(+)
>> 
>> diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c 
>> index 94e69be..a0668a2 100644 --- a/arch/arm/mach-tegra/pm.c +++
>> b/arch/arm/mach-tegra/pm.c @@ -52,6 +52,7 @@ static void
>> tegra_tear_down_cpu_init(void) tegra_tear_down_cpu =
>> tegra20_tear_down_cpu; break; case TEGRA30: +	case TEGRA114: if
>> (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) tegra_tear_down_cpu =
>> tegra30_tear_down_cpu;
> 
> This is getting a little weird. Suppose I want to build a Tegra114
> only kernel. With the above code it means the tegra_tear_down_cpu
> won't be hooked because ARCH_TEGRA_3x_SOC isn't selected.
> 
> Perhaps tegra30_tear_down_cpu() should be built unconditionally so
> that it's always available? I suspect that something similar will
> need to be done for future chips too, further complicating
> matters.
> 
> There are other alternatives like adding another Kconfig symbol
> which doesn't cover all of Tegra30 but only code shared with
> Tegra114 (and possible future chips) or building sleep-tegra30.S if
> either one of the ARCH_TEGRA_3x_SOC or ARCH_TEGRA_114_SOC symbols
> is selected.

To be honest, I wonder if we should just get rid of ARCH_TEGRA_*_SOC,
and build everything if ARCH_TEGRA is defined. tegra_defconfig enables
all ARCH_TEGRA_*_SOC anyway, and I'm afraid I don't test other
configurations very often, and I assume that distros will enable
everything...

[PATCH 06/11] ARM: tegra114: hook tegra_tear_down_cpu function

[Thierry Reding]

On Thu, Jun 27, 2013 at 11:48:49AM -0600, Stephen Warren wrote:
> On 06/27/2013 04:13 AM, Thierry Reding wrote:
> > On Tue, Jun 25, 2013 at 05:27:50PM +0800, Joseph Lo wrote:
> >> Hooking tegra_tear_down_cpu for Tegra114 for supporting cluster
> >> power down when CPU cluster suspneded in LP2.
> >> 
> >> Signed-off-by: Joseph Lo <josephl@nvidia.com> --- 
> >> arch/arm/mach-tegra/pm.c | 1 + 1 file changed, 1 insertion(+)
> >> 
> >> diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c 
> >> index 94e69be..a0668a2 100644 --- a/arch/arm/mach-tegra/pm.c +++
> >> b/arch/arm/mach-tegra/pm.c @@ -52,6 +52,7 @@ static void
> >> tegra_tear_down_cpu_init(void) tegra_tear_down_cpu =
> >> tegra20_tear_down_cpu; break; case TEGRA30: +	case TEGRA114: if
> >> (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) tegra_tear_down_cpu =
> >> tegra30_tear_down_cpu;
> > 
> > This is getting a little weird. Suppose I want to build a Tegra114
> > only kernel. With the above code it means the tegra_tear_down_cpu
> > won't be hooked because ARCH_TEGRA_3x_SOC isn't selected.
> > 
> > Perhaps tegra30_tear_down_cpu() should be built unconditionally so
> > that it's always available? I suspect that something similar will
> > need to be done for future chips too, further complicating
> > matters.
> > 
> > There are other alternatives like adding another Kconfig symbol
> > which doesn't cover all of Tegra30 but only code shared with
> > Tegra114 (and possible future chips) or building sleep-tegra30.S if
> > either one of the ARCH_TEGRA_3x_SOC or ARCH_TEGRA_114_SOC symbols
> > is selected.
> 
> To be honest, I wonder if we should just get rid of ARCH_TEGRA_*_SOC,
> and build everything if ARCH_TEGRA is defined. tegra_defconfig enables
> all ARCH_TEGRA_*_SOC anyway, and I'm afraid I don't test other
> configurations very often, and I assume that distros will enable
> everything...

The same thing had occurred to me as well. Obviously there could be some
savings in executable code for people that really only need one specific
generation. But, without having any concrete numbers, I suspect that all
the ARCH_TEGRA code is less than 100 KiB in total so I don't think it
matters that much given that there aren't any devices with less than 256
MiB of RAM (that I've heard of at least).

Thierry
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[PATCH 08/11] clk: tegra114: add suspend/resume function for tegar_cpu_car_ops

[Mike Turquette]

Quoting Joseph Lo (2013-06-25 02:27:52)
> Adding suspend/resume function for tegra_cpu_car_ops. We only save and
> restore the setting of the clock of CoreSight. Other clocks still need
> to be taken care by clock driver.
> 
> Cc: Mike Turquette <mturquette@linaro.org>
> Signed-off-by: Joseph Lo <josephl@nvidia.com>

Change looks OK to me, besides Stephen's comments. I was waiting for a
V2 to hit the list but I never saw it. Any plans?

Regards,
Mike

> ---
>  drivers/clk/tegra/clk-tegra114.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index dbd0428..cd51d75 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -258,6 +258,12 @@
>  #define PMC_PLLM_WB0_OVERRIDE 0x1dc
>  #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
>  
> +#ifdef CONFIG_PM_SLEEP
> +static struct cpu_clk_suspend_context {
> +       u32 clk_csite_src;
> +} tegra114_cpu_clk_sctx;
> +#endif
> +
>  static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
>  
>  static void __iomem *clk_base;
> @@ -2107,9 +2113,29 @@ static void tegra114_disable_cpu_clock(u32 cpu)
>         /* flow controller would take care in the power sequence. */
>  }
>  
> +#ifdef CONFIG_PM_SLEEP
> +static void tegra114_cpu_clock_suspend(void)
> +{
> +       /* switch coresite to clk_m, save off original source */
> +       tegra114_cpu_clk_sctx.clk_csite_src =
> +                               readl(clk_base + CLK_SOURCE_CSITE);
> +       writel(3<<30, clk_base + CLK_SOURCE_CSITE);
> +}
> +
> +static void tegra114_cpu_clock_resume(void)
> +{
> +       writel(tegra114_cpu_clk_sctx.clk_csite_src,
> +                                       clk_base + CLK_SOURCE_CSITE);
> +}
> +#endif
> +
>  static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
>         .wait_for_reset = tegra114_wait_cpu_in_reset,
>         .disable_clock  = tegra114_disable_cpu_clock,
> +#ifdef CONFIG_PM_SLEEP
> +       .suspend        = tegra114_cpu_clock_suspend,
> +       .resume         = tegra114_cpu_clock_resume,
> +#endif
>  };
>  
>  static const struct of_device_id pmc_match[] __initconst = {
> -- 
> 1.8.3.1

[PATCH 08/11] clk: tegra114: add suspend/resume function for tegar_cpu_car_ops

[Joseph Lo]

On Wed, 2013-07-31 at 05:21 +0800, Mike Turquette wrote:
> Quoting Joseph Lo (2013-06-25 02:27:52)
> > Adding suspend/resume function for tegra_cpu_car_ops. We only save and
> > restore the setting of the clock of CoreSight. Other clocks still need
> > to be taken care by clock driver.
> > 
> > Cc: Mike Turquette <mturquette@linaro.org>
> > Signed-off-by: Joseph Lo <josephl@nvidia.com>
> 
> Change looks OK to me, besides Stephen's comments. I was waiting for a
> V2 to hit the list but I never saw it. Any plans?
> 
Hi Mike,

The V2 was sent on 2013/7/3.

Thanks,
Joseph

[PATCH 08/11] clk: tegra114: add suspend/resume function for tegar_cpu_car_ops

[Mike Turquette]

On Tue, Jul 30, 2013 at 7:27 PM, Joseph Lo <josephl@nvidia.com> wrote:
> On Wed, 2013-07-31 at 05:21 +0800, Mike Turquette wrote:
>> Quoting Joseph Lo (2013-06-25 02:27:52)
>> > Adding suspend/resume function for tegra_cpu_car_ops. We only save and
>> > restore the setting of the clock of CoreSight. Other clocks still need
>> > to be taken care by clock driver.
>> >
>> > Cc: Mike Turquette <mturquette@linaro.org>
>> > Signed-off-by: Joseph Lo <josephl@nvidia.com>
>>
>> Change looks OK to me, besides Stephen's comments. I was waiting for a
>> V2 to hit the list but I never saw it. Any plans?
>>
> Hi Mike,
>
> The V2 was sent on 2013/7/3.

Ok, looks like Stephen took it into his branch.

Thanks,
Mike

>
> Thanks,
> Joseph
>
>