[PATCHv5 00/31] CLK: OMAP conversion to DT

[PATCHv5 00/31] CLK: OMAP conversion to DT

[Tero Kristo]

Hi,

This set mainly fixes comments received from Nishanth Menon for v4.
AM43xx + AM35xx clock data was added as new feature, also OMAP3
platforms use either the old style kernel clock data or DT data,
based on boot type.

Testing done:

omap3 beagle : boot, suspend / resume
omap4 panda es: boot, suspend / resume
omap5 sevm: boot
am335x bone: boot

Branch available here:
git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
branch: mainline-3.11-rc3-omap-dt-clks-v5

-Tero

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Tero Kristo]

clk_get_sys / clk_get can now find clocks from device-tree. If a DT clock
is found, an entry is added to the clk_lookup list also for subsequent
searches.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
---
 drivers/clk/clkdev.c |   33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 442a313..cbeb252 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -93,6 +93,18 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
 EXPORT_SYMBOL(of_clk_get_by_name);
 #endif
 
+/**
+ * clkdev_add_nolock - add lookup entry for a clock
+ * @cl: pointer to new clock lookup entry
+ *
+ * Non-locking version, used internally by clk_find() to add DT based
+ * clock lookup entries.
+ */
+static void clkdev_add_nolock(struct clk_lookup *cl)
+{
+	list_add_tail(&cl->node, &clocks);
+}
+
 /*
  * Find the correct struct clk for the device and connection ID.
  * We do slightly fuzzy matching here:
@@ -106,6 +118,9 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
 {
 	struct clk_lookup *p, *cl = NULL;
 	int match, best_found = 0, best_possible = 0;
+	struct device_node *node;
+	struct clk *clk;
+	struct of_phandle_args clkspec;
 
 	if (dev_id)
 		best_possible += 2;
@@ -133,6 +148,24 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
 				break;
 		}
 	}
+
+	if (cl)
+		return cl;
+
+	/* If clock was not found, attempt to look-up from DT */
+	node = of_find_node_by_name(NULL, con_id);
+
+	clkspec.np = node;
+
+	clk = of_clk_get_from_provider(&clkspec);
+
+	if (!IS_ERR(clk)) {
+		/* We found a clock, add node to clkdev */
+		cl = clkdev_alloc(clk, con_id, dev_id);
+		if (cl)
+			clkdev_add_nolock(cl);
+	}
+
 	return cl;
 }
 
-- 
1.7.9.5

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Tomasz Figa]

Hi Tero,

On Friday 02 of August 2013 19:25:20 Tero Kristo wrote:
> clk_get_sys / clk_get can now find clocks from device-tree. If a DT
> clock is found, an entry is added to the clk_lookup list also for
> subsequent searches.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> ---
>  drivers/clk/clkdev.c |   33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
> index 442a313..cbeb252 100644
> --- a/drivers/clk/clkdev.c
> +++ b/drivers/clk/clkdev.c
> @@ -93,6 +93,18 @@ struct clk *of_clk_get_by_name(struct device_node
> *np, const char *name) EXPORT_SYMBOL(of_clk_get_by_name);
>  #endif
> 
> +/**
> + * clkdev_add_nolock - add lookup entry for a clock
> + * @cl: pointer to new clock lookup entry
> + *
> + * Non-locking version, used internally by clk_find() to add DT based
> + * clock lookup entries.
> + */
> +static void clkdev_add_nolock(struct clk_lookup *cl)
> +{
> +	list_add_tail(&cl->node, &clocks);
> +}
> +
>  /*
>   * Find the correct struct clk for the device and connection ID.
>   * We do slightly fuzzy matching here:
> @@ -106,6 +118,9 @@ static struct clk_lookup *clk_find(const char
> *dev_id, const char *con_id) {
>  	struct clk_lookup *p, *cl = NULL;
>  	int match, best_found = 0, best_possible = 0;
> +	struct device_node *node;
> +	struct clk *clk;
> +	struct of_phandle_args clkspec;
> 
>  	if (dev_id)
>  		best_possible += 2;
> @@ -133,6 +148,24 @@ static struct clk_lookup *clk_find(const char
> *dev_id, const char *con_id) break;
>  		}
>  	}
> +
> +	if (cl)
> +		return cl;
> +
> +	/* If clock was not found, attempt to look-up from DT */
> +	node = of_find_node_by_name(NULL, con_id);

Why are we introducing the "lookup by name" brokenness to the yet (mostly) 
sane DT world?

We already have a good way of binding things together in DT, which is 
using phandles.

Not even saying that this (or something this patch relies on) breaks the 
ePAPR recommendation about node naming, which states that node names 
should not be used to convey platform-specific data, but instead should be 
as generic as possible to show what kind of hardware is represented by the 
node.

Best regards,
Tomasz

P.S. Added missing DT maintainers to CC.

> +	clkspec.np = node;
> +
> +	clk = of_clk_get_from_provider(&clkspec);
> +
> +	if (!IS_ERR(clk)) {
> +		/* We found a clock, add node to clkdev */
> +		cl = clkdev_alloc(clk, con_id, dev_id);
> +		if (cl)
> +			clkdev_add_nolock(cl);
> +	}
> +
>  	return cl;
>  }

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Russell King - ARM Linux]

On Sat, Aug 03, 2013 at 04:02:36PM +0200, Tomasz Figa wrote:
> > +	if (cl)
> > +		return cl;
> > +
> > +	/* If clock was not found, attempt to look-up from DT */
> > +	node = of_find_node_by_name(NULL, con_id);
> 
> Why are we introducing the "lookup by name" brokenness to the yet (mostly) 
> sane DT world?
> 
> We already have a good way of binding things together in DT, which is 
> using phandles.
> 
> Not even saying that this (or something this patch relies on) breaks the 
> ePAPR recommendation about node naming, which states that node names 
> should not be used to convey platform-specific data, but instead should be 
> as generic as possible to show what kind of hardware is represented by the 
> node.

Tell me this: many devices name their clock inputs.  You can find these
input names in data sheets and the like.  These are the names defined
by the hardware.  What is wrong about using those names in DT?

Remember that the second argument to clk_get() is the _clock_ _input_
_name_ on the _device_ passed in the first argument.  It is not *ever*
some random name of the clock producer unless someone's fscked up their
use of this API (in which case they're the ones with the problem.)

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Tomasz Figa]

Hi Russell,

On Saturday 03 of August 2013 19:35:43 Russell King - ARM Linux wrote:
> On Sat, Aug 03, 2013 at 04:02:36PM +0200, Tomasz Figa wrote:
> > > +	if (cl)
> > > +		return cl;
> > > +
> > > +	/* If clock was not found, attempt to look-up from DT */
> > > +	node = of_find_node_by_name(NULL, con_id);
> > 
> > Why are we introducing the "lookup by name" brokenness to the yet
> > (mostly) sane DT world?
> > 
> > We already have a good way of binding things together in DT, which is
> > using phandles.
> > 
> > Not even saying that this (or something this patch relies on) breaks
> > the ePAPR recommendation about node naming, which states that node
> > names should not be used to convey platform-specific data, but
> > instead should be as generic as possible to show what kind of
> > hardware is represented by the node.
> 
> Tell me this: many devices name their clock inputs.  You can find these
> input names in data sheets and the like.  These are the names defined
> by the hardware.  What is wrong about using those names in DT?

Yes, clock inputs. But this is about lookup by clock name, not clock input 
name, as far as I can tell from the patch, based on looking for a node 
with given name over the whole DT.

> Remember that the second argument to clk_get() is the _clock_ _input_
> _name_ on the _device_ passed in the first argument.  It is not *ever*
> some random name of the clock producer unless someone's fscked up their
> use of this API (in which case they're the ones with the problem.)

This is perfectly fine and this is how the generic common clock framework 
DT bindings work - clock-names property is a list of clock input names and 
clocks property contain specifiers of respective clocks.

Best regards,
Tomasz

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Russell King - ARM Linux]

On Sat, Aug 03, 2013 at 08:39:34PM +0200, Tomasz Figa wrote:
> Hi Russell,
> 
> On Saturday 03 of August 2013 19:35:43 Russell King - ARM Linux wrote:
> > On Sat, Aug 03, 2013 at 04:02:36PM +0200, Tomasz Figa wrote:
> > > > +	if (cl)
> > > > +		return cl;
> > > > +
> > > > +	/* If clock was not found, attempt to look-up from DT */
> > > > +	node = of_find_node_by_name(NULL, con_id);
> > > 
> > > Why are we introducing the "lookup by name" brokenness to the yet
> > > (mostly) sane DT world?
> > > 
> > > We already have a good way of binding things together in DT, which is
> > > using phandles.
> > > 
> > > Not even saying that this (or something this patch relies on) breaks
> > > the ePAPR recommendation about node naming, which states that node
> > > names should not be used to convey platform-specific data, but
> > > instead should be as generic as possible to show what kind of
> > > hardware is represented by the node.
> > 
> > Tell me this: many devices name their clock inputs.  You can find these
> > input names in data sheets and the like.  These are the names defined
> > by the hardware.  What is wrong about using those names in DT?
> 
> Yes, clock inputs. But this is about lookup by clock name, not clock input 
> name, as far as I can tell from the patch, based on looking for a node 
> with given name over the whole DT.

"con_id" is supposed to be the clock input name when the clock API is
used correctly.

> > Remember that the second argument to clk_get() is the _clock_ _input_
> > _name_ on the _device_ passed in the first argument.  It is not *ever*
> > some random name of the clock producer unless someone's fscked up their
> > use of this API (in which case they're the ones with the problem.)
> 
> This is perfectly fine and this is how the generic common clock framework 
> DT bindings work - clock-names property is a list of clock input names and 
> clocks property contain specifiers of respective clocks.

There seems to be a some pressure to do clk_get()->of_clk_get()
conversions, and also to find ways to lookup clocks.  It seems to me
that no one understands how DT handles clocks.  Maybe that's where the
problem is - lack of documentation about how DT clocks are handled.

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Tomasz Figa]

On Saturday 03 of August 2013 19:48:05 Russell King - ARM Linux wrote:
> On Sat, Aug 03, 2013 at 08:39:34PM +0200, Tomasz Figa wrote:
> > Hi Russell,
> > 
> > On Saturday 03 of August 2013 19:35:43 Russell King - ARM Linux wrote:
> > > On Sat, Aug 03, 2013 at 04:02:36PM +0200, Tomasz Figa wrote:
> > > > > +	if (cl)
> > > > > +		return cl;
> > > > > +
> > > > > +	/* If clock was not found, attempt to look-up from DT */
> > > > > +	node = of_find_node_by_name(NULL, con_id);
> > > > 
> > > > Why are we introducing the "lookup by name" brokenness to the yet
> > > > (mostly) sane DT world?
> > > > 
> > > > We already have a good way of binding things together in DT, which
> > > > is
> > > > using phandles.
> > > > 
> > > > Not even saying that this (or something this patch relies on)
> > > > breaks
> > > > the ePAPR recommendation about node naming, which states that node
> > > > names should not be used to convey platform-specific data, but
> > > > instead should be as generic as possible to show what kind of
> > > > hardware is represented by the node.
> > > 
> > > Tell me this: many devices name their clock inputs.  You can find
> > > these
> > > input names in data sheets and the like.  These are the names
> > > defined
> > > by the hardware.  What is wrong about using those names in DT?
> > 
> > Yes, clock inputs. But this is about lookup by clock name, not clock
> > input name, as far as I can tell from the patch, based on looking for
> > a node with given name over the whole DT.
> 
> "con_id" is supposed to be the clock input name when the clock API is
> used correctly.

Right. Still, the code is looking for a node with the same name as the 
supposed input name, which seems strange to me, because clock input names 
are supposed to be defined in consumer's node, inside clock-names 
property.

> > > Remember that the second argument to clk_get() is the _clock_
> > > _input_
> > > _name_ on the _device_ passed in the first argument.  It is not
> > > *ever*
> > > some random name of the clock producer unless someone's fscked up
> > > their
> > > use of this API (in which case they're the ones with the problem.)
> > 
> > This is perfectly fine and this is how the generic common clock
> > framework DT bindings work - clock-names property is a list of clock
> > input names and clocks property contain specifiers of respective
> > clocks.
> 
> There seems to be a some pressure to do clk_get()->of_clk_get()
> conversions, and also to find ways to lookup clocks.

I don't really see any need for this kind of conversion. clk_get() already 
handles lookup using DT correctly and from drivers perspective nothing 
changes.

> It seems to me
> that no one understands how DT handles clocks.  Maybe that's where the
> problem is - lack of documentation about how DT clocks are handled.

Hmm, there is pretty much of description and examples in

Documentation/devicetree/bindings/clock/clock-bindings.txt

For me it was enough to learn how DT based clock lookup works, but I'm 
quite used to DT, so I'm not a good test sample.

Best regards,
Tomasz

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Tero Kristo]

Hey,

(Sorry was out for a short vacation, thus late reply.)

On 08/03/2013 10:04 PM, Tomasz Figa wrote:
> On Saturday 03 of August 2013 19:48:05 Russell King - ARM Linux wrote:
>> On Sat, Aug 03, 2013 at 08:39:34PM +0200, Tomasz Figa wrote:
>>> Hi Russell,
>>>
>>> On Saturday 03 of August 2013 19:35:43 Russell King - ARM Linux wrote:
>>>> On Sat, Aug 03, 2013 at 04:02:36PM +0200, Tomasz Figa wrote:
>>>>>> +	if (cl)
>>>>>> +		return cl;
>>>>>> +
>>>>>> +	/* If clock was not found, attempt to look-up from DT */
>>>>>> +	node = of_find_node_by_name(NULL, con_id);
>>>>>
>>>>> Why are we introducing the "lookup by name" brokenness to the yet
>>>>> (mostly) sane DT world?
>>>>>
>>>>> We already have a good way of binding things together in DT, which
>>>>> is
>>>>> using phandles.
>>>>>
>>>>> Not even saying that this (or something this patch relies on)
>>>>> breaks
>>>>> the ePAPR recommendation about node naming, which states that node
>>>>> names should not be used to convey platform-specific data, but
>>>>> instead should be as generic as possible to show what kind of
>>>>> hardware is represented by the node.
>>>>
>>>> Tell me this: many devices name their clock inputs.  You can find
>>>> these
>>>> input names in data sheets and the like.  These are the names
>>>> defined
>>>> by the hardware.  What is wrong about using those names in DT?
>>>
>>> Yes, clock inputs. But this is about lookup by clock name, not clock
>>> input name, as far as I can tell from the patch, based on looking for
>>> a node with given name over the whole DT.
>>
>> "con_id" is supposed to be the clock input name when the clock API is
>> used correctly.
>
> Right. Still, the code is looking for a node with the same name as the
> supposed input name, which seems strange to me, because clock input names
> are supposed to be defined in consumer's node, inside clock-names
> property.
>
>>>> Remember that the second argument to clk_get() is the _clock_
>>>> _input_
>>>> _name_ on the _device_ passed in the first argument.  It is not
>>>> *ever*
>>>> some random name of the clock producer unless someone's fscked up
>>>> their
>>>> use of this API (in which case they're the ones with the problem.)
>>>
>>> This is perfectly fine and this is how the generic common clock
>>> framework DT bindings work - clock-names property is a list of clock
>>> input names and clocks property contain specifiers of respective
>>> clocks.
>>
>> There seems to be a some pressure to do clk_get()->of_clk_get()
>> conversions, and also to find ways to lookup clocks.
>
> I don't really see any need for this kind of conversion. clk_get() already
> handles lookup using DT correctly and from drivers perspective nothing
> changes.
>
>> It seems to me
>> that no one understands how DT handles clocks.  Maybe that's where the
>> problem is - lack of documentation about how DT clocks are handled.
>
> Hmm, there is pretty much of description and examples in
>
> Documentation/devicetree/bindings/clock/clock-bindings.txt
>
> For me it was enough to learn how DT based clock lookup works, but I'm
> quite used to DT, so I'm not a good test sample.
>
> Best regards,
> Tomasz
>

I think based on these comments this patch needs to go away, I will have 
to find another way to map the devices in and to avoid supporting the 
legacy mappings (hwmod depends on this heavily atm, but Rajendra posted 
some patches to address this.) I'll see what I can do for next rev. I 
might implement some tweak inside the OMAP codebase for this.

-Tero

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Russell King - ARM Linux]

On Fri, Aug 02, 2013 at 07:25:20PM +0300, Tero Kristo wrote:
> +
> +	if (cl)
> +		return cl;
> +
> +	/* If clock was not found, attempt to look-up from DT */
> +	node = of_find_node_by_name(NULL, con_id);

This is utterly broken if you're looking up purely by a connection ID.
Please, go back and read clk_get()'s documentation in linux/clk.h.
It's spelt out very plainly there.

NAK.

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Tero Kristo]

On 08/03/2013 09:31 PM, Russell King - ARM Linux wrote:
> On Fri, Aug 02, 2013 at 07:25:20PM +0300, Tero Kristo wrote:
>> +
>> +	if (cl)
>> +		return cl;
>> +
>> +	/* If clock was not found, attempt to look-up from DT */
>> +	node = of_find_node_by_name(NULL, con_id);
>
> This is utterly broken if you're looking up purely by a connection ID.
> Please, go back and read clk_get()'s documentation in linux/clk.h.
> It's spelt out very plainly there.
>
> NAK.
>

Hi Russell,

After looking at this a bit more, it seems difficult to get rid of the 
clk_get -> of_clk_get conversion, however based on this comment I am 
somewhat stuck. Do you think it would be acceptable if I change the 
implementation of this patch to work like this:

1) both dev_id + con_id defined:
    a) search for device node named dev_id
    b) check clock-names for matching con_id
    c) return matching clock

    Example in kernel:
       clocksource-nomadik-mtu.c :
           clk_get_sys("mtu0", "apb_pclk");

       ste-nomadik-snt8815.dts:
         mtu0: mtu at 101e2000 {
                 /* Nomadik system timer */
                 compatible = "st,nomadik-mtu";
                 reg = <0x101e2000 0x1000>;
                 interrupt-parent = <&vica>;
                 interrupts = <4>;
                 clocks = <&timclk>, <&pclk>;
                 clock-names = "timclk", "apb_pclk";
         };

2) dev_id = NULL, con_id defined (current patch implementation, most of 
the OMAP clocks use this approach):
    a) search for a device node named con_id
    b) return corresponding clock from the node

Alternatively I must implement a regression and break some of the OMAP 
drivers with this set, and also implement omap internal clk_get 
functionality (basically adding a similar wrapper that I have 
implemented in this patch) under mach-omap2 to get some basic OMAP infra 
to work properly (namely, hwmod.) I can probably avoid part of this by 
adding more beef to the *.dts files for the critical parts to get boot 
working at least.

-Tero

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Russell King - ARM Linux]

On Mon, Aug 26, 2013 at 05:36:15PM +0300, Tero Kristo wrote:
> On 08/03/2013 09:31 PM, Russell King - ARM Linux wrote:
>> On Fri, Aug 02, 2013 at 07:25:20PM +0300, Tero Kristo wrote:
>>> +
>>> +	if (cl)
>>> +		return cl;
>>> +
>>> +	/* If clock was not found, attempt to look-up from DT */
>>> +	node = of_find_node_by_name(NULL, con_id);
>>
>> This is utterly broken if you're looking up purely by a connection ID.
>> Please, go back and read clk_get()'s documentation in linux/clk.h.
>> It's spelt out very plainly there.
>>
>> NAK.
>>
>
> Hi Russell,
>
> After looking at this a bit more, it seems difficult to get rid of the  
> clk_get -> of_clk_get conversion, however based on this comment I am  
> somewhat stuck. Do you think it would be acceptable if I change the  
> implementation of this patch to work like this:

Firstly, for clk_get(), you don't need to do anything - clk_get() already
deals with DT, and if your DT is correct, it should already be returning
the appropriate clock(s).

I guess the problem here is clk_get_sys(), because that doesn't take a
struct device (and it doesn't take a struct device because it's used
from code where there is no struct device to use with it.)

If you have an OF node, what's wrong with using of_clk_get_by_name()?
If you don't have an OF node, how do you expect to find the clock in
the device tree, remembering that clocks are specific to devices, and
the 2nd argument to clk_get()/clk_get_sys() is not a unique identifier.

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Tero Kristo]

On 08/26/2013 08:03 PM, Russell King - ARM Linux wrote:
> On Mon, Aug 26, 2013 at 05:36:15PM +0300, Tero Kristo wrote:
>> On 08/03/2013 09:31 PM, Russell King - ARM Linux wrote:
>>> On Fri, Aug 02, 2013 at 07:25:20PM +0300, Tero Kristo wrote:
>>>> +
>>>> +	if (cl)
>>>> +		return cl;
>>>> +
>>>> +	/* If clock was not found, attempt to look-up from DT */
>>>> +	node = of_find_node_by_name(NULL, con_id);
>>>
>>> This is utterly broken if you're looking up purely by a connection ID.
>>> Please, go back and read clk_get()'s documentation in linux/clk.h.
>>> It's spelt out very plainly there.
>>>
>>> NAK.
>>>
>>
>> Hi Russell,
>>
>> After looking at this a bit more, it seems difficult to get rid of the
>> clk_get -> of_clk_get conversion, however based on this comment I am
>> somewhat stuck. Do you think it would be acceptable if I change the
>> implementation of this patch to work like this:
>
> Firstly, for clk_get(), you don't need to do anything - clk_get() already
> deals with DT, and if your DT is correct, it should already be returning
> the appropriate clock(s).
>
> I guess the problem here is clk_get_sys(), because that doesn't take a
> struct device (and it doesn't take a struct device because it's used
> from code where there is no struct device to use with it.)

Yeah, most of the OMAP clocks have been traditionally referenced in this 
way, they are using clk_get_sys and with dev=NULL. conn-id is mostly unique.

>
> If you have an OF node, what's wrong with using of_clk_get_by_name()?
> If you don't have an OF node, how do you expect to find the clock in
> the device tree, remembering that clocks are specific to devices, and
> the 2nd argument to clk_get()/clk_get_sys() is not a unique identifier.

In the legacy code, pretty much all the clocks are mapped through 
clk_get_sys(NULL, conn), and large amount of the drivers don't even have 
DT conversion in place yet. I am attempting to handle the cases where we 
don't have OF nodes.... yet at least, without converting everything to 
DT, and without causing regressions (also, I don't even pretend to be 
capable of testing all the potential drivers for this.) Some parts of 
the basic infra which are using clk_get_sys are pretty silly also, like 
the ocp_if parts of the hwmod, I haven't figured out yet how to convert 
that to DT.

Personally I don't mind causing a regressions here though, if I get 
approval for it from Tony.

-Tero

[PATCHv5 01/31] CLK: clkdev: add support for looking up clocks from DT

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [130826 11:19]:
> On 08/26/2013 08:03 PM, Russell King - ARM Linux wrote:
> >On Mon, Aug 26, 2013 at 05:36:15PM +0300, Tero Kristo wrote:
> >>On 08/03/2013 09:31 PM, Russell King - ARM Linux wrote:
> >>>On Fri, Aug 02, 2013 at 07:25:20PM +0300, Tero Kristo wrote:
> >>>>+
> >>>>+	if (cl)
> >>>>+		return cl;
> >>>>+
> >>>>+	/* If clock was not found, attempt to look-up from DT */
> >>>>+	node = of_find_node_by_name(NULL, con_id);
> >>>
> >>>This is utterly broken if you're looking up purely by a connection ID.
> >>>Please, go back and read clk_get()'s documentation in linux/clk.h.
> >>>It's spelt out very plainly there.
> >>>
> >>>NAK.
> >>>
> >>
> >>Hi Russell,
> >>
> >>After looking at this a bit more, it seems difficult to get rid of the
> >>clk_get -> of_clk_get conversion, however based on this comment I am
> >>somewhat stuck. Do you think it would be acceptable if I change the
> >>implementation of this patch to work like this:
> >
> >Firstly, for clk_get(), you don't need to do anything - clk_get() already
> >deals with DT, and if your DT is correct, it should already be returning
> >the appropriate clock(s).
> >
> >I guess the problem here is clk_get_sys(), because that doesn't take a
> >struct device (and it doesn't take a struct device because it's used
> >from code where there is no struct device to use with it.)
> 
> Yeah, most of the OMAP clocks have been traditionally referenced in
> this way, they are using clk_get_sys and with dev=NULL. conn-id is
> mostly unique.
> 
> >
> >If you have an OF node, what's wrong with using of_clk_get_by_name()?
> >If you don't have an OF node, how do you expect to find the clock in
> >the device tree, remembering that clocks are specific to devices, and
> >the 2nd argument to clk_get()/clk_get_sys() is not a unique identifier.
> 
> In the legacy code, pretty much all the clocks are mapped through
> clk_get_sys(NULL, conn), and large amount of the drivers don't even
> have DT conversion in place yet. I am attempting to handle the cases
> where we don't have OF nodes.... yet at least, without converting
> everything to DT, and without causing regressions (also, I don't
> even pretend to be capable of testing all the potential drivers for
> this.) Some parts of the basic infra which are using clk_get_sys are
> pretty silly also, like the ocp_if parts of the hwmod, I haven't
> figured out yet how to convert that to DT.
> 
> Personally I don't mind causing a regressions here though, if I get
> approval for it from Tony.

No, let's not do that. We don't want to break existing drivers.

How about initialize the platform driver clocks in the clock driver
and set up the clock alias? Then when the driver is fixed for DT,
those can be dropped one at a time.

Regards,

Tony

[PATCHv5 02/31] CLK: TI: Add DPLL clock support

[Tero Kristo]

The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti/dpll.txt          |   70 +++
 arch/arm/mach-omap2/clock.h                        |  144 +-----
 arch/arm/mach-omap2/clock3xxx.h                    |    2 -
 drivers/clk/Makefile                               |    1 +
 drivers/clk/ti/Makefile                            |    3 +
 drivers/clk/ti/dpll.c                              |  488 ++++++++++++++++++++
 include/linux/clk/ti.h                             |  164 +++++++
 7 files changed, 727 insertions(+), 145 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
 create mode 100644 drivers/clk/ti/Makefile
 create mode 100644 drivers/clk/ti/dpll.c
 create mode 100644 include/linux/clk/ti.h

diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
new file mode 100644
index 0000000..dcd6e63
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
@@ -0,0 +1,70 @@
+Binding for Texas Instruments DPLL clock.
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped DPLL with usually two selectable input clocks
+(reference clock and bypass clock), with digital phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) This binding has several
+sub-types, which effectively result in slightly different setup
+for the actual DPLL clock.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of:
+		"ti,omap4-dpll-x2-clock",
+		"ti,omap3-dpll-clock",
+		"ti,omap3-dpll-core-clock",
+		"ti,omap3-dpll-per-clock",
+		"ti,omap3-dpll-per-j-type-clock",
+		"ti,omap4-dpll-clock",
+		"ti,omap4-dpll-core-clock",
+		"ti,omap4-dpll-m4xen-clock",
+		"ti,omap4-dpll-j-type-clock",
+		"ti,omap4-dpll-no-gate-clock",
+		"ti,omap4-dpll-no-gate-j-type-clock",
+
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : array of register base addresses for controlling the DPLL (some
+  of these can also be left as NULL):
+	reg[0] = control register
+	reg[1] = idle status register
+	reg[2] = autoidle register
+	reg[3] = multiplier / divider set register
+- ti,clk-ref : link phandle for the reference clock
+- ti,clk-bypass : link phandle for the bypass clock
+
+Optional properties:
+- ti,modes : available modes for the DPLL
+- ti,recal-en-bit : recalibration enable bit
+- ti,recal-st-bit : recalibration status bit
+- ti,auto-recal-bit : auto recalibration enable bit
+- ti,clkdm-name : clockdomain name for the DPLL
+
+Examples:
+	dpll_core_ck: dpll_core_ck at 44e00490 {
+		#clock-cells = <0>;
+		compatible = "ti,omap4-dpll-core-clock";
+		clocks = <&sys_clkin_ck>;
+		reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x0 0x4>,
+				<0x44e00468 0x4>;
+		ti,clk-ref = <&sys_clkin_ck>;
+		ti,clk-bypass = <&sys_clkin_ck>;
+	};
+
+	dpll2_ck: dpll2_ck at 48004004 {
+		#clock-cells = <0>;
+		compatible = "ti,omap3-dpll-clock";
+		clocks = <&sys_ck>;
+		ti,modes = <0xa2>;
+		ti,clk-bypass = <&dpll2_fck>;
+		reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>,
+			<0x48004040 0x4>;
+		ti,clkdm-name = "dpll2_clkdm";
+		ti,clk-ref = <&sys_ck>;
+		ti,recal-en-bit = <0x8>;
+		ti,auto-recal-bit = <0x3>;
+		ti,recal-st-bit = <0x8>;
+	};
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd..079536a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
 
 struct omap_clk {
 	u16				cpu;
@@ -178,83 +179,6 @@ struct clksel {
 	const struct clksel_rate *rates;
 };
 
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @last_rounded_m4xen: cache of the last M4X result of
- *			omap4_dpll_regm4xen_round_rate()
- * @last_rounded_lpmode: cache of the last lpmode result of
- *			 omap4_dpll_lpmode_recalc()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
- * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
-	void __iomem		*mult_div1_reg;
-	u32			mult_mask;
-	u32			div1_mask;
-	struct clk		*clk_bypass;
-	struct clk		*clk_ref;
-	void __iomem		*control_reg;
-	u32			enable_mask;
-	unsigned long		last_rounded_rate;
-	u16			last_rounded_m;
-	u8			last_rounded_m4xen;
-	u8			last_rounded_lpmode;
-	u16			max_multiplier;
-	u8			last_rounded_n;
-	u8			min_divider;
-	u16			max_divider;
-	u8			modes;
-	void __iomem		*autoidle_reg;
-	void __iomem		*idlest_reg;
-	u32			autoidle_mask;
-	u32			freqsel_mask;
-	u32			idlest_mask;
-	u32			dco_mask;
-	u32			sddiv_mask;
-	u32			lpmode_mask;
-	u32			m4xen_mask;
-	u8			auto_recal_bit;
-	u8			recal_en_bit;
-	u8			recal_st_bit;
-	u8			flags;
-};
-
 /*
  * struct clk.flags possibilities
  *
@@ -274,45 +198,6 @@ struct dpll_data {
 #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
 #define CLOCK_CLKOUTX2		(1 << 5)
 
-/**
- * struct clk_hw_omap - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- */
-
-struct clk_hw_omap_ops;
-
-struct clk_hw_omap {
-	struct clk_hw		hw;
-	struct list_head	node;
-	unsigned long		fixed_rate;
-	u8			fixed_div;
-	void __iomem		*enable_reg;
-	u8			enable_bit;
-	u8			flags;
-	void __iomem		*clksel_reg;
-	u32			clksel_mask;
-	const struct clksel	*clksel;
-	struct dpll_data	*dpll_data;
-	const char		*clkdm_name;
-	struct clockdomain	*clkdm;
-	const struct clk_hw_omap_ops	*ops;
-};
-
 struct clk_hw_omap_ops {
 	void			(*find_idlest)(struct clk_hw_omap *oclk,
 					void __iomem **idlest_reg,
@@ -348,36 +233,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 #define OMAP4XXX_EN_DPLL_FRBYPASS		0x6
 #define OMAP4XXX_EN_DPLL_LOCKED			0x7
 
-/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
-#define DPLL_LOW_POWER_STOP	0x1
-#define DPLL_LOW_POWER_BYPASS	0x5
-#define DPLL_LOCKED		0x7
-
-/* DPLL Type and DCO Selection Flags */
-#define DPLL_J_TYPE		0x1
-
-long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
-			unsigned long *parent_rate);
-unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
-int omap3_noncore_dpll_enable(struct clk_hw *hw);
-void omap3_noncore_dpll_disable(struct clk_hw *hw);
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
-				unsigned long parent_rate);
 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
 void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
 void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
-unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
-				    unsigned long parent_rate);
 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
-unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
-				unsigned long parent_rate);
-long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
-				    unsigned long target_rate,
-				    unsigned long *parent_rate);
 
-void omap2_init_clk_clkdm(struct clk_hw *clk);
 void __init omap2_clk_disable_clkdm_control(void);
 
 /* clkt_clksel.c public functions */
@@ -396,7 +258,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
 
-u8 omap2_init_dpll_parent(struct clk_hw *hw);
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
 int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -408,7 +269,6 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 				void __iomem **idlest_reg,
 				u8 *idlest_bit, u8 *idlest_val);
-void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap2_clk_enable_autoidle_all(void);
 int omap2_clk_disable_autoidle_all(void);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
@@ -431,10 +291,8 @@ extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 extern struct clk dummy_ck;
 
-extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
 extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 8cd4b0a..dab90e2 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,8 +9,6 @@
 #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
 
 int omap3xxx_clk_init(void);
-int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
-					unsigned long parent_rate);
 int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
 					unsigned long parent_rate);
 void omap3_clk_lock_dpll5(void);
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4038c2b..cf55585 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
 obj-$(CONFIG_ARCH_ZYNQ)		+= zynq/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
+obj-$(CONFIG_ARCH_OMAP)		+= ti/
 
 obj-$(CONFIG_X86)		+= x86/
 
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
new file mode 100644
index 0000000..93177987
--- /dev/null
+++ b/drivers/clk/ti/Makefile
@@ -0,0 +1,3 @@
+ifneq ($(CONFIG_OF),)
+obj-y					+= dpll.o
+endif
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
new file mode 100644
index 0000000..089b68d
--- /dev/null
+++ b/drivers/clk/ti/dpll.c
@@ -0,0 +1,488 @@
+/*
+ * OMAP DPLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+static const struct clk_ops dpll_m4xen_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
+	.round_rate	= &omap4_dpll_regm4xen_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.get_parent	= &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops dpll_core_ck_ops = {
+	.recalc_rate	= &omap3_dpll_recalc,
+	.get_parent	= &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops omap3_dpll_core_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+
+static const struct clk_ops dpll_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.round_rate	= &omap2_dpll_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.get_parent	= &omap2_init_dpll_parent,
+	.init		= &omap2_init_clk_clkdm,
+};
+
+static const struct clk_ops dpll_no_gate_ck_ops = {
+	.recalc_rate	= &omap3_dpll_recalc,
+	.get_parent	= &omap2_init_dpll_parent,
+	.round_rate	= &omap2_dpll_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+};
+
+static const struct clk_ops omap3_dpll_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+
+static const struct clk_ops omap3_dpll_per_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.set_rate	= &omap3_dpll4_set_rate,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+
+static const struct clk_ops dpll_x2_ck_ops = {
+	.recalc_rate	= &omap3_clkoutx2_recalc,
+};
+
+static struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
+		const char **parent_names, int num_parents, unsigned long flags,
+		struct dpll_data *dpll_data, const char *clkdm_name,
+		const struct clk_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init = { 0 };
+	struct clk_hw_omap *clk_hw;
+
+	/* allocate the divider */
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk_hw->dpll_data = dpll_data;
+	clk_hw->ops = &clkhwops_omap3_dpll;
+	clk_hw->clkdm_name = clkdm_name;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.flags = flags;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	/* register the clock */
+	clk = clk_register(dev, &clk_hw->hw);
+
+	if (IS_ERR(clk))
+		kfree(clk_hw);
+	else
+		omap2_init_clk_hw_omap_clocks(clk);
+
+	return clk;
+}
+
+static struct clk *omap_clk_register_dpll_x2(struct device *dev,
+		const char *name, const char *parent_name, void __iomem *reg,
+		const struct clk_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init = { 0 };
+	struct clk_hw_omap *clk_hw;
+
+	if (!parent_name) {
+		pr_err("%s: dpll_x2 must have parent\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk_hw->ops = &clkhwops_omap4_dpllmx;
+	clk_hw->clksel_reg = reg;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	/* register the clock */
+	clk = clk_register(dev, &clk_hw->hw);
+
+	if (IS_ERR(clk))
+		kfree(clk_hw);
+	else
+		omap2_init_clk_hw_omap_clocks(clk);
+
+	return clk;
+}
+
+static inline void __iomem *get_dt_register(struct device_node *node,
+					    int index)
+{
+	u32 val;
+
+	of_property_read_u32_index(node, "reg", 2 * index, &val);
+	if (val)
+		return of_iomap(node, index);
+	else
+		return NULL;
+}
+
+/**
+ * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
+ *
+ * @node: device node containing the DPLL info
+ * @ops: ops for the DPLL
+ * @ddt: DPLL data template to use
+ */
+static void __init of_omap_dpll_setup(struct device_node *node,
+					const struct clk_ops *ops,
+					const struct dpll_data *ddt)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names = NULL;
+	const char *clkdm_name = NULL;
+	struct of_phandle_args clkspec;
+	u8 dpll_flags = 0;
+	struct dpll_data *dd;
+	int i;
+	u32 val;
+
+	dd = kzalloc(sizeof(*dd), GFP_KERNEL);
+	if (!dd) {
+		pr_err("%s: could not allocate dpll_data\n", __func__);
+		return;
+	}
+
+	memcpy(dd, ddt, sizeof(*dd));
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap dpll %s must have parent(s)\n",
+		       __func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
+	dd->clk_ref = of_clk_get_from_provider(&clkspec);
+	if (IS_ERR(dd->clk_ref)) {
+		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+		       clk_name);
+		goto cleanup;
+	}
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
+	dd->clk_bypass = of_clk_get_from_provider(&clkspec);
+	if (IS_ERR(dd->clk_bypass)) {
+		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+		       clk_name);
+		goto cleanup;
+	}
+
+	of_property_read_string(node, "ti,clkdm-name", &clkdm_name);
+
+	dd->control_reg = get_dt_register(node, 0);
+	dd->idlest_reg = get_dt_register(node, 1);
+	dd->autoidle_reg = get_dt_register(node, 2);
+	dd->mult_div1_reg = get_dt_register(node, 3);
+
+	if (!of_property_read_u32(node, "ti,modes", &val))
+		dd->modes = val;
+
+	if (!of_property_read_u32(node, "ti,recal-en-bit", &val))
+		dd->recal_en_bit = val;
+
+	if (!of_property_read_u32(node, "ti,recal-st-bit", &val))
+		dd->recal_st_bit = val;
+
+	if (!of_property_read_u32(node, "ti,auto-recal-bit", &val))
+		dd->auto_recal_bit = val;
+
+	clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
+				num_parents, dpll_flags, dd,
+				clkdm_name, ops);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	return;
+
+cleanup:
+	kfree(dd);
+	kfree(parent_names);
+	return;
+}
+
+static void __init of_omap_dpll_x2_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	const char *parent_name;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	reg = get_dt_register(node, 0);
+
+	clk = omap_clk_register_dpll_x2(NULL, clk_name, parent_name,
+				reg, &dpll_x2_ck_ops);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(omap_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
+	       of_omap_dpll_x2_setup);
+
+static void __init of_omap3_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.freqsel_mask = 0xf0,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_omap_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
+
+static void __init of_omap3_core_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 16,
+		.div1_mask = 0x7f << 8,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.freqsel_mask = 0xf0,
+	};
+
+	of_omap_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
+	       of_omap3_core_dpll_setup);
+
+static void __init of_omap3_per_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1 << 1,
+		.enable_mask = 0x7 << 16,
+		.autoidle_mask = 0x7 << 3,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.freqsel_mask = 0xf00000,
+		.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+	};
+
+	of_omap_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
+	       of_omap3_per_dpll_setup);
+
+static void __init of_omap3_per_jtype_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1 << 1,
+		.enable_mask = 0x7 << 16,
+		.autoidle_mask = 0x7 << 3,
+		.mult_mask = 0xfff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 4095,
+		.max_divider = 128,
+		.min_divider = 1,
+		.sddiv_mask = 0xff << 24,
+		.dco_mask = 0xe << 20,
+		.flags = DPLL_J_TYPE,
+		.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+	};
+
+	of_omap_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
+	       of_omap3_per_jtype_dpll_setup);
+
+static void __init of_omap4_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_omap_dpll_setup(node, &dpll_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
+
+static void __init of_omap4_core_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_omap_dpll_setup(node, &dpll_core_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
+	       of_omap4_core_dpll_setup);
+
+static void __init of_omap4_m4xen_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.m4xen_mask = 0x800,
+		.lpmode_mask = 1 << 10,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_omap_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
+	       of_omap4_m4xen_dpll_setup);
+
+static void __init of_omap4_jtype_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0xfff << 8,
+		.div1_mask = 0xff,
+		.max_multiplier = 4095,
+		.max_divider = 256,
+		.min_divider = 1,
+		.sddiv_mask = 0xff << 24,
+		.flags = DPLL_J_TYPE,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_omap_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
+	       of_omap4_jtype_dpll_setup);
+
+static void __init of_omap4_no_gate_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_omap_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_no_gate_dpll_clock, "ti,omap4-dpll-no-gate-clock",
+	       of_omap4_no_gate_dpll_setup);
+
+static void __init of_omap4_no_gate_jtype_dpll_setup(struct device_node *node)
+{
+	const struct dpll_data dd = {
+		.idlest_mask = 0x1,
+		.enable_mask = 0x7,
+		.autoidle_mask = 0x7,
+		.mult_mask = 0x7ff << 8,
+		.div1_mask = 0x7f,
+		.max_multiplier = 2047,
+		.max_divider = 128,
+		.min_divider = 1,
+		.flags = DPLL_J_TYPE,
+		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+	};
+
+	of_omap_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
+}
+CLK_OF_DECLARE(omap4_no_gate_jtype_dpll_clock,
+	       "ti,omap4-dpll-no-gate-j-type-clock",
+	       of_omap4_no_gate_jtype_dpll_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
new file mode 100644
index 0000000..385384a
--- /dev/null
+++ b/include/linux/clk/ti.h
@@ -0,0 +1,164 @@
+/*
+ * TI clock drivers support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __LINUX_CLK_TI_H__
+#define __LINUX_CLK_TI_H__
+
+/**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @last_rounded_m4xen: cache of the last M4X result of
+ *                     omap4_dpll_regm4xen_round_rate()
+ * @last_rounded_lpmode: cache of the last lpmode result of
+ *                      omap4_dpll_lpmode_recalc()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
+ * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ *
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a different structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+struct dpll_data {
+	void __iomem		*mult_div1_reg;
+	u32			mult_mask;
+	u32			div1_mask;
+	struct clk		*clk_bypass;
+	struct clk		*clk_ref;
+	void __iomem		*control_reg;
+	u32			enable_mask;
+	unsigned long		last_rounded_rate;
+	u16			last_rounded_m;
+	u8			last_rounded_m4xen;
+	u8			last_rounded_lpmode;
+	u16			max_multiplier;
+	u8			last_rounded_n;
+	u8			min_divider;
+	u16			max_divider;
+	u8			modes;
+	void __iomem		*autoidle_reg;
+	void __iomem		*idlest_reg;
+	u32			autoidle_mask;
+	u32			freqsel_mask;
+	u32			idlest_mask;
+	u32			dco_mask;
+	u32			sddiv_mask;
+	u32			lpmode_mask;
+	u32			m4xen_mask;
+	u8			auto_recal_bit;
+	u8			recal_en_bit;
+	u8			recal_st_bit;
+	u8			flags;
+};
+
+struct clk_hw_omap_ops;
+
+/**
+ * struct clk_hw_omap - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @flags: see "struct clk.flags possibilities" above
+ * @clksel_reg: for clksel clks, register va containing src/divisor select
+ * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ * @clksel: for clksel clks, pointer to struct clksel for this clock
+ * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ * @clkdm_name: clockdomain name that this clock is contained in
+ * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name@runtime
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ */
+struct clk_hw_omap {
+	struct clk_hw		hw;
+	struct list_head	node;
+	unsigned long		fixed_rate;
+	u8			fixed_div;
+	void __iomem		*enable_reg;
+	u8			enable_bit;
+	u8			flags;
+	void __iomem		*clksel_reg;
+	u32			clksel_mask;
+	const struct clksel	*clksel;
+	struct dpll_data	*dpll_data;
+	const char		*clkdm_name;
+	struct clockdomain	*clkdm;
+	const struct clk_hw_omap_ops	*ops;
+};
+
+/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
+#define DPLL_LOW_POWER_STOP	0x1
+#define DPLL_LOW_POWER_BYPASS	0x5
+#define DPLL_LOCKED		0x7
+
+/* DPLL Type and DCO Selection Flags */
+#define DPLL_J_TYPE		0x1
+
+void omap2_init_clk_hw_omap_clocks(struct clk *clk);
+int omap3_noncore_dpll_enable(struct clk_hw *hw);
+void omap3_noncore_dpll_disable(struct clk_hw *hw);
+int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate);
+unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
+					 unsigned long parent_rate);
+long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
+				    unsigned long target_rate,
+				    unsigned long *parent_rate);
+u8 omap2_init_dpll_parent(struct clk_hw *hw);
+unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
+long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+			   unsigned long *parent_rate);
+void omap2_init_clk_clkdm(struct clk_hw *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
+				    unsigned long parent_rate);
+int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
+			 unsigned long parent_rate);
+
+extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
+extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+
+#endif
-- 
1.7.9.5

[PATCHv5 02/31] CLK: TI: Add DPLL clock support

[Mark Rutland]

Hi,

On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
> The OMAP clock driver now supports DPLL clock type. This patch also
> adds support for DT DPLL nodes.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  .../devicetree/bindings/clock/ti/dpll.txt          |   70 +++
>  arch/arm/mach-omap2/clock.h                        |  144 +-----
>  arch/arm/mach-omap2/clock3xxx.h                    |    2 -
>  drivers/clk/Makefile                               |    1 +
>  drivers/clk/ti/Makefile                            |    3 +
>  drivers/clk/ti/dpll.c                              |  488 ++++++++++++++++++++
>  include/linux/clk/ti.h                             |  164 +++++++
>  7 files changed, 727 insertions(+), 145 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
>  create mode 100644 drivers/clk/ti/Makefile
>  create mode 100644 drivers/clk/ti/dpll.c
>  create mode 100644 include/linux/clk/ti.h
>
> diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> new file mode 100644
> index 0000000..dcd6e63
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> @@ -0,0 +1,70 @@
> +Binding for Texas Instruments DPLL clock.
> +
> +This binding uses the common clock binding[1].  It assumes a
> +register-mapped DPLL with usually two selectable input clocks
> +(reference clock and bypass clock), with digital phase locked
> +loop logic for multiplying the input clock to a desired output
> +clock. This clock also typically supports different operation
> +modes (locked, low power stop etc.) This binding has several
> +sub-types, which effectively result in slightly different setup
> +for the actual DPLL clock.
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible : shall be one of:
> +               "ti,omap4-dpll-x2-clock",
> +               "ti,omap3-dpll-clock",
> +               "ti,omap3-dpll-core-clock",
> +               "ti,omap3-dpll-per-clock",
> +               "ti,omap3-dpll-per-j-type-clock",
> +               "ti,omap4-dpll-clock",
> +               "ti,omap4-dpll-core-clock",
> +               "ti,omap4-dpll-m4xen-clock",
> +               "ti,omap4-dpll-j-type-clock",
> +               "ti,omap4-dpll-no-gate-clock",
> +               "ti,omap4-dpll-no-gate-j-type-clock",
> +
> +- #clock-cells : from common clock binding; shall be set to 0.
> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)

It might be a good idea to use clock-names to clarify which clocks are
present (I notice your examples contain only one clock input).

> +- reg : array of register base addresses for controlling the DPLL (some
> +  of these can also be left as NULL):
> +       reg[0] = control register
> +       reg[1] = idle status register
> +       reg[2] = autoidle register
> +       reg[3] = multiplier / divider set register

Are all of these always present? Using reg-names seems sensible here.

> +- ti,clk-ref : link phandle for the reference clock
> +- ti,clk-bypass : link phandle for the bypass clock

You already have these in clocks, why do you need them again here?

> +
> +Optional properties:
> +- ti,modes : available modes for the DPLL

Huh? What type is that property? What does it mean?

> +- ti,recal-en-bit : recalibration enable bit
> +- ti,recal-st-bit : recalibration status bit
> +- ti,auto-recal-bit : auto recalibration enable bit

These seem rather low-level, but I see other clock bindings are doing
similar things. When are these needed, and why? What type are they?

> +- ti,clkdm-name : clockdomain name for the DPLL

Could you elaborate on what this is for? What constitutes a valid name?

I'm not sure a string is the best way to define the linkage of several
elements to a domain...

> +
> +Examples:
> +       dpll_core_ck: dpll_core_ck at 44e00490 {
> +               #clock-cells = <0>;
> +               compatible = "ti,omap4-dpll-core-clock";
> +               clocks = <&sys_clkin_ck>;
> +               reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x0 0x4>,
> +                               <0x44e00468 0x4>;
> +               ti,clk-ref = <&sys_clkin_ck>;
> +               ti,clk-bypass = <&sys_clkin_ck>;

Huh? Why aren't these both in the clocks property?

[...]

> +static inline void __iomem *get_dt_register(struct device_node *node,
> +                                           int index)
> +{
> +       u32 val;
> +
> +       of_property_read_u32_index(node, "reg", 2 * index, &val);
> +       if (val)
> +               return of_iomap(node, index);
> +       else
> +               return NULL;

NAK. Use reg-names to handle registers being optional.

[...]

> +       clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
> +       dd->clk_ref = of_clk_get_from_provider(&clkspec);
> +       if (IS_ERR(dd->clk_ref)) {
> +               pr_err("%s: ti,clk-ref for %s not found\n", __func__,
> +                      clk_name);
> +               goto cleanup;
> +       }
> +
> +       clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
> +       dd->clk_bypass = of_clk_get_from_provider(&clkspec);
> +       if (IS_ERR(dd->clk_bypass)) {
> +               pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
> +                      clk_name);
> +               goto cleanup;
> +       }

You can get these from the standard clocks property. Don't do this.

Look at of_clk_get_by_name().

Thanks,
Mark.

[PATCHv5 02/31] CLK: TI: Add DPLL clock support

[Tero Kristo]

On 08/13/2013 01:50 PM, Mark Rutland wrote:
> Hi,
>
> On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
>> The OMAP clock driver now supports DPLL clock type. This patch also
>> adds support for DT DPLL nodes.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   .../devicetree/bindings/clock/ti/dpll.txt          |   70 +++
>>   arch/arm/mach-omap2/clock.h                        |  144 +-----
>>   arch/arm/mach-omap2/clock3xxx.h                    |    2 -
>>   drivers/clk/Makefile                               |    1 +
>>   drivers/clk/ti/Makefile                            |    3 +
>>   drivers/clk/ti/dpll.c                              |  488 ++++++++++++++++++++
>>   include/linux/clk/ti.h                             |  164 +++++++
>>   7 files changed, 727 insertions(+), 145 deletions(-)
>>   create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
>>   create mode 100644 drivers/clk/ti/Makefile
>>   create mode 100644 drivers/clk/ti/dpll.c
>>   create mode 100644 include/linux/clk/ti.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
>> new file mode 100644
>> index 0000000..dcd6e63
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
>> @@ -0,0 +1,70 @@
>> +Binding for Texas Instruments DPLL clock.
>> +
>> +This binding uses the common clock binding[1].  It assumes a
>> +register-mapped DPLL with usually two selectable input clocks
>> +(reference clock and bypass clock), with digital phase locked
>> +loop logic for multiplying the input clock to a desired output
>> +clock. This clock also typically supports different operation
>> +modes (locked, low power stop etc.) This binding has several
>> +sub-types, which effectively result in slightly different setup
>> +for the actual DPLL clock.
>> +
>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +
>> +Required properties:
>> +- compatible : shall be one of:
>> +               "ti,omap4-dpll-x2-clock",
>> +               "ti,omap3-dpll-clock",
>> +               "ti,omap3-dpll-core-clock",
>> +               "ti,omap3-dpll-per-clock",
>> +               "ti,omap3-dpll-per-j-type-clock",
>> +               "ti,omap4-dpll-clock",
>> +               "ti,omap4-dpll-core-clock",
>> +               "ti,omap4-dpll-m4xen-clock",
>> +               "ti,omap4-dpll-j-type-clock",
>> +               "ti,omap4-dpll-no-gate-clock",
>> +               "ti,omap4-dpll-no-gate-j-type-clock",
>> +
>> +- #clock-cells : from common clock binding; shall be set to 0.
>> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
>
> It might be a good idea to use clock-names to clarify which clocks are
> present (I notice your examples contain only one clock input).

All DPLLs have both bypass and reference clocks, but these can be the 
same. Is it better to just list both always (and hence drop 
clock-names), or provide clock-names always?

>
>> +- reg : array of register base addresses for controlling the DPLL (some
>> +  of these can also be left as NULL):
>> +       reg[0] = control register
>> +       reg[1] = idle status register
>> +       reg[2] = autoidle register
>> +       reg[3] = multiplier / divider set register
>
> Are all of these always present? Using reg-names seems sensible here.

Not always, I'll change the code. I am quite new to DT and didn't 
actually know of the existence of reg-names prop.

>
>> +- ti,clk-ref : link phandle for the reference clock
>> +- ti,clk-bypass : link phandle for the bypass clock
>
> You already have these in clocks, why do you need them again here?

Yea good point. Will fix based on the above.

>
>> +
>> +Optional properties:
>> +- ti,modes : available modes for the DPLL
>
> Huh? What type is that property? What does it mean?

Will add some documentation to this.

>
>> +- ti,recal-en-bit : recalibration enable bit
>> +- ti,recal-st-bit : recalibration status bit
>> +- ti,auto-recal-bit : auto recalibration enable bit
>
> These seem rather low-level, but I see other clock bindings are doing
> similar things. When are these needed, and why? What type are they?

Bit shift values for the auto recalibration feature. HOWEVER, it seems 
these are actually legacy, kernel does not have support for these 
anymore if it ever had.... I think I can just drop these for now as they 
are unused by the support code even.

>
>> +- ti,clkdm-name : clockdomain name for the DPLL
>
> Could you elaborate on what this is for? What constitutes a valid name?
>
> I'm not sure a string is the best way to define the linkage of several
> elements to a domain...

Well, I am not sure if we can do this any better at this point, we don't 
have DT nodes for clockdomain at the moment (I am not sure if we will 
have those either as there are only a handful of those per SoC) but I'll 
add some more documentation for this.

>
>> +
>> +Examples:
>> +       dpll_core_ck: dpll_core_ck at 44e00490 {
>> +               #clock-cells = <0>;
>> +               compatible = "ti,omap4-dpll-core-clock";
>> +               clocks = <&sys_clkin_ck>;
>> +               reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x0 0x4>,
>> +                               <0x44e00468 0x4>;
>> +               ti,clk-ref = <&sys_clkin_ck>;
>> +               ti,clk-bypass = <&sys_clkin_ck>;
>
> Huh? Why aren't these both in the clocks property?

Will fix based on comments above.

>
> [...]
>
>> +static inline void __iomem *get_dt_register(struct device_node *node,
>> +                                           int index)
>> +{
>> +       u32 val;
>> +
>> +       of_property_read_u32_index(node, "reg", 2 * index, &val);
>> +       if (val)
>> +               return of_iomap(node, index);
>> +       else
>> +               return NULL;
>
> NAK. Use reg-names to handle registers being optional.

Yea will change this.

>
> [...]
>
>> +       clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
>> +       dd->clk_ref = of_clk_get_from_provider(&clkspec);
>> +       if (IS_ERR(dd->clk_ref)) {
>> +               pr_err("%s: ti,clk-ref for %s not found\n", __func__,
>> +                      clk_name);
>> +               goto cleanup;
>> +       }
>> +
>> +       clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
>> +       dd->clk_bypass = of_clk_get_from_provider(&clkspec);
>> +       if (IS_ERR(dd->clk_bypass)) {
>> +               pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
>> +                      clk_name);
>> +               goto cleanup;
>> +       }
>
> You can get these from the standard clocks property. Don't do this.
>
> Look at of_clk_get_by_name().

Or of_clk_get(node, index), which would be better?

-Tero

>
> Thanks,
> Mark.
>

[PATCHv5 02/31] CLK: TI: Add DPLL clock support

[Mark Rutland]

On Mon, Aug 19, 2013 at 02:34:45PM +0100, Tero Kristo wrote:
> On 08/13/2013 01:50 PM, Mark Rutland wrote:
> > Hi,
> >
> > On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
> >> The OMAP clock driver now supports DPLL clock type. This patch also
> >> adds support for DT DPLL nodes.
> >>
> >> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >> ---
> >>   .../devicetree/bindings/clock/ti/dpll.txt          |   70 +++
> >>   arch/arm/mach-omap2/clock.h                        |  144 +-----
> >>   arch/arm/mach-omap2/clock3xxx.h                    |    2 -
> >>   drivers/clk/Makefile                               |    1 +
> >>   drivers/clk/ti/Makefile                            |    3 +
> >>   drivers/clk/ti/dpll.c                              |  488 ++++++++++++++++++++
> >>   include/linux/clk/ti.h                             |  164 +++++++
> >>   7 files changed, 727 insertions(+), 145 deletions(-)
> >>   create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
> >>   create mode 100644 drivers/clk/ti/Makefile
> >>   create mode 100644 drivers/clk/ti/dpll.c
> >>   create mode 100644 include/linux/clk/ti.h
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> >> new file mode 100644
> >> index 0000000..dcd6e63
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> >> @@ -0,0 +1,70 @@
> >> +Binding for Texas Instruments DPLL clock.
> >> +
> >> +This binding uses the common clock binding[1].  It assumes a
> >> +register-mapped DPLL with usually two selectable input clocks
> >> +(reference clock and bypass clock), with digital phase locked
> >> +loop logic for multiplying the input clock to a desired output
> >> +clock. This clock also typically supports different operation
> >> +modes (locked, low power stop etc.) This binding has several
> >> +sub-types, which effectively result in slightly different setup
> >> +for the actual DPLL clock.
> >> +
> >> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> >> +
> >> +Required properties:
> >> +- compatible : shall be one of:
> >> +               "ti,omap4-dpll-x2-clock",
> >> +               "ti,omap3-dpll-clock",
> >> +               "ti,omap3-dpll-core-clock",
> >> +               "ti,omap3-dpll-per-clock",
> >> +               "ti,omap3-dpll-per-j-type-clock",
> >> +               "ti,omap4-dpll-clock",
> >> +               "ti,omap4-dpll-core-clock",
> >> +               "ti,omap4-dpll-m4xen-clock",
> >> +               "ti,omap4-dpll-j-type-clock",
> >> +               "ti,omap4-dpll-no-gate-clock",
> >> +               "ti,omap4-dpll-no-gate-j-type-clock",
> >> +
> >> +- #clock-cells : from common clock binding; shall be set to 0.
> >> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
> >
> > It might be a good idea to use clock-names to clarify which clocks are
> > present (I notice your examples contain only one clock input).
> 
> All DPLLs have both bypass and reference clocks, but these can be the 
> same. Is it better to just list both always (and hence drop 
> clock-names), or provide clock-names always?

If they're separate inputs, it's worth listing both (even if they're fed
by the same provider). If it's possible one input might not be wired up,
use clock-names.

> 
> >
> >> +- reg : array of register base addresses for controlling the DPLL (some
> >> +  of these can also be left as NULL):
> >> +       reg[0] = control register
> >> +       reg[1] = idle status register
> >> +       reg[2] = autoidle register
> >> +       reg[3] = multiplier / divider set register
> >
> > Are all of these always present? Using reg-names seems sensible here.
> 
> Not always, I'll change the code. I am quite new to DT and didn't 
> actually know of the existence of reg-names prop.

Ok. :)

> >
> >> +- ti,recal-en-bit : recalibration enable bit
> >> +- ti,recal-st-bit : recalibration status bit
> >> +- ti,auto-recal-bit : auto recalibration enable bit
> >
> > These seem rather low-level, but I see other clock bindings are doing
> > similar things. When are these needed, and why? What type are they?
> 
> Bit shift values for the auto recalibration feature. HOWEVER, it seems 
> these are actually legacy, kernel does not have support for these 
> anymore if it ever had.... I think I can just drop these for now as they 
> are unused by the support code even.

Ok.

> 
> >
> >> +- ti,clkdm-name : clockdomain name for the DPLL
> >
> > Could you elaborate on what this is for? What constitutes a valid name?
> >
> > I'm not sure a string is the best way to define the linkage of several
> > elements to a domain...
> 
> Well, I am not sure if we can do this any better at this point, we don't 
> have DT nodes for clockdomain at the moment (I am not sure if we will 
> have those either as there are only a handful of those per SoC) but I'll 
> add some more documentation for this.

I'll have to see the documentation, but I'd be very wary of putting that
in as-is. Does having the clock domain string link this up to domains in
platform data?

I'm not sure how well we'll be able to maintain support for that in
future if it requires other platform code to use now, and we're not sure
how the domains themselves will be represented in dt.

> >
> > [...]
> >
> >> +static inline void __iomem *get_dt_register(struct device_node *node,
> >> +                                           int index)
> >> +{
> >> +       u32 val;
> >> +
> >> +       of_property_read_u32_index(node, "reg", 2 * index, &val);
> >> +       if (val)
> >> +               return of_iomap(node, index);
> >> +       else
> >> +               return NULL;
> >
> > NAK. Use reg-names to handle registers being optional.
> 
> Yea will change this.

Cheers.

> 
> >
> > [...]
> >
> >> +       clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
> >> +       dd->clk_ref = of_clk_get_from_provider(&clkspec);
> >> +       if (IS_ERR(dd->clk_ref)) {
> >> +               pr_err("%s: ti,clk-ref for %s not found\n", __func__,
> >> +                      clk_name);
> >> +               goto cleanup;
> >> +       }
> >> +
> >> +       clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
> >> +       dd->clk_bypass = of_clk_get_from_provider(&clkspec);
> >> +       if (IS_ERR(dd->clk_bypass)) {
> >> +               pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
> >> +                      clk_name);
> >> +               goto cleanup;
> >> +       }
> >
> > You can get these from the standard clocks property. Don't do this.
> >
> > Look at of_clk_get_by_name().
> 
> Or of_clk_get(node, index), which would be better?

If you know you always have both clocks, then yes.

Cheers,
Mark.

[PATCHv5 02/31] CLK: TI: Add DPLL clock support

[Tero Kristo]

On 08/19/2013 05:18 PM, Mark Rutland wrote:
> On Mon, Aug 19, 2013 at 02:34:45PM +0100, Tero Kristo wrote:
>> On 08/13/2013 01:50 PM, Mark Rutland wrote:
>>> Hi,
>>>
>>> On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
>>>> The OMAP clock driver now supports DPLL clock type. This patch also
>>>> adds support for DT DPLL nodes.
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> ---
>>>>    .../devicetree/bindings/clock/ti/dpll.txt          |   70 +++
>>>>    arch/arm/mach-omap2/clock.h                        |  144 +-----
>>>>    arch/arm/mach-omap2/clock3xxx.h                    |    2 -
>>>>    drivers/clk/Makefile                               |    1 +
>>>>    drivers/clk/ti/Makefile                            |    3 +
>>>>    drivers/clk/ti/dpll.c                              |  488 ++++++++++++++++++++
>>>>    include/linux/clk/ti.h                             |  164 +++++++
>>>>    7 files changed, 727 insertions(+), 145 deletions(-)
>>>>    create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
>>>>    create mode 100644 drivers/clk/ti/Makefile
>>>>    create mode 100644 drivers/clk/ti/dpll.c
>>>>    create mode 100644 include/linux/clk/ti.h
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
>>>> new file mode 100644
>>>> index 0000000..dcd6e63
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
>>>> @@ -0,0 +1,70 @@
>>>> +Binding for Texas Instruments DPLL clock.
>>>> +
>>>> +This binding uses the common clock binding[1].  It assumes a
>>>> +register-mapped DPLL with usually two selectable input clocks
>>>> +(reference clock and bypass clock), with digital phase locked
>>>> +loop logic for multiplying the input clock to a desired output
>>>> +clock. This clock also typically supports different operation
>>>> +modes (locked, low power stop etc.) This binding has several
>>>> +sub-types, which effectively result in slightly different setup
>>>> +for the actual DPLL clock.
>>>> +
>>>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>> +
>>>> +Required properties:
>>>> +- compatible : shall be one of:
>>>> +               "ti,omap4-dpll-x2-clock",
>>>> +               "ti,omap3-dpll-clock",
>>>> +               "ti,omap3-dpll-core-clock",
>>>> +               "ti,omap3-dpll-per-clock",
>>>> +               "ti,omap3-dpll-per-j-type-clock",
>>>> +               "ti,omap4-dpll-clock",
>>>> +               "ti,omap4-dpll-core-clock",
>>>> +               "ti,omap4-dpll-m4xen-clock",
>>>> +               "ti,omap4-dpll-j-type-clock",
>>>> +               "ti,omap4-dpll-no-gate-clock",
>>>> +               "ti,omap4-dpll-no-gate-j-type-clock",
>>>> +
>>>> +- #clock-cells : from common clock binding; shall be set to 0.
>>>> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
>>>
>>> It might be a good idea to use clock-names to clarify which clocks are
>>> present (I notice your examples contain only one clock input).
>>
>> All DPLLs have both bypass and reference clocks, but these can be the
>> same. Is it better to just list both always (and hence drop
>> clock-names), or provide clock-names always?
>
> If they're separate inputs, it's worth listing both (even if they're fed
> by the same provider). If it's possible one input might not be wired up,
> use clock-names.

Ref and bypass clocks are used currently by all DPLLs (also the APLL) so 
I guess I just enforce both to be specified.

>
>>
>>>
>>>> +- reg : array of register base addresses for controlling the DPLL (some
>>>> +  of these can also be left as NULL):
>>>> +       reg[0] = control register
>>>> +       reg[1] = idle status register
>>>> +       reg[2] = autoidle register
>>>> +       reg[3] = multiplier / divider set register
>>>
>>> Are all of these always present? Using reg-names seems sensible here.
>>
>> Not always, I'll change the code. I am quite new to DT and didn't
>> actually know of the existence of reg-names prop.
>
> Ok. :)
>
>>>
>>>> +- ti,recal-en-bit : recalibration enable bit
>>>> +- ti,recal-st-bit : recalibration status bit
>>>> +- ti,auto-recal-bit : auto recalibration enable bit
>>>
>>> These seem rather low-level, but I see other clock bindings are doing
>>> similar things. When are these needed, and why? What type are they?
>>
>> Bit shift values for the auto recalibration feature. HOWEVER, it seems
>> these are actually legacy, kernel does not have support for these
>> anymore if it ever had.... I think I can just drop these for now as they
>> are unused by the support code even.
>
> Ok.
>
>>
>>>
>>>> +- ti,clkdm-name : clockdomain name for the DPLL
>>>
>>> Could you elaborate on what this is for? What constitutes a valid name?
>>>
>>> I'm not sure a string is the best way to define the linkage of several
>>> elements to a domain...
>>
>> Well, I am not sure if we can do this any better at this point, we don't
>> have DT nodes for clockdomain at the moment (I am not sure if we will
>> have those either as there are only a handful of those per SoC) but I'll
>> add some more documentation for this.
>
> I'll have to see the documentation, but I'd be very wary of putting that
> in as-is. Does having the clock domain string link this up to domains in
> platform data?
>
> I'm not sure how well we'll be able to maintain support for that in
> future if it requires other platform code to use now, and we're not sure
> how the domains themselves will be represented in dt.

Hmm so, should I add a stub representation for the clockdomains to the 
DT then for now or how should this be handled? The stubs could then be 
mapped to the actual clock domains based on their node names.

>
>>>
>>> [...]
>>>
>>>> +static inline void __iomem *get_dt_register(struct device_node *node,
>>>> +                                           int index)
>>>> +{
>>>> +       u32 val;
>>>> +
>>>> +       of_property_read_u32_index(node, "reg", 2 * index, &val);
>>>> +       if (val)
>>>> +               return of_iomap(node, index);
>>>> +       else
>>>> +               return NULL;
>>>
>>> NAK. Use reg-names to handle registers being optional.
>>
>> Yea will change this.
>
> Cheers.
>
>>
>>>
>>> [...]
>>>
>>>> +       clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
>>>> +       dd->clk_ref = of_clk_get_from_provider(&clkspec);
>>>> +       if (IS_ERR(dd->clk_ref)) {
>>>> +               pr_err("%s: ti,clk-ref for %s not found\n", __func__,
>>>> +                      clk_name);
>>>> +               goto cleanup;
>>>> +       }
>>>> +
>>>> +       clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
>>>> +       dd->clk_bypass = of_clk_get_from_provider(&clkspec);
>>>> +       if (IS_ERR(dd->clk_bypass)) {
>>>> +               pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
>>>> +                      clk_name);
>>>> +               goto cleanup;
>>>> +       }
>>>
>>> You can get these from the standard clocks property. Don't do this.
>>>
>>> Look at of_clk_get_by_name().
>>
>> Or of_clk_get(node, index), which would be better?
>
> If you know you always have both clocks, then yes.

Ok, will do it this way then.

-Tero

>
> Cheers,
> Mark.
>

[PATCHv5 02/31] CLK: TI: Add DPLL clock support

[Mark Rutland]

On Mon, Aug 19, 2013 at 04:09:37PM +0100, Tero Kristo wrote:
> On 08/19/2013 05:18 PM, Mark Rutland wrote:
> > On Mon, Aug 19, 2013 at 02:34:45PM +0100, Tero Kristo wrote:
> >> On 08/13/2013 01:50 PM, Mark Rutland wrote:
> >>> Hi,
> >>>
> >>> On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
> >>>> The OMAP clock driver now supports DPLL clock type. This patch also
> >>>> adds support for DT DPLL nodes.
> >>>>
> >>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >>>> ---
> >>>>    .../devicetree/bindings/clock/ti/dpll.txt          |   70 +++
> >>>>    arch/arm/mach-omap2/clock.h                        |  144 +-----
> >>>>    arch/arm/mach-omap2/clock3xxx.h                    |    2 -
> >>>>    drivers/clk/Makefile                               |    1 +
> >>>>    drivers/clk/ti/Makefile                            |    3 +
> >>>>    drivers/clk/ti/dpll.c                              |  488 ++++++++++++++++++++
> >>>>    include/linux/clk/ti.h                             |  164 +++++++
> >>>>    7 files changed, 727 insertions(+), 145 deletions(-)
> >>>>    create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
> >>>>    create mode 100644 drivers/clk/ti/Makefile
> >>>>    create mode 100644 drivers/clk/ti/dpll.c
> >>>>    create mode 100644 include/linux/clk/ti.h
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> >>>> new file mode 100644
> >>>> index 0000000..dcd6e63
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> >>>> @@ -0,0 +1,70 @@
> >>>> +Binding for Texas Instruments DPLL clock.
> >>>> +
> >>>> +This binding uses the common clock binding[1].  It assumes a
> >>>> +register-mapped DPLL with usually two selectable input clocks
> >>>> +(reference clock and bypass clock), with digital phase locked
> >>>> +loop logic for multiplying the input clock to a desired output
> >>>> +clock. This clock also typically supports different operation
> >>>> +modes (locked, low power stop etc.) This binding has several
> >>>> +sub-types, which effectively result in slightly different setup
> >>>> +for the actual DPLL clock.
> >>>> +
> >>>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> >>>> +
> >>>> +Required properties:
> >>>> +- compatible : shall be one of:
> >>>> +               "ti,omap4-dpll-x2-clock",
> >>>> +               "ti,omap3-dpll-clock",
> >>>> +               "ti,omap3-dpll-core-clock",
> >>>> +               "ti,omap3-dpll-per-clock",
> >>>> +               "ti,omap3-dpll-per-j-type-clock",
> >>>> +               "ti,omap4-dpll-clock",
> >>>> +               "ti,omap4-dpll-core-clock",
> >>>> +               "ti,omap4-dpll-m4xen-clock",
> >>>> +               "ti,omap4-dpll-j-type-clock",
> >>>> +               "ti,omap4-dpll-no-gate-clock",
> >>>> +               "ti,omap4-dpll-no-gate-j-type-clock",
> >>>> +
> >>>> +- #clock-cells : from common clock binding; shall be set to 0.
> >>>> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
> >>>
> >>> It might be a good idea to use clock-names to clarify which clocks are
> >>> present (I notice your examples contain only one clock input).
> >>
> >> All DPLLs have both bypass and reference clocks, but these can be the
> >> same. Is it better to just list both always (and hence drop
> >> clock-names), or provide clock-names always?
> >
> > If they're separate inputs, it's worth listing both (even if they're fed
> > by the same provider). If it's possible one input might not be wired up,
> > use clock-names.
> 
> Ref and bypass clocks are used currently by all DPLLs (also the APLL) so 
> I guess I just enforce both to be specified.

Ok. It's always possible to add clock-names later if a platform doesn't
wire an input. We lose the possibility of future compatibility, but
backwards compatibility is easy enough to maintain.

> >>>> +- ti,clkdm-name : clockdomain name for the DPLL
> >>>
> >>> Could you elaborate on what this is for? What constitutes a valid name?
> >>>
> >>> I'm not sure a string is the best way to define the linkage of several
> >>> elements to a domain...
> >>
> >> Well, I am not sure if we can do this any better at this point, we don't
> >> have DT nodes for clockdomain at the moment (I am not sure if we will
> >> have those either as there are only a handful of those per SoC) but I'll
> >> add some more documentation for this.
> >
> > I'll have to see the documentation, but I'd be very wary of putting that
> > in as-is. Does having the clock domain string link this up to domains in
> > platform data?
> >
> > I'm not sure how well we'll be able to maintain support for that in
> > future if it requires other platform code to use now, and we're not sure
> > how the domains themselves will be represented in dt.
> 
> Hmm so, should I add a stub representation for the clockdomains to the 
> DT then for now or how should this be handled? The stubs could then be 
> mapped to the actual clock domains based on their node names.
> 

I unfortunately don't have a good answer here, because I'm not that
familiar with how we handle clockdomains for power management purposes.

As I understand it, each clock domain is essentially a clock gate
controlling multiple clock signals, so it's possible to describe that
with the common clock bindings, with a domain's clocks all coming from a
"domain-gate-clock" node (or something like that). That would make the
wiring of clocks to a domain explicit and in line with the rest of the
common clock bindings. But perhaps I've simplified things a bit too
far.

I'm not sure how easy it would be to use that information for power
management. I don't know what the kernel logic for clock domain power
management needs to know about consumers of the clocks and how it would
need to poke those consumers.

Cheers,
Mark.

[PATCHv5 02/31] CLK: TI: Add DPLL clock support

[Tero Kristo]

On 08/19/2013 07:24 PM, Mark Rutland wrote:
> On Mon, Aug 19, 2013 at 04:09:37PM +0100, Tero Kristo wrote:
>> On 08/19/2013 05:18 PM, Mark Rutland wrote:
>>> On Mon, Aug 19, 2013 at 02:34:45PM +0100, Tero Kristo wrote:
>>>> On 08/13/2013 01:50 PM, Mark Rutland wrote:
>>>>> Hi,
>>>>>
>>>>> On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
>>>>>> The OMAP clock driver now supports DPLL clock type. This patch also
>>>>>> adds support for DT DPLL nodes.
>>>>>>
>>>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>>>> ---
>>>>>>     .../devicetree/bindings/clock/ti/dpll.txt          |   70 +++
>>>>>>     arch/arm/mach-omap2/clock.h                        |  144 +-----
>>>>>>     arch/arm/mach-omap2/clock3xxx.h                    |    2 -
>>>>>>     drivers/clk/Makefile                               |    1 +
>>>>>>     drivers/clk/ti/Makefile                            |    3 +
>>>>>>     drivers/clk/ti/dpll.c                              |  488 ++++++++++++++++++++
>>>>>>     include/linux/clk/ti.h                             |  164 +++++++
>>>>>>     7 files changed, 727 insertions(+), 145 deletions(-)
>>>>>>     create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
>>>>>>     create mode 100644 drivers/clk/ti/Makefile
>>>>>>     create mode 100644 drivers/clk/ti/dpll.c
>>>>>>     create mode 100644 include/linux/clk/ti.h
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
>>>>>> new file mode 100644
>>>>>> index 0000000..dcd6e63
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
>>>>>> @@ -0,0 +1,70 @@
>>>>>> +Binding for Texas Instruments DPLL clock.
>>>>>> +
>>>>>> +This binding uses the common clock binding[1].  It assumes a
>>>>>> +register-mapped DPLL with usually two selectable input clocks
>>>>>> +(reference clock and bypass clock), with digital phase locked
>>>>>> +loop logic for multiplying the input clock to a desired output
>>>>>> +clock. This clock also typically supports different operation
>>>>>> +modes (locked, low power stop etc.) This binding has several
>>>>>> +sub-types, which effectively result in slightly different setup
>>>>>> +for the actual DPLL clock.
>>>>>> +
>>>>>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>>> +
>>>>>> +Required properties:
>>>>>> +- compatible : shall be one of:
>>>>>> +               "ti,omap4-dpll-x2-clock",
>>>>>> +               "ti,omap3-dpll-clock",
>>>>>> +               "ti,omap3-dpll-core-clock",
>>>>>> +               "ti,omap3-dpll-per-clock",
>>>>>> +               "ti,omap3-dpll-per-j-type-clock",
>>>>>> +               "ti,omap4-dpll-clock",
>>>>>> +               "ti,omap4-dpll-core-clock",
>>>>>> +               "ti,omap4-dpll-m4xen-clock",
>>>>>> +               "ti,omap4-dpll-j-type-clock",
>>>>>> +               "ti,omap4-dpll-no-gate-clock",
>>>>>> +               "ti,omap4-dpll-no-gate-j-type-clock",
>>>>>> +
>>>>>> +- #clock-cells : from common clock binding; shall be set to 0.
>>>>>> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
>>>>>
>>>>> It might be a good idea to use clock-names to clarify which clocks are
>>>>> present (I notice your examples contain only one clock input).
>>>>
>>>> All DPLLs have both bypass and reference clocks, but these can be the
>>>> same. Is it better to just list both always (and hence drop
>>>> clock-names), or provide clock-names always?
>>>
>>> If they're separate inputs, it's worth listing both (even if they're fed
>>> by the same provider). If it's possible one input might not be wired up,
>>> use clock-names.
>>
>> Ref and bypass clocks are used currently by all DPLLs (also the APLL) so
>> I guess I just enforce both to be specified.
>
> Ok. It's always possible to add clock-names later if a platform doesn't
> wire an input. We lose the possibility of future compatibility, but
> backwards compatibility is easy enough to maintain.
>
>>>>>> +- ti,clkdm-name : clockdomain name for the DPLL
>>>>>
>>>>> Could you elaborate on what this is for? What constitutes a valid name?
>>>>>
>>>>> I'm not sure a string is the best way to define the linkage of several
>>>>> elements to a domain...
>>>>
>>>> Well, I am not sure if we can do this any better at this point, we don't
>>>> have DT nodes for clockdomain at the moment (I am not sure if we will
>>>> have those either as there are only a handful of those per SoC) but I'll
>>>> add some more documentation for this.
>>>
>>> I'll have to see the documentation, but I'd be very wary of putting that
>>> in as-is. Does having the clock domain string link this up to domains in
>>> platform data?
>>>
>>> I'm not sure how well we'll be able to maintain support for that in
>>> future if it requires other platform code to use now, and we're not sure
>>> how the domains themselves will be represented in dt.
>>
>> Hmm so, should I add a stub representation for the clockdomains to the
>> DT then for now or how should this be handled? The stubs could then be
>> mapped to the actual clock domains based on their node names.
>>
>
> I unfortunately don't have a good answer here, because I'm not that
> familiar with how we handle clockdomains for power management purposes.
>
> As I understand it, each clock domain is essentially a clock gate
> controlling multiple clock signals, so it's possible to describe that
> with the common clock bindings, with a domain's clocks all coming from a
> "domain-gate-clock" node (or something like that). That would make the
> wiring of clocks to a domain explicit and in line with the rest of the
> common clock bindings. But perhaps I've simplified things a bit too
> far.

You got it basically right, but maybe oversimplified it a bit. The 
root/parent clocks can still cross clockdomain boundaries, so mapping 
everything under a simple clockdomain gate would not work. Basically 
each clock has a mapping on the SoC for both its parent clock signal and 
the clockdomain association, kind of having two parents at the same 
time. In OMAP case, most of the clockdomains support hardware autoidle 
type functionality, which puts the domain to idle once all the clocks on 
it are disabled.

-Tero

> I'm not sure how easy it would be to use that information for power
> management. I don't know what the kernel logic for clock domain power
> management needs to know about consumers of the clocks and how it would
> need to poke those consumers.

>
> Cheers,
> Mark.
>

[PATCHv5 02/31] CLK: TI: Add DPLL clock support

[Mike Turquette]

Quoting Tero Kristo (2013-08-19 10:06:39)
> On 08/19/2013 07:24 PM, Mark Rutland wrote:
> > On Mon, Aug 19, 2013 at 04:09:37PM +0100, Tero Kristo wrote:
> >> On 08/19/2013 05:18 PM, Mark Rutland wrote:
> >>> On Mon, Aug 19, 2013 at 02:34:45PM +0100, Tero Kristo wrote:
> >>>> On 08/13/2013 01:50 PM, Mark Rutland wrote:
> >>>>> Hi,
> >>>>>
> >>>>> On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
> >>>>>> The OMAP clock driver now supports DPLL clock type. This patch also
> >>>>>> adds support for DT DPLL nodes.
> >>>>>>
> >>>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >>>>>> ---
> >>>>>>     .../devicetree/bindings/clock/ti/dpll.txt          |   70 +++
> >>>>>>     arch/arm/mach-omap2/clock.h                        |  144 +-----
> >>>>>>     arch/arm/mach-omap2/clock3xxx.h                    |    2 -
> >>>>>>     drivers/clk/Makefile                               |    1 +
> >>>>>>     drivers/clk/ti/Makefile                            |    3 +
> >>>>>>     drivers/clk/ti/dpll.c                              |  488 ++++++++++++++++++++
> >>>>>>     include/linux/clk/ti.h                             |  164 +++++++
> >>>>>>     7 files changed, 727 insertions(+), 145 deletions(-)
> >>>>>>     create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
> >>>>>>     create mode 100644 drivers/clk/ti/Makefile
> >>>>>>     create mode 100644 drivers/clk/ti/dpll.c
> >>>>>>     create mode 100644 include/linux/clk/ti.h
> >>>>>>
> >>>>>> diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> >>>>>> new file mode 100644
> >>>>>> index 0000000..dcd6e63
> >>>>>> --- /dev/null
> >>>>>> +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> >>>>>> @@ -0,0 +1,70 @@
> >>>>>> +Binding for Texas Instruments DPLL clock.
> >>>>>> +
> >>>>>> +This binding uses the common clock binding[1].  It assumes a
> >>>>>> +register-mapped DPLL with usually two selectable input clocks
> >>>>>> +(reference clock and bypass clock), with digital phase locked
> >>>>>> +loop logic for multiplying the input clock to a desired output
> >>>>>> +clock. This clock also typically supports different operation
> >>>>>> +modes (locked, low power stop etc.) This binding has several
> >>>>>> +sub-types, which effectively result in slightly different setup
> >>>>>> +for the actual DPLL clock.
> >>>>>> +
> >>>>>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> >>>>>> +
> >>>>>> +Required properties:
> >>>>>> +- compatible : shall be one of:
> >>>>>> +               "ti,omap4-dpll-x2-clock",
> >>>>>> +               "ti,omap3-dpll-clock",
> >>>>>> +               "ti,omap3-dpll-core-clock",
> >>>>>> +               "ti,omap3-dpll-per-clock",
> >>>>>> +               "ti,omap3-dpll-per-j-type-clock",
> >>>>>> +               "ti,omap4-dpll-clock",
> >>>>>> +               "ti,omap4-dpll-core-clock",
> >>>>>> +               "ti,omap4-dpll-m4xen-clock",
> >>>>>> +               "ti,omap4-dpll-j-type-clock",
> >>>>>> +               "ti,omap4-dpll-no-gate-clock",
> >>>>>> +               "ti,omap4-dpll-no-gate-j-type-clock",
> >>>>>> +
> >>>>>> +- #clock-cells : from common clock binding; shall be set to 0.
> >>>>>> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
> >>>>>
> >>>>> It might be a good idea to use clock-names to clarify which clocks are
> >>>>> present (I notice your examples contain only one clock input).
> >>>>
> >>>> All DPLLs have both bypass and reference clocks, but these can be the
> >>>> same. Is it better to just list both always (and hence drop
> >>>> clock-names), or provide clock-names always?
> >>>
> >>> If they're separate inputs, it's worth listing both (even if they're fed
> >>> by the same provider). If it's possible one input might not be wired up,
> >>> use clock-names.
> >>
> >> Ref and bypass clocks are used currently by all DPLLs (also the APLL) so
> >> I guess I just enforce both to be specified.
> >
> > Ok. It's always possible to add clock-names later if a platform doesn't
> > wire an input. We lose the possibility of future compatibility, but
> > backwards compatibility is easy enough to maintain.
> >
> >>>>>> +- ti,clkdm-name : clockdomain name for the DPLL
> >>>>>
> >>>>> Could you elaborate on what this is for? What constitutes a valid name?
> >>>>>
> >>>>> I'm not sure a string is the best way to define the linkage of several
> >>>>> elements to a domain...
> >>>>
> >>>> Well, I am not sure if we can do this any better at this point, we don't
> >>>> have DT nodes for clockdomain at the moment (I am not sure if we will
> >>>> have those either as there are only a handful of those per SoC) but I'll
> >>>> add some more documentation for this.
> >>>
> >>> I'll have to see the documentation, but I'd be very wary of putting that
> >>> in as-is. Does having the clock domain string link this up to domains in
> >>> platform data?
> >>>
> >>> I'm not sure how well we'll be able to maintain support for that in
> >>> future if it requires other platform code to use now, and we're not sure
> >>> how the domains themselves will be represented in dt.
> >>
> >> Hmm so, should I add a stub representation for the clockdomains to the
> >> DT then for now or how should this be handled? The stubs could then be
> >> mapped to the actual clock domains based on their node names.

I'm not sure that this binding should know about the clock domain at
all. Maybe the clock domain binding should list the clocks that are
within the domain?

> >>
> >
> > I unfortunately don't have a good answer here, because I'm not that
> > familiar with how we handle clockdomains for power management purposes.
> >
> > As I understand it, each clock domain is essentially a clock gate
> > controlling multiple clock signals, so it's possible to describe that
> > with the common clock bindings, with a domain's clocks all coming from a
> > "domain-gate-clock" node (or something like that). That would make the
> > wiring of clocks to a domain explicit and in line with the rest of the
> > common clock bindings. But perhaps I've simplified things a bit too
> > far.
> 
> You got it basically right, but maybe oversimplified it a bit. The 
> root/parent clocks can still cross clockdomain boundaries, so mapping 
> everything under a simple clockdomain gate would not work. Basically 
> each clock has a mapping on the SoC for both its parent clock signal and 
> the clockdomain association, kind of having two parents at the same 
> time. In OMAP case, most of the clockdomains support hardware autoidle 
> type functionality, which puts the domain to idle once all the clocks on 
> it are disabled.

I always thought that OMAP clock domains were poorly named. Seems to me
that they had more to do with the IP/module programming than clocks per
se.  Again, I'm not sure that putting clkdm data into this binding is
correct.

Is it because you want a call to clk_enable to program the clock domain
in the .enable callback? I always thought that this was better left to a
pm_runtime_get callback...

Regards,
Mike

> 
> -Tero
> 
> > I'm not sure how easy it would be to use that information for power
> > management. I don't know what the kernel logic for clock domain power
> > management needs to know about consumers of the clocks and how it would
> > need to poke those consumers.
> 
> >
> > Cheers,
> > Mark.
> >

[PATCHv5 02/31] CLK: TI: Add DPLL clock support

[Tero Kristo]

On 08/20/2013 01:00 AM, Mike Turquette wrote:
> Quoting Tero Kristo (2013-08-19 10:06:39)
>> On 08/19/2013 07:24 PM, Mark Rutland wrote:
>>> On Mon, Aug 19, 2013 at 04:09:37PM +0100, Tero Kristo wrote:
>>>> On 08/19/2013 05:18 PM, Mark Rutland wrote:
>>>>> On Mon, Aug 19, 2013 at 02:34:45PM +0100, Tero Kristo wrote:
>>>>>> On 08/13/2013 01:50 PM, Mark Rutland wrote:
>>>>>>> Hi,
>>>>>>>
>>>>>>> On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
>>>>>>>> The OMAP clock driver now supports DPLL clock type. This patch also
>>>>>>>> adds support for DT DPLL nodes.
>>>>>>>>
>>>>>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>>>>>> ---
>>>>>>>>      .../devicetree/bindings/clock/ti/dpll.txt          |   70 +++
>>>>>>>>      arch/arm/mach-omap2/clock.h                        |  144 +-----
>>>>>>>>      arch/arm/mach-omap2/clock3xxx.h                    |    2 -
>>>>>>>>      drivers/clk/Makefile                               |    1 +
>>>>>>>>      drivers/clk/ti/Makefile                            |    3 +
>>>>>>>>      drivers/clk/ti/dpll.c                              |  488 ++++++++++++++++++++
>>>>>>>>      include/linux/clk/ti.h                             |  164 +++++++
>>>>>>>>      7 files changed, 727 insertions(+), 145 deletions(-)
>>>>>>>>      create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
>>>>>>>>      create mode 100644 drivers/clk/ti/Makefile
>>>>>>>>      create mode 100644 drivers/clk/ti/dpll.c
>>>>>>>>      create mode 100644 include/linux/clk/ti.h
>>>>>>>>
>>>>>>>> diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
>>>>>>>> new file mode 100644
>>>>>>>> index 0000000..dcd6e63
>>>>>>>> --- /dev/null
>>>>>>>> +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
>>>>>>>> @@ -0,0 +1,70 @@
>>>>>>>> +Binding for Texas Instruments DPLL clock.
>>>>>>>> +
>>>>>>>> +This binding uses the common clock binding[1].  It assumes a
>>>>>>>> +register-mapped DPLL with usually two selectable input clocks
>>>>>>>> +(reference clock and bypass clock), with digital phase locked
>>>>>>>> +loop logic for multiplying the input clock to a desired output
>>>>>>>> +clock. This clock also typically supports different operation
>>>>>>>> +modes (locked, low power stop etc.) This binding has several
>>>>>>>> +sub-types, which effectively result in slightly different setup
>>>>>>>> +for the actual DPLL clock.
>>>>>>>> +
>>>>>>>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>>>>> +
>>>>>>>> +Required properties:
>>>>>>>> +- compatible : shall be one of:
>>>>>>>> +               "ti,omap4-dpll-x2-clock",
>>>>>>>> +               "ti,omap3-dpll-clock",
>>>>>>>> +               "ti,omap3-dpll-core-clock",
>>>>>>>> +               "ti,omap3-dpll-per-clock",
>>>>>>>> +               "ti,omap3-dpll-per-j-type-clock",
>>>>>>>> +               "ti,omap4-dpll-clock",
>>>>>>>> +               "ti,omap4-dpll-core-clock",
>>>>>>>> +               "ti,omap4-dpll-m4xen-clock",
>>>>>>>> +               "ti,omap4-dpll-j-type-clock",
>>>>>>>> +               "ti,omap4-dpll-no-gate-clock",
>>>>>>>> +               "ti,omap4-dpll-no-gate-j-type-clock",
>>>>>>>> +
>>>>>>>> +- #clock-cells : from common clock binding; shall be set to 0.
>>>>>>>> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
>>>>>>>
>>>>>>> It might be a good idea to use clock-names to clarify which clocks are
>>>>>>> present (I notice your examples contain only one clock input).
>>>>>>
>>>>>> All DPLLs have both bypass and reference clocks, but these can be the
>>>>>> same. Is it better to just list both always (and hence drop
>>>>>> clock-names), or provide clock-names always?
>>>>>
>>>>> If they're separate inputs, it's worth listing both (even if they're fed
>>>>> by the same provider). If it's possible one input might not be wired up,
>>>>> use clock-names.
>>>>
>>>> Ref and bypass clocks are used currently by all DPLLs (also the APLL) so
>>>> I guess I just enforce both to be specified.
>>>
>>> Ok. It's always possible to add clock-names later if a platform doesn't
>>> wire an input. We lose the possibility of future compatibility, but
>>> backwards compatibility is easy enough to maintain.
>>>
>>>>>>>> +- ti,clkdm-name : clockdomain name for the DPLL
>>>>>>>
>>>>>>> Could you elaborate on what this is for? What constitutes a valid name?
>>>>>>>
>>>>>>> I'm not sure a string is the best way to define the linkage of several
>>>>>>> elements to a domain...
>>>>>>
>>>>>> Well, I am not sure if we can do this any better at this point, we don't
>>>>>> have DT nodes for clockdomain at the moment (I am not sure if we will
>>>>>> have those either as there are only a handful of those per SoC) but I'll
>>>>>> add some more documentation for this.
>>>>>
>>>>> I'll have to see the documentation, but I'd be very wary of putting that
>>>>> in as-is. Does having the clock domain string link this up to domains in
>>>>> platform data?
>>>>>
>>>>> I'm not sure how well we'll be able to maintain support for that in
>>>>> future if it requires other platform code to use now, and we're not sure
>>>>> how the domains themselves will be represented in dt.
>>>>
>>>> Hmm so, should I add a stub representation for the clockdomains to the
>>>> DT then for now or how should this be handled? The stubs could then be
>>>> mapped to the actual clock domains based on their node names.
>
> I'm not sure that this binding should know about the clock domain at
> all. Maybe the clock domain binding should list the clocks that are
> within the domain?

Ok, I experimented with this stuff a bit to have a proper reply, and it 
looks like I can get this done with a clockdomain mapping, which has its 
own binding. Something like this:

         clockdomains {
                 usbhost_clkdm: usbhost_clkdm {
                         compatible = "ti,clockdomain";
                         clocks = <&usbhost_48m_fck>, <&usbhost_ick>;
                 };
	};

Mike, what is your approach on this? Are you okay having the 
implementation for this under drivers/clk? I recall you mentioned 
earlier that you don't want clockdomain stuff under drivers/clk, hence I 
am asking.

Here is the initial implementation for the binding:

void __init of_omap_clockdomain_setup(struct device_node *node)
{
         struct clk *clk;
         struct clk_hw *clk_hw;
         const char *clkdm_name = node->name;
         int i;
         int num_clks;

         num_clks = of_count_phandle_with_args(node, "clocks", 
"#clock-cells");

         for (i = 0; i < num_clks; i++) {
                 clk = of_clk_get(node, i);
                 if (__clk_get_flags(clk) & CLK_IS_BASIC) {
                         pr_warn("%s: can't setup clkdm for basic clk %s\n",
                                 __func__, __clk_get_name(clk));
                         continue;
                 }
                 clk_hw = __clk_get_hw(clk);
                 to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
                 omap2_init_clk_clkdm(clk_hw);
         }
}
CLK_OF_DECLARE(omap_clockdomain, "ti,clockdomain", 
of_omap_clockdomain_setup);

>
>>>>
>>>
>>> I unfortunately don't have a good answer here, because I'm not that
>>> familiar with how we handle clockdomains for power management purposes.
>>>
>>> As I understand it, each clock domain is essentially a clock gate
>>> controlling multiple clock signals, so it's possible to describe that
>>> with the common clock bindings, with a domain's clocks all coming from a
>>> "domain-gate-clock" node (or something like that). That would make the
>>> wiring of clocks to a domain explicit and in line with the rest of the
>>> common clock bindings. But perhaps I've simplified things a bit too
>>> far.
>>
>> You got it basically right, but maybe oversimplified it a bit. The
>> root/parent clocks can still cross clockdomain boundaries, so mapping
>> everything under a simple clockdomain gate would not work. Basically
>> each clock has a mapping on the SoC for both its parent clock signal and
>> the clockdomain association, kind of having two parents at the same
>> time. In OMAP case, most of the clockdomains support hardware autoidle
>> type functionality, which puts the domain to idle once all the clocks on
>> it are disabled.
>
> I always thought that OMAP clock domains were poorly named. Seems to me
> that they had more to do with the IP/module programming than clocks per
> se.  Again, I'm not sure that putting clkdm data into this binding is
> correct.
>
> Is it because you want a call to clk_enable to program the clock domain
> in the .enable callback? I always thought that this was better left to a
> pm_runtime_get callback...

My guess is that some clocks require the clockdomain itself to be forced 
on before they are enabled, some of the DPLLs do this for example. I am 
just trying not to cause any regressions with this set, thus attempting 
to keep most of the implementation specifics intact.

-Tero

>
> Regards,
> Mike
>
>>
>> -Tero
>>
>>> I'm not sure how easy it would be to use that information for power
>>> management. I don't know what the kernel logic for clock domain power
>>> management needs to know about consumers of the clocks and how it would
>>> need to poke those consumers.
>>
>>>
>>> Cheers,
>>> Mark.
>>>

[PATCHv5 02/31] CLK: TI: Add DPLL clock support

[Mike Turquette]

Quoting Tero Kristo (2013-08-21 09:16:45)
> On 08/20/2013 01:00 AM, Mike Turquette wrote:
> > Quoting Tero Kristo (2013-08-19 10:06:39)
> >> On 08/19/2013 07:24 PM, Mark Rutland wrote:
> >>> On Mon, Aug 19, 2013 at 04:09:37PM +0100, Tero Kristo wrote:
> >>>> On 08/19/2013 05:18 PM, Mark Rutland wrote:
> >>>>> On Mon, Aug 19, 2013 at 02:34:45PM +0100, Tero Kristo wrote:
> >>>>>> On 08/13/2013 01:50 PM, Mark Rutland wrote:
> >>>>>>> Hi,
> >>>>>>>
> >>>>>>> On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
> >>>>>>>> The OMAP clock driver now supports DPLL clock type. This patch also
> >>>>>>>> adds support for DT DPLL nodes.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >>>>>>>> ---
> >>>>>>>>      .../devicetree/bindings/clock/ti/dpll.txt          |   70 +++
> >>>>>>>>      arch/arm/mach-omap2/clock.h                        |  144 +-----
> >>>>>>>>      arch/arm/mach-omap2/clock3xxx.h                    |    2 -
> >>>>>>>>      drivers/clk/Makefile                               |    1 +
> >>>>>>>>      drivers/clk/ti/Makefile                            |    3 +
> >>>>>>>>      drivers/clk/ti/dpll.c                              |  488 ++++++++++++++++++++
> >>>>>>>>      include/linux/clk/ti.h                             |  164 +++++++
> >>>>>>>>      7 files changed, 727 insertions(+), 145 deletions(-)
> >>>>>>>>      create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt
> >>>>>>>>      create mode 100644 drivers/clk/ti/Makefile
> >>>>>>>>      create mode 100644 drivers/clk/ti/dpll.c
> >>>>>>>>      create mode 100644 include/linux/clk/ti.h
> >>>>>>>>
> >>>>>>>> diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> >>>>>>>> new file mode 100644
> >>>>>>>> index 0000000..dcd6e63
> >>>>>>>> --- /dev/null
> >>>>>>>> +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
> >>>>>>>> @@ -0,0 +1,70 @@
> >>>>>>>> +Binding for Texas Instruments DPLL clock.
> >>>>>>>> +
> >>>>>>>> +This binding uses the common clock binding[1].  It assumes a
> >>>>>>>> +register-mapped DPLL with usually two selectable input clocks
> >>>>>>>> +(reference clock and bypass clock), with digital phase locked
> >>>>>>>> +loop logic for multiplying the input clock to a desired output
> >>>>>>>> +clock. This clock also typically supports different operation
> >>>>>>>> +modes (locked, low power stop etc.) This binding has several
> >>>>>>>> +sub-types, which effectively result in slightly different setup
> >>>>>>>> +for the actual DPLL clock.
> >>>>>>>> +
> >>>>>>>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> >>>>>>>> +
> >>>>>>>> +Required properties:
> >>>>>>>> +- compatible : shall be one of:
> >>>>>>>> +               "ti,omap4-dpll-x2-clock",
> >>>>>>>> +               "ti,omap3-dpll-clock",
> >>>>>>>> +               "ti,omap3-dpll-core-clock",
> >>>>>>>> +               "ti,omap3-dpll-per-clock",
> >>>>>>>> +               "ti,omap3-dpll-per-j-type-clock",
> >>>>>>>> +               "ti,omap4-dpll-clock",
> >>>>>>>> +               "ti,omap4-dpll-core-clock",
> >>>>>>>> +               "ti,omap4-dpll-m4xen-clock",
> >>>>>>>> +               "ti,omap4-dpll-j-type-clock",
> >>>>>>>> +               "ti,omap4-dpll-no-gate-clock",
> >>>>>>>> +               "ti,omap4-dpll-no-gate-j-type-clock",
> >>>>>>>> +
> >>>>>>>> +- #clock-cells : from common clock binding; shall be set to 0.
> >>>>>>>> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
> >>>>>>>
> >>>>>>> It might be a good idea to use clock-names to clarify which clocks are
> >>>>>>> present (I notice your examples contain only one clock input).
> >>>>>>
> >>>>>> All DPLLs have both bypass and reference clocks, but these can be the
> >>>>>> same. Is it better to just list both always (and hence drop
> >>>>>> clock-names), or provide clock-names always?
> >>>>>
> >>>>> If they're separate inputs, it's worth listing both (even if they're fed
> >>>>> by the same provider). If it's possible one input might not be wired up,
> >>>>> use clock-names.
> >>>>
> >>>> Ref and bypass clocks are used currently by all DPLLs (also the APLL) so
> >>>> I guess I just enforce both to be specified.
> >>>
> >>> Ok. It's always possible to add clock-names later if a platform doesn't
> >>> wire an input. We lose the possibility of future compatibility, but
> >>> backwards compatibility is easy enough to maintain.
> >>>
> >>>>>>>> +- ti,clkdm-name : clockdomain name for the DPLL
> >>>>>>>
> >>>>>>> Could you elaborate on what this is for? What constitutes a valid name?
> >>>>>>>
> >>>>>>> I'm not sure a string is the best way to define the linkage of several
> >>>>>>> elements to a domain...
> >>>>>>
> >>>>>> Well, I am not sure if we can do this any better at this point, we don't
> >>>>>> have DT nodes for clockdomain at the moment (I am not sure if we will
> >>>>>> have those either as there are only a handful of those per SoC) but I'll
> >>>>>> add some more documentation for this.
> >>>>>
> >>>>> I'll have to see the documentation, but I'd be very wary of putting that
> >>>>> in as-is. Does having the clock domain string link this up to domains in
> >>>>> platform data?
> >>>>>
> >>>>> I'm not sure how well we'll be able to maintain support for that in
> >>>>> future if it requires other platform code to use now, and we're not sure
> >>>>> how the domains themselves will be represented in dt.
> >>>>
> >>>> Hmm so, should I add a stub representation for the clockdomains to the
> >>>> DT then for now or how should this be handled? The stubs could then be
> >>>> mapped to the actual clock domains based on their node names.
> >
> > I'm not sure that this binding should know about the clock domain at
> > all. Maybe the clock domain binding should list the clocks that are
> > within the domain?
> 
> Ok, I experimented with this stuff a bit to have a proper reply, and it 
> looks like I can get this done with a clockdomain mapping, which has its 
> own binding. Something like this:
> 
>          clockdomains {
>                  usbhost_clkdm: usbhost_clkdm {
>                          compatible = "ti,clockdomain";
>                          clocks = <&usbhost_48m_fck>, <&usbhost_ick>;
>                  };
>         };

Cool, this is much closer to what I had in mind. I guess the clock
domain DT binding can be marked as "Unstable - ABI compatibility may be
broken in the future" since the binding isn't really fleshed out yet.

> 
> Mike, what is your approach on this? Are you okay having the 
> implementation for this under drivers/clk? I recall you mentioned 
> earlier that you don't want clockdomain stuff under drivers/clk, hence I 
> am asking.

I do not want them to live there permanently. There has been some talk
about drivers/syscon/ or whatever for a while now, but this clkdm stuff
is also not a good candidate for that since none of the clkdm bits here
are really fleshed out with an eye towards a reusable core framework.
Maybe someday though...

I guess I could take it into drivers/clk/ti/ on a temporary basis, with
a commitment to move it out when the right driver infrastructure for
clock domains comes along.

Regards,
Mike

> 
> Here is the initial implementation for the binding:
> 
> void __init of_omap_clockdomain_setup(struct device_node *node)
> {
>          struct clk *clk;
>          struct clk_hw *clk_hw;
>          const char *clkdm_name = node->name;
>          int i;
>          int num_clks;
> 
>          num_clks = of_count_phandle_with_args(node, "clocks", 
> "#clock-cells");
> 
>          for (i = 0; i < num_clks; i++) {
>                  clk = of_clk_get(node, i);
>                  if (__clk_get_flags(clk) & CLK_IS_BASIC) {
>                          pr_warn("%s: can't setup clkdm for basic clk %s\n",
>                                  __func__, __clk_get_name(clk));
>                          continue;
>                  }
>                  clk_hw = __clk_get_hw(clk);
>                  to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
>                  omap2_init_clk_clkdm(clk_hw);
>          }
> }
> CLK_OF_DECLARE(omap_clockdomain, "ti,clockdomain", 
> of_omap_clockdomain_setup);
> 
> >
> >>>>
> >>>
> >>> I unfortunately don't have a good answer here, because I'm not that
> >>> familiar with how we handle clockdomains for power management purposes.
> >>>
> >>> As I understand it, each clock domain is essentially a clock gate
> >>> controlling multiple clock signals, so it's possible to describe that
> >>> with the common clock bindings, with a domain's clocks all coming from a
> >>> "domain-gate-clock" node (or something like that). That would make the
> >>> wiring of clocks to a domain explicit and in line with the rest of the
> >>> common clock bindings. But perhaps I've simplified things a bit too
> >>> far.
> >>
> >> You got it basically right, but maybe oversimplified it a bit. The
> >> root/parent clocks can still cross clockdomain boundaries, so mapping
> >> everything under a simple clockdomain gate would not work. Basically
> >> each clock has a mapping on the SoC for both its parent clock signal and
> >> the clockdomain association, kind of having two parents at the same
> >> time. In OMAP case, most of the clockdomains support hardware autoidle
> >> type functionality, which puts the domain to idle once all the clocks on
> >> it are disabled.
> >
> > I always thought that OMAP clock domains were poorly named. Seems to me
> > that they had more to do with the IP/module programming than clocks per
> > se.  Again, I'm not sure that putting clkdm data into this binding is
> > correct.
> >
> > Is it because you want a call to clk_enable to program the clock domain
> > in the .enable callback? I always thought that this was better left to a
> > pm_runtime_get callback...
> 
> My guess is that some clocks require the clockdomain itself to be forced 
> on before they are enabled, some of the DPLLs do this for example. I am 
> just trying not to cause any regressions with this set, thus attempting 
> to keep most of the implementation specifics intact.
> 
> -Tero
> 
> >
> > Regards,
> > Mike
> >
> >>
> >> -Tero
> >>
> >>> I'm not sure how easy it would be to use that information for power
> >>> management. I don't know what the kernel logic for clock domain power
> >>> management needs to know about consumers of the clocks and how it would
> >>> need to poke those consumers.
> >>
> >>>
> >>> Cheers,
> >>> Mark.
> >>>

[PATCHv5 03/31] CLK: TI: add DT alias clock registration mechanism

[Tero Kristo]

Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific clock names.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/ti/Makefile |    2 +-
 drivers/clk/ti/clk.c    |   37 +++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h  |   23 +++++++++++++++++++++++
 3 files changed, 61 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clk.c

diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 93177987..05af5d8 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
 ifneq ($(CONFIG_OF),)
-obj-y					+= dpll.o
+obj-y					+= clk.o dpll.o
 endif
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
new file mode 100644
index 0000000..b6eb756
--- /dev/null
+++ b/drivers/clk/ti/clk.c
@@ -0,0 +1,37 @@
+/*
+ * TI clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+
+/**
+ * omap_dt_clocks_register - register DT duplicate clocks during boot
+ * @oclks: list of clocks to register
+ *
+ * Register duplicate or non-standard DT clock entries during boot. By
+ * default, DT clocks are found based on their node name. If any
+ * additional con-id / dev-id -> clock mapping is required, use this
+ * function to list these.
+ */
+void __init omap_dt_clocks_register(struct omap_dt_clk oclks[])
+{
+	struct omap_dt_clk *c;
+
+	for (c = oclks; c->node_name != NULL; c++)
+		clk_add_alias(c->con_id, c->dev_id, c->node_name, NULL);
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 385384a..dee3234 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -15,6 +15,8 @@
 #ifndef __LINUX_CLK_TI_H__
 #define __LINUX_CLK_TI_H__
 
+#include <linux/clkdev.h>
+
 /**
  * struct dpll_data - DPLL registers and integration data
  * @mult_div1_reg: register containing the DPLL M and N bitfields
@@ -138,6 +140,25 @@ struct clk_hw_omap {
 /* DPLL Type and DCO Selection Flags */
 #define DPLL_J_TYPE		0x1
 
+/**
+ * struct omap_dt_clk - OMAP DT clock alias declarations
+ * @dev_id: alias device ID
+ * @conn_id: alias connection ID
+ * @node_name: clock DT node to map to
+ */
+struct omap_dt_clk {
+	const char			*dev_id;
+	const char			*con_id;
+	char				*node_name;
+};
+
+#define DT_CLK(dev, con, name)		\
+	{				\
+		.dev_id = dev,		\
+		.con_id = con,		\
+		.node_name = name,	\
+	}
+
 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap3_noncore_dpll_enable(struct clk_hw *hw);
 void omap3_noncore_dpll_disable(struct clk_hw *hw);
@@ -158,6 +179,8 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 			 unsigned long parent_rate);
 
+void omap_dt_clocks_register(struct omap_dt_clk *oclks);
+
 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 
-- 
1.7.9.5

[PATCHv5 04/31] CLK: TI: add autoidle support

[Tero Kristo]

TI clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti/autoidle.txt      |   48 ++++++++
 arch/arm/mach-omap2/clock.c                        |    6 +
 drivers/clk/ti/Makefile                            |    2 +-
 drivers/clk/ti/autoidle.c                          |  121 ++++++++++++++++++++
 include/linux/clk/ti.h                             |    7 ++
 5 files changed, 183 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/autoidle.txt
 create mode 100644 drivers/clk/ti/autoidle.c

diff --git a/Documentation/devicetree/bindings/clock/ti/autoidle.txt b/Documentation/devicetree/bindings/clock/ti/autoidle.txt
new file mode 100644
index 0000000..cc09910
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/autoidle.txt
@@ -0,0 +1,48 @@
+Binding for Texas Instruments autoidling clock.
+
+This binding uses the common clock binding[1]. Autoidle clocks
+are inherited clocks from basic divider-clock [2] or
+fixed-factor-clock [3] and just add autoidle support on top of
+this. Autoidle is an OMAP clock feature, which allows the clock
+to gate autonomously by hardware when they are no longer needed.
+The autoidle feature must be enabled manually for these clocks.
+Otherwise the clocks behave exactly as their base clock type.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/divider-clock.txt
+[3] Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
+
+Required properties:
+- compatible : shall be one of:
+		"ti,divider-clock",
+		"ti,fixed-factor-clock"
+- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock
+- reg : base address for the control register of this clock
+
+Optional properties:
+- ti,autoidle-low : autoidle is enabled by setting the bit to 0
+
+Other properties as per the base clock type.
+
+Examples:
+	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0051f0 {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_abe_x2_ck>;
+		ti,autoidle-shift = <8>;
+		reg = <0x4a0051f0 0x4>;
+		bit-mask = <0x1f>;
+		index-starts-at-one;
+		ti,autoidle-low;
+	};
+
+	dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck at 4a0081b4 {
+		#clock-cells = <0>;
+		compatible = "ti,fixed-factor-clock";
+		clocks = <&dpll_usb_ck>;
+		ti,autoidle-shift = <8>;
+		clock-div = <1>;
+		reg = <0x4a0081b4 0x4>;
+		clock-mult = <1>;
+		ti,autoidle-low;
+	};
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca9..669d4c4 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
 		if (c->ops && c->ops->allow_idle)
 			c->ops->allow_idle(c);
+
+	of_omap_clk_allow_autoidle_all();
+
 	return 0;
 }
 
@@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
 		if (c->ops && c->ops->deny_idle)
 			c->ops->deny_idle(c);
+
+	of_omap_clk_deny_autoidle_all();
+
 	return 0;
 }
 
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 05af5d8..533efb4 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
 ifneq ($(CONFIG_OF),)
-obj-y					+= clk.o dpll.o
+obj-y					+= clk.o dpll.o autoidle.o
 endif
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
new file mode 100644
index 0000000..a52a42b
--- /dev/null
+++ b/drivers/clk/ti/autoidle.c
@@ -0,0 +1,121 @@
+/*
+ * OMAP clock autoidle support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+struct clk_omap_autoidle {
+	void __iomem		*reg;
+	u8			shift;
+	u8			flags;
+	const char		*name;
+	struct list_head	node;
+};
+
+#define AUTOIDLE_LOW		0x1
+
+static LIST_HEAD(autoidle_clks);
+
+static void omap_allow_autoidle(struct clk_omap_autoidle *clk)
+{
+	u32 val;
+
+	val = readl(clk->reg);
+
+	if (clk->flags & AUTOIDLE_LOW)
+		val &= ~(1 << clk->shift);
+	else
+		val |= (1 << clk->shift);
+
+	writel(val, clk->reg);
+}
+
+static void omap_deny_autoidle(struct clk_omap_autoidle *clk)
+{
+	u32 val;
+
+	val = readl(clk->reg);
+
+	if (clk->flags & AUTOIDLE_LOW)
+		val |= (1 << clk->shift);
+	else
+		val &= ~(1 << clk->shift);
+
+	writel(val, clk->reg);
+}
+
+void of_omap_clk_allow_autoidle_all(void)
+{
+	struct clk_omap_autoidle *c;
+
+	list_for_each_entry(c, &autoidle_clks, node)
+		omap_allow_autoidle(c);
+}
+
+void of_omap_clk_deny_autoidle_all(void)
+{
+	struct clk_omap_autoidle *c;
+
+	list_for_each_entry(c, &autoidle_clks, node)
+		omap_deny_autoidle(c);
+}
+
+static void __init of_omap_autoidle_setup(struct device_node *node)
+{
+	u32 shift;
+	void __iomem *reg;
+	struct clk_omap_autoidle *clk;
+
+	if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
+		return;
+
+	reg = of_iomap(node, 0);
+
+	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+
+	if (!clk) {
+		pr_err("%s: kzalloc failed\n", __func__);
+		return;
+	}
+
+	clk->shift = shift;
+	clk->name = node->name;
+	clk->reg = reg;
+
+	if (of_property_read_bool(node, "ti,autoidle-low"))
+		clk->flags |= AUTOIDLE_LOW;
+
+	list_add(&clk->node, &autoidle_clks);
+}
+
+static void __init of_omap_divider_setup(struct device_node *node)
+{
+	of_divider_clk_setup(node);
+	of_omap_autoidle_setup(node);
+}
+CLK_OF_DECLARE(omap_divider_clock, "ti,divider-clock", of_omap_divider_setup);
+
+static void __init of_omap_fixed_factor_setup(struct device_node *node)
+{
+	of_fixed_factor_clk_setup(node);
+	of_omap_autoidle_setup(node);
+}
+CLK_OF_DECLARE(omap_fixed_factor_clock, "ti,fixed-factor-clock",
+	       of_omap_fixed_factor_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index dee3234..781ef23 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -180,6 +180,13 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 			 unsigned long parent_rate);
 
 void omap_dt_clocks_register(struct omap_dt_clk *oclks);
+#ifdef CONFIG_OF
+void of_omap_clk_allow_autoidle_all(void);
+void of_omap_clk_deny_autoidle_all(void);
+#else
+static inline void of_omap_clk_allow_autoidle_all(void) { }
+static inline void of_omap_clk_deny_autoidle_all(void) { }
+#endif
 
 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
-- 
1.7.9.5

[PATCHv5 05/31] CLK: TI: add support for OMAP gate clock

[Tero Kristo]

This node adds support for a clock node which allows control to the
clockdomain enable / disable.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti/gate.txt          |   41 ++++++++
 arch/arm/mach-omap2/clock.h                        |    9 --
 drivers/clk/ti/Makefile                            |    2 +-
 drivers/clk/ti/gate.c                              |  106 ++++++++++++++++++++
 include/linux/clk/ti.h                             |    8 ++
 5 files changed, 156 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
 create mode 100644 drivers/clk/ti/gate.c

diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
new file mode 100644
index 0000000..620a73d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
@@ -0,0 +1,41 @@
+Binding for Texas Instruments gate clock.
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features. If no register
+is provided for this clock, the code assumes that a clockdomain
+will be controlled instead and the corresponding hw-ops for
+that is used.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+
+Required properties:
+- compatible : shall be "ti,gate-clock"
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+
+Optional properties:
+- reg : base address for register controlling adjustable gate
+- ti,enable-bit : bit shift for programming the clock gate
+- ti,dss-clk : use DSS hardware OPS for the clock
+- ti,am35xx-clk : use AM35xx hardware OPS for the clock
+- ti,clkdm-name : clockdomain to control this gate
+
+Examples:
+	trace_clk_div_ck: trace_clk_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&trace_clk_div_div_ck>;
+		ti,clkdm-name = "emu_sys_clkdm";
+	};
+
+	emac_ick: emac_ick at 4800259c {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&ipss_ick>;
+		reg = <0x4800259c 0x4>;
+		ti,clkdm-name = "core_l3_clkdm";
+		ti,enable-bit = <1>;
+		ti,am35xx-clk;
+	};
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 079536a..1a8c41a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -260,9 +260,6 @@ extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
 
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
-int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap2_dflt_clk_disable(struct clk_hw *hw);
-int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
 				   void __iomem **other_reg,
 				   u8 *other_bit);
@@ -292,15 +289,12 @@ extern const struct clksel_rate dsp_ick_rates[];
 extern struct clk dummy_ck;
 
 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
-extern const struct clk_hw_omap_ops clkhwops_wait;
 extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
 extern const struct clk_hw_omap_ops clkhwops_apll54;
 extern const struct clk_hw_omap_ops clkhwops_apll96;
@@ -318,8 +312,5 @@ extern const struct clksel_rate div31_1to31_rates[];
 
 extern int am33xx_clk_init(void);
 
-extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
-extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
-
 extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
 #endif
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 533efb4..57bfbaa 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,3 @@
 ifneq ($(CONFIG_OF),)
-obj-y					+= clk.o dpll.o autoidle.o
+obj-y					+= clk.o dpll.o autoidle.o gate.o
 endif
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
new file mode 100644
index 0000000..2c68310
--- /dev/null
+++ b/drivers/clk/ti/gate.c
@@ -0,0 +1,106 @@
+/*
+ * OMAP gate clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+static const struct clk_ops omap_gate_clkdm_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_clkops_enable_clkdm,
+	.disable	= &omap2_clkops_disable_clkdm,
+};
+
+static const struct clk_ops omap_gate_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+void __init of_omap_gate_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_init_data init = { 0 };
+	struct clk_hw_omap *clk_hw;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names = NULL;
+	int i;
+	u32 val;
+
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return;
+	}
+
+	clk_hw->hw.init = &init;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
+
+	init.name = clk_name;
+	init.flags = 0;
+
+	if (of_property_read_u32_index(node, "reg", 0, &val)) {
+		/* No register, clkdm control only */
+		init.ops = &omap_gate_clkdm_clk_ops;
+	} else {
+		init.ops = &omap_gate_clk_ops;
+		clk_hw->enable_reg = of_iomap(node, 0);
+		of_property_read_u32(node, "ti,enable-bit", &val);
+		clk_hw->enable_bit = val;
+
+		clk_hw->ops = &clkhwops_wait;
+
+		if (of_property_read_bool(node, "ti,dss-clk"))
+			clk_hw->ops = &clkhwops_omap3430es2_dss_usbhost_wait;
+
+		if (of_property_read_bool(node, "ti,am35xx-clk"))
+			clk_hw->ops = &clkhwops_am35xx_ipss_module_wait;
+	}
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap trace_clk %s must have parent(s)\n",
+		       __func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	init.num_parents = num_parents;
+	init.parent_names = parent_names;
+
+	clk = clk_register(NULL, &clk_hw->hw);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		return;
+	}
+
+cleanup:
+	kfree(parent_names);
+	kfree(clk_hw);
+}
+CLK_OF_DECLARE(omap_gate_clk, "ti,gate-clock", of_omap_gate_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 781ef23..eec4973 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -176,8 +176,13 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 void omap2_init_clk_clkdm(struct clk_hw *clk);
 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 				    unsigned long parent_rate);
+int omap2_clkops_enable_clkdm(struct clk_hw *hw);
+void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 			 unsigned long parent_rate);
+int omap2_dflt_clk_enable(struct clk_hw *hw);
+void omap2_dflt_clk_disable(struct clk_hw *hw);
+int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
 
 void omap_dt_clocks_register(struct omap_dt_clk *oclks);
 #ifdef CONFIG_OF
@@ -190,5 +195,8 @@ static inline void of_omap_clk_deny_autoidle_all(void) { }
 
 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+extern const struct clk_hw_omap_ops clkhwops_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
 
 #endif
-- 
1.7.9.5

[PATCHv5 05/31] CLK: TI: add support for OMAP gate clock

[Mark Rutland]

On Fri, Aug 02, 2013 at 05:25:24PM +0100, Tero Kristo wrote:
> This node adds support for a clock node which allows control to the
> clockdomain enable / disable.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  .../devicetree/bindings/clock/ti/gate.txt          |   41 ++++++++
>  arch/arm/mach-omap2/clock.h                        |    9 --
>  drivers/clk/ti/Makefile                            |    2 +-
>  drivers/clk/ti/gate.c                              |  106 ++++++++++++++++++++
>  include/linux/clk/ti.h                             |    8 ++
>  5 files changed, 156 insertions(+), 10 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
>  create mode 100644 drivers/clk/ti/gate.c
> 
> diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
> new file mode 100644
> index 0000000..620a73d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
> @@ -0,0 +1,41 @@
> +Binding for Texas Instruments gate clock.
> +
> +This binding uses the common clock binding[1]. This clock is
> +quite much similar to the basic gate-clock [2], however,
> +it supports a number of additional features. If no register
> +is provided for this clock, the code assumes that a clockdomain
> +will be controlled instead and the corresponding hw-ops for
> +that is used.
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +[2] Documentation/devicetree/bindings/clock/gate-clock.txt
> +
> +Required properties:
> +- compatible : shall be "ti,gate-clock"
> +- #clock-cells : from common clock binding; shall be set to 0
> +- clocks : link to phandle of parent clock
> +
> +Optional properties:
> +- reg : base address for register controlling adjustable gate

Optional? That's odd. If I have a clock with registers, but don't
specify the register, will it still work? i.e. are registerless clocks
really compatible with clocks with registers?.

> +- ti,enable-bit : bit shift for programming the clock gate

Why is this needed? Does the hardware vary wildly, or are several clocks
sharing the same register(s)?

> +- ti,dss-clk : use DSS hardware OPS for the clock
> +- ti,am35xx-clk : use AM35xx hardware OPS for the clock

Those last two sounds like the kind of thing that should be derived from
the compatible string (e.g. ti,am35xx-gate-clock).

> +- ti,clkdm-name : clockdomain to control this gate

As previously mentioned, I'm not a fan of this property. It would make
more sense to describe the domain and have an explicit link to it
(either nodes being children of the domain or having a phandle).

[...]

> +void __init of_omap_gate_clk_setup(struct device_node *node)
> +{
> +       struct clk *clk;
> +       struct clk_init_data init = { 0 };
> +       struct clk_hw_omap *clk_hw;
> +       const char *clk_name = node->name;
> +       int num_parents;
> +       const char **parent_names = NULL;
> +       int i;
> +       u32 val;
> +
> +       clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
> +       if (!clk_hw) {
> +               pr_err("%s: could not allocate clk_hw_omap\n", __func__);
> +               return;
> +       }
> +
> +       clk_hw->hw.init = &init;
> +
> +       of_property_read_string(node, "clock-output-names", &clk_name);
> +       of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
> +
> +       init.name = clk_name;
> +       init.flags = 0;
> +
> +       if (of_property_read_u32_index(node, "reg", 0, &val)) {
> +               /* No register, clkdm control only */
> +               init.ops = &omap_gate_clkdm_clk_ops;

If they're truly compatible, you can just see if you can of_iomap, and
if not, continue. Your reg values might be wider than 32 bits, and usig
of_property_read_u32 to read this feels wrong.

> +       } else {
> +               init.ops = &omap_gate_clk_ops;
> +               clk_hw->enable_reg = of_iomap(node, 0);
> +               of_property_read_u32(node, "ti,enable-bit", &val);
> +               clk_hw->enable_bit = val;

What if of_property_read_u32 failed to read the "ti,enable-bit"
property? One might not be present, it's marked as optional in the
binding description.

> +
> +               clk_hw->ops = &clkhwops_wait;
> +
> +               if (of_property_read_bool(node, "ti,dss-clk"))
> +                       clk_hw->ops = &clkhwops_omap3430es2_dss_usbhost_wait;
> +
> +               if (of_property_read_bool(node, "ti,am35xx-clk"))
> +                       clk_hw->ops = &clkhwops_am35xx_ipss_module_wait;

I really don't like this. I think this should be done based on the
compatible string.

Thanks,
Mark.

[PATCHv5 05/31] CLK: TI: add support for OMAP gate clock

[Tero Kristo]

On 08/13/2013 02:04 PM, Mark Rutland wrote:
> On Fri, Aug 02, 2013 at 05:25:24PM +0100, Tero Kristo wrote:
>> This node adds support for a clock node which allows control to the
>> clockdomain enable / disable.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   .../devicetree/bindings/clock/ti/gate.txt          |   41 ++++++++
>>   arch/arm/mach-omap2/clock.h                        |    9 --
>>   drivers/clk/ti/Makefile                            |    2 +-
>>   drivers/clk/ti/gate.c                              |  106 ++++++++++++++++++++
>>   include/linux/clk/ti.h                             |    8 ++
>>   5 files changed, 156 insertions(+), 10 deletions(-)
>>   create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
>>   create mode 100644 drivers/clk/ti/gate.c
>>
>> diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
>> new file mode 100644
>> index 0000000..620a73d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
>> @@ -0,0 +1,41 @@
>> +Binding for Texas Instruments gate clock.
>> +
>> +This binding uses the common clock binding[1]. This clock is
>> +quite much similar to the basic gate-clock [2], however,
>> +it supports a number of additional features. If no register
>> +is provided for this clock, the code assumes that a clockdomain
>> +will be controlled instead and the corresponding hw-ops for
>> +that is used.
>> +
>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +[2] Documentation/devicetree/bindings/clock/gate-clock.txt
>> +
>> +Required properties:
>> +- compatible : shall be "ti,gate-clock"
>> +- #clock-cells : from common clock binding; shall be set to 0
>> +- clocks : link to phandle of parent clock
>> +
>> +Optional properties:
>> +- reg : base address for register controlling adjustable gate
>
> Optional? That's odd. If I have a clock with registers, but don't
> specify the register, will it still work? i.e. are registerless clocks
> really compatible with clocks with registers?.

I think I implemented this in somewhat confusing manner. This could be 
split to:

ti,gate-clock:
   requires reg and ti,enable-bit info
ti,clkdm-clock:
   requires ti,clkdm-name

clkdm clock is kind of a master clock for clockdomain, the clock is 
provided always if the clockdomain is active.

>
>> +- ti,enable-bit : bit shift for programming the clock gate
>
> Why is this needed? Does the hardware vary wildly, or are several clocks
> sharing the same register(s)?

Yea, same register is shared.

>
>> +- ti,dss-clk : use DSS hardware OPS for the clock
>> +- ti,am35xx-clk : use AM35xx hardware OPS for the clock
>
> Those last two sounds like the kind of thing that should be derived from
> the compatible string (e.g. ti,am35xx-gate-clock).

Hmm yea, I think I can change this and add some sub-types.

>
>> +- ti,clkdm-name : clockdomain to control this gate
>
> As previously mentioned, I'm not a fan of this property. It would make
> more sense to describe the domain and have an explicit link to it
> (either nodes being children of the domain or having a phandle).

Same comments as with patch #2.

>
> [...]
>
>> +void __init of_omap_gate_clk_setup(struct device_node *node)
>> +{
>> +       struct clk *clk;
>> +       struct clk_init_data init = { 0 };
>> +       struct clk_hw_omap *clk_hw;
>> +       const char *clk_name = node->name;
>> +       int num_parents;
>> +       const char **parent_names = NULL;
>> +       int i;
>> +       u32 val;
>> +
>> +       clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
>> +       if (!clk_hw) {
>> +               pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>> +               return;
>> +       }
>> +
>> +       clk_hw->hw.init = &init;
>> +
>> +       of_property_read_string(node, "clock-output-names", &clk_name);
>> +       of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
>> +
>> +       init.name = clk_name;
>> +       init.flags = 0;
>> +
>> +       if (of_property_read_u32_index(node, "reg", 0, &val)) {
>> +               /* No register, clkdm control only */
>> +               init.ops = &omap_gate_clkdm_clk_ops;
>
> If they're truly compatible, you can just see if you can of_iomap, and
> if not, continue. Your reg values might be wider than 32 bits, and usig
> of_property_read_u32 to read this feels wrong.

I'll split this to two separate supported types.

>
>> +       } else {
>> +               init.ops = &omap_gate_clk_ops;
>> +               clk_hw->enable_reg = of_iomap(node, 0);
>> +               of_property_read_u32(node, "ti,enable-bit", &val);
>> +               clk_hw->enable_bit = val;
>
> What if of_property_read_u32 failed to read the "ti,enable-bit"
> property? One might not be present, it's marked as optional in the
> binding description.

I'll make sure this is present in case it is needed.

>
>> +
>> +               clk_hw->ops = &clkhwops_wait;
>> +
>> +               if (of_property_read_bool(node, "ti,dss-clk"))
>> +                       clk_hw->ops = &clkhwops_omap3430es2_dss_usbhost_wait;
>> +
>> +               if (of_property_read_bool(node, "ti,am35xx-clk"))
>> +                       clk_hw->ops = &clkhwops_am35xx_ipss_module_wait;
>
> I really don't like this. I think this should be done based on the
> compatible string.

Yea, will change.

-Tero

[PATCHv5 05/31] CLK: TI: add support for OMAP gate clock

[Mark Rutland]

On Mon, Aug 19, 2013 at 02:42:05PM +0100, Tero Kristo wrote:
> On 08/13/2013 02:04 PM, Mark Rutland wrote:
> > On Fri, Aug 02, 2013 at 05:25:24PM +0100, Tero Kristo wrote:
> >> This node adds support for a clock node which allows control to the
> >> clockdomain enable / disable.
> >>
> >> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >> ---
> >>   .../devicetree/bindings/clock/ti/gate.txt          |   41 ++++++++
> >>   arch/arm/mach-omap2/clock.h                        |    9 --
> >>   drivers/clk/ti/Makefile                            |    2 +-
> >>   drivers/clk/ti/gate.c                              |  106 ++++++++++++++++++++
> >>   include/linux/clk/ti.h                             |    8 ++
> >>   5 files changed, 156 insertions(+), 10 deletions(-)
> >>   create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
> >>   create mode 100644 drivers/clk/ti/gate.c
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
> >> new file mode 100644
> >> index 0000000..620a73d
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
> >> @@ -0,0 +1,41 @@
> >> +Binding for Texas Instruments gate clock.
> >> +
> >> +This binding uses the common clock binding[1]. This clock is
> >> +quite much similar to the basic gate-clock [2], however,
> >> +it supports a number of additional features. If no register
> >> +is provided for this clock, the code assumes that a clockdomain
> >> +will be controlled instead and the corresponding hw-ops for
> >> +that is used.
> >> +
> >> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> >> +[2] Documentation/devicetree/bindings/clock/gate-clock.txt
> >> +
> >> +Required properties:
> >> +- compatible : shall be "ti,gate-clock"
> >> +- #clock-cells : from common clock binding; shall be set to 0
> >> +- clocks : link to phandle of parent clock
> >> +
> >> +Optional properties:
> >> +- reg : base address for register controlling adjustable gate
> >
> > Optional? That's odd. If I have a clock with registers, but don't
> > specify the register, will it still work? i.e. are registerless clocks
> > really compatible with clocks with registers?.
> 
> I think I implemented this in somewhat confusing manner. This could be 
> split to:
> 
> ti,gate-clock:
>    requires reg and ti,enable-bit info
> ti,clkdm-clock:
>    requires ti,clkdm-name
> 
> clkdm clock is kind of a master clock for clockdomain, the clock is 
> provided always if the clockdomain is active.

Ok.

> 
> >
> >> +- ti,enable-bit : bit shift for programming the clock gate
> >
> > Why is this needed? Does the hardware vary wildly, or are several clocks
> > sharing the same register(s)?
> 
> Yea, same register is shared.

Ok. Are those gate clocks are part of a larger "gate clocks" block, with
the register that controls them? or are they really independent? Does
the register control other items too?

If they were part of some bigger unit, it might be possible to have a
binding like the following (though maybe not):

gate_clks: gate_clks {
	compatible = "ti,gate-clocks-block";
	reg = <0x4003a000 0x1000>;

	#clock-cells = <1>;
	/*
	 * has 4 gate clocks at bit shifts 0,1,2,3,
	 * corresponding to input clocks 0,1,2,3
	 */
	clocks = <&clk1 0 23>,
		 <&clk1 0 4>,
		 <&clk3 2>,
		 <&clk3 5>;
};

device {
	compatible = "vendor,some-device";
	clocks = <&gate_clks 1>; /* gate clock with bitshift 1*/
};

> 
> >
> >> +- ti,dss-clk : use DSS hardware OPS for the clock
> >> +- ti,am35xx-clk : use AM35xx hardware OPS for the clock
> >
> > Those last two sounds like the kind of thing that should be derived from
> > the compatible string (e.g. ti,am35xx-gate-clock).
> 
> Hmm yea, I think I can change this and add some sub-types.
> 
> >
> >> +- ti,clkdm-name : clockdomain to control this gate
> >
> > As previously mentioned, I'm not a fan of this property. It would make
> > more sense to describe the domain and have an explicit link to it
> > (either nodes being children of the domain or having a phandle).
> 
> Same comments as with patch #2.

Same reply as to patch #2 :)

> 
> >
> > [...]
> >
> >> +void __init of_omap_gate_clk_setup(struct device_node *node)
> >> +{
> >> +       struct clk *clk;
> >> +       struct clk_init_data init = { 0 };
> >> +       struct clk_hw_omap *clk_hw;
> >> +       const char *clk_name = node->name;
> >> +       int num_parents;
> >> +       const char **parent_names = NULL;
> >> +       int i;
> >> +       u32 val;
> >> +
> >> +       clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
> >> +       if (!clk_hw) {
> >> +               pr_err("%s: could not allocate clk_hw_omap\n", __func__);
> >> +               return;
> >> +       }
> >> +
> >> +       clk_hw->hw.init = &init;
> >> +
> >> +       of_property_read_string(node, "clock-output-names", &clk_name);
> >> +       of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
> >> +
> >> +       init.name = clk_name;
> >> +       init.flags = 0;
> >> +
> >> +       if (of_property_read_u32_index(node, "reg", 0, &val)) {
> >> +               /* No register, clkdm control only */
> >> +               init.ops = &omap_gate_clkdm_clk_ops;
> >
> > If they're truly compatible, you can just see if you can of_iomap, and
> > if not, continue. Your reg values might be wider than 32 bits, and usig
> > of_property_read_u32 to read this feels wrong.
> 
> I'll split this to two separate supported types.
> 
> >
> >> +       } else {
> >> +               init.ops = &omap_gate_clk_ops;
> >> +               clk_hw->enable_reg = of_iomap(node, 0);
> >> +               of_property_read_u32(node, "ti,enable-bit", &val);
> >> +               clk_hw->enable_bit = val;
> >
> > What if of_property_read_u32 failed to read the "ti,enable-bit"
> > property? One might not be present, it's marked as optional in the
> > binding description.
> 
> I'll make sure this is present in case it is needed.
> 
> >
> >> +
> >> +               clk_hw->ops = &clkhwops_wait;
> >> +
> >> +               if (of_property_read_bool(node, "ti,dss-clk"))
> >> +                       clk_hw->ops = &clkhwops_omap3430es2_dss_usbhost_wait;
> >> +
> >> +               if (of_property_read_bool(node, "ti,am35xx-clk"))
> >> +                       clk_hw->ops = &clkhwops_am35xx_ipss_module_wait;
> >
> > I really don't like this. I think this should be done based on the
> > compatible string.
> 
> Yea, will change.

Cheers!

Mark.

[PATCHv5 05/31] CLK: TI: add support for OMAP gate clock

[Tero Kristo]

On 08/19/2013 05:29 PM, Mark Rutland wrote:
> On Mon, Aug 19, 2013 at 02:42:05PM +0100, Tero Kristo wrote:
>> On 08/13/2013 02:04 PM, Mark Rutland wrote:
>>> On Fri, Aug 02, 2013 at 05:25:24PM +0100, Tero Kristo wrote:
>>>> This node adds support for a clock node which allows control to the
>>>> clockdomain enable / disable.
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> ---
>>>>    .../devicetree/bindings/clock/ti/gate.txt          |   41 ++++++++
>>>>    arch/arm/mach-omap2/clock.h                        |    9 --
>>>>    drivers/clk/ti/Makefile                            |    2 +-
>>>>    drivers/clk/ti/gate.c                              |  106 ++++++++++++++++++++
>>>>    include/linux/clk/ti.h                             |    8 ++
>>>>    5 files changed, 156 insertions(+), 10 deletions(-)
>>>>    create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
>>>>    create mode 100644 drivers/clk/ti/gate.c
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
>>>> new file mode 100644
>>>> index 0000000..620a73d
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
>>>> @@ -0,0 +1,41 @@
>>>> +Binding for Texas Instruments gate clock.
>>>> +
>>>> +This binding uses the common clock binding[1]. This clock is
>>>> +quite much similar to the basic gate-clock [2], however,
>>>> +it supports a number of additional features. If no register
>>>> +is provided for this clock, the code assumes that a clockdomain
>>>> +will be controlled instead and the corresponding hw-ops for
>>>> +that is used.
>>>> +
>>>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>> +[2] Documentation/devicetree/bindings/clock/gate-clock.txt
>>>> +
>>>> +Required properties:
>>>> +- compatible : shall be "ti,gate-clock"
>>>> +- #clock-cells : from common clock binding; shall be set to 0
>>>> +- clocks : link to phandle of parent clock
>>>> +
>>>> +Optional properties:
>>>> +- reg : base address for register controlling adjustable gate
>>>
>>> Optional? That's odd. If I have a clock with registers, but don't
>>> specify the register, will it still work? i.e. are registerless clocks
>>> really compatible with clocks with registers?.
>>
>> I think I implemented this in somewhat confusing manner. This could be
>> split to:
>>
>> ti,gate-clock:
>>     requires reg and ti,enable-bit info
>> ti,clkdm-clock:
>>     requires ti,clkdm-name
>>
>> clkdm clock is kind of a master clock for clockdomain, the clock is
>> provided always if the clockdomain is active.
>
> Ok.
>
>>
>>>
>>>> +- ti,enable-bit : bit shift for programming the clock gate
>>>
>>> Why is this needed? Does the hardware vary wildly, or are several clocks
>>> sharing the same register(s)?
>>
>> Yea, same register is shared.
>
> Ok. Are those gate clocks are part of a larger "gate clocks" block, with
> the register that controls them? or are they really independent? Does
> the register control other items too?

Not really. Typically they only have the clockdomain in common, and the 
individual clocks are mostly controlled independently from each other. 
For example on omap3 we have following register:

CM_FCLKEN_PER
Physical Address 0x4800 5000
BIT31:19 RESERVED Write 0s for future compatibility. Read returns 0.
BIT18 EN_UART4 UART4 functional clock control.
BIT17 EN_GPIO6 GPIO6 functional clock control.
BIT16 EN_GPIO5 GPIO5 functional clock control.
BIT15 EN_GPIO4 GPIO4 functional clock control.
BIT14 EN_GPIO3 GPIO3 functional clock control.
BIT13 EN_GPIO2 GPIO2 functional clock control.
BIT12 EN_WDT3 WDT3 functional clock control.
BIT11 EN_UART3 Type UART3 functional clock control.
BIT10 EN_GPT9 GPTIMER 9 functional clock control.
BIT9 EN_GPT8 GPTIMER 8 functional clock control.
BIT8 EN_GPT7 GPTIMER 7 functional clock control.
BIT7 EN_GPT6 GPTIMER 6 functional clock control.
BIT6 EN_GPT5 GPTIMER 5 functional clock control.
BIT5 EN_GPT4 GPTIMER 4 functional clock control.
BIT4 EN_GPT3GPTIMER 3 functional clock control.
BIT3 EN_GPT2 GPTIMER 2 functional clock control.
BIT2 EN_MCBSP4 McBSP 4 functional clock control.
BIT1 EN_MCBSP3 McBSP3 functional clock control.
BIT0 EN_MCBSP2 McBSP 2 functional clock control.

So multiple drivers will be using this register for example.

> If they were part of some bigger unit, it might be possible to have a
> binding like the following (though maybe not):
>
> gate_clks: gate_clks {
> 	compatible = "ti,gate-clocks-block";
> 	reg = <0x4003a000 0x1000>;
>
> 	#clock-cells = <1>;
> 	/*
> 	 * has 4 gate clocks at bit shifts 0,1,2,3,
> 	 * corresponding to input clocks 0,1,2,3
> 	 */
> 	clocks = <&clk1 0 23>,
> 		 <&clk1 0 4>,
> 		 <&clk3 2>,
> 		 <&clk3 5>;
> };
>
> device {
> 	compatible = "vendor,some-device";
> 	clocks = <&gate_clks 1>; /* gate clock with bitshift 1*/
> };
>
>>
>>>
>>>> +- ti,dss-clk : use DSS hardware OPS for the clock
>>>> +- ti,am35xx-clk : use AM35xx hardware OPS for the clock
>>>
>>> Those last two sounds like the kind of thing that should be derived from
>>> the compatible string (e.g. ti,am35xx-gate-clock).
>>
>> Hmm yea, I think I can change this and add some sub-types.
>>
>>>
>>>> +- ti,clkdm-name : clockdomain to control this gate
>>>
>>> As previously mentioned, I'm not a fan of this property. It would make
>>> more sense to describe the domain and have an explicit link to it
>>> (either nodes being children of the domain or having a phandle).
>>
>> Same comments as with patch #2.
>
> Same reply as to patch #2 :)

I'll think of a proper reply there. :)

-Tero

>
>>
>>>
>>> [...]
>>>
>>>> +void __init of_omap_gate_clk_setup(struct device_node *node)
>>>> +{
>>>> +       struct clk *clk;
>>>> +       struct clk_init_data init = { 0 };
>>>> +       struct clk_hw_omap *clk_hw;
>>>> +       const char *clk_name = node->name;
>>>> +       int num_parents;
>>>> +       const char **parent_names = NULL;
>>>> +       int i;
>>>> +       u32 val;
>>>> +
>>>> +       clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
>>>> +       if (!clk_hw) {
>>>> +               pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>>>> +               return;
>>>> +       }
>>>> +
>>>> +       clk_hw->hw.init = &init;
>>>> +
>>>> +       of_property_read_string(node, "clock-output-names", &clk_name);
>>>> +       of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
>>>> +
>>>> +       init.name = clk_name;
>>>> +       init.flags = 0;
>>>> +
>>>> +       if (of_property_read_u32_index(node, "reg", 0, &val)) {
>>>> +               /* No register, clkdm control only */
>>>> +               init.ops = &omap_gate_clkdm_clk_ops;
>>>
>>> If they're truly compatible, you can just see if you can of_iomap, and
>>> if not, continue. Your reg values might be wider than 32 bits, and usig
>>> of_property_read_u32 to read this feels wrong.
>>
>> I'll split this to two separate supported types.
>>
>>>
>>>> +       } else {
>>>> +               init.ops = &omap_gate_clk_ops;
>>>> +               clk_hw->enable_reg = of_iomap(node, 0);
>>>> +               of_property_read_u32(node, "ti,enable-bit", &val);
>>>> +               clk_hw->enable_bit = val;
>>>
>>> What if of_property_read_u32 failed to read the "ti,enable-bit"
>>> property? One might not be present, it's marked as optional in the
>>> binding description.
>>
>> I'll make sure this is present in case it is needed.
>>
>>>
>>>> +
>>>> +               clk_hw->ops = &clkhwops_wait;
>>>> +
>>>> +               if (of_property_read_bool(node, "ti,dss-clk"))
>>>> +                       clk_hw->ops = &clkhwops_omap3430es2_dss_usbhost_wait;
>>>> +
>>>> +               if (of_property_read_bool(node, "ti,am35xx-clk"))
>>>> +                       clk_hw->ops = &clkhwops_am35xx_ipss_module_wait;
>>>
>>> I really don't like this. I think this should be done based on the
>>> compatible string.
>>
>> Yea, will change.
>
> Cheers!
>
> Mark.
>

[PATCHv5 05/31] CLK: TI: add support for OMAP gate clock

[Mark Rutland]

On Mon, Aug 19, 2013 at 03:43:15PM +0100, Tero Kristo wrote:
> On 08/19/2013 05:29 PM, Mark Rutland wrote:
> > On Mon, Aug 19, 2013 at 02:42:05PM +0100, Tero Kristo wrote:
> >> On 08/13/2013 02:04 PM, Mark Rutland wrote:
> >>> On Fri, Aug 02, 2013 at 05:25:24PM +0100, Tero Kristo wrote:
> >>>> This node adds support for a clock node which allows control to the
> >>>> clockdomain enable / disable.
> >>>>
> >>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >>>> ---
> >>>>    .../devicetree/bindings/clock/ti/gate.txt          |   41 ++++++++
> >>>>    arch/arm/mach-omap2/clock.h                        |    9 --
> >>>>    drivers/clk/ti/Makefile                            |    2 +-
> >>>>    drivers/clk/ti/gate.c                              |  106 ++++++++++++++++++++
> >>>>    include/linux/clk/ti.h                             |    8 ++
> >>>>    5 files changed, 156 insertions(+), 10 deletions(-)
> >>>>    create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
> >>>>    create mode 100644 drivers/clk/ti/gate.c
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
> >>>> new file mode 100644
> >>>> index 0000000..620a73d
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
> >>>> @@ -0,0 +1,41 @@
> >>>> +Binding for Texas Instruments gate clock.
> >>>> +
> >>>> +This binding uses the common clock binding[1]. This clock is
> >>>> +quite much similar to the basic gate-clock [2], however,
> >>>> +it supports a number of additional features. If no register
> >>>> +is provided for this clock, the code assumes that a clockdomain
> >>>> +will be controlled instead and the corresponding hw-ops for
> >>>> +that is used.
> >>>> +
> >>>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> >>>> +[2] Documentation/devicetree/bindings/clock/gate-clock.txt
> >>>> +
> >>>> +Required properties:
> >>>> +- compatible : shall be "ti,gate-clock"
> >>>> +- #clock-cells : from common clock binding; shall be set to 0
> >>>> +- clocks : link to phandle of parent clock
> >>>> +
> >>>> +Optional properties:
> >>>> +- reg : base address for register controlling adjustable gate
> >>>
> >>> Optional? That's odd. If I have a clock with registers, but don't
> >>> specify the register, will it still work? i.e. are registerless clocks
> >>> really compatible with clocks with registers?.
> >>
> >> I think I implemented this in somewhat confusing manner. This could be
> >> split to:
> >>
> >> ti,gate-clock:
> >>     requires reg and ti,enable-bit info
> >> ti,clkdm-clock:
> >>     requires ti,clkdm-name
> >>
> >> clkdm clock is kind of a master clock for clockdomain, the clock is
> >> provided always if the clockdomain is active.
> >
> > Ok.
> >
> >>
> >>>
> >>>> +- ti,enable-bit : bit shift for programming the clock gate
> >>>
> >>> Why is this needed? Does the hardware vary wildly, or are several clocks
> >>> sharing the same register(s)?
> >>
> >> Yea, same register is shared.
> >
> > Ok. Are those gate clocks are part of a larger "gate clocks" block, with
> > the register that controls them? or are they really independent? Does
> > the register control other items too?
> 
> Not really. Typically they only have the clockdomain in common, and the 
> individual clocks are mostly controlled independently from each other. 
> For example on omap3 we have following register:

You say they typically only have the clockdomain in common. Do you mean
that they always have the same clockdomain, but not necessarily other
properties, or may they not even have the clockdomain in common?

> 
> CM_FCLKEN_PER
> Physical Address 0x4800 5000
> BIT31:19 RESERVED Write 0s for future compatibility. Read returns 0.
> BIT18 EN_UART4 UART4 functional clock control.
> BIT17 EN_GPIO6 GPIO6 functional clock control.
> BIT16 EN_GPIO5 GPIO5 functional clock control.
> BIT15 EN_GPIO4 GPIO4 functional clock control.
> BIT14 EN_GPIO3 GPIO3 functional clock control.
> BIT13 EN_GPIO2 GPIO2 functional clock control.
> BIT12 EN_WDT3 WDT3 functional clock control.
> BIT11 EN_UART3 Type UART3 functional clock control.
> BIT10 EN_GPT9 GPTIMER 9 functional clock control.
> BIT9 EN_GPT8 GPTIMER 8 functional clock control.
> BIT8 EN_GPT7 GPTIMER 7 functional clock control.
> BIT7 EN_GPT6 GPTIMER 6 functional clock control.
> BIT6 EN_GPT5 GPTIMER 5 functional clock control.
> BIT5 EN_GPT4 GPTIMER 4 functional clock control.
> BIT4 EN_GPT3GPTIMER 3 functional clock control.
> BIT3 EN_GPT2 GPTIMER 2 functional clock control.
> BIT2 EN_MCBSP4 McBSP 4 functional clock control.
> BIT1 EN_MCBSP3 McBSP3 functional clock control.
> BIT0 EN_MCBSP2 McBSP 2 functional clock control.
> 
> So multiple drivers will be using this register for example.

The point I was trying to get across is that this looks like a single
logical block which controls the (independent) gating of several clocks,
along the same lines as multiple swtiches bound together in a DIP
switch.

It's equally valid to view that as several clock gates which happen to
have their control bits in close proximity in the memory map, as you
suggest.

Thanks,
Mark.

[PATCHv5 05/31] CLK: TI: add support for OMAP gate clock

[Tero Kristo]

On 08/19/2013 06:58 PM, Mark Rutland wrote:
> On Mon, Aug 19, 2013 at 03:43:15PM +0100, Tero Kristo wrote:
>> On 08/19/2013 05:29 PM, Mark Rutland wrote:
>>> On Mon, Aug 19, 2013 at 02:42:05PM +0100, Tero Kristo wrote:
>>>> On 08/13/2013 02:04 PM, Mark Rutland wrote:
>>>>> On Fri, Aug 02, 2013 at 05:25:24PM +0100, Tero Kristo wrote:
>>>>>> This node adds support for a clock node which allows control to the
>>>>>> clockdomain enable / disable.
>>>>>>
>>>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>>>> ---
>>>>>>     .../devicetree/bindings/clock/ti/gate.txt          |   41 ++++++++
>>>>>>     arch/arm/mach-omap2/clock.h                        |    9 --
>>>>>>     drivers/clk/ti/Makefile                            |    2 +-
>>>>>>     drivers/clk/ti/gate.c                              |  106 ++++++++++++++++++++
>>>>>>     include/linux/clk/ti.h                             |    8 ++
>>>>>>     5 files changed, 156 insertions(+), 10 deletions(-)
>>>>>>     create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt
>>>>>>     create mode 100644 drivers/clk/ti/gate.c
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
>>>>>> new file mode 100644
>>>>>> index 0000000..620a73d
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
>>>>>> @@ -0,0 +1,41 @@
>>>>>> +Binding for Texas Instruments gate clock.
>>>>>> +
>>>>>> +This binding uses the common clock binding[1]. This clock is
>>>>>> +quite much similar to the basic gate-clock [2], however,
>>>>>> +it supports a number of additional features. If no register
>>>>>> +is provided for this clock, the code assumes that a clockdomain
>>>>>> +will be controlled instead and the corresponding hw-ops for
>>>>>> +that is used.
>>>>>> +
>>>>>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>>> +[2] Documentation/devicetree/bindings/clock/gate-clock.txt
>>>>>> +
>>>>>> +Required properties:
>>>>>> +- compatible : shall be "ti,gate-clock"
>>>>>> +- #clock-cells : from common clock binding; shall be set to 0
>>>>>> +- clocks : link to phandle of parent clock
>>>>>> +
>>>>>> +Optional properties:
>>>>>> +- reg : base address for register controlling adjustable gate
>>>>>
>>>>> Optional? That's odd. If I have a clock with registers, but don't
>>>>> specify the register, will it still work? i.e. are registerless clocks
>>>>> really compatible with clocks with registers?.
>>>>
>>>> I think I implemented this in somewhat confusing manner. This could be
>>>> split to:
>>>>
>>>> ti,gate-clock:
>>>>      requires reg and ti,enable-bit info
>>>> ti,clkdm-clock:
>>>>      requires ti,clkdm-name
>>>>
>>>> clkdm clock is kind of a master clock for clockdomain, the clock is
>>>> provided always if the clockdomain is active.
>>>
>>> Ok.
>>>
>>>>
>>>>>
>>>>>> +- ti,enable-bit : bit shift for programming the clock gate
>>>>>
>>>>> Why is this needed? Does the hardware vary wildly, or are several clocks
>>>>> sharing the same register(s)?
>>>>
>>>> Yea, same register is shared.
>>>
>>> Ok. Are those gate clocks are part of a larger "gate clocks" block, with
>>> the register that controls them? or are they really independent? Does
>>> the register control other items too?
>>
>> Not really. Typically they only have the clockdomain in common, and the
>> individual clocks are mostly controlled independently from each other.
>> For example on omap3 we have following register:
>
> You say they typically only have the clockdomain in common. Do you mean
> that they always have the same clockdomain, but not necessarily other
> properties, or may they not even have the clockdomain in common?

Currently it seems if the clocks share a register, they are in the same 
clockdomain (I guess this is something that might also change in 
future.) The input clocks can be different (some are using the same), 
and the outputs are routed to different destinations on the SoC. For the 
below example, GPTs can have either sys_ck or 32k_ck as parent, UARTs 
are fed from 48M clock etc.

>
>>
>> CM_FCLKEN_PER
>> Physical Address 0x4800 5000
>> BIT31:19 RESERVED Write 0s for future compatibility. Read returns 0.
>> BIT18 EN_UART4 UART4 functional clock control.
>> BIT17 EN_GPIO6 GPIO6 functional clock control.
>> BIT16 EN_GPIO5 GPIO5 functional clock control.
>> BIT15 EN_GPIO4 GPIO4 functional clock control.
>> BIT14 EN_GPIO3 GPIO3 functional clock control.
>> BIT13 EN_GPIO2 GPIO2 functional clock control.
>> BIT12 EN_WDT3 WDT3 functional clock control.
>> BIT11 EN_UART3 Type UART3 functional clock control.
>> BIT10 EN_GPT9 GPTIMER 9 functional clock control.
>> BIT9 EN_GPT8 GPTIMER 8 functional clock control.
>> BIT8 EN_GPT7 GPTIMER 7 functional clock control.
>> BIT7 EN_GPT6 GPTIMER 6 functional clock control.
>> BIT6 EN_GPT5 GPTIMER 5 functional clock control.
>> BIT5 EN_GPT4 GPTIMER 4 functional clock control.
>> BIT4 EN_GPT3GPTIMER 3 functional clock control.
>> BIT3 EN_GPT2 GPTIMER 2 functional clock control.
>> BIT2 EN_MCBSP4 McBSP 4 functional clock control.
>> BIT1 EN_MCBSP3 McBSP3 functional clock control.
>> BIT0 EN_MCBSP2 McBSP 2 functional clock control.
>>
>> So multiple drivers will be using this register for example.
>
> The point I was trying to get across is that this looks like a single
> logical block which controls the (independent) gating of several clocks,
> along the same lines as multiple swtiches bound together in a DIP
> switch.
>
> It's equally valid to view that as several clock gates which happen to
> have their control bits in close proximity in the memory map, as you
> suggest.

For clarity, I think it is better to have the clocks as separate nodes, 
as otherwise specifying the mapping for individual clocks becomes a pain 
for the layers that are going to use the clock mapping. You would end up 
with obfuscated name for UART3 / GPTIMER5 for example, and this would be 
rather error prone approach also if I understand your point correctly.

-Tero

>
> Thanks,
> Mark.
>

[PATCHv5 06/31] ARM: dts: omap4 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap443x-clocks.dtsi |   17 +
 arch/arm/boot/dts/omap443x.dtsi        |    8 +
 arch/arm/boot/dts/omap4460.dtsi        |    8 +
 arch/arm/boot/dts/omap446x-clocks.dtsi |   27 +
 arch/arm/boot/dts/omap44xx-clocks.dtsi | 1648 ++++++++++++++++++++++++++++++++
 5 files changed, 1708 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 0000000..2bd82b2
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Device Tree Source for OMAP443x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+bandgap_fclk: bandgap_fclk at 4a307888 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index bcf455e..dfd648c 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -30,4 +30,12 @@
 		       0x4a00232C 0x4>;
 		compatible = "ti,omap4430-bandgap";
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap44xx-clocks.dtsi"
+		/include/ "omap443x-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c2f0f39..d9d00b2 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -38,4 +38,12 @@
 		interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
 		gpios = <&gpio3 22 0>; /* tshut */
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap44xx-clocks.dtsi"
+		/include/ "omap446x-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 0000000..86d0805
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for OMAP446x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+div_ts_ck: div_ts_ck at 4a307888 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <24>;
+	reg = <0x4a307888 0x4>;
+	table = < 8 0 >, < 16 1 >, < 32 2 >;
+	bit-mask = <0x3>;
+};
+
+bandgap_ts_fclk: bandgap_ts_fclk at 4a307888 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&div_ts_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 0000000..23f623c
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1648 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+extalt_clkin_ck: extalt_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <59000000>;
+};
+
+pad_clks_src_ck: pad_clks_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_clks_src_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004108 0x4>;
+};
+
+pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_src_clk>;
+	bit-shift = <10>;
+	reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+sys_clkin_ck: sys_clkin_ck at 4a306110 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	reg = <0x4a306110 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+tie_low_clock_ck: tie_low_clock_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60motg_ck: xclk60motg_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a306108 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck at 4a30610c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	reg = <0x4a30610c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck at 4a0041e0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-m4xen-clock";
+	clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+	reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+	ti,clk-ref = <&abe_dpll_refclk_mux_ck>;
+	ti,clk-bypass = <&abe_dpll_bypass_clk_mux_ck>;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck at 4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_abe_ck>;
+	reg = <0x4a0041f0 0x4>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+abe_clk: abe_clk at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4a004108 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+aess_fclk: aess_fclk at 4a004528 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&abe_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004528 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0041f4 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck at 4a00412c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+	bit-shift = <23>;
+	reg = <0x4a00412c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_core_ck: dpll_core_ck at 4a004120 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-core-clock";
+	clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+	reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&core_hsd_byp_clk_mux_ck>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m6x2_ck: dpll_core_m6x2_ck at 4a004140 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004140 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dbgclk_mux_ck: dbgclk_mux_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck at 4a004130 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004130 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+ddrphy_ck: ddrphy_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_core_m5x2_ck: dpll_core_m5x2_ck at 4a00413c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00413c 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+div_core_ck: div_core_ck at 4a004100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+};
+
+div_iva_hs_clk: div_iva_hs_clk at 4a0041dc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a0041dc 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+div_mpu_hs_clk: div_mpu_hs_clk at 4a00419c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a00419c 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+dpll_core_m4x2_ck: dpll_core_m4x2_ck at 4a004138 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004138 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dll_clk_div_ck: dll_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck at 4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_ck>;
+	reg = <0x4a0041f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck at 4a004134 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x4a004134 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck at 4a004134 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m3x2_div_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004134 0x4>;
+};
+
+dpll_core_m7x2_ck: dpll_core_m7x2_ck at 4a004144 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004144 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck at 4a0041ac {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+	bit-shift = <23>;
+	reg = <0x4a0041ac 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_iva_ck: dpll_iva_ck at 4a0041a0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+	reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&iva_hsd_byp_clk_mux_ck>;
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_iva_ck>;
+};
+
+dpll_iva_m4x2_ck: dpll_iva_m4x2_ck at 4a0041b8 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041b8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_iva_m5x2_ck: dpll_iva_m5x2_ck at 4a0041bc {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041bc 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 4a004160 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+	reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&div_mpu_hs_clk>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a004170 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004170 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+per_hs_clk_div_ck: per_hs_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck at 4a00814c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+	bit-shift = <23>;
+	reg = <0x4a00814c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_per_ck: dpll_per_ck at 4a008140 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+	reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&per_hsd_byp_clk_mux_ck>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_ck>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_per_ck>;
+	reg = <0x4a008150 0x4>;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck at 4a008154 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	reg = <0x4a008154 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck at 4a008154 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m3x2_div_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008154 0x4>;
+};
+
+dpll_per_m4x2_ck: dpll_per_m4x2_ck at 4a008158 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008158 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m5x2_ck: dpll_per_m5x2_ck at 4a00815c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00815c 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m6x2_ck: dpll_per_m6x2_ck at 4a008160 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008160 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m7x2_ck: dpll_per_m7x2_ck at 4a008164 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008164 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck at 4a008180 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-j-type-clock";
+	clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+	ti,clk-bypass = <&usb_hs_clk_div_ck>;
+	reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clkdm-name = "l3_init_clkdm";
+	ti,dpll-j-type;
+};
+
+dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck at 4a0081b4 {
+	#clock-cells = <0>;
+	compatible = "ti,fixed-factor-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	clock-div = <1>;
+	reg = <0x4a0081b4 0x4>;
+	clock-mult = <1>;
+	ti,autoidle-low;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008190 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+ducati_clk_mux_ck: ducati_clk_mux_ck at 4a008100 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+	reg = <0x4a008100 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_12m_fclk: func_12m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_24mc_fclk: func_24mc_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+func_48m_fclk: func_48m_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	reg = <0x4a008108 0x4>;
+	table = < 4 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+func_48mc_fclk: func_48mc_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_64m_fclk: func_64m_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	reg = <0x4a008108 0x4>;
+	table = < 2 0 >, < 4 1 >;
+	bit-mask = <0x1>;
+};
+
+func_96m_fclk: func_96m_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	reg = <0x4a008108 0x4>;
+	table = < 2 0 >, < 4 1 >;
+	bit-mask = <0x1>;
+};
+
+init_60m_fclk: init_60m_fclk at 4a008104 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4a008104 0x4>;
+	table = < 1 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+l3_div_ck: l3_div_ck at 4a004100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&div_core_ck>;
+	bit-shift = <4>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+};
+
+l4_div_ck: l4_div_ck at 4a004100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+};
+
+lp_clk_div_ck: lp_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck at 4a306108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+	reg = <0x4a306108 0x4>;
+	bit-mask = <0x1>;
+};
+
+mpu_periphclk: mpu_periphclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_mpu_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+ocp_abe_iclk: ocp_abe_iclk at 4a004528 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&aess_fclk>;
+	bit-shift = <24>;
+	reg = <0x4a004528 0x4>;
+	table = < 2 0 >, < 1 1 >;
+	bit-mask = <0x1>;
+};
+
+per_abe_24m_fclk: per_abe_24m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+per_abe_nc_fclk: per_abe_nc_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	reg = <0x4a008108 0x4>;
+	bit-mask = <0x1>;
+};
+
+syc_clk_div_ck: syc_clk_div_ck at 4a306100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x4a306100 0x4>;
+	bit-mask = <0x1>;
+};
+
+aes1_fck: aes1_fck at 4a0095a0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a0095a0 0x4>;
+};
+
+aes2_fck: aes2_fck at 4a0095a8 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a0095a8 0x4>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck at 4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_dmic_abe_gfclk: func_dmic_abe_gfclk at 4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x3>;
+};
+
+dss_sys_clk: dss_sys_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&syc_clk_div_ck>;
+	bit-shift = <10>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_tv_clk: dss_tv_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&extalt_clkin_ck>;
+	bit-shift = <11>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m5x2_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48mc_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_fck: dss_fck at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a009120 0x4>;
+};
+
+fdif_fck: fdif_fck at 4a009028 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009028 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+gpio1_dbclk: gpio1_dbclk at 4a307838 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 4a009460 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009460 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 4a009468 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009468 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 4a009470 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009470 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 4a009478 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009478 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk at 4a009480 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009480 0x4>;
+};
+
+sgx_clk_mux: sgx_clk_mux at 4a009220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009220 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsi_fck: hsi_fck at 4a009338 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009338 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+iss_ctrlclk: iss_ctrlclk at 4a009020 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_96m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009020 0x4>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck at 4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcasp_abe_gfclk: func_mcasp_abe_gfclk at 4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck at 4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcbsp1_gfclk: func_mcbsp1_gfclk at 4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcbsp2_gfclk: func_mcbsp2_gfclk at 4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcbsp3_gfclk: func_mcbsp3_gfclk at 4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck at 4a0094e0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+	bit-shift = <25>;
+	reg = <0x4a0094e0 0x4>;
+	bit-mask = <0x1>;
+};
+
+per_mcbsp4_gfclk: per_mcbsp4_gfclk at 4a0094e0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0094e0 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsmmc1_fclk: hsmmc1_fclk at 4a009328 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+	bit-shift = <24>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsmmc2_fclk: hsmmc2_fclk at 4a009330 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+	bit-shift = <24>;
+	reg = <0x4a009330 0x4>;
+	bit-mask = <0x1>;
+};
+
+ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m at 4a0093e0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a0093e0 0x4>;
+};
+
+sha2md5_fck: sha2md5_fck at 4a0095c8 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a0095c8 0x4>;
+};
+
+slimbus1_fclk_1: slimbus1_fclk_1 at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_24m_clk>;
+	bit-shift = <9>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_0: slimbus1_fclk_0 at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&abe_24m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_2: slimbus1_fclk_2 at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_clks_ck>;
+	bit-shift = <10>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_clk>;
+	bit-shift = <11>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus2_fclk_1: slimbus2_fclk_1 at 4a009538 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_abe_24m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009538 0x4>;
+};
+
+slimbus2_fclk_0: slimbus2_fclk_0 at 4a009538 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_24mc_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009538 0x4>;
+};
+
+slimbus2_slimbus_clk: slimbus2_slimbus_clk at 4a009538 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_slimbus_core_clks_ck>;
+	bit-shift = <10>;
+	reg = <0x4a009538 0x4>;
+};
+
+smartreflex_core_fck: smartreflex_core_fck at 4a008638 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <1>;
+	reg = <0x4a008638 0x4>;
+};
+
+smartreflex_iva_fck: smartreflex_iva_fck at 4a008630 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <1>;
+	reg = <0x4a008630 0x4>;
+};
+
+smartreflex_mpu_fck: smartreflex_mpu_fck at 4a008628 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <1>;
+	reg = <0x4a008628 0x4>;
+};
+
+dmt1_clk_mux: dmt1_clk_mux at 4a307840 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a307840 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm10_mux: cm2_dm10_mux at 4a009428 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009428 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm11_mux: cm2_dm11_mux at 4a009430 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009430 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm2_mux: cm2_dm2_mux at 4a009438 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009438 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm3_mux: cm2_dm3_mux at 4a009440 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009440 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm4_mux: cm2_dm4_mux at 4a009448 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009448 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer5_sync_mux: timer5_sync_mux at 4a004568 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004568 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer6_sync_mux: timer6_sync_mux at 4a004570 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004570 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer7_sync_mux: timer7_sync_mux at 4a004578 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004578 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer8_sync_mux: timer8_sync_mux at 4a004580 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004580 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm9_mux: cm2_dm9_mux at 4a009450 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009450 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_fs_fck: usb_host_fs_fck at 4a0093d0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48mc_fclk>;
+	reg = <0x4a0093d0 0x4>;
+	bit-shift = <1>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009358 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p1_gfclk>;
+	bit-shift = <8>;
+	reg = <0x4a009358 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+	bit-shift = <25>;
+	reg = <0x4a009358 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p2_gfclk>;
+	bit-shift = <9>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <13>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <11>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <12>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <14>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_func48mclk: usb_host_hs_func48mclk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48mc_fclk>;
+	bit-shift = <15>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_fck: usb_host_hs_fck at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <1>;
+	reg = <0x4a009358 0x4>;
+};
+
+otg_60m_gfclk: otg_60m_gfclk at 4a009360 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009360 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_otg_hs_xclk: usb_otg_hs_xclk at 4a009360 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&otg_60m_gfclk>;
+	bit-shift = <8>;
+	reg = <0x4a009360 0x4>;
+};
+
+usb_otg_hs_ick: usb_otg_hs_ick at 4a009360 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <0>;
+	reg = <0x4a009360 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k at 4a008640 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_ick: usb_tll_hs_ick at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_div_ck>;
+	bit-shift = <0>;
+	reg = <0x4a009368 0x4>;
+};
+
+usim_ck: usim_ck at 4a307858 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a307858 0x4>;
+	table = < 14 0 >, < 18 1 >;
+	bit-mask = <0x1>;
+};
+
+usim_fclk: usim_fclk at 4a307858 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&usim_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307858 0x4>;
+};
+
+pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+	bit-shift = <20>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x3>;
+};
+
+pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+	bit-shift = <22>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x3>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&pmd_stm_clock_mux_ck>;
+	bit-shift = <27>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+trace_clk_div_div_ck: trace_clk_div_div_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	bit-shift = <24>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&trace_clk_div_div_ck>;
+	ti,clkdm-name = "emu_sys_clkdm";
+};
+
+auxclk0_src_mux_ck: auxclk0_src_mux_ck at 4a30a310 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a310 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck at 4a30a310 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk0_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a310 0x4>;
+};
+
+auxclk0_ck: auxclk0_ck at 4a30a310 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk0_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a310 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk1_src_mux_ck: auxclk1_src_mux_ck at 4a30a314 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a314 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck at 4a30a314 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk1_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a314 0x4>;
+};
+
+auxclk1_ck: auxclk1_ck at 4a30a314 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk1_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a314 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk2_src_mux_ck: auxclk2_src_mux_ck at 4a30a318 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a318 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck at 4a30a318 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk2_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a318 0x4>;
+};
+
+auxclk2_ck: auxclk2_ck at 4a30a318 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk2_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a318 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk3_src_mux_ck: auxclk3_src_mux_ck at 4a30a31c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a31c 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck at 4a30a31c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk3_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a31c 0x4>;
+};
+
+auxclk3_ck: auxclk3_ck at 4a30a31c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk3_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a31c 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk4_src_mux_ck: auxclk4_src_mux_ck at 4a30a320 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a320 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck at 4a30a320 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk4_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a320 0x4>;
+};
+
+auxclk4_ck: auxclk4_ck at 4a30a320 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk4_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a320 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk5_src_mux_ck: auxclk5_src_mux_ck at 4a30a324 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a324 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk5_src_ck: auxclk5_src_ck at 4a30a324 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk5_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a324 0x4>;
+};
+
+auxclk5_ck: auxclk5_ck at 4a30a324 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk5_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a324 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck at 4a30a210 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a210 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck at 4a30a214 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a214 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck at 4a30a218 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a218 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck at 4a30a21c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a21c 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq4_ck: auxclkreq4_ck at 4a30a220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a220 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq5_ck: auxclkreq5_ck at 4a30a224 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a224 0x4>;
+	bit-mask = <0x7>;
+};
-- 
1.7.9.5

[PATCHv5 06/31] ARM: dts: omap4 clock data

[Tomasz Figa]

On Friday 02 of August 2013 19:25:25 Tero Kristo wrote:
> This patch creates a unique node for each clock in the OMAP4 power,
> reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
> different clock tree which is taken into account in the data.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  arch/arm/boot/dts/omap443x-clocks.dtsi |   17 +
>  arch/arm/boot/dts/omap443x.dtsi        |    8 +
>  arch/arm/boot/dts/omap4460.dtsi        |    8 +
>  arch/arm/boot/dts/omap446x-clocks.dtsi |   27 +
>  arch/arm/boot/dts/omap44xx-clocks.dtsi | 1648
> ++++++++++++++++++++++++++++++++ 5 files changed, 1708 insertions(+)
>  create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
>  create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
>  create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi
> 
> diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi
> b/arch/arm/boot/dts/omap443x-clocks.dtsi new file mode 100644
> index 0000000..2bd82b2
> --- /dev/null
> +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
> @@ -0,0 +1,17 @@
> +/*
> + * Device Tree Source for OMAP443x clock data
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as +
> * published by the Free Software Foundation.
> + */
> +
> +bandgap_fclk: bandgap_fclk at 4a307888 {
> +	#clock-cells = <0>;
> +	compatible = "gate-clock";
> +	clocks = <&sys_32k_ck>;
> +	bit-shift = <8>;
> +	reg = <0x4a307888 0x4>;
> +};
> diff --git a/arch/arm/boot/dts/omap443x.dtsi
> b/arch/arm/boot/dts/omap443x.dtsi index bcf455e..dfd648c 100644
> --- a/arch/arm/boot/dts/omap443x.dtsi
> +++ b/arch/arm/boot/dts/omap443x.dtsi
> @@ -30,4 +30,12 @@
>  		       0x4a00232C 0x4>;
>  		compatible = "ti,omap4430-bandgap";
>  	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +		/include/ "omap44xx-clocks.dtsi"
> +		/include/ "omap443x-clocks.dtsi"
> +	};
>  };
> diff --git a/arch/arm/boot/dts/omap4460.dtsi
> b/arch/arm/boot/dts/omap4460.dtsi index c2f0f39..d9d00b2 100644
> --- a/arch/arm/boot/dts/omap4460.dtsi
> +++ b/arch/arm/boot/dts/omap4460.dtsi
> @@ -38,4 +38,12 @@
>  		interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
>  		gpios = <&gpio3 22 0>; /* tshut */
>  	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +		/include/ "omap44xx-clocks.dtsi"
> +		/include/ "omap446x-clocks.dtsi"
> +	};
>  };
> diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi
> b/arch/arm/boot/dts/omap446x-clocks.dtsi new file mode 100644
> index 0000000..86d0805
> --- /dev/null
> +++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
> @@ -0,0 +1,27 @@
> +/*
> + * Device Tree Source for OMAP446x clock data
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as +
> * published by the Free Software Foundation.
> + */
> +
> +div_ts_ck: div_ts_ck at 4a307888 {
> +	#clock-cells = <0>;
> +	compatible = "divider-clock";
> +	clocks = <&l4_wkup_clk_mux_ck>;
> +	bit-shift = <24>;
> +	reg = <0x4a307888 0x4>;
> +	table = < 8 0 >, < 16 1 >, < 32 2 >;
> +	bit-mask = <0x3>;
> +};
> +
> +bandgap_ts_fclk: bandgap_ts_fclk at 4a307888 {
> +	#clock-cells = <0>;
> +	compatible = "gate-clock";
> +	clocks = <&div_ts_ck>;
> +	bit-shift = <8>;
> +	reg = <0x4a307888 0x4>;
> +};
> diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi
> b/arch/arm/boot/dts/omap44xx-clocks.dtsi new file mode 100644
> index 0000000..23f623c
> --- /dev/null
> +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
> @@ -0,0 +1,1648 @@
> +/*
> + * Device Tree Source for OMAP4 clock data
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as +
> * published by the Free Software Foundation.
> + */
> +
> +extalt_clkin_ck: extalt_clkin_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <59000000>;
> +};
> +
> +pad_clks_src_ck: pad_clks_src_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <12000000>;
> +};
> +
> +pad_clks_ck: pad_clks_ck at 4a004108 {
> +	#clock-cells = <0>;
> +	compatible = "gate-clock";
> +	clocks = <&pad_clks_src_ck>;
> +	bit-shift = <8>;
> +	reg = <0x4a004108 0x4>;
> +};
> +
> +pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <12000000>;
> +};
> +
> +secure_32k_clk_src_ck: secure_32k_clk_src_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <32768>;
> +};
> +
> +slimbus_src_clk: slimbus_src_clk {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <12000000>;
> +};
> +
> +slimbus_clk: slimbus_clk at 4a004108 {
> +	#clock-cells = <0>;
> +	compatible = "gate-clock";
> +	clocks = <&slimbus_src_clk>;
> +	bit-shift = <10>;
> +	reg = <0x4a004108 0x4>;
> +};
> +
> +sys_32k_ck: sys_32k_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <32768>;
> +};
> +
> +virt_12000000_ck: virt_12000000_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <12000000>;
> +};
> +
> +virt_13000000_ck: virt_13000000_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <13000000>;
> +};
> +
> +virt_16800000_ck: virt_16800000_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <16800000>;
> +};
> +
> +virt_19200000_ck: virt_19200000_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <19200000>;
> +};
> +
> +virt_26000000_ck: virt_26000000_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <26000000>;
> +};
> +
> +virt_27000000_ck: virt_27000000_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <27000000>;
> +};
> +
> +virt_38400000_ck: virt_38400000_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <38400000>;
> +};
> +
> +sys_clkin_ck: sys_clkin_ck at 4a306110 {
> +	#clock-cells = <0>;
> +	compatible = "mux-clock";
> +	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>,
> <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>,
> <&virt_27000000_ck>, <&virt_38400000_ck>; +	reg = <0x4a306110 0x4>;
> +	bit-mask = <0x7>;
> +	index-starts-at-one;
> +};
> +
> +tie_low_clock_ck: tie_low_clock_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <0>;
> +};
> +
> +utmi_phy_clkout_ck: utmi_phy_clkout_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <60000000>;
> +};
> +
> +xclk60mhsp1_ck: xclk60mhsp1_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <60000000>;
> +};
> +
> +xclk60mhsp2_ck: xclk60mhsp2_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <60000000>;
> +};
> +
> +xclk60motg_ck: xclk60motg_ck {
> +	#clock-cells = <0>;
> +	compatible = "fixed-clock";
> +	clock-frequency = <60000000>;
> +};
> +
> +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {
> +	#clock-cells = <0>;
> +	compatible = "mux-clock";
> +	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
> +	bit-shift = <24>;
> +	reg = <0x4a306108 0x4>;
> +	bit-mask = <0x1>;
> +};
> +
> +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck at 4a30610c {
> +	#clock-cells = <0>;
> +	compatible = "mux-clock";
> +	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
> +	reg = <0x4a30610c 0x4>;
> +	bit-mask = <0x1>;
> +};
> +
> +dpll_abe_ck: dpll_abe_ck at 4a0041e0 {
> +	#clock-cells = <0>;
> +	compatible = "ti,omap4-dpll-m4xen-clock";
> +	clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
> +	reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>,
> <0x4a0041ec 0x4>; +	ti,clk-ref = <&abe_dpll_refclk_mux_ck>;
> +	ti,clk-bypass = <&abe_dpll_bypass_clk_mux_ck>;

Hmm, why do you need to pass references to other clocks using private 
properties? Is there a reason you can't use the clocks and clock-names 
properties defined by standard clock bindings?

The same for other PLLs defined in this patch.

Best regards,
Tomasz

[PATCHv5 06/31] ARM: dts: omap4 clock data

[Tero Kristo]

On 08/03/2013 05:16 PM, Tomasz Figa wrote:
> On Friday 02 of August 2013 19:25:25 Tero Kristo wrote:
>> This patch creates a unique node for each clock in the OMAP4 power,
>> reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
>> different clock tree which is taken into account in the data.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/boot/dts/omap443x-clocks.dtsi |   17 +
>>   arch/arm/boot/dts/omap443x.dtsi        |    8 +
>>   arch/arm/boot/dts/omap4460.dtsi        |    8 +
>>   arch/arm/boot/dts/omap446x-clocks.dtsi |   27 +
>>   arch/arm/boot/dts/omap44xx-clocks.dtsi | 1648
>> ++++++++++++++++++++++++++++++++ 5 files changed, 1708 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
>>   create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
>>   create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi
>>
>> diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi
>> b/arch/arm/boot/dts/omap443x-clocks.dtsi new file mode 100644
>> index 0000000..2bd82b2
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
>> @@ -0,0 +1,17 @@
>> +/*
>> + * Device Tree Source for OMAP443x clock data
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as +
>> * published by the Free Software Foundation.
>> + */
>> +
>> +bandgap_fclk: bandgap_fclk at 4a307888 {
>> +	#clock-cells = <0>;
>> +	compatible = "gate-clock";
>> +	clocks = <&sys_32k_ck>;
>> +	bit-shift = <8>;
>> +	reg = <0x4a307888 0x4>;
>> +};
>> diff --git a/arch/arm/boot/dts/omap443x.dtsi
>> b/arch/arm/boot/dts/omap443x.dtsi index bcf455e..dfd648c 100644
>> --- a/arch/arm/boot/dts/omap443x.dtsi
>> +++ b/arch/arm/boot/dts/omap443x.dtsi
>> @@ -30,4 +30,12 @@
>>   		       0x4a00232C 0x4>;
>>   		compatible = "ti,omap4430-bandgap";
>>   	};
>> +
>> +	clocks {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +		/include/ "omap44xx-clocks.dtsi"
>> +		/include/ "omap443x-clocks.dtsi"
>> +	};
>>   };
>> diff --git a/arch/arm/boot/dts/omap4460.dtsi
>> b/arch/arm/boot/dts/omap4460.dtsi index c2f0f39..d9d00b2 100644
>> --- a/arch/arm/boot/dts/omap4460.dtsi
>> +++ b/arch/arm/boot/dts/omap4460.dtsi
>> @@ -38,4 +38,12 @@
>>   		interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
>>   		gpios = <&gpio3 22 0>; /* tshut */
>>   	};
>> +
>> +	clocks {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +		/include/ "omap44xx-clocks.dtsi"
>> +		/include/ "omap446x-clocks.dtsi"
>> +	};
>>   };
>> diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi
>> b/arch/arm/boot/dts/omap446x-clocks.dtsi new file mode 100644
>> index 0000000..86d0805
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
>> @@ -0,0 +1,27 @@
>> +/*
>> + * Device Tree Source for OMAP446x clock data
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as +
>> * published by the Free Software Foundation.
>> + */
>> +
>> +div_ts_ck: div_ts_ck at 4a307888 {
>> +	#clock-cells = <0>;
>> +	compatible = "divider-clock";
>> +	clocks = <&l4_wkup_clk_mux_ck>;
>> +	bit-shift = <24>;
>> +	reg = <0x4a307888 0x4>;
>> +	table = < 8 0 >, < 16 1 >, < 32 2 >;
>> +	bit-mask = <0x3>;
>> +};
>> +
>> +bandgap_ts_fclk: bandgap_ts_fclk at 4a307888 {
>> +	#clock-cells = <0>;
>> +	compatible = "gate-clock";
>> +	clocks = <&div_ts_ck>;
>> +	bit-shift = <8>;
>> +	reg = <0x4a307888 0x4>;
>> +};
>> diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi
>> b/arch/arm/boot/dts/omap44xx-clocks.dtsi new file mode 100644
>> index 0000000..23f623c
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
>> @@ -0,0 +1,1648 @@
>> +/*
>> + * Device Tree Source for OMAP4 clock data
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as +
>> * published by the Free Software Foundation.
>> + */
>> +
>> +extalt_clkin_ck: extalt_clkin_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <59000000>;
>> +};
>> +
>> +pad_clks_src_ck: pad_clks_src_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <12000000>;
>> +};
>> +
>> +pad_clks_ck: pad_clks_ck at 4a004108 {
>> +	#clock-cells = <0>;
>> +	compatible = "gate-clock";
>> +	clocks = <&pad_clks_src_ck>;
>> +	bit-shift = <8>;
>> +	reg = <0x4a004108 0x4>;
>> +};
>> +
>> +pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <12000000>;
>> +};
>> +
>> +secure_32k_clk_src_ck: secure_32k_clk_src_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <32768>;
>> +};
>> +
>> +slimbus_src_clk: slimbus_src_clk {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <12000000>;
>> +};
>> +
>> +slimbus_clk: slimbus_clk at 4a004108 {
>> +	#clock-cells = <0>;
>> +	compatible = "gate-clock";
>> +	clocks = <&slimbus_src_clk>;
>> +	bit-shift = <10>;
>> +	reg = <0x4a004108 0x4>;
>> +};
>> +
>> +sys_32k_ck: sys_32k_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <32768>;
>> +};
>> +
>> +virt_12000000_ck: virt_12000000_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <12000000>;
>> +};
>> +
>> +virt_13000000_ck: virt_13000000_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <13000000>;
>> +};
>> +
>> +virt_16800000_ck: virt_16800000_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <16800000>;
>> +};
>> +
>> +virt_19200000_ck: virt_19200000_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <19200000>;
>> +};
>> +
>> +virt_26000000_ck: virt_26000000_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <26000000>;
>> +};
>> +
>> +virt_27000000_ck: virt_27000000_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <27000000>;
>> +};
>> +
>> +virt_38400000_ck: virt_38400000_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <38400000>;
>> +};
>> +
>> +sys_clkin_ck: sys_clkin_ck at 4a306110 {
>> +	#clock-cells = <0>;
>> +	compatible = "mux-clock";
>> +	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>,
>> <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>,
>> <&virt_27000000_ck>, <&virt_38400000_ck>; +	reg = <0x4a306110 0x4>;
>> +	bit-mask = <0x7>;
>> +	index-starts-at-one;
>> +};
>> +
>> +tie_low_clock_ck: tie_low_clock_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <0>;
>> +};
>> +
>> +utmi_phy_clkout_ck: utmi_phy_clkout_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <60000000>;
>> +};
>> +
>> +xclk60mhsp1_ck: xclk60mhsp1_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <60000000>;
>> +};
>> +
>> +xclk60mhsp2_ck: xclk60mhsp2_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <60000000>;
>> +};
>> +
>> +xclk60motg_ck: xclk60motg_ck {
>> +	#clock-cells = <0>;
>> +	compatible = "fixed-clock";
>> +	clock-frequency = <60000000>;
>> +};
>> +
>> +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {
>> +	#clock-cells = <0>;
>> +	compatible = "mux-clock";
>> +	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
>> +	bit-shift = <24>;
>> +	reg = <0x4a306108 0x4>;
>> +	bit-mask = <0x1>;
>> +};
>> +
>> +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck at 4a30610c {
>> +	#clock-cells = <0>;
>> +	compatible = "mux-clock";
>> +	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
>> +	reg = <0x4a30610c 0x4>;
>> +	bit-mask = <0x1>;
>> +};
>> +
>> +dpll_abe_ck: dpll_abe_ck at 4a0041e0 {
>> +	#clock-cells = <0>;
>> +	compatible = "ti,omap4-dpll-m4xen-clock";
>> +	clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
>> +	reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>,
>> <0x4a0041ec 0x4>; +	ti,clk-ref = <&abe_dpll_refclk_mux_ck>;
>> +	ti,clk-bypass = <&abe_dpll_bypass_clk_mux_ck>;
>
> Hmm, why do you need to pass references to other clocks using private
> properties? Is there a reason you can't use the clocks and clock-names
> properties defined by standard clock bindings?
>
> The same for other PLLs defined in this patch.

Will be changed for next rev, clk-bypass / clk-ref will be populated 
from clocks property directly.

-Tero

[PATCHv5 07/31] CLK: TI: add omap4 clock init file

[Tero Kristo]

clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.h |    1 -
 drivers/clk/ti/clk-44xx.c   |  118 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h      |    1 +
 3 files changed, 119 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clk-44xx.c

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 1a8c41a..f0ee28c 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -267,7 +267,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 				void __iomem **idlest_reg,
 				u8 *idlest_bit, u8 *idlest_val);
 int omap2_clk_enable_autoidle_all(void);
-int omap2_clk_disable_autoidle_all(void);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
new file mode 100644
index 0000000..2c2ec72
--- /dev/null
+++ b/drivers/clk/ti/clk-44xx.c
@@ -0,0 +1,118 @@
+/*
+ * OMAP4 Clock data
+ *
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ * Rajendra Nayak (rnayak at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ * Mike Turquette (mturquette at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ *
+ * XXX All of the remaining MODULEMODE clock nodes should be removed
+ * once the drivers are updated to use pm_runtime or to use the appropriate
+ * upstream clock node for rate/parent selection.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+
+/*
+ * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
+ * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
+ * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
+ * half of this value.
+ */
+#define OMAP4_DPLL_ABE_DEFFREQ				98304000
+
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ				960000000
+
+static struct omap_dt_clk omap44xx_clks[] = {
+	DT_CLK("smp_twd",	NULL,			"mpu_periphclk"),
+	DT_CLK("omapdss_dss", "ick", "dss_fck"),
+	DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
+	DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
+	DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
+	DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
+	DT_CLK(NULL,	"timer_32k_ck",	"sys_32k_ck"),
+	/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
+	DT_CLK("omap_timer.1",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.2",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.3",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.4",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.9",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.10",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.11",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.5",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.6",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.7",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.8",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4a318000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48032000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48034000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48036000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("4803e000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48086000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48088000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("40138000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013a000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013c000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013e000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK(NULL,	"cpufreq_ck",	"dpll_mpu_ck"),
+	{ NULL },
+};
+
+int __init omap4xxx_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
+
+	/* FIXME register clocks from DT first */
+	of_clk_init(NULL);
+
+	omap_dt_clocks_register(omap44xx_clks);
+
+	omap2_clk_disable_autoidle_all();
+
+	/*
+	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
+	 * state when turning the ABE clock domain. Workaround this by
+	 * locking the ABE DPLL on boot.
+	 * Lock the ABE DPLL in any case to avoid issues with audio.
+	 */
+	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
+	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+	if (!rc)
+		rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	/*
+	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+	 * domain can transition to retention state when not in use.
+	 */
+	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+	rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+	return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index eec4973..c4f0c1b 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -178,6 +178,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 				    unsigned long parent_rate);
 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+int omap2_clk_disable_autoidle_all(void);
 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 			 unsigned long parent_rate);
 int omap2_dflt_clk_enable(struct clk_hw *hw);
-- 
1.7.9.5

[PATCHv5 07/31] CLK: TI: add omap4 clock init file

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [130802 09:33]:
> clk-44xx.c now contains the clock init functionality for omap4, including
> DT clock registration and adding of static clkdev entries.

Few comments below from "boot new hardware with old kernels" point of
view that seems to be pretty close for clocks.
 
> --- /dev/null
> +++ b/drivers/clk/ti/clk-44xx.c
...

> +int __init omap4xxx_clk_init(void)
> +{
> +	int rc;
> +	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
> +
> +	/* FIXME register clocks from DT first */
> +	of_clk_init(NULL);
> +
> +	omap_dt_clocks_register(omap44xx_clks);
> +
> +	omap2_clk_disable_autoidle_all();
> +
> +	/*
> +	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
> +	 * state when turning the ABE clock domain. Workaround this by
> +	 * locking the ABE DPLL on boot.
> +	 * Lock the ABE DPLL in any case to avoid issues with audio.
> +	 */
> +	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
> +	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
> +	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
> +	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
> +	if (!rc)
> +		rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
> +	if (rc)
> +		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
> +
> +	/*
> +	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
> +	 * domain can transition to retention state when not in use.
> +	 */
> +	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
> +	rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
> +	if (rc)
> +		pr_err("%s: failed to configure USB DPLL!\n", __func__);
> +
> +	return 0;
> +}

Maybe try to have a generic init function, then have SoC specific
quirk function pointers set up based on the DT compatible property?

Grep for varioius _of_match[] examples in the drivers.

That way you might be able to make clocks work for some new similar
hardware with just .dts change and patching in the quirks later on
as needed ;)

Regards,

Tony

[PATCHv5 07/31] CLK: TI: add omap4 clock init file

[Tero Kristo]

On 08/05/2013 10:27 AM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [130802 09:33]:
>> clk-44xx.c now contains the clock init functionality for omap4, including
>> DT clock registration and adding of static clkdev entries.
>
> Few comments below from "boot new hardware with old kernels" point of
> view that seems to be pretty close for clocks.
>
>> --- /dev/null
>> +++ b/drivers/clk/ti/clk-44xx.c
> ...
>
>> +int __init omap4xxx_clk_init(void)
>> +{
>> +	int rc;
>> +	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
>> +
>> +	/* FIXME register clocks from DT first */
>> +	of_clk_init(NULL);
>> +
>> +	omap_dt_clocks_register(omap44xx_clks);
>> +
>> +	omap2_clk_disable_autoidle_all();
>> +
>> +	/*
>> +	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
>> +	 * state when turning the ABE clock domain. Workaround this by
>> +	 * locking the ABE DPLL on boot.
>> +	 * Lock the ABE DPLL in any case to avoid issues with audio.
>> +	 */
>> +	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
>> +	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
>> +	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
>> +	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
>> +	if (!rc)
>> +		rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
>> +	if (rc)
>> +		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>> +
>> +	/*
>> +	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
>> +	 * domain can transition to retention state when not in use.
>> +	 */
>> +	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
>> +	rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
>> +	if (rc)
>> +		pr_err("%s: failed to configure USB DPLL!\n", __func__);
>> +
>> +	return 0;
>> +}
>
> Maybe try to have a generic init function, then have SoC specific
> quirk function pointers set up based on the DT compatible property?
>
> Grep for varioius _of_match[] examples in the drivers.
>
> That way you might be able to make clocks work for some new similar
> hardware with just .dts change and patching in the quirks later on
> as needed ;)

I'll see what can be done for this once I figure out what to do with the 
clkdev alias stuff. :)

-Tero

>
> Regards,
>
> Tony
>

[PATCHv5 08/31] ARM: OMAP4: remove old clock data and link in new clock init code

[Tero Kristo]

OMAP4 clocks have now been moved to DT, thus remove the old data file
and use the new init code under drivers/clk/omap/clk-44xx.c.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/Makefile          |    2 +-
 arch/arm/mach-omap2/cclock44xx_data.c | 1730 ---------------------------------
 drivers/clk/ti/Makefile               |    3 +-
 3 files changed, 3 insertions(+), 1732 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cclock44xx_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4f6715..9f8d3ed 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -175,7 +175,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clock34xx.o clkt34xx_dpll3m2.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clock3517.o clock36xx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= dpll3xxx.o cclock3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) cclock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o
 obj-$(CONFIG_SOC_AM33XX)		+= cclock33xx_data.o
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
deleted file mode 100644
index 88e37a4..0000000
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ /dev/null
@@ -1,1730 +0,0 @@
-/*
- * OMAP4 Clock data
- *
- * Copyright (C) 2009-2012 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul at pwsan.com)
- * Rajendra Nayak (rnayak at ti.com)
- * Benoit Cousson (b-cousson at ti.com)
- * Mike Turquette (mturquette at ti.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX Some of the ES1 clocks have been removed/changed; once support
- * is added for discriminating clocks by ES level, these should be added back
- * in.
- *
- * XXX All of the remaining MODULEMODE clock nodes should be removed
- * once the drivers are updated to use pm_runtime or to use the appropriate
- * upstream clock node for rate/parent selection.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock44xx.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm44xx.h"
-#include "prm-regbits-44xx.h"
-#include "control.h"
-#include "scrm44xx.h"
-
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL_SHIFT		0
-#define OMAP4430_MODULEMODE_SWCTRL_SHIFT		1
-
-/*
- * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
- * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
- * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
- * half of this value.
- */
-#define OMAP4_DPLL_ABE_DEFFREQ				98304000
-
-/*
- * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
- * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
- * locked frequency for the USB DPLL is 960MHz.
- */
-#define OMAP4_DPLL_USB_DEFFREQ				960000000
-
-/* Root clocks */
-
-DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
-		OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
-		OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
-
-static const char *sys_clkin_ck_parents[] = {
-	"virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
-	"virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
-	"virt_38400000_ck",
-};
-
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
-	       OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-
-DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
-
-DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
-	       NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
-	       OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-/* DPLL_ABE */
-static struct dpll_data dpll_abe_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_ABE,
-	.clk_bypass	= &abe_dpll_bypass_clk_mux_ck,
-	.clk_ref	= &abe_dpll_refclk_mux_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_ABE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_ABE,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_ABE,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.m4xen_mask	= OMAP4430_DPLL_REGM4XEN_MASK,
-	.lpmode_mask	= OMAP4430_DPLL_LPMODE_EN_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-
-static const char *dpll_abe_ck_parents[] = {
-	"abe_dpll_refclk_mux_ck",
-};
-
-static struct clk dpll_abe_ck;
-
-static const struct clk_ops dpll_abe_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
-	.round_rate	= &omap4_dpll_regm4xen_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_abe_ck_hw = {
-	.hw = {
-		.clk = &dpll_abe_ck,
-	},
-	.dpll_data	= &dpll_abe_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
-
-static const char *dpll_abe_x2_ck_parents[] = {
-	"dpll_abe_ck",
-};
-
-static struct clk dpll_abe_x2_ck;
-
-static const struct clk_ops dpll_abe_x2_ck_ops = {
-	.recalc_rate	= &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_abe_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_abe_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-static const struct clk_ops omap_hsdivider_ops = {
-	.set_rate	= &omap2_clksel_set_rate,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-};
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-			0x0, 1, 8);
-
-DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
-		   OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
-		   OMAP4430_CM1_ABE_AESS_CLKCTRL,
-		   OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-		   OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
-			  OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
-
-static const char *core_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "dpll_abe_m3x2_ck",
-};
-
-DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
-	       OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
-	       0x0, NULL);
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_CORE,
-	.clk_bypass	= &core_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_CORE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_CORE,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_CORE,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-
-static const char *dpll_core_ck_parents[] = {
-	"sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-	.hw = {
-		.clk = &dpll_core_ck,
-	},
-	.dpll_data	= &dpll_core_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-	"dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_core_x2_ck,
-	},
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_CORE,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
-			2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
-		   OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-		   0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
-		   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-		   0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
-		   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
-			0x0, 1, 2);
-
-DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
-		   OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-		   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const struct clk_ops dpll_hsd_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static const struct clk_ops func_dmic_abe_gfclk_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-};
-
-static const char *dpll_core_m3x2_ck_parents[] = {
-	"dpll_core_x2_ck",
-};
-
-static const struct clksel dpll_core_m3x2_div[] = {
-	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
-			 OMAP4430_CM_DIV_M3_DPLL_CORE,
-			 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-			 OMAP4430_CM_DIV_M3_DPLL_CORE,
-			 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-			 dpll_core_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "div_iva_hs_clk",
-};
-
-DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-	       OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_IVA */
-static struct dpll_data dpll_iva_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_IVA,
-	.clk_bypass	= &iva_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_IVA,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_IVA,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_IVA,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_iva_ck_parents[] = {
-	"sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_iva_ck;
-
-static const struct clk_ops dpll_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_iva_ck_hw = {
-	.hw = {
-		.clk = &dpll_iva_ck,
-	},
-	.dpll_data	= &dpll_iva_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
-
-static const char *dpll_iva_x2_ck_parents[] = {
-	"dpll_iva_ck",
-};
-
-static struct clk dpll_iva_x2_ck;
-
-static struct clk_hw_omap dpll_iva_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_iva_x2_ck,
-	},
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_MPU,
-	.clk_bypass	= &div_mpu_hs_clk,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_MPU,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_MPU,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_MPU,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_mpu_ck_parents[] = {
-	"sys_clkin_ck", "div_mpu_hs_clk"
-};
-
-static struct clk dpll_mpu_ck;
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-	.hw = {
-		.clk = &dpll_mpu_ck,
-	},
-	.dpll_data	= &dpll_mpu_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_MPU,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-			&dpll_abe_m3x2_ck, 0x0, 1, 2);
-
-static const char *per_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "per_hs_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-	       OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_PER,
-	.clk_bypass	= &per_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_PER,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_PER,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_PER,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_per_ck_parents[] = {
-	"sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-	.hw = {
-		.clk = &dpll_per_ck,
-	},
-	.dpll_data	= &dpll_per_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		   OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-		   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const char *dpll_per_x2_ck_parents[] = {
-	"dpll_per_ck",
-};
-
-static struct clk dpll_per_x2_ck;
-
-static struct clk_hw_omap dpll_per_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_per_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-static const char *dpll_per_m3x2_ck_parents[] = {
-	"dpll_per_x2_ck",
-};
-
-static const struct clksel dpll_per_m3x2_div[] = {
-	{ .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
-			 OMAP4430_CM_DIV_M3_DPLL_PER,
-			 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-			 OMAP4430_CM_DIV_M3_DPLL_PER,
-			 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-			 dpll_per_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-			&dpll_abe_m3x2_ck, 0x0, 1, 3);
-
-/* DPLL_USB */
-static struct dpll_data dpll_usb_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_USB,
-	.clk_bypass	= &usb_hs_clk_div_ck,
-	.flags		= DPLL_J_TYPE,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_USB,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_USB,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_USB,
-	.mult_mask	= OMAP4430_DPLL_MULT_USB_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_0_7_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.sddiv_mask	= OMAP4430_DPLL_SD_DIV_MASK,
-	.max_multiplier	= 4095,
-	.max_divider	= 256,
-	.min_divider	= 1,
-};
-
-static const char *dpll_usb_ck_parents[] = {
-	"sys_clkin_ck", "usb_hs_clk_div_ck"
-};
-
-static struct clk dpll_usb_ck;
-
-static const struct clk_ops dpll_usb_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap dpll_usb_ck_hw = {
-	.hw = {
-		.clk = &dpll_usb_ck,
-	},
-	.dpll_data	= &dpll_usb_dd,
-	.clkdm_name	= "l3_init_clkdm",
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
-
-static const char *dpll_usb_clkdcoldo_ck_parents[] = {
-	"dpll_usb_ck",
-};
-
-static struct clk dpll_usb_clkdcoldo_ck;
-
-static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
-};
-
-static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
-	.hw = {
-		.clk = &dpll_usb_clkdcoldo_ck,
-	},
-	.clksel_reg	= OMAP4430_CM_CLKDCOLDO_DPLL_USB,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
-		  dpll_usb_clkdcoldo_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_USB,
-			  OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
-
-static const char *ducati_clk_mux_ck_parents[] = {
-	"div_core_ck", "dpll_per_m6x2_ck",
-};
-
-DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 16);
-
-DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
-			1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 8);
-
-static const struct clk_div_table func_48m_fclk_rates[] = {
-	{ .div = 4, .val = 0 },
-	{ .div = 8, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
-			 NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk,	"dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 4);
-
-static const struct clk_div_table func_64m_fclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 4, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
-			 NULL);
-
-static const struct clk_div_table func_96m_fclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 4, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
-			 NULL);
-
-static const struct clk_div_table init_60m_fclk_rates[] = {
-	{ .div = 1, .val = 0 },
-	{ .div = 8, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
-			 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
-			 OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
-			 0x0, init_60m_fclk_rates, NULL);
-
-DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
-		   OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
-		   OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-			0x0, 1, 16);
-
-static const char *l4_wkup_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "lp_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const struct clk_div_table ocp_abe_iclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 1, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
-			 OMAP4430_CM1_ABE_AESS_CLKCTRL,
-			 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-			 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-			 0x0, ocp_abe_iclk_rates, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
-			0x0, 1, 4);
-
-DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
-		   OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-		   OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-		   OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-		   OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const char *dbgclk_mux_ck_parents[] = {
-	"sys_clkin_ck"
-};
-
-static struct clk dbgclk_mux_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
-DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
-		  dpll_usb_clkdcoldo_ck_ops);
-
-/* Leaf clocks controlled by modules */
-
-DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_AES1_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_AES2_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-		OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table div_ts_ck_rates[] = {
-	{ .div = 8, .val = 0 },
-	{ .div = 16, .val = 1 },
-	{ .div = 32, .val = 2 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-			 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-			 OMAP4430_CLKSEL_24_25_SHIFT,
-			 OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
-			 NULL);
-
-DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
-		OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-		OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
-		0x0, NULL);
-
-static const char *dmic_sync_mux_ck_parents[] = {
-	"abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
-};
-
-DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
-	{ .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_dmic_abe_gfclk_parents[] = {
-	"dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
-		    OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-		    func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-		   OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
-		   OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-		OMAP4430_OPTFCLKEN_DBCLK_SHIFT,	0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-		OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-static const struct clksel sgx_clk_mux_sel[] = {
-	{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *sgx_clk_mux_parents[] = {
-	"dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
-		    OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
-		    sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
-		   OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
-		   OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
-		OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
-	{ .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcasp_abe_gfclk_parents[] = {
-	"mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-		    func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
-	{ .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp1_gfclk_parents[] = {
-	"mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
-	{ .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp2_gfclk_parents[] = {
-	"mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
-	{ .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp3_gfclk_parents[] = {
-	"mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const char *mcbsp4_sync_mux_ck_parents[] = {
-	"func_96m_fclk", "per_abe_nc_fclk",
-};
-
-DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
-	{ .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *per_mcbsp4_gfclk_parents[] = {
-	"mcbsp4_sync_mux_ck", "pad_clks_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
-		    OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const struct clksel hsmmc1_fclk_sel[] = {
-	{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
-	{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *hsmmc1_fclk_parents[] = {
-	"func_64m_fclk", "func_96m_fclk",
-};
-
-DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-		    OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-		    OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
-		&pad_slimbus_core_clks_ck, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clksel dmt1_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const struct clksel timer5_sync_mux_sel[] = {
-	{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer5_sync_mux_parents[] = {
-	"syc_clk_div_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static struct clk usb_host_fs_fck;
-
-static const char *usb_host_fs_fck_parent_names[] = {
-	"func_48mc_fclk",
-};
-
-static const struct clk_ops usb_host_fs_fck_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-};
-
-static struct clk_hw_omap usb_host_fs_fck_hw = {
-	.hw = {
-		.clk = &usb_host_fs_fck,
-	},
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-};
-
-DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
-		  usb_host_fs_fck_ops);
-
-static const char *utmi_p1_gfclk_parents[] = {
-	"init_60m_fclk", "xclk60mhsp1_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	       OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
-
-static const char *utmi_p2_gfclk_parents[] = {
-	"init_60m_fclk", "xclk60mhsp2_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	       OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
-		&dpll_usb_m2_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
-		&init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
-		&init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
-		&dpll_usb_m2_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const char *otg_60m_gfclk_parents[] = {
-	"utmi_phy_clkout_ck", "xclk60motg_ck",
-};
-
-DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
-	       OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-		OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-		OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
-		OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table usim_ck_rates[] = {
-	{ .div = 14, .val = 0 },
-	{ .div = 18, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-			 OMAP4430_CM_WKUP_USIM_CLKCTRL,
-			 OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
-			 0x0, usim_ck_rates, NULL);
-
-DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
-		OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
-		0x0, NULL);
-
-/* Remaining optional clocks */
-static const char *pmd_stm_clock_mux_ck_parents[] = {
-	"sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
-};
-
-DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
-	       OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	       OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
-	       OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
-		   &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-		   OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
-		   OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-static const char *trace_clk_div_ck_parents[] = {
-	"pmd_trace_clk_mux_ck",
-};
-
-static const struct clksel trace_clk_div_div[] = {
-	{ .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
-
-static struct clk trace_clk_div_ck;
-
-static const struct clk_ops trace_clk_div_ck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.set_rate	= &omap2_clksel_set_rate,
-	.round_rate	= &omap2_clksel_round_rate,
-	.init		= &omap2_init_clk_clkdm,
-	.enable		= &omap2_clkops_enable_clkdm,
-	.disable	= &omap2_clkops_disable_clkdm,
-};
-
-static struct clk_hw_omap trace_clk_div_ck_hw = {
-	.hw = {
-		.clk = &trace_clk_div_ck,
-	},
-	.clkdm_name	= "emu_sys_clkdm",
-	.clksel		= trace_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
-		  trace_clk_div_ck_ops);
-
-/* SCRM aux clk nodes */
-
-static const struct clksel auxclk_src_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
-	{ .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *auxclk_src_ck_parents[] = {
-	"sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
-};
-
-static const struct clk_ops auxclk_src_ck_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-static const char *auxclkreq_ck_parents[] = {
-	"auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
-	"auxclk5_ck",
-};
-
-DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-/*
- * clocks specific to omap4460
- */
-static struct omap_clk omap446x_clks[] = {
-	CLK(NULL,	"div_ts_ck",			&div_ts_ck),
-	CLK(NULL,	"bandgap_ts_fclk",		&bandgap_ts_fclk),
-};
-
-/*
- * clocks specific to omap4430
- */
-static struct omap_clk omap443x_clks[] = {
-	CLK(NULL,	"bandgap_fclk",			&bandgap_fclk),
-};
-
-/*
- * clocks common to omap44xx
- */
-static struct omap_clk omap44xx_clks[] = {
-	CLK(NULL,	"extalt_clkin_ck",		&extalt_clkin_ck),
-	CLK(NULL,	"pad_clks_src_ck",		&pad_clks_src_ck),
-	CLK(NULL,	"pad_clks_ck",			&pad_clks_ck),
-	CLK(NULL,	"pad_slimbus_core_clks_ck",	&pad_slimbus_core_clks_ck),
-	CLK(NULL,	"secure_32k_clk_src_ck",	&secure_32k_clk_src_ck),
-	CLK(NULL,	"slimbus_src_clk",		&slimbus_src_clk),
-	CLK(NULL,	"slimbus_clk",			&slimbus_clk),
-	CLK(NULL,	"sys_32k_ck",			&sys_32k_ck),
-	CLK(NULL,	"virt_12000000_ck",		&virt_12000000_ck),
-	CLK(NULL,	"virt_13000000_ck",		&virt_13000000_ck),
-	CLK(NULL,	"virt_16800000_ck",		&virt_16800000_ck),
-	CLK(NULL,	"virt_19200000_ck",		&virt_19200000_ck),
-	CLK(NULL,	"virt_26000000_ck",		&virt_26000000_ck),
-	CLK(NULL,	"virt_27000000_ck",		&virt_27000000_ck),
-	CLK(NULL,	"virt_38400000_ck",		&virt_38400000_ck),
-	CLK(NULL,	"sys_clkin_ck",			&sys_clkin_ck),
-	CLK(NULL,	"tie_low_clock_ck",		&tie_low_clock_ck),
-	CLK(NULL,	"utmi_phy_clkout_ck",		&utmi_phy_clkout_ck),
-	CLK(NULL,	"xclk60mhsp1_ck",		&xclk60mhsp1_ck),
-	CLK(NULL,	"xclk60mhsp2_ck",		&xclk60mhsp2_ck),
-	CLK(NULL,	"xclk60motg_ck",		&xclk60motg_ck),
-	CLK(NULL,	"abe_dpll_bypass_clk_mux_ck",	&abe_dpll_bypass_clk_mux_ck),
-	CLK(NULL,	"abe_dpll_refclk_mux_ck",	&abe_dpll_refclk_mux_ck),
-	CLK(NULL,	"dpll_abe_ck",			&dpll_abe_ck),
-	CLK(NULL,	"dpll_abe_x2_ck",		&dpll_abe_x2_ck),
-	CLK(NULL,	"dpll_abe_m2x2_ck",		&dpll_abe_m2x2_ck),
-	CLK(NULL,	"abe_24m_fclk",			&abe_24m_fclk),
-	CLK(NULL,	"abe_clk",			&abe_clk),
-	CLK(NULL,	"aess_fclk",			&aess_fclk),
-	CLK(NULL,	"dpll_abe_m3x2_ck",		&dpll_abe_m3x2_ck),
-	CLK(NULL,	"core_hsd_byp_clk_mux_ck",	&core_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_core_ck",			&dpll_core_ck),
-	CLK(NULL,	"dpll_core_x2_ck",		&dpll_core_x2_ck),
-	CLK(NULL,	"dpll_core_m6x2_ck",		&dpll_core_m6x2_ck),
-	CLK(NULL,	"dbgclk_mux_ck",		&dbgclk_mux_ck),
-	CLK(NULL,	"dpll_core_m2_ck",		&dpll_core_m2_ck),
-	CLK(NULL,	"ddrphy_ck",			&ddrphy_ck),
-	CLK(NULL,	"dpll_core_m5x2_ck",		&dpll_core_m5x2_ck),
-	CLK(NULL,	"div_core_ck",			&div_core_ck),
-	CLK(NULL,	"div_iva_hs_clk",		&div_iva_hs_clk),
-	CLK(NULL,	"div_mpu_hs_clk",		&div_mpu_hs_clk),
-	CLK(NULL,	"dpll_core_m4x2_ck",		&dpll_core_m4x2_ck),
-	CLK(NULL,	"dll_clk_div_ck",		&dll_clk_div_ck),
-	CLK(NULL,	"dpll_abe_m2_ck",		&dpll_abe_m2_ck),
-	CLK(NULL,	"dpll_core_m3x2_ck",		&dpll_core_m3x2_ck),
-	CLK(NULL,	"dpll_core_m7x2_ck",		&dpll_core_m7x2_ck),
-	CLK(NULL,	"iva_hsd_byp_clk_mux_ck",	&iva_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_iva_ck",			&dpll_iva_ck),
-	CLK(NULL,	"dpll_iva_x2_ck",		&dpll_iva_x2_ck),
-	CLK(NULL,	"dpll_iva_m4x2_ck",		&dpll_iva_m4x2_ck),
-	CLK(NULL,	"dpll_iva_m5x2_ck",		&dpll_iva_m5x2_ck),
-	CLK(NULL,	"dpll_mpu_ck",			&dpll_mpu_ck),
-	CLK(NULL,	"dpll_mpu_m2_ck",		&dpll_mpu_m2_ck),
-	CLK(NULL,	"per_hs_clk_div_ck",		&per_hs_clk_div_ck),
-	CLK(NULL,	"per_hsd_byp_clk_mux_ck",	&per_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_per_ck",			&dpll_per_ck),
-	CLK(NULL,	"dpll_per_m2_ck",		&dpll_per_m2_ck),
-	CLK(NULL,	"dpll_per_x2_ck",		&dpll_per_x2_ck),
-	CLK(NULL,	"dpll_per_m2x2_ck",		&dpll_per_m2x2_ck),
-	CLK(NULL,	"dpll_per_m3x2_ck",		&dpll_per_m3x2_ck),
-	CLK(NULL,	"dpll_per_m4x2_ck",		&dpll_per_m4x2_ck),
-	CLK(NULL,	"dpll_per_m5x2_ck",		&dpll_per_m5x2_ck),
-	CLK(NULL,	"dpll_per_m6x2_ck",		&dpll_per_m6x2_ck),
-	CLK(NULL,	"dpll_per_m7x2_ck",		&dpll_per_m7x2_ck),
-	CLK(NULL,	"usb_hs_clk_div_ck",		&usb_hs_clk_div_ck),
-	CLK(NULL,	"dpll_usb_ck",			&dpll_usb_ck),
-	CLK(NULL,	"dpll_usb_clkdcoldo_ck",	&dpll_usb_clkdcoldo_ck),
-	CLK(NULL,	"dpll_usb_m2_ck",		&dpll_usb_m2_ck),
-	CLK(NULL,	"ducati_clk_mux_ck",		&ducati_clk_mux_ck),
-	CLK(NULL,	"func_12m_fclk",		&func_12m_fclk),
-	CLK(NULL,	"func_24m_clk",			&func_24m_clk),
-	CLK(NULL,	"func_24mc_fclk",		&func_24mc_fclk),
-	CLK(NULL,	"func_48m_fclk",		&func_48m_fclk),
-	CLK(NULL,	"func_48mc_fclk",		&func_48mc_fclk),
-	CLK(NULL,	"func_64m_fclk",		&func_64m_fclk),
-	CLK(NULL,	"func_96m_fclk",		&func_96m_fclk),
-	CLK(NULL,	"init_60m_fclk",		&init_60m_fclk),
-	CLK(NULL,	"l3_div_ck",			&l3_div_ck),
-	CLK(NULL,	"l4_div_ck",			&l4_div_ck),
-	CLK(NULL,	"lp_clk_div_ck",		&lp_clk_div_ck),
-	CLK(NULL,	"l4_wkup_clk_mux_ck",		&l4_wkup_clk_mux_ck),
-	CLK("smp_twd",	NULL,				&mpu_periphclk),
-	CLK(NULL,	"ocp_abe_iclk",			&ocp_abe_iclk),
-	CLK(NULL,	"per_abe_24m_fclk",		&per_abe_24m_fclk),
-	CLK(NULL,	"per_abe_nc_fclk",		&per_abe_nc_fclk),
-	CLK(NULL,	"syc_clk_div_ck",		&syc_clk_div_ck),
-	CLK(NULL,	"aes1_fck",			&aes1_fck),
-	CLK(NULL,	"aes2_fck",			&aes2_fck),
-	CLK(NULL,	"dmic_sync_mux_ck",		&dmic_sync_mux_ck),
-	CLK(NULL,	"func_dmic_abe_gfclk",		&func_dmic_abe_gfclk),
-	CLK(NULL,	"dss_sys_clk",			&dss_sys_clk),
-	CLK(NULL,	"dss_tv_clk",			&dss_tv_clk),
-	CLK(NULL,	"dss_dss_clk",			&dss_dss_clk),
-	CLK(NULL,	"dss_48mhz_clk",		&dss_48mhz_clk),
-	CLK(NULL,	"dss_fck",			&dss_fck),
-	CLK("omapdss_dss",	"ick",			&dss_fck),
-	CLK(NULL,	"fdif_fck",			&fdif_fck),
-	CLK(NULL,	"gpio1_dbclk",			&gpio1_dbclk),
-	CLK(NULL,	"gpio2_dbclk",			&gpio2_dbclk),
-	CLK(NULL,	"gpio3_dbclk",			&gpio3_dbclk),
-	CLK(NULL,	"gpio4_dbclk",			&gpio4_dbclk),
-	CLK(NULL,	"gpio5_dbclk",			&gpio5_dbclk),
-	CLK(NULL,	"gpio6_dbclk",			&gpio6_dbclk),
-	CLK(NULL,	"sgx_clk_mux",			&sgx_clk_mux),
-	CLK(NULL,	"hsi_fck",			&hsi_fck),
-	CLK(NULL,	"iss_ctrlclk",			&iss_ctrlclk),
-	CLK(NULL,	"mcasp_sync_mux_ck",		&mcasp_sync_mux_ck),
-	CLK(NULL,	"func_mcasp_abe_gfclk",		&func_mcasp_abe_gfclk),
-	CLK(NULL,	"mcbsp1_sync_mux_ck",		&mcbsp1_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp1_gfclk",		&func_mcbsp1_gfclk),
-	CLK(NULL,	"mcbsp2_sync_mux_ck",		&mcbsp2_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp2_gfclk",		&func_mcbsp2_gfclk),
-	CLK(NULL,	"mcbsp3_sync_mux_ck",		&mcbsp3_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp3_gfclk",		&func_mcbsp3_gfclk),
-	CLK(NULL,	"mcbsp4_sync_mux_ck",		&mcbsp4_sync_mux_ck),
-	CLK(NULL,	"per_mcbsp4_gfclk",		&per_mcbsp4_gfclk),
-	CLK(NULL,	"hsmmc1_fclk",			&hsmmc1_fclk),
-	CLK(NULL,	"hsmmc2_fclk",			&hsmmc2_fclk),
-	CLK(NULL,	"ocp2scp_usb_phy_phy_48m",	&ocp2scp_usb_phy_phy_48m),
-	CLK(NULL,	"sha2md5_fck",			&sha2md5_fck),
-	CLK(NULL,	"slimbus1_fclk_1",		&slimbus1_fclk_1),
-	CLK(NULL,	"slimbus1_fclk_0",		&slimbus1_fclk_0),
-	CLK(NULL,	"slimbus1_fclk_2",		&slimbus1_fclk_2),
-	CLK(NULL,	"slimbus1_slimbus_clk",		&slimbus1_slimbus_clk),
-	CLK(NULL,	"slimbus2_fclk_1",		&slimbus2_fclk_1),
-	CLK(NULL,	"slimbus2_fclk_0",		&slimbus2_fclk_0),
-	CLK(NULL,	"slimbus2_slimbus_clk",		&slimbus2_slimbus_clk),
-	CLK(NULL,	"smartreflex_core_fck",		&smartreflex_core_fck),
-	CLK(NULL,	"smartreflex_iva_fck",		&smartreflex_iva_fck),
-	CLK(NULL,	"smartreflex_mpu_fck",		&smartreflex_mpu_fck),
-	CLK(NULL,	"dmt1_clk_mux",			&dmt1_clk_mux),
-	CLK(NULL,	"cm2_dm10_mux",			&cm2_dm10_mux),
-	CLK(NULL,	"cm2_dm11_mux",			&cm2_dm11_mux),
-	CLK(NULL,	"cm2_dm2_mux",			&cm2_dm2_mux),
-	CLK(NULL,	"cm2_dm3_mux",			&cm2_dm3_mux),
-	CLK(NULL,	"cm2_dm4_mux",			&cm2_dm4_mux),
-	CLK(NULL,	"timer5_sync_mux",		&timer5_sync_mux),
-	CLK(NULL,	"timer6_sync_mux",		&timer6_sync_mux),
-	CLK(NULL,	"timer7_sync_mux",		&timer7_sync_mux),
-	CLK(NULL,	"timer8_sync_mux",		&timer8_sync_mux),
-	CLK(NULL,	"cm2_dm9_mux",			&cm2_dm9_mux),
-	CLK(NULL,	"usb_host_fs_fck",		&usb_host_fs_fck),
-	CLK("usbhs_omap",	"fs_fck",		&usb_host_fs_fck),
-	CLK(NULL,	"utmi_p1_gfclk",		&utmi_p1_gfclk),
-	CLK(NULL,	"usb_host_hs_utmi_p1_clk",	&usb_host_hs_utmi_p1_clk),
-	CLK(NULL,	"utmi_p2_gfclk",		&utmi_p2_gfclk),
-	CLK(NULL,	"usb_host_hs_utmi_p2_clk",	&usb_host_hs_utmi_p2_clk),
-	CLK(NULL,	"usb_host_hs_utmi_p3_clk",	&usb_host_hs_utmi_p3_clk),
-	CLK(NULL,	"usb_host_hs_hsic480m_p1_clk",	&usb_host_hs_hsic480m_p1_clk),
-	CLK(NULL,	"usb_host_hs_hsic60m_p1_clk",	&usb_host_hs_hsic60m_p1_clk),
-	CLK(NULL,	"usb_host_hs_hsic60m_p2_clk",	&usb_host_hs_hsic60m_p2_clk),
-	CLK(NULL,	"usb_host_hs_hsic480m_p2_clk",	&usb_host_hs_hsic480m_p2_clk),
-	CLK(NULL,	"usb_host_hs_func48mclk",	&usb_host_hs_func48mclk),
-	CLK(NULL,	"usb_host_hs_fck",		&usb_host_hs_fck),
-	CLK("usbhs_omap",	"hs_fck",		&usb_host_hs_fck),
-	CLK(NULL,	"otg_60m_gfclk",		&otg_60m_gfclk),
-	CLK(NULL,	"usb_otg_hs_xclk",		&usb_otg_hs_xclk),
-	CLK(NULL,	"usb_otg_hs_ick",		&usb_otg_hs_ick),
-	CLK("musb-omap2430",	"ick",			&usb_otg_hs_ick),
-	CLK(NULL,	"usb_phy_cm_clk32k",		&usb_phy_cm_clk32k),
-	CLK(NULL,	"usb_tll_hs_usb_ch2_clk",	&usb_tll_hs_usb_ch2_clk),
-	CLK(NULL,	"usb_tll_hs_usb_ch0_clk",	&usb_tll_hs_usb_ch0_clk),
-	CLK(NULL,	"usb_tll_hs_usb_ch1_clk",	&usb_tll_hs_usb_ch1_clk),
-	CLK(NULL,	"usb_tll_hs_ick",		&usb_tll_hs_ick),
-	CLK("usbhs_omap",	"usbtll_ick",		&usb_tll_hs_ick),
-	CLK("usbhs_tll",	"usbtll_ick",		&usb_tll_hs_ick),
-	CLK(NULL,	"usim_ck",			&usim_ck),
-	CLK(NULL,	"usim_fclk",			&usim_fclk),
-	CLK(NULL,	"pmd_stm_clock_mux_ck",		&pmd_stm_clock_mux_ck),
-	CLK(NULL,	"pmd_trace_clk_mux_ck",		&pmd_trace_clk_mux_ck),
-	CLK(NULL,	"stm_clk_div_ck",		&stm_clk_div_ck),
-	CLK(NULL,	"trace_clk_div_ck",		&trace_clk_div_ck),
-	CLK(NULL,	"auxclk0_src_ck",		&auxclk0_src_ck),
-	CLK(NULL,	"auxclk0_ck",			&auxclk0_ck),
-	CLK(NULL,	"auxclkreq0_ck",		&auxclkreq0_ck),
-	CLK(NULL,	"auxclk1_src_ck",		&auxclk1_src_ck),
-	CLK(NULL,	"auxclk1_ck",			&auxclk1_ck),
-	CLK(NULL,	"auxclkreq1_ck",		&auxclkreq1_ck),
-	CLK(NULL,	"auxclk2_src_ck",		&auxclk2_src_ck),
-	CLK(NULL,	"auxclk2_ck",			&auxclk2_ck),
-	CLK(NULL,	"auxclkreq2_ck",		&auxclkreq2_ck),
-	CLK(NULL,	"auxclk3_src_ck",		&auxclk3_src_ck),
-	CLK(NULL,	"auxclk3_ck",			&auxclk3_ck),
-	CLK(NULL,	"auxclkreq3_ck",		&auxclkreq3_ck),
-	CLK(NULL,	"auxclk4_src_ck",		&auxclk4_src_ck),
-	CLK(NULL,	"auxclk4_ck",			&auxclk4_ck),
-	CLK(NULL,	"auxclkreq4_ck",		&auxclkreq4_ck),
-	CLK(NULL,	"auxclk5_src_ck",		&auxclk5_src_ck),
-	CLK(NULL,	"auxclk5_ck",			&auxclk5_ck),
-	CLK(NULL,	"auxclkreq5_ck",		&auxclkreq5_ck),
-	CLK("omap-gpmc",	"fck",			&dummy_ck),
-	CLK("omap_i2c.1",	"ick",			&dummy_ck),
-	CLK("omap_i2c.2",	"ick",			&dummy_ck),
-	CLK("omap_i2c.3",	"ick",			&dummy_ck),
-	CLK("omap_i2c.4",	"ick",			&dummy_ck),
-	CLK(NULL,	"mailboxes_ick",		&dummy_ck),
-	CLK("omap_hsmmc.0",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.1",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.2",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.3",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.4",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.1",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.2",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.3",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.4",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.1",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.2",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.3",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.4",	"ick",			&dummy_ck),
-	CLK(NULL,	"uart1_ick",			&dummy_ck),
-	CLK(NULL,	"uart2_ick",			&dummy_ck),
-	CLK(NULL,	"uart3_ick",			&dummy_ck),
-	CLK(NULL,	"uart4_ick",			&dummy_ck),
-	CLK("usbhs_omap",	"usbhost_ick",		&dummy_ck),
-	CLK("usbhs_omap",	"usbtll_fck",		&dummy_ck),
-	CLK("usbhs_tll",	"usbtll_fck",		&dummy_ck),
-	CLK("omap_wdt",	"ick",				&dummy_ck),
-	CLK(NULL,	"timer_32k_ck",	&sys_32k_ck),
-	/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
-	CLK("omap_timer.1",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.2",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.3",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.4",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.9",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.10",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.11",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.5",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.6",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.7",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.8",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4a318000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48032000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48034000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48036000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("4803e000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48086000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48088000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("40138000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013a000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013c000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013e000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK(NULL,	"cpufreq_ck",	&dpll_mpu_ck),
-};
-
-int __init omap4xxx_clk_init(void)
-{
-	int rc;
-
-	if (cpu_is_omap443x()) {
-		cpu_mask = RATE_IN_4430;
-		omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
-	} else if (cpu_is_omap446x() || cpu_is_omap447x()) {
-		cpu_mask = RATE_IN_4460 | RATE_IN_4430;
-		omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
-		if (cpu_is_omap447x())
-			pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
-	} else {
-		return 0;
-	}
-
-	omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
-
-	omap2_clk_disable_autoidle_all();
-
-	/*
-	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
-	 * state when turning the ABE clock domain. Workaround this by
-	 * locking the ABE DPLL on boot.
-	 * Lock the ABE DPLL in any case to avoid issues with audio.
-	 */
-	rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
-	if (!rc)
-		rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
-	if (rc)
-		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
-
-	/*
-	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
-	 * domain can transition to retention state when not in use.
-	 */
-	rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
-	if (rc)
-		pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
-	return 0;
-}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 57bfbaa..c2b6a44 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,3 +1,4 @@
 ifneq ($(CONFIG_OF),)
-obj-y					+= clk.o dpll.o autoidle.o gate.o
+obj-y					+= clk.o dpll.o autoidle.o gate.o \
+					   clk-44xx.o
 endif
-- 
1.7.9.5

[PATCHv5 09/31] ARM: dts: omap5 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi           |    7 +
 arch/arm/boot/dts/omap54xx-clocks.dtsi | 1410 ++++++++++++++++++++++++++++++++
 2 files changed, 1417 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap54xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index e643620..1de39c2 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -713,4 +713,11 @@
 			compatible = "ti,omap5430-bandgap";
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap54xx-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 0000000..4cb48be
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1410 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+pad_clks_src_ck: pad_clks_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_clks_src_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004108 0x4>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_src_clk>;
+	bit-shift = <10>;
+	reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+sys_clkin: sys_clkin at 4ae06110 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	reg = <0x4ae06110 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 4ae06108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	reg = <0x4ae06108 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux at 4ae0610c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	reg = <0x4ae0610c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck at 4a0041e0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-m4xen-clock";
+	clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+	reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+	ti,clk-ref = <&abe_dpll_clk_mux>;
+	ti,clk-bypass = <&abe_dpll_bypass_clk_mux>;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_abe_ck>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+abe_clk: abe_clk at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4a004108 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+abe_iclk: abe_iclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&abe_clk>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0041f4 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck at 4a004120 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-core-clock";
+	clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_core_ck>;
+};
+
+dpll_core_h21x2_ck: dpll_core_h21x2_ck at 4a004150 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004150 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+c2c_fclk: c2c_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h21x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+c2c_iclk: c2c_iclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&c2c_fclk>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_core_h11x2_ck: dpll_core_h11x2_ck at 4a004138 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004138 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck at 4a00413c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00413c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck at 4a004140 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004140 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck at 4a004144 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004144 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck at 4a004154 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004154 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck at 4a004158 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck at 4a00415c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00415c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck at 4a004130 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004130 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck at 4a004134 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004134 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck at 4a0041a0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+	reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&iva_dpll_hs_clk_div>;
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_iva_ck>;
+};
+
+dpll_iva_h11x2_ck: dpll_iva_h11x2_ck at 4a0041b8 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041b8 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_iva_h12x2_ck: dpll_iva_h12x2_ck at 4a0041bc {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041bc 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 4a004160 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+	reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&mpu_dpll_hs_clk_div>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a004170 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004170 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck at 4a008140 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+	reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&per_dpll_hs_clk_div>;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_per_ck>;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck at 4a008158 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck at 4a00815c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00815c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck at 4a008164 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008164 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck at 4a008154 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008154 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_unipro1_ck: dpll_unipro1_ck at 4a008200 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>;
+	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&sys_clkin>;
+};
+
+dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_unipro1_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_unipro1_m2_ck: dpll_unipro1_m2_ck at 4a008210 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_unipro1_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008210 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_unipro2_ck: dpll_unipro2_ck at 4a0081c0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>;
+	reg = <0x4a0081c0 0x4>, <0x4a0081c4 0x4>, <0x4a0081c8 0x4>, <0x4a0081cc 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&sys_clkin>;
+};
+
+dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_unipro2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_unipro2_m2_ck: dpll_unipro2_m2_ck at 4a0081d0 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_unipro2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0081d0 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck at 4a008180 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-j-type-clock";
+	clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+	ti,clk-bypass = <&usb_dpll_hs_clk_div>;
+	reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clkdm-name = "l3init_clkdm";
+	ti,dpll-j-type;
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_usb_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008190 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dss_syc_gfclk_div: dss_syc_gfclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+func_128m_clk: func_128m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_h11x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+l3_iclk_div: l3_iclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpu_l3_iclk: gpu_l3_iclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_iclk_div>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk at 4a008104 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4a008104 0x4>;
+	table = < 1 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux at 4ae06108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+	reg = <0x4ae06108 0x4>;
+	bit-mask = <0x1>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&wkupaon_iclk_mux>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_iclk_div>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dss_32khz_clk: dss_32khz_clk at 4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <11>;
+	reg = <0x4a009420 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk at 4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009420 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk at 4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_h12x2_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009420 0x4>;
+};
+
+dss_sys_clk: dss_sys_clk at 4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dss_syc_gfclk_div>;
+	bit-shift = <10>;
+	reg = <0x4a009420 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk at 4ae07938 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae07938 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 4a009060 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009060 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 4a009068 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009068 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 4a009070 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009070 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 4a009078 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009078 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk at 4a009080 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009080 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk at 4a009110 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009110 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk at 4a009118 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009118 0x4>;
+};
+
+iss_ctrlclk: iss_ctrlclk at 4a009320 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_96m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009320 0x4>;
+};
+
+lli_txphy_clk: lli_txphy_clk at 4a008f20 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_unipro1_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a008f20 0x4>;
+};
+
+lli_txphy_ls_clk: lli_txphy_ls_clk at 4a008f20 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_unipro1_m2_ck>;
+	bit-shift = <9>;
+	reg = <0x4a008f20 0x4>;
+};
+
+mmc1_32khz_clk: mmc1_32khz_clk at 4a009628 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009628 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk at 4a009688 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin>;
+	bit-shift = <8>;
+	reg = <0x4a009688 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_clk>;
+	bit-shift = <11>;
+	reg = <0x4a004560 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <13>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <14>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <7>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <11>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <12>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <6>;
+	reg = <0x4a009658 0x4>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009658 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p1_gfclk>;
+	bit-shift = <8>;
+	reg = <0x4a009658 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
+	bit-shift = <25>;
+	reg = <0x4a009658 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p2_gfclk>;
+	bit-shift = <9>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_otg_ss_refclk960m: usb_otg_ss_refclk960m at 4a0096f0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a0096f0 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k at 4a008640 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 4a009668 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 4a009668 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 4a009668 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009668 0x4>;
+};
+
+aess_fclk: aess_fclk at 4a004528 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&abe_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004528 0x4>;
+	bit-mask = <0x1>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck at 4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x3>;
+};
+
+dmic_gfclk: dmic_gfclk at 4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x3>;
+};
+
+fdif_fclk: fdif_fclk at 4a009328 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_h11x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux at 4a009520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009520 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux at 4a009520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+	bit-shift = <25>;
+	reg = <0x4a009520 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsi_fclk: hsi_fclk at 4a009638 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009638 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck at 4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp_gfclk: mcasp_gfclk at 4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck at 4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp1_gfclk: mcbsp1_gfclk at 4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp2_gfclk: mcbsp2_gfclk at 4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp3_gfclk: mcbsp3_gfclk at 4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x3>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux at 4a009628 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009628 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc1_fclk: mmc1_fclk at 4a009628 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc1_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009628 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux at 4a009630 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009630 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc2_fclk: mmc2_fclk at 4a009630 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc2_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009630 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux at 4a009028 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009028 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux at 4a009030 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009030 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux at 4ae07940 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4ae07940 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux at 4a009038 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009038 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux at 4a009040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009040 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux at 4a009048 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009048 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux at 4a004568 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004568 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux at 4a004570 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004570 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux at 4a004578 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004578 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux at 4a004580 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004580 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux at 4a009050 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009050 0x4>;
+	bit-mask = <0x1>;
+};
+
+auxclk0_src_mux_ck: auxclk0_src_mux_ck at 4ae0a310 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a310 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck at 4ae0a310 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk0_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a310 0x4>;
+};
+
+auxclk0_ck: auxclk0_ck at 4ae0a310 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk0_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a310 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk1_src_mux_ck: auxclk1_src_mux_ck at 4ae0a314 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a314 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck at 4ae0a314 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk1_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a314 0x4>;
+};
+
+auxclk1_ck: auxclk1_ck at 4ae0a314 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk1_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a314 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk2_src_mux_ck: auxclk2_src_mux_ck at 4ae0a318 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a318 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck at 4ae0a318 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk2_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a318 0x4>;
+};
+
+auxclk2_ck: auxclk2_ck at 4ae0a318 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk2_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a318 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk3_src_mux_ck: auxclk3_src_mux_ck at 4ae0a31c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a31c 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck at 4ae0a31c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk3_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a31c 0x4>;
+};
+
+auxclk3_ck: auxclk3_ck at 4ae0a31c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk3_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a31c 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk4_src_mux_ck: auxclk4_src_mux_ck at 4ae0a320 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a320 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck at 4ae0a320 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk4_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a320 0x4>;
+};
+
+auxclk4_ck: auxclk4_ck at 4ae0a320 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk4_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a320 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck at 4ae0a210 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a210 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck at 4ae0a214 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a214 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck at 4ae0a218 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a218 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck at 4ae0a21c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a21c 0x4>;
+	bit-mask = <0x7>;
+};
-- 
1.7.9.5

[PATCHv5 10/31] CLK: TI: add omap5 clock init file

[Tero Kristo]

clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/io.c  |    1 +
 drivers/clk/ti/Makefile   |    2 +-
 drivers/clk/ti/clk-54xx.c |   59 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h    |    2 ++
 4 files changed, 63 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clk-54xx.c

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4a3f06f..e8d5d75 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -650,6 +650,7 @@ void __init omap5_init_early(void)
 	omap54xx_clockdomains_init();
 	omap54xx_hwmod_init();
 	omap_hwmod_init_postsetup();
+	omap_clk_init = omap5xxx_clk_init;
 }
 #endif
 
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index c2b6a44..e54f6f7 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
-					   clk-44xx.o
+					   clk-44xx.o clk-54xx.o
 endif
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
new file mode 100644
index 0000000..52133e7
--- /dev/null
+++ b/drivers/clk/ti/clk-54xx.c
@@ -0,0 +1,59 @@
+/*
+ * OMAP5 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk/ti.h>
+
+#define OMAP5_DPLL_ABE_DEFFREQ				98304000
+
+static struct omap_dt_clk omap54xx_clks[] = {
+	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+	DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"),
+	{ NULL },
+};
+
+int __init omap5xxx_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+
+	of_clk_init(NULL);
+
+	omap_dt_clocks_register(omap54xx_clks);
+
+	omap2_clk_disable_autoidle_all();
+
+	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
+	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+	if (!rc)
+		rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index c4f0c1b..59df9f6 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -194,6 +194,8 @@ static inline void of_omap_clk_allow_autoidle_all(void) { }
 static inline void of_omap_clk_deny_autoidle_all(void) { }
 #endif
 
+int omap5xxx_clk_init(void);
+
 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 extern const struct clk_hw_omap_ops clkhwops_wait;
-- 
1.7.9.5

[PATCHv5 11/31] CLK: TI: omap5: Initialize USB_DPLL at boot

[Tero Kristo]

From: Roger Quadros <rogerq@ti.com>

USB_DPLL must be initialized and locked at boot so that
USB modules can work.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/ti/clk-54xx.c |   18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index 52133e7..d539080 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -19,6 +19,12 @@
 
 #define OMAP5_DPLL_ABE_DEFFREQ				98304000
 
+/*
+ * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
+ * states it must be at 960MHz
+ */
+#define OMAP5_DPLL_USB_DEFFREQ				960000000
+
 static struct omap_dt_clk omap54xx_clks[] = {
 	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
 	DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
@@ -38,7 +44,7 @@ static struct omap_dt_clk omap54xx_clks[] = {
 int __init omap5xxx_clk_init(void)
 {
 	int rc;
-	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
 
 	of_clk_init(NULL);
 
@@ -55,5 +61,15 @@ int __init omap5xxx_clk_init(void)
 	if (rc)
 		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
+	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+	rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+	usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
+	rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
+	if (rc)
+		pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
+
 	return 0;
 }
-- 
1.7.9.5

[PATCHv5 12/31] ARM: dts: dra7 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).

TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 2073 ++++++++++++++++++++++++++++++++++
 1 file changed, 2073 insertions(+)
 create mode 100644 arch/arm/boot/dts/dra7xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 0000000..e4853f8
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,2073 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+atl_clkin0_ck: atl_clkin0_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+atl_clkin1_ck: atl_clkin1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+atl_clkin2_ck: atl_clkin2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+atlclkin3_ck: atlclkin3_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+hdmi_clkin_ck: hdmi_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+mlb_clkin_ck: mlb_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+mlbp_clkin_ck: mlbp_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <100000000>;
+};
+
+ref_clkin0_ck: ref_clkin0_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+ref_clkin1_ck: ref_clkin1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+ref_clkin2_ck: ref_clkin2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+ref_clkin3_ck: ref_clkin3_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+rmii_clk_ck: rmii_clk_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+sdvenc_clkin_ck: sdvenc_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+sys_32k_ck: sys_32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_20000000_ck: virt_20000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <20000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+sys_clkin1: sys_clkin1 at 4ae06110 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	reg = <0x4ae06110 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+sys_clkin2: sys_clkin2 {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <22579200>;
+};
+
+usb_otg_clkin_ck: usb_otg_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video1_clkin_ck: video1_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video1_m2_clkin_ck: video1_m2_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video2_clkin_ck: video2_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video2_m2_clkin_ck: video2_m2_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux at 4ae06118 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae06118 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 4ae06114 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+	reg = <0x4ae06114 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux at 4ae0610c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+	reg = <0x4ae0610c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck at 4a0051e0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-m4xen-clock";
+	clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+	reg = <0x4a0051e0 0x4>, <0x4a0051e4 0x4>, <0x4a0051e8 0x4>, <0x4a0051ec 0x4>;
+	ti,clk-ref = <&abe_dpll_clk_mux>;
+	ti,clk-bypass = <&abe_dpll_bypass_clk_mux>;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_abe_ck>;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0051f0 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk at 4ae0611c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4ae0611c 0x4>;
+	table = < 8 0 >, < 16 1 >;
+	bit-mask = <0x1>;
+};
+
+abe_clk: abe_clk at 4a005108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4a005108 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+aess_fclk: aess_fclk at 4ae06178 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&abe_clk>;
+	reg = <0x4ae06178 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_giclk_div: abe_giclk_div at 4ae06174 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&aess_fclk>;
+	reg = <0x4ae06174 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div at 4ae061d8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4ae061d8 0x4>;
+	table = < 16 0 >, < 32 1 >;
+	bit-mask = <0x1>;
+};
+
+abe_sys_clk_div: abe_sys_clk_div at 4ae06120 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae06120 0x4>;
+	bit-mask = <0x1>;
+};
+
+adc_gfclk_mux: adc_gfclk_mux at 4ae061dc {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+	reg = <0x4ae061dc 0x4>;
+	bit-mask = <0x7>;
+};
+
+dpll_pcie_ref_ck: dpll_pcie_ref_ck at 4a008200 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&sys_clkin1>;
+};
+
+dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck at 4a008210 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_pcie_ref_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008210 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+apll_pcie_ck: apll_pcie_ck at 4a008200 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_pcie_ref_ck>;
+	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+	ti,clk-ref = <&dpll_pcie_ref_ck>;
+	ti,clk-bypass = <&dpll_pcie_ref_ck>;
+};
+
+apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&apll_pcie_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&apll_pcie_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+apll_pcie_m2_ck: apll_pcie_m2_ck at 4a008224 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&apll_pcie_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008224 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+sys_clk1_dclk_div: sys_clk1_dclk_div at 4ae061c8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae061c8 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+sys_clk2_dclk_div: sys_clk2_dclk_div at 4ae061cc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin2>;
+	reg = <0x4ae061cc 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck at 4a0051f0 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+per_abe_x1_dclk_div: per_abe_x1_dclk_div at 4ae061bc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	reg = <0x4ae061bc 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0051f4 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051f4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck at 4a005120 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-core-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a005120 0x4>, <0x4a005124 0x4>, <0x4a005128 0x4>, <0x4a00512c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_core_ck>;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck at 4a00513c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00513c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 4a005160 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+	reg = <0x4a005160 0x4>, <0x4a005164 0x4>, <0x4a005168 0x4>, <0x4a00516c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&mpu_dpll_hs_clk_div>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a005170 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005170 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+mpu_dclk_div: mpu_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_mpu_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_dsp_ck: dpll_dsp_ck at 4a005234 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+	reg = <0x4a005234 0x4>, <0x4a005238 0x4>, <0x4a00523c 0x4>, <0x4a005240 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dsp_dpll_hs_clk_div>;
+};
+
+dpll_dsp_m2_ck: dpll_dsp_m2_ck at 4a005244 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_dsp_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005244 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dsp_gclk_div: dsp_gclk_div at 4ae0618c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_dsp_m2_ck>;
+	reg = <0x4ae0618c 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck at 4a0051a0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+	reg = <0x4a0051a0 0x4>, <0x4a0051a4 0x4>, <0x4a0051a8 0x4>, <0x4a0051ac 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&iva_dpll_hs_clk_div>;
+};
+
+dpll_iva_m2_ck: dpll_iva_m2_ck at 4a0051b0 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_iva_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051b0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+iva_dclk: iva_dclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_iva_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_gpu_ck: dpll_gpu_ck at 4a0052d8 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a0052d8 0x4>, <0x4a0052dc 0x4>, <0x4a0052e0 0x4>, <0x4a0052e4 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+};
+
+dpll_gpu_m2_ck: dpll_gpu_m2_ck at 4a0052e8 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_gpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052e8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+gpu_dclk: gpu_dclk at 4ae061a0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gpu_m2_ck>;
+	reg = <0x4ae061a0 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck at 4a005130 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005130 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_ddr_ck: dpll_ddr_ck at 4a005210 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a005210 0x4>, <0x4a005214 0x4>, <0x4a005218 0x4>, <0x4a00521c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck at 4a005220 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_ddr_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005220 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+emif_phy_dclk_div: emif_phy_dclk_div at 4ae06190 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_ddr_m2_ck>;
+	reg = <0x4ae06190 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_gmac_ck: dpll_gmac_ck at 4a0052a8 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a0052a8 0x4>, <0x4a0052ac 0x4>, <0x4a0052b0 0x4>, <0x4a0052b4 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+};
+
+dpll_gmac_m2_ck: dpll_gmac_m2_ck at 4a0052b8 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_gmac_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052b8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+gmac_250m_dclk_div: gmac_250m_dclk_div at 4ae0619c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_m2_ck>;
+	reg = <0x4ae0619c 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+video2_dclk_div: video2_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video2_m2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video1_dclk_div: video1_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video1_m2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdmi_dclk_div: hdmi_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&hdmi_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck at 4a008140 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+	reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&per_dpll_hs_clk_div>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck at 4a008180 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-j-type-clock";
+	clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+	ti,clk-bypass = <&usb_dpll_hs_clk_div>;
+	reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clkdm-name = "coreaon_clkdm";
+	ti,dpll-j-type;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008190 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+l3init_480m_dclk_div: l3init_480m_dclk_div at 4ae061ac {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4ae061ac 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+usb_otg_dclk_div: usb_otg_dclk_div at 4ae06184 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&usb_otg_clkin_ck>;
+	reg = <0x4ae06184 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+sata_dclk_div: sata_dclk_div at 4ae061c0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae061c0 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck at 4a008210 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_pcie_ref_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008210 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+pcie2_dclk_div: pcie2_dclk_div at 4ae061b8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_pcie_ref_m2_ck>;
+	reg = <0x4ae061b8 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+pcie_dclk_div: pcie_dclk_div at 4ae061b4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&apll_pcie_m2_ck>;
+	reg = <0x4ae061b4 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+emu_dclk_div: emu_dclk_div at 4ae06194 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae06194 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+secure_32k_dclk_div: secure_32k_dclk_div at 4ae061c4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&secure_32k_clk_src_ck>;
+	reg = <0x4ae061c4 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_eve_ck: dpll_eve_ck at 4a005284 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+	reg = <0x4a005284 0x4>, <0x4a005288 0x4>, <0x4a00528c 0x4>, <0x4a005290 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&eve_dpll_hs_clk_div>;
+};
+
+dpll_eve_m2_ck: dpll_eve_m2_ck at 4a005294 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_eve_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005294 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+eve_dclk_div: eve_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_eve_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+clkoutmux0_clk_mux: clkoutmux0_clk_mux at 4ae06158 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+	reg = <0x4ae06158 0x4>;
+	bit-mask = <0x1f>;
+};
+
+clkoutmux1_clk_mux: clkoutmux1_clk_mux at 4ae0615c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+	reg = <0x4ae0615c 0x4>;
+	bit-mask = <0x1f>;
+};
+
+clkoutmux2_clk_mux: clkoutmux2_clk_mux at 4ae06160 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+	reg = <0x4ae06160 0x4>;
+	bit-mask = <0x1f>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin1>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck at 4a005140 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005140 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck at 4a005144 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005144 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck at 4a005154 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005154 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck at 4a005158 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck at 4a00515c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00515c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_ddr_ck>;
+};
+
+dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck at 4a005228 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_ddr_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005228 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_dsp_ck>;
+};
+
+dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck at 4a005248 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_dsp_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005248 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_gmac_ck>;
+};
+
+dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck at 4a0052c0 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052c0 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck at 4a0052c4 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052c4 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck at 4a0052c8 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052c8 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck at 4a0052bc {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052bc 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_per_ck>;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck at 4a008158 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck at 4a00815c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00815c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h13x2_ck: dpll_per_h13x2_ck at 4a008160 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008160 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck at 4a008164 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008164 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_usb_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+eve_clk: eve_clk at 4ae06180 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+	reg = <0x4ae06180 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_128m_clk: func_128m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_h11x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+gmii_m_clk_div: gmii_m_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_gmac_h11x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+hdmi_clk2_div: hdmi_clk2_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&hdmi_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdmi_div_clk: hdmi_div_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&hdmi_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdmi_dpll_clk_mux: hdmi_dpll_clk_mux at 4ae061a4 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae061a4 0x4>;
+	bit-mask = <0x7>;
+};
+
+l3_iclk_div: l3_iclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk at 4a008104 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4a008104 0x4>;
+	table = < 1 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_iclk_div>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mlb_clk: mlb_clk at 4ae06134 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mlb_clkin_ck>;
+	reg = <0x4ae06134 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+mlbp_clk: mlbp_clk at 4ae06130 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mlbp_clkin_ck>;
+	reg = <0x4ae06130 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div at 4ae06138 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	reg = <0x4ae06138 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+timer_sys_clk_div: timer_sys_clk_div at 4ae06144 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae06144 0x4>;
+	bit-mask = <0x1>;
+};
+
+video1_clk2_div: video1_clk2_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video1_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video1_div_clk: video1_div_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video1_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video1_dpll_clk_mux: video1_dpll_clk_mux at 4ae061d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae061d0 0x4>;
+	bit-mask = <0x7>;
+};
+
+video2_clk2_div: video2_clk2_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video2_div_clk: video2_div_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video2_dpll_clk_mux: video2_dpll_clk_mux at 4ae061d4 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae061d4 0x4>;
+	bit-mask = <0x7>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux at 4ae06108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+	reg = <0x4ae06108 0x4>;
+	bit-mask = <0x1>;
+};
+
+dss_32khz_clk: dss_32khz_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <11>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_h12x2_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_hdmi_clk: dss_hdmi_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&hdmi_dpll_clk_mux>;
+	bit-shift = <10>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_video1_clk: dss_video1_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&video1_dpll_clk_mux>;
+	bit-shift = <12>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_video2_clk: dss_video2_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&video2_dpll_clk_mux>;
+	bit-shift = <13>;
+	reg = <0x4a009120 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk at 4ae07838 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae07838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 4a009760 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009760 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 4a009768 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009768 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 4a009770 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009770 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 4a009778 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009778 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk at 4a009780 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009780 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk at 4a009810 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009810 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk at 4a009818 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009818 0x4>;
+};
+
+mmc1_clk32k: mmc1_clk32k at 4a009328 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009328 0x4>;
+};
+
+mmc2_clk32k: mmc2_clk32k at 4a009330 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009330 0x4>;
+};
+
+mmc3_clk32k: mmc3_clk32k at 4a009820 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009820 0x4>;
+};
+
+mmc4_clk32k: mmc4_clk32k at 4a009828 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009828 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk at 4a009388 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin1>;
+	bit-shift = <8>;
+	reg = <0x4a009388 0x4>;
+};
+
+usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m at 4a0093f0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a0093f0 0x4>;
+};
+
+usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m at 4a009340 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a009340 0x4>;
+};
+
+usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k at 4a008640 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008640 0x4>;
+};
+
+usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k at 4a008688 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008688 0x4>;
+};
+
+usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k at 4a008698 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008698 0x4>;
+};
+
+atl_dpll_clk_mux: atl_dpll_clk_mux at 4a008c00 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+	bit-shift = <24>;
+	reg = <0x4a008c00 0x4>;
+	bit-mask = <0x3>;
+};
+
+atl_gfclk_mux: atl_gfclk_mux at 4a008c00 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+	bit-shift = <26>;
+	reg = <0x4a008c00 0x4>;
+	bit-mask = <0x3>;
+};
+
+dcan1_sys_clk_mux: dcan1_sys_clk_mux at 4ae07888 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	bit-shift = <24>;
+	reg = <0x4ae07888 0x4>;
+	bit-mask = <0x1>;
+};
+
+gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div at 4a0093d0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_m2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0093d0 0x4>;
+	table = < 2 0 >;
+	bit-mask = <0x1>;
+};
+
+gmac_rft_clk_mux: gmac_rft_clk_mux at 4a0093d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+	bit-shift = <25>;
+	reg = <0x4a0093d0 0x4>;
+	bit-mask = <0x7>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux at 4a009220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009220 0x4>;
+	bit-mask = <0x3>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux at 4a009220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+	bit-shift = <26>;
+	reg = <0x4a009220 0x4>;
+	bit-mask = <0x3>;
+};
+
+ipu1_gfclk_mux: ipu1_gfclk_mux at 4a005520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a005520 0x4>;
+	bit-mask = <0x1>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div at 4a008e50 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&wkupaon_iclk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a008e50 0x4>;
+	table = < 8 0 >, < 16 1 >, < 32 2 >;
+	bit-mask = <0x3>;
+};
+
+mcasp1_ahclkr_mux: mcasp1_ahclkr_mux at 4a005550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <28>;
+	reg = <0x4a005550 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp1_ahclkx_mux: mcasp1_ahclkx_mux at 4a005550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a005550 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux at 4a005550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a005550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp2_ahclkr_mux: mcasp2_ahclkr_mux at 4a009860 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <28>;
+	reg = <0x4a009860 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp2_ahclkx_mux: mcasp2_ahclkx_mux at 4a009860 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <28>;
+	reg = <0x4a009860 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux at 4a009860 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009860 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp3_ahclkx_mux: mcasp3_ahclkx_mux at 4a009868 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009868 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux at 4a009868 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009868 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp4_ahclkx_mux: mcasp4_ahclkx_mux at 4a009898 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009898 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux at 4a009898 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009898 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp5_ahclkx_mux: mcasp5_ahclkx_mux at 4a009878 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009878 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux at 4a009878 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009878 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp6_ahclkx_mux: mcasp6_ahclkx_mux at 4a009904 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009904 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux at 4a009904 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009904 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp7_ahclkx_mux: mcasp7_ahclkx_mux at 4a009908 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009908 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux at 4a009908 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009908 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp8_ahclk_mux: mcasp8_ahclk_mux at 4a009890 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <22>;
+	reg = <0x4a009890 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux at 4a009890 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <24>;
+	reg = <0x4a009890 0x4>;
+	bit-mask = <0xf>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux at 4a009328 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc1_fclk_div: mmc1_fclk_div at 4a009328 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc1_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux at 4a009330 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009330 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc2_fclk_div: mmc2_fclk_div at 4a009330 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc2_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009330 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+mmc3_gfclk_mux: mmc3_gfclk_mux at 4a009820 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009820 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc3_gfclk_div: mmc3_gfclk_div at 4a009820 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc3_gfclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009820 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+mmc4_gfclk_mux: mmc4_gfclk_mux at 4a009828 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009828 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc4_gfclk_div: mmc4_gfclk_div at 4a009828 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc4_gfclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009828 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+qspi_gfclk_mux: qspi_gfclk_mux at 4a009838 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009838 0x4>;
+	bit-mask = <0x1>;
+};
+
+qspi_gfclk_div: qspi_gfclk_div at 4a009838 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&qspi_gfclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009838 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux at 4a009728 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009728 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux at 4a009730 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009730 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer13_gfclk_mux: timer13_gfclk_mux at 4a0097c8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a0097c8 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer14_gfclk_mux: timer14_gfclk_mux at 4a0097d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a0097d0 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer15_gfclk_mux: timer15_gfclk_mux at 4a0097d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a0097d8 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer16_gfclk_mux: timer16_gfclk_mux at 4a009830 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009830 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux at 4ae07840 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4ae07840 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux at 4a009738 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009738 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux at 4a009740 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009740 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux at 4a009748 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009748 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux at 4a005558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005558 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux at 4a005560 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005560 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux at 4a005568 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005568 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux at 4a005570 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005570 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux at 4a009750 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009750 0x4>;
+	bit-mask = <0xf>;
+};
+
+uart10_gfclk_mux: uart10_gfclk_mux at 4ae07880 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4ae07880 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart1_gfclk_mux: uart1_gfclk_mux at 4a009840 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009840 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart2_gfclk_mux: uart2_gfclk_mux at 4a009848 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009848 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart3_gfclk_mux: uart3_gfclk_mux at 4a009850 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009850 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart4_gfclk_mux: uart4_gfclk_mux at 4a009858 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009858 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart5_gfclk_mux: uart5_gfclk_mux at 4a009870 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009870 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart6_gfclk_mux: uart6_gfclk_mux at 4a005580 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a005580 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart7_gfclk_mux: uart7_gfclk_mux at 4a0098d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0098d0 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart8_gfclk_mux: uart8_gfclk_mux at 4a0098e0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0098e0 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart9_gfclk_mux: uart9_gfclk_mux at 4a0098e8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0098e8 0x4>;
+	bit-mask = <0x1>;
+};
+
+vip1_gclk_mux: vip1_gclk_mux at 4a009020 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009020 0x4>;
+	bit-mask = <0x1>;
+};
+
+vip2_gclk_mux: vip2_gclk_mux at 4a009028 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009028 0x4>;
+	bit-mask = <0x1>;
+};
+
+vip3_gclk_mux: vip3_gclk_mux at 4a009030 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009030 0x4>;
+	bit-mask = <0x1>;
+};
-- 
1.7.9.5

[PATCHv5 13/31] ARM: dts: clk: Add apll related clocks

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

The patch adds a mux node to choose the parent of apll_pcie_ck node.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e4853f8..b377526 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -326,13 +326,24 @@ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck at 4a008210 {
 	ti,autoidle-low;
 };
 
+/* APLL_PCIE */
+
+/* mux clock to select the reference clock */
+apll_pcie_in_clk_mux: apll_pcie_in_clk_mux at 4ae06118 {
+	compatible = "mux-clock";
+	clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a00821c 0x4>;
+	bit-mask = <0x80>;
+};
+
 apll_pcie_ck: apll_pcie_ck at 4a008200 {
 	#clock-cells = <0>;
-	compatible = "ti,omap4-dpll-clock";
-	clocks = <&dpll_pcie_ref_ck>;
-	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
-	ti,clk-ref = <&dpll_pcie_ref_ck>;
+	clocks = <&apll_pcie_in_clk_mux>;
+	reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
 	ti,clk-bypass = <&dpll_pcie_ref_ck>;
+	ti,clk-ref = <&apll_pcie_in_clk_mux>;
+	compatible = "ti,dra7-apll-clock";
 };
 
 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
-- 
1.7.9.5

[PATCHv5 14/31] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |    9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index b377526..eef899a 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -364,13 +364,10 @@ apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
 
 apll_pcie_m2_ck: apll_pcie_m2_ck at 4a008224 {
 	#clock-cells = <0>;
-	compatible = "ti,divider-clock";
+	compatible = "fixed-factor-clock";
 	clocks = <&apll_pcie_ck>;
-	ti,autoidle-shift = <8>;
-	reg = <0x4a008224 0x4>;
-	bit-mask = <0x7f>;
-	index-starts-at-one;
-	ti,autoidle-low;
+	clock-mult = <1>;
+	clock-div = <1>;
 };
 
 sys_clk1_dclk_div: sys_clk1_dclk_div at 4ae061c8 {
-- 
1.7.9.5

[PATCHv5 15/31] ARM: dts: DRA7: Add PCIe related clock nodes

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index eef899a..60ce28b 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -2079,3 +2079,27 @@ vip3_gclk_mux: vip3_gclk_mux at 4a009030 {
 	reg = <0x4a009030 0x4>;
 	bit-mask = <0x1>;
 };
+
+optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c {
+	compatible = "divider-clock";
+	clocks = <&apll_pcie_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a00821c 0x4>;
+	bit-mask = <0x100>;
+};
+
+optfclk_pciephy_clk: optfclk_pciephy_clk at 4a0093b0 {
+	compatible = "gate-clock";
+	clocks = <&apll_pcie_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0093b0 0x4>;
+	bit-shift = <9>;
+};
+
+optfclk_pciephy_div_clk: optfclk_pciephy_div_clk at 4a0093b0 {
+	compatible = "gate-clock";
+	clocks = <&optfclk_pciephy_div>;
+	#clock-cells = <0>;
+	reg = <0x4a0093b0 0x4>;
+	bit-shift = <10>;
+};
-- 
1.7.9.5

[PATCHv5 16/31] CLK: TI: DRA7: Add APLL support

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.

APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti/apll.txt          |   32 +++
 arch/arm/mach-omap2/clock.h                        |    1 -
 drivers/clk/ti/Makefile                            |    2 +-
 drivers/clk/ti/apll.c                              |  209 ++++++++++++++++++++
 include/linux/clk/ti.h                             |    2 +
 5 files changed, 244 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt
 create mode 100644 drivers/clk/ti/apll.c

diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt
new file mode 100644
index 0000000..f7a82e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
@@ -0,0 +1,32 @@
+Binding for Texas Instruments APLL clock.
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped APLL with usually two selectable input clocks
+(reference clock and bypass clock), with analog phase locked
+loop logic for multiplying the input clock to a desired output
+clock. This clock also typically supports different operation
+modes (locked, low power stop etc.) APLL mostly behaves like
+a subtype of a DPLL [2], although a simplified one at that.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
+
+Required properties:
+- compatible : shall be "ti,dra7-apll-clock"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : array of register base addresses for controlling the APLL:
+	reg[0] = control register
+	reg[1] = idle status register
+- ti,clk-ref : link phandle for the reference clock
+- ti,clk-bypass : link phandle for the bypass clock
+
+Examples:
+	apll_pcie_ck: apll_pcie_ck at 4a008200 {
+		#clock-cells = <0>;
+		clocks = <&apll_pcie_in_clk_mux>;
+		reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
+		ti,clk-bypass = <&dpll_pcie_ref_ck>;
+		ti,clk-ref = <&apll_pcie_in_clk_mux>;
+		compatible = "ti,dra7-apll-clock";
+	};
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index f0ee28c..46b3672 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -38,7 +38,6 @@ struct omap_clk {
 	}
 
 struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name)	\
 	static struct clk _name = {				\
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index e54f6f7..a75b9da 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,4 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
-					   clk-44xx.o clk-54xx.o
+					   apll.o clk-44xx.o clk-54xx.o
 endif
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
new file mode 100644
index 0000000..3084bd2
--- /dev/null
+++ b/drivers/clk/ti/apll.c
@@ -0,0 +1,209 @@
+/*
+ * OMAP APLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * J Keerthy <j-keerthy@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+#include <linux/delay.h>
+
+#define APLL_FORCE_LOCK 0x1
+#define APLL_AUTO_IDLE	0x2
+#define MAX_APLL_WAIT_TRIES		1000000
+
+static int dra7_apll_enable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	int r = 0, i = 0;
+	struct dpll_data *ad;
+	const char *clk_name;
+	u8 state = 1;
+	u32 v;
+
+	ad = clk->dpll_data;
+	if (!ad)
+		return -EINVAL;
+
+	clk_name = __clk_get_name(clk->hw.clk);
+
+	state <<= __ffs(ad->idlest_mask);
+
+	/* Check is already locked */
+	if ((__raw_readl(ad->idlest_reg) & ad->idlest_mask) == state)
+		return r;
+
+	v = __raw_readl(ad->control_reg);
+	v &= ~ad->enable_mask;
+	v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
+	__raw_writel(v, ad->control_reg);
+
+	state <<= __ffs(ad->idlest_mask);
+
+	while (((__raw_readl(ad->idlest_reg) & ad->idlest_mask) != state) &&
+	       i < MAX_APLL_WAIT_TRIES) {
+		i++;
+		udelay(1);
+	}
+
+	if (i == MAX_APLL_WAIT_TRIES) {
+		pr_warn("clock: %s failed transition to '%s'\n",
+			clk_name, (state) ? "locked" : "bypassed");
+	} else {
+		pr_debug("clock: %s transition to '%s' in %d loops\n",
+			 clk_name, (state) ? "locked" : "bypassed", i);
+
+		r = 0;
+	}
+
+	return r;
+}
+
+static void dra7_apll_disable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	struct dpll_data *ad;
+	u8 state = 1;
+	u32 v;
+
+	ad = clk->dpll_data;
+
+	state <<= __ffs(ad->idlest_mask);
+
+	v = __raw_readl(ad->control_reg);
+	v &= ~ad->enable_mask;
+	v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
+	__raw_writel(v, ad->control_reg);
+}
+
+static u8 dra7_init_apll_parent(struct clk_hw *hw)
+{
+	return 0;
+}
+
+static const struct clk_ops apll_ck_ops = {
+	.enable		= &dra7_apll_enable,
+	.disable	= &dra7_apll_disable,
+	.get_parent	= &dra7_init_apll_parent,
+};
+
+static struct clk *omap_clk_register_apll(struct device *dev, const char *name,
+		const char **parent_names, int num_parents, unsigned long flags,
+		struct dpll_data *dpll_data, const char *clkdm_name,
+		const struct clk_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init = { 0 };
+	struct clk_hw_omap *clk_hw;
+
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk_hw->dpll_data = dpll_data;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.flags = flags;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	/* register the clock */
+	clk = clk_register(dev, &clk_hw->hw);
+
+	return clk;
+}
+
+void __init of_dra7_apll_setup(struct device_node *node)
+{
+	const struct clk_ops *ops;
+	struct clk *clk;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names = NULL;
+	struct of_phandle_args clkspec;
+	u8 apll_flags = 0;
+	struct dpll_data *ad;
+	u32 idlest_mask = 0x1;
+	u32 autoidle_mask = 0x3;
+	int i;
+
+	ops = &apll_ck_ops;
+	ad = kzalloc(sizeof(*ad), GFP_KERNEL);
+	if (!ad) {
+		pr_err("%s: could not allocate dpll_data\n", __func__);
+		return;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap dpll %s must have parent(s)\n",
+		       __func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
+	ad->clk_ref = of_clk_get_from_provider(&clkspec);
+	if (!ad->clk_ref) {
+		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+		       clk_name);
+		goto cleanup;
+	}
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
+	ad->clk_bypass = of_clk_get_from_provider(&clkspec);
+	if (!ad->clk_bypass) {
+		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+		       clk_name);
+		goto cleanup;
+	}
+
+	ad->control_reg = of_iomap(node, 0);
+	ad->idlest_reg = of_iomap(node, 1);
+
+	ad->idlest_mask = idlest_mask;
+	ad->enable_mask = autoidle_mask;
+
+	clk = omap_clk_register_apll(NULL, clk_name, parent_names,
+				num_parents, apll_flags, ad,
+				NULL, ops);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	return;
+
+cleanup:
+	kfree(parent_names);
+	kfree(ad);
+	return;
+}
+CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 59df9f6..54f5a4f 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -159,6 +159,8 @@ struct omap_dt_clk {
 		.node_name = name,	\
 	}
 
+#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
+
 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap3_noncore_dpll_enable(struct clk_hw *hw);
 void omap3_noncore_dpll_disable(struct clk_hw *hw);
-- 
1.7.9.5

[PATCHv5 16/31] CLK: TI: DRA7: Add APLL support

[Mark Rutland]

On Fri, Aug 02, 2013 at 05:25:35PM +0100, Tero Kristo wrote:
> From: Keerthy <j-keerthy@ti.com>
> 
> The patch adds support for DRA7 PCIe APLL. The APLL
> sources the optional functional clocks for PCIe module.
> 
> APLL stands for Analog PLL. This is different when comapred
> with DPLL meaning Digital PLL, the phase detection is done
> using an analog circuit.
> 
> Signed-off-by: Keerthy <j-keerthy@ti.com>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  .../devicetree/bindings/clock/ti/apll.txt          |   32 +++
>  arch/arm/mach-omap2/clock.h                        |    1 -
>  drivers/clk/ti/Makefile                            |    2 +-
>  drivers/clk/ti/apll.c                              |  209 ++++++++++++++++++++
>  include/linux/clk/ti.h                             |    2 +
>  5 files changed, 244 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt
>  create mode 100644 drivers/clk/ti/apll.c
> 
> diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt
> new file mode 100644
> index 0000000..f7a82e9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
> @@ -0,0 +1,32 @@
> +Binding for Texas Instruments APLL clock.
> +
> +This binding uses the common clock binding[1].  It assumes a
> +register-mapped APLL with usually two selectable input clocks
> +(reference clock and bypass clock), with analog phase locked
> +loop logic for multiplying the input clock to a desired output
> +clock. This clock also typically supports different operation
> +modes (locked, low power stop etc.) APLL mostly behaves like
> +a subtype of a DPLL [2], although a simplified one at that.
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
> +
> +Required properties:
> +- compatible : shall be "ti,dra7-apll-clock"
> +- #clock-cells : from common clock binding; shall be set to 0.
> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
> +- reg : array of register base addresses for controlling the APLL:
> +       reg[0] = control register
> +       reg[1] = idle status register

Using reg-names is likely a good idea here.

> +- ti,clk-ref : link phandle for the reference clock
> +- ti,clk-bypass : link phandle for the bypass clock

You don't need this. Use the clocks and clock-names properties.

[...]

> +static int dra7_apll_enable(struct clk_hw *hw)
> +{
> +       struct clk_hw_omap *clk = to_clk_hw_omap(hw);
> +       int r = 0, i = 0;
> +       struct dpll_data *ad;
> +       const char *clk_name;
> +       u8 state = 1;
> +       u32 v;
> +
> +       ad = clk->dpll_data;
> +       if (!ad)
> +               return -EINVAL;
> +
> +       clk_name = __clk_get_name(clk->hw.clk);
> +
> +       state <<= __ffs(ad->idlest_mask);
> +
> +       /* Check is already locked */
> +       if ((__raw_readl(ad->idlest_reg) & ad->idlest_mask) == state)
> +               return r;

Why __raw_readl rather than raw_readl?

> +
> +       v = __raw_readl(ad->control_reg);
> +       v &= ~ad->enable_mask;
> +       v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
> +       __raw_writel(v, ad->control_reg);

Why not raw_writel? Do you not need the rmb() provided by writel, here
or anywhere else?

[...]

> +void __init of_dra7_apll_setup(struct device_node *node)
> +{
> +       const struct clk_ops *ops;
> +       struct clk *clk;
> +       const char *clk_name = node->name;
> +       int num_parents;
> +       const char **parent_names = NULL;
> +       struct of_phandle_args clkspec;
> +       u8 apll_flags = 0;
> +       struct dpll_data *ad;
> +       u32 idlest_mask = 0x1;
> +       u32 autoidle_mask = 0x3;
> +       int i;
> +
> +       ops = &apll_ck_ops;
> +       ad = kzalloc(sizeof(*ad), GFP_KERNEL);
> +       if (!ad) {
> +               pr_err("%s: could not allocate dpll_data\n", __func__);
> +               return;
> +       }
> +
> +       of_property_read_string(node, "clock-output-names", &clk_name);
> +
> +       num_parents = of_clk_get_parent_count(node);
> +       if (num_parents < 1) {
> +               pr_err("%s: omap dpll %s must have parent(s)\n",
> +                      __func__, node->name);
> +               goto cleanup;
> +       }
> +
> +       parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
> +
> +       for (i = 0; i < num_parents; i++)
> +               parent_names[i] = of_clk_get_parent_name(node, i);
> +
> +       clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
> +       ad->clk_ref = of_clk_get_from_provider(&clkspec);

Use clocks, clock-names, and of_clk_get_by_name().

Thanks,
Mark.

[PATCHv5 16/31] CLK: TI: DRA7: Add APLL support

[Tero Kristo]

On 08/13/2013 02:14 PM, Mark Rutland wrote:
> On Fri, Aug 02, 2013 at 05:25:35PM +0100, Tero Kristo wrote:
>> From: Keerthy <j-keerthy@ti.com>
>>
>> The patch adds support for DRA7 PCIe APLL. The APLL
>> sources the optional functional clocks for PCIe module.
>>
>> APLL stands for Analog PLL. This is different when comapred
>> with DPLL meaning Digital PLL, the phase detection is done
>> using an analog circuit.
>>
>> Signed-off-by: Keerthy <j-keerthy@ti.com>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   .../devicetree/bindings/clock/ti/apll.txt          |   32 +++
>>   arch/arm/mach-omap2/clock.h                        |    1 -
>>   drivers/clk/ti/Makefile                            |    2 +-
>>   drivers/clk/ti/apll.c                              |  209 ++++++++++++++++++++
>>   include/linux/clk/ti.h                             |    2 +
>>   5 files changed, 244 insertions(+), 2 deletions(-)
>>   create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt
>>   create mode 100644 drivers/clk/ti/apll.c
>>
>> diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt
>> new file mode 100644
>> index 0000000..f7a82e9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
>> @@ -0,0 +1,32 @@
>> +Binding for Texas Instruments APLL clock.
>> +
>> +This binding uses the common clock binding[1].  It assumes a
>> +register-mapped APLL with usually two selectable input clocks
>> +(reference clock and bypass clock), with analog phase locked
>> +loop logic for multiplying the input clock to a desired output
>> +clock. This clock also typically supports different operation
>> +modes (locked, low power stop etc.) APLL mostly behaves like
>> +a subtype of a DPLL [2], although a simplified one at that.
>> +
>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
>> +
>> +Required properties:
>> +- compatible : shall be "ti,dra7-apll-clock"
>> +- #clock-cells : from common clock binding; shall be set to 0.
>> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
>> +- reg : array of register base addresses for controlling the APLL:
>> +       reg[0] = control register
>> +       reg[1] = idle status register
>
> Using reg-names is likely a good idea here.

I'll change these for next rev to be similar to what was discussed in 
the DPLL part.

>
>> +- ti,clk-ref : link phandle for the reference clock
>> +- ti,clk-bypass : link phandle for the bypass clock
>
> You don't need this. Use the clocks and clock-names properties.

Ditto.

>
> [...]
>
>> +static int dra7_apll_enable(struct clk_hw *hw)
>> +{
>> +       struct clk_hw_omap *clk = to_clk_hw_omap(hw);
>> +       int r = 0, i = 0;
>> +       struct dpll_data *ad;
>> +       const char *clk_name;
>> +       u8 state = 1;
>> +       u32 v;
>> +
>> +       ad = clk->dpll_data;
>> +       if (!ad)
>> +               return -EINVAL;
>> +
>> +       clk_name = __clk_get_name(clk->hw.clk);
>> +
>> +       state <<= __ffs(ad->idlest_mask);
>> +
>> +       /* Check is already locked */
>> +       if ((__raw_readl(ad->idlest_reg) & ad->idlest_mask) == state)
>> +               return r;
>
> Why __raw_readl rather than raw_readl?

Hmm not sure, Keerthy, do you have any comment on this as the patch was 
originally written by you? :)

>
>> +
>> +       v = __raw_readl(ad->control_reg);
>> +       v &= ~ad->enable_mask;
>> +       v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
>> +       __raw_writel(v, ad->control_reg);
>
> Why not raw_writel? Do you not need the rmb() provided by writel, here
> or anywhere else?

Same, Keerthy? Probably just legacy copy paste from omap2 code and can 
be updated based on your comment. Some of these might actually be some 
old optimizations, but the APLL enable/disable should be called so 
seldom it shouldn't matter. If no objections, I'll just change these all 
for next rev.

>
> [...]
>
>> +void __init of_dra7_apll_setup(struct device_node *node)
>> +{
>> +       const struct clk_ops *ops;
>> +       struct clk *clk;
>> +       const char *clk_name = node->name;
>> +       int num_parents;
>> +       const char **parent_names = NULL;
>> +       struct of_phandle_args clkspec;
>> +       u8 apll_flags = 0;
>> +       struct dpll_data *ad;
>> +       u32 idlest_mask = 0x1;
>> +       u32 autoidle_mask = 0x3;
>> +       int i;
>> +
>> +       ops = &apll_ck_ops;
>> +       ad = kzalloc(sizeof(*ad), GFP_KERNEL);
>> +       if (!ad) {
>> +               pr_err("%s: could not allocate dpll_data\n", __func__);
>> +               return;
>> +       }
>> +
>> +       of_property_read_string(node, "clock-output-names", &clk_name);
>> +
>> +       num_parents = of_clk_get_parent_count(node);
>> +       if (num_parents < 1) {
>> +               pr_err("%s: omap dpll %s must have parent(s)\n",
>> +                      __func__, node->name);
>> +               goto cleanup;
>> +       }
>> +
>> +       parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
>> +
>> +       for (i = 0; i < num_parents; i++)
>> +               parent_names[i] = of_clk_get_parent_name(node, i);
>> +
>> +       clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
>> +       ad->clk_ref = of_clk_get_from_provider(&clkspec);
>
> Use clocks, clock-names, and of_clk_get_by_name().

Yea, will change.

-Tero

[PATCHv5 16/31] CLK: TI: DRA7: Add APLL support

[Keerthy]

Hi Mark/Tero,

Sorry for responding late.

On Monday 19 August 2013 07:22 PM, Tero Kristo wrote:
> On 08/13/2013 02:14 PM, Mark Rutland wrote:
>> On Fri, Aug 02, 2013 at 05:25:35PM +0100, Tero Kristo wrote:
>>> From: Keerthy <j-keerthy@ti.com>
>>>
>>> The patch adds support for DRA7 PCIe APLL. The APLL
>>> sources the optional functional clocks for PCIe module.
>>>
>>> APLL stands for Analog PLL. This is different when comapred
>>> with DPLL meaning Digital PLL, the phase detection is done
>>> using an analog circuit.
>>>
>>> Signed-off-by: Keerthy <j-keerthy@ti.com>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> ---
>>>   .../devicetree/bindings/clock/ti/apll.txt          |   32 +++
>>>   arch/arm/mach-omap2/clock.h                        |    1 -
>>>   drivers/clk/ti/Makefile                            |    2 +-
>>>   drivers/clk/ti/apll.c                              |  209 
>>> ++++++++++++++++++++
>>>   include/linux/clk/ti.h                             |    2 +
>>>   5 files changed, 244 insertions(+), 2 deletions(-)
>>>   create mode 100644 
>>> Documentation/devicetree/bindings/clock/ti/apll.txt
>>>   create mode 100644 drivers/clk/ti/apll.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt 
>>> b/Documentation/devicetree/bindings/clock/ti/apll.txt
>>> new file mode 100644
>>> index 0000000..f7a82e9
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/ti/apll.txt
>>> @@ -0,0 +1,32 @@
>>> +Binding for Texas Instruments APLL clock.
>>> +
>>> +This binding uses the common clock binding[1].  It assumes a
>>> +register-mapped APLL with usually two selectable input clocks
>>> +(reference clock and bypass clock), with analog phase locked
>>> +loop logic for multiplying the input clock to a desired output
>>> +clock. This clock also typically supports different operation
>>> +modes (locked, low power stop etc.) APLL mostly behaves like
>>> +a subtype of a DPLL [2], although a simplified one at that.
>>> +
>>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>>> +[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
>>> +
>>> +Required properties:
>>> +- compatible : shall be "ti,dra7-apll-clock"
>>> +- #clock-cells : from common clock binding; shall be set to 0.
>>> +- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
>>> +- reg : array of register base addresses for controlling the APLL:
>>> +       reg[0] = control register
>>> +       reg[1] = idle status register
>>
>> Using reg-names is likely a good idea here.
>
> I'll change these for next rev to be similar to what was discussed in 
> the DPLL part.
>
>>
>>> +- ti,clk-ref : link phandle for the reference clock
>>> +- ti,clk-bypass : link phandle for the bypass clock
>>
>> You don't need this. Use the clocks and clock-names properties.
>
> Ditto.
>
>>
>> [...]
>>
>>> +static int dra7_apll_enable(struct clk_hw *hw)
>>> +{
>>> +       struct clk_hw_omap *clk = to_clk_hw_omap(hw);
>>> +       int r = 0, i = 0;
>>> +       struct dpll_data *ad;
>>> +       const char *clk_name;
>>> +       u8 state = 1;
>>> +       u32 v;
>>> +
>>> +       ad = clk->dpll_data;
>>> +       if (!ad)
>>> +               return -EINVAL;
>>> +
>>> +       clk_name = __clk_get_name(clk->hw.clk);
>>> +
>>> +       state <<= __ffs(ad->idlest_mask);
>>> +
>>> +       /* Check is already locked */
>>> +       if ((__raw_readl(ad->idlest_reg) & ad->idlest_mask) == state)
>>> +               return r;
>>
>> Why __raw_readl rather than raw_readl?
>
> Hmm not sure, Keerthy, do you have any comment on this as the patch 
> was originally written by you? :)

It was more taking the reference from omap2 code. raw_readl can be used.

>
>>
>>> +
>>> +       v = __raw_readl(ad->control_reg);
>>> +       v &= ~ad->enable_mask;
>>> +       v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
>>> +       __raw_writel(v, ad->control_reg);
>>
>> Why not raw_writel? Do you not need the rmb() provided by writel, here
>> or anywhere else?
>
> Same, Keerthy? Probably just legacy copy paste from omap2 code and can 
> be updated based on your comment. Some of these might actually be some 
> old optimizations, but the APLL enable/disable should be called so 
> seldom it shouldn't matter. If no objections, I'll just change these 
> all for next rev.

Thanks Tero.

>
>>
>> [...]
>>
>>> +void __init of_dra7_apll_setup(struct device_node *node)
>>> +{
>>> +       const struct clk_ops *ops;
>>> +       struct clk *clk;
>>> +       const char *clk_name = node->name;
>>> +       int num_parents;
>>> +       const char **parent_names = NULL;
>>> +       struct of_phandle_args clkspec;
>>> +       u8 apll_flags = 0;
>>> +       struct dpll_data *ad;
>>> +       u32 idlest_mask = 0x1;
>>> +       u32 autoidle_mask = 0x3;
>>> +       int i;
>>> +
>>> +       ops = &apll_ck_ops;
>>> +       ad = kzalloc(sizeof(*ad), GFP_KERNEL);
>>> +       if (!ad) {
>>> +               pr_err("%s: could not allocate dpll_data\n", __func__);
>>> +               return;
>>> +       }
>>> +
>>> +       of_property_read_string(node, "clock-output-names", &clk_name);
>>> +
>>> +       num_parents = of_clk_get_parent_count(node);
>>> +       if (num_parents < 1) {
>>> +               pr_err("%s: omap dpll %s must have parent(s)\n",
>>> +                      __func__, node->name);
>>> +               goto cleanup;
>>> +       }
>>> +
>>> +       parent_names = kzalloc(sizeof(char *) * num_parents, 
>>> GFP_KERNEL);
>>> +
>>> +       for (i = 0; i < num_parents; i++)
>>> +               parent_names[i] = of_clk_get_parent_name(node, i);
>>> +
>>> +       clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
>>> +       ad->clk_ref = of_clk_get_from_provider(&clkspec);
>>
>> Use clocks, clock-names, and of_clk_get_by_name().
>
> Yea, will change.
>
> -Tero

Regards,
Keerthy

[PATCHv5 17/31] CLK: TI: add dra7 clock init file

[Tero Kristo]

clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/ti/Makefile  |    3 ++-
 drivers/clk/ti/clk-7xx.c |   67 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clk-7xx.c

diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index a75b9da..54969b9 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,4 +1,5 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
-					   apll.o clk-44xx.o clk-54xx.o
+					   apll.o clk-44xx.o clk-54xx.o \
+					   clk-7xx.o
 endif
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
new file mode 100644
index 0000000..a00a9d7
--- /dev/null
+++ b/drivers/clk/ti/clk-7xx.c
@@ -0,0 +1,67 @@
+/*
+ * DRA7 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/clk/ti.h>
+
+#define DRA7_DPLL_ABE_DEFFREQ				361267200
+#define DRA7_DPLL_GMAC_DEFFREQ				1000000000
+
+
+static struct omap_dt_clk dra7xx_clks[] = {
+	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+	DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
+	{ NULL },
+};
+
+int __init dra7xx_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+
+	of_clk_init(NULL);
+
+	omap_dt_clocks_register(dra7xx_clks);
+
+	omap2_clk_disable_autoidle_all();
+
+	abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
+	sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
+	dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
+
+	rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
+	if (!rc)
+		rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
+	rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
+
+	return rc;
+}
-- 
1.7.9.5

[PATCHv5 18/31] CLK: DT: add support for set-rate-parent flag

[Tero Kristo]

Adding set-rate-parent to clock node now allows a node to forward
clk_set_rate request to its parent clock.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk-divider.c      |    6 +++++-
 drivers/clk/clk-fixed-factor.c |    6 +++++-
 drivers/clk/clk-gate.c         |    8 ++++++--
 drivers/clk/clk-mux.c          |    6 +++++-
 4 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index ff24ec2..01d967f 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -388,6 +388,7 @@ void of_divider_clk_setup(struct device_node *node)
 	u32 mask = 0;
 	u32 shift = 0;
 	struct clk_div_table *table;
+	u32 flags = 0;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -418,12 +419,15 @@ void of_divider_clk_setup(struct device_node *node)
 	if (of_property_read_bool(node, "hiword-mask"))
 		clk_divider_flags |= CLK_DIVIDER_HIWORD_MASK;
 
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
 	table = of_clk_get_div_table(node);
 	if (IS_ERR(table))
 		return;
 
 	clk = _register_divider(NULL, clk_name,
-			parent_name, 0,
+			parent_name, flags,
 			reg, (u8) shift, mask,
 			clk_divider_flags, table,
 			NULL);
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 9ff7d51..30aa121 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -107,6 +107,7 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
 	const char *clk_name = node->name;
 	const char *parent_name;
 	u32 div, mult;
+	u32 flags = 0;
 
 	if (of_property_read_u32(node, "clock-div", &div)) {
 		pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
@@ -123,7 +124,10 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
 	of_property_read_string(node, "clock-output-names", &clk_name);
 	parent_name = of_clk_get_parent_name(node, 0);
 
-	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
+	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
 					mult, div);
 	if (!IS_ERR(clk))
 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index cd595ec..0be25b9 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -176,6 +176,7 @@ void of_gate_clk_setup(struct device_node *node)
 	const char *parent_name;
 	u8 clk_gate_flags = 0;
 	u32 bit_idx = 0;
+	u32 flags = 0;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -195,8 +196,11 @@ void of_gate_clk_setup(struct device_node *node)
 	if (of_property_read_bool(node, "hiword-mask"))
 		clk_gate_flags |= CLK_GATE_HIWORD_MASK;
 
-	clk = clk_register_gate(NULL, clk_name, parent_name, 0, reg, (u8) bit_idx,
-			clk_gate_flags, NULL);
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
+	clk = clk_register_gate(NULL, clk_name, parent_name, flags, reg,
+			(u8) bit_idx, clk_gate_flags, NULL);
 
 	if (!IS_ERR(clk))
 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 4751bce..890ddbf 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -184,6 +184,7 @@ void of_mux_clk_setup(struct device_node *node)
 	u8 clk_mux_flags = 0;
 	u32 mask = 0;
 	u32 shift = 0;
+	u32 flags = 0;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -219,8 +220,11 @@ void of_mux_clk_setup(struct device_node *node)
 	if (of_property_read_bool(node, "hiword-mask"))
 		clk_mux_flags |= CLK_MUX_HIWORD_MASK;
 
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
 	clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents,
-			0, reg, (u8) shift, mask, clk_mux_flags,
+			flags, reg, (u8) shift, mask, clk_mux_flags,
 			NULL, NULL);
 
 	if (!IS_ERR(clk))
-- 
1.7.9.5

[PATCHv5 18/31] CLK: DT: add support for set-rate-parent flag

[Mark Rutland]

On Fri, Aug 02, 2013 at 05:25:37PM +0100, Tero Kristo wrote:
> Adding set-rate-parent to clock node now allows a node to forward
> clk_set_rate request to its parent clock.

Why do you need this?

Is this a description of the hardware, or configuration for Linux?
It feels like the latter, which shouldn't really be in DT.

I'm not that familiar with the internals of the clock framework, and
don't understand the implications of this.

If this is necessary, the bindings need to be updated.

Mike, thoughts?

Mark.

> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  drivers/clk/clk-divider.c      |    6 +++++-
>  drivers/clk/clk-fixed-factor.c |    6 +++++-
>  drivers/clk/clk-gate.c         |    8 ++++++--
>  drivers/clk/clk-mux.c          |    6 +++++-
>  4 files changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index ff24ec2..01d967f 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -388,6 +388,7 @@ void of_divider_clk_setup(struct device_node *node)
>  	u32 mask = 0;
>  	u32 shift = 0;
>  	struct clk_div_table *table;
> +	u32 flags = 0;
>  
>  	of_property_read_string(node, "clock-output-names", &clk_name);
>  
> @@ -418,12 +419,15 @@ void of_divider_clk_setup(struct device_node *node)
>  	if (of_property_read_bool(node, "hiword-mask"))
>  		clk_divider_flags |= CLK_DIVIDER_HIWORD_MASK;
>  
> +	if (of_property_read_bool(node, "set-rate-parent"))
> +		flags |= CLK_SET_RATE_PARENT;
> +
>  	table = of_clk_get_div_table(node);
>  	if (IS_ERR(table))
>  		return;
>  
>  	clk = _register_divider(NULL, clk_name,
> -			parent_name, 0,
> +			parent_name, flags,
>  			reg, (u8) shift, mask,
>  			clk_divider_flags, table,
>  			NULL);
> diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
> index 9ff7d51..30aa121 100644
> --- a/drivers/clk/clk-fixed-factor.c
> +++ b/drivers/clk/clk-fixed-factor.c
> @@ -107,6 +107,7 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
>  	const char *clk_name = node->name;
>  	const char *parent_name;
>  	u32 div, mult;
> +	u32 flags = 0;
>  
>  	if (of_property_read_u32(node, "clock-div", &div)) {
>  		pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
> @@ -123,7 +124,10 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
>  	of_property_read_string(node, "clock-output-names", &clk_name);
>  	parent_name = of_clk_get_parent_name(node, 0);
>  
> -	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
> +	if (of_property_read_bool(node, "set-rate-parent"))
> +		flags |= CLK_SET_RATE_PARENT;
> +
> +	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
>  					mult, div);
>  	if (!IS_ERR(clk))
>  		of_clk_add_provider(node, of_clk_src_simple_get, clk);
> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> index cd595ec..0be25b9 100644
> --- a/drivers/clk/clk-gate.c
> +++ b/drivers/clk/clk-gate.c
> @@ -176,6 +176,7 @@ void of_gate_clk_setup(struct device_node *node)
>  	const char *parent_name;
>  	u8 clk_gate_flags = 0;
>  	u32 bit_idx = 0;
> +	u32 flags = 0;
>  
>  	of_property_read_string(node, "clock-output-names", &clk_name);
>  
> @@ -195,8 +196,11 @@ void of_gate_clk_setup(struct device_node *node)
>  	if (of_property_read_bool(node, "hiword-mask"))
>  		clk_gate_flags |= CLK_GATE_HIWORD_MASK;
>  
> -	clk = clk_register_gate(NULL, clk_name, parent_name, 0, reg, (u8) bit_idx,
> -			clk_gate_flags, NULL);
> +	if (of_property_read_bool(node, "set-rate-parent"))
> +		flags |= CLK_SET_RATE_PARENT;
> +
> +	clk = clk_register_gate(NULL, clk_name, parent_name, flags, reg,
> +			(u8) bit_idx, clk_gate_flags, NULL);
>  
>  	if (!IS_ERR(clk))
>  		of_clk_add_provider(node, of_clk_src_simple_get, clk);
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index 4751bce..890ddbf 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -184,6 +184,7 @@ void of_mux_clk_setup(struct device_node *node)
>  	u8 clk_mux_flags = 0;
>  	u32 mask = 0;
>  	u32 shift = 0;
> +	u32 flags = 0;
>  
>  	of_property_read_string(node, "clock-output-names", &clk_name);
>  
> @@ -219,8 +220,11 @@ void of_mux_clk_setup(struct device_node *node)
>  	if (of_property_read_bool(node, "hiword-mask"))
>  		clk_mux_flags |= CLK_MUX_HIWORD_MASK;
>  
> +	if (of_property_read_bool(node, "set-rate-parent"))
> +		flags |= CLK_SET_RATE_PARENT;
> +
>  	clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents,
> -			0, reg, (u8) shift, mask, clk_mux_flags,
> +			flags, reg, (u8) shift, mask, clk_mux_flags,
>  			NULL, NULL);
>  
>  	if (!IS_ERR(clk))
> -- 
> 1.7.9.5
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

[PATCHv5 19/31] ARM: dts: am33xx clock data

[Tero Kristo]

This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/am33xx-clocks.dtsi |  658 ++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/am33xx.dtsi        |    7 +
 2 files changed, 665 insertions(+)
 create mode 100644 arch/arm/boot/dts/am33xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 0000000..a7a7462
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,658 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clk_32768_ck: clk_32768_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+clk_rc32k_ck: clk_rc32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_24000000_ck: virt_24000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <24000000>;
+};
+
+virt_25000000_ck: virt_25000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <25000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+sys_clkin_ck: sys_clkin_ck at 44e10040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+	bit-shift = <22>;
+	reg = <0x44e10040 0x4>;
+	bit-mask = <0x3>;
+};
+
+tclkin_ck: tclkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+dpll_core_ck: dpll_core_ck at 44e00490 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-core-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x0 0x4>, <0x44e00468 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m4_ck: dpll_core_m4_ck at 44e00480 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x44e00480 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m5_ck: dpll_core_m5_ck at 44e00484 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x44e00484 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m6_ck: dpll_core_m6_ck at 44e004d8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x44e004d8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 44e00488 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00488 0x4>, <0x44e00420 0x4>, <0x0 0x4>, <0x44e0042c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 44e004a8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	reg = <0x44e004a8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_ddr_ck: dpll_ddr_ck at 44e00494 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-no-gate-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00494 0x4>, <0x44e00434 0x4>, <0x0 0x4>, <0x44e00440 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck at 44e004a0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_ddr_ck>;
+	reg = <0x44e004a0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_ddr_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_disp_ck: dpll_disp_ck at 44e00498 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-no-gate-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00498 0x4>, <0x44e00448 0x4>, <0x0 0x4>, <0x44e00454 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_disp_m2_ck: dpll_disp_m2_ck at 44e004a4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_disp_ck>;
+	reg = <0x44e004a4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	set-rate-parent;
+};
+
+dpll_per_ck: dpll_per_ck at 44e0048c {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-no-gate-j-type-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e0048c 0x4>, <0x44e00470 0x4>, <0x0 0x4>, <0x44e0049c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 44e004ac {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_ck>;
+	reg = <0x44e004ac 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+adc_tsc_fck: adc_tsc_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+cefuse_fck: cefuse_fck at 44e00a20 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin_ck>;
+	bit-shift = <1>;
+	reg = <0x44e00a20 0x4>;
+};
+
+clk_24mhz: clk_24mhz {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+clkdiv32k_ck: clkdiv32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&clk_24mhz>;
+	clock-mult = <1>;
+	clock-div = <732>;
+};
+
+clkdiv32k_ick: clkdiv32k_ick at 44e0014c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ck>;
+	reg = <0x44e0014c 0x4>;
+	bit-shift = <1>;
+};
+
+dcan0_fck: dcan0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dcan1_fck: dcan1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3_gclk: l3_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+pruss_ocp_gclk: pruss_ocp_gclk at 44e00530 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+	reg = <0x44e00530 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcasp0_fck: mcasp0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mcasp1_fck: mcasp1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mmu_fck: mmu_fck at 44e00914 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m4_ck>;
+	bit-shift = <1>;
+	reg = <0x44e00914 0x4>;
+};
+
+smartreflex0_fck: smartreflex0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+smartreflex1_fck: smartreflex1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sha0_fck: sha0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+aes0_fck: aes0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+timer1_fck: timer1_fck at 44e00528 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+	reg = <0x44e00528 0x4>;
+	bit-mask = <0x7>;
+};
+
+timer2_fck: timer2_fck at 44e00508 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00508 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer3_fck: timer3_fck at 44e0050c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e0050c 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer4_fck: timer4_fck at 44e00510 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00510 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer5_fck: timer5_fck at 44e00518 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00518 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer6_fck: timer6_fck at 44e0051c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e0051c 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer7_fck: timer7_fck at 44e00504 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00504 0x4>;
+	bit-mask = <0x3>;
+};
+
+usbotg_fck: usbotg_fck at 44e0047c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_ck>;
+	bit-shift = <8>;
+	reg = <0x44e0047c 0x4>;
+};
+
+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+ieee5000_fck: ieee5000_fck at 44e000e4 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	bit-shift = <1>;
+	reg = <0x44e000e4 0x4>;
+};
+
+wdt1_fck: wdt1_fck at 44e00538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00538 0x4>;
+	bit-mask = <0x3>;
+};
+
+l4_rtc_gclk: l4_rtc_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+l4hs_gclk: l4hs_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3s_gclk: l3s_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l4fw_gclk: l4fw_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l4ls_gclk: l4ls_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sysclk_div_ck: sysclk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m5_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk at 44e00520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+	reg = <0x44e00520 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck at 44e0053c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e0053c 0x4>;
+	bit-mask = <0x3>;
+};
+
+gpio0_dbclk: gpio0_dbclk at 44e00408 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpio0_dbclk_mux_ck>;
+	bit-shift = <18>;
+	reg = <0x44e00408 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk at 44e000ac {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <18>;
+	reg = <0x44e000ac 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 44e000b0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <18>;
+	reg = <0x44e000b0 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 44e000b4 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <18>;
+	reg = <0x44e000b4 0x4>;
+};
+
+lcd_gclk: lcd_gclk at 44e00534 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+	reg = <0x44e00534 0x4>;
+	bit-mask = <0x3>;
+	set-rate-parent;
+};
+
+mmc_clk: mmc_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck at 44e0052c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+	bit-shift = <1>;
+	reg = <0x44e0052c 0x4>;
+	bit-mask = <0x1>;
+};
+
+gfx_fck_div_ck: gfx_fck_div_ck at 44e0052c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&gfx_fclk_clksel_ck>;
+	reg = <0x44e0052c 0x4>;
+	table = < 1 0 >, < 2 1 >;
+	bit-mask = <0x1>;
+};
+
+sysclkout_pre_ck: sysclkout_pre_ck at 44e00700 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+	reg = <0x44e00700 0x4>;
+	bit-mask = <0x7>;
+};
+
+clkout2_div_ck: clkout2_div_ck at 44e00700 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sysclkout_pre_ck>;
+	bit-shift = <3>;
+	reg = <0x44e00700 0x4>;
+	table = < 1 0 >, < 2 1 >, < 3 2 >, < 4 3 >, < 5 4 >, < 6 5 >, < 7 6 >, < 8 7 >;
+	bit-mask = <0x7>;
+};
+
+dbg_sysclk_ck: dbg_sysclk_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin_ck>;
+	bit-shift = <19>;
+	reg = <0x44e00414 0x4>;
+};
+
+dbg_clka_ck: dbg_clka_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m4_ck>;
+	bit-shift = <30>;
+	reg = <0x44e00414 0x4>;
+};
+
+stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+	bit-shift = <22>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x3>;
+};
+
+trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+	bit-shift = <20>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x3>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&stm_pmd_clock_mux_ck>;
+	bit-shift = <27>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&trace_pmd_clk_mux_ck>;
+	bit-shift = <24>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+clkout2_ck: clkout2_ck at 44e00700 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkout2_div_ck>;
+	bit-shift = <7>;
+	reg = <0x44e00700 0x4>;
+};
+
+ehrpwm0_tbclk: ehrpwm0_tbclk at 44e10664 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m2_ck>;
+	bit-shift = <0>;
+	reg = <0x44e10664 0x4>;
+};
+
+ehrpwm1_tbclk: ehrpwm1_tbclk at 44e10664 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m2_ck>;
+	bit-shift = <1>;
+	reg = <0x44e10664 0x4>;
+};
+
+ehrpwm2_tbclk: ehrpwm2_tbclk at 44e10664 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m2_ck>;
+	bit-shift = <2>;
+	reg = <0x44e10664 0x4>;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 38b446b..4701e3c 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -531,4 +531,11 @@
 			status = "disabled";
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "am33xx-clocks.dtsi"
+	};
 };
-- 
1.7.9.5

[PATCHv5 20/31] CLK: TI: add am33xx clock init file

[Tero Kristo]

clk-33xx.c now contains the clock init functionality for am33xx, including
DT clock registration and adding of static clkdev entries.

This patch also moves the omap2_clk_enable_init_clocks declaration to
the driver include, as this is needed by the am33xx clock init code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.h |    1 -
 drivers/clk/ti/clk-33xx.c   |   85 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h      |    1 +
 3 files changed, 86 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clk-33xx.c

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 46b3672..08c9aa6 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -266,7 +266,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 				void __iomem **idlest_reg,
 				u8 *idlest_bit, u8 *idlest_val);
 int omap2_clk_enable_autoidle_all(void);
-void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 			       const char *core_ck_name,
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
new file mode 100644
index 0000000..b3d4942
--- /dev/null
+++ b/drivers/clk/ti/clk-33xx.c
@@ -0,0 +1,85 @@
+/*
+ * AM33XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ *     Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+static struct omap_dt_clk am33xx_clks[] = {
+	DT_CLK("cpu0", NULL, "dpll_mpu_ck"),
+	DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
+	DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
+	DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
+	DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
+	DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
+	{ NULL },
+};
+
+static const char *enable_init_clks[] = {
+	"dpll_ddr_m2_ck",
+	"dpll_mpu_m2_ck",
+	"l3_gclk",
+	"l4hs_gclk",
+	"l4fw_gclk",
+	"l4ls_gclk",
+	/* Required for external peripherals like, Audio codecs */
+	"clkout2_ck",
+};
+
+int __init am33xx_clk_init(void)
+{
+	struct clk *clk1, *clk2;
+
+	of_clk_init(NULL);
+
+	omap_dt_clocks_register(am33xx_clks);
+
+	omap2_clk_disable_autoidle_all();
+
+	omap2_clk_enable_init_clocks(enable_init_clks,
+				     ARRAY_SIZE(enable_init_clks));
+
+	/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
+	 *    physically present, in such a case HWMOD enabling of
+	 *    clock would be failure with default parent. And timer
+	 *    probe thinks clock is already enabled, this leads to
+	 *    crash upon accessing timer 3 & 6 registers in probe.
+	 *    Fix by setting parent of both these timers to master
+	 *    oscillator clock.
+	 */
+
+	clk1 = clk_get_sys(NULL, "sys_clkin_ck");
+	clk2 = clk_get_sys(NULL, "timer3_fck");
+	clk_set_parent(clk2, clk1);
+
+	clk2 = clk_get_sys(NULL, "timer6_fck");
+	clk_set_parent(clk2, clk1);
+	/*
+	 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
+	 * the design/spec, so as a result, for example, timer which supposed
+	 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
+	 * not expected by any use-case, so change WDT1 clock source to PRCM
+	 * 32KHz clock.
+	 */
+	clk1 = clk_get_sys(NULL, "wdt1_fck");
+	clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
+	clk_set_parent(clk1, clk2);
+
+	return 0;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 54f5a4f..8ff2c29 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -181,6 +181,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 int omap2_clk_disable_autoidle_all(void);
+void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 			 unsigned long parent_rate);
 int omap2_dflt_clk_enable(struct clk_hw *hw);
-- 
1.7.9.5

[PATCHv5 21/31] ARM: AM33xx: remove old clock data and link in new clock init code

[Tero Kristo]

AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/Makefile          |    1 -
 arch/arm/mach-omap2/cclock33xx_data.c | 1059 ---------------------------------
 drivers/clk/ti/Makefile               |    2 +-
 3 files changed, 1 insertion(+), 1061 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cclock33xx_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9f8d3ed..a4782e2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -178,7 +178,6 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX)		+= cclock33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)			+= $(clock-common)
 obj-$(CONFIG_SOC_OMAP5)			+= dpll3xxx.o dpll44xx.o
 
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index ba6534d..0000000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1059 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "am33xx.h"
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "control.h"
-#include "cm.h"
-#include "cm33xx.h"
-#include "cm-regbits-33xx.h"
-#include "prm.h"
-
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL_SHIFT		0
-#define AM33XX_MODULEMODE_SWCTRL_SHIFT		1
-
-/*LIST_HEAD(clocks);*/
-
-/* Root clocks */
-
-/* RTC 32k */
-DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
-
-/* On-Chip 32KHz RC OSC */
-DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
-
-/* Crystal input clks */
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const char *sys_clkin_ck_parents[] = {
-	"virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
-	"virt_26000000_ck",
-};
-
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- *   adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-	       AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
-	       AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
-	       AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
-	       0, NULL);
-
-/* External clock - 12 MHz */
-DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_CORE,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_CORE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_CORE,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKDCOLDO output */
-static const char *dpll_core_ck_parents[] = {
-	"sys_clkin_ck",
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_core_ck,
-	},
-	.dpll_data	= &dpll_core_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-	"dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static const struct clk_ops dpll_x2_ck_ops = {
-	.recalc_rate	= &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_core_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-		   NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_MPU,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_MPU,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_MPU,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_mpu_ck;
-
-static const struct clk_ops dpll_mpu_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-	.hw = {
-		.clk	= &dpll_mpu_ck,
-	},
-	.dpll_data	= &dpll_mpu_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
-		   0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-		   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_DDR */
-static struct dpll_data dpll_ddr_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DDR,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DDR,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DDR,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_ddr_ck;
-
-static const struct clk_ops dpll_ddr_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk_hw_omap dpll_ddr_ck_hw = {
-	.hw = {
-		.clk	= &dpll_ddr_ck,
-	},
-	.dpll_data	= &dpll_ddr_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
-		   0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
-		   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* emif_fck functional clock */
-DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
-			0x0, 1, 2);
-
-/* DPLL_DISP */
-static struct dpll_data dpll_disp_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DISP,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DISP,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DISP,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_disp_ck;
-
-static struct clk_hw_omap dpll_disp_ck_hw = {
-	.hw = {
-		.clk	= &dpll_disp_ck,
-	},
-	.dpll_data	= &dpll_disp_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
-		   CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
-		   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_PERIPH,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_PER,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_PER,
-	.mult_mask	= AM33XX_DPLL_MULT_PERIPH_MASK,
-	.div1_mask	= AM33XX_DPLL_PER_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-	.flags		= DPLL_J_TYPE,
-};
-
-/* CLKDCOLDO */
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_per_ck,
-	},
-	.dpll_data	= &dpll_per_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/* CLKOUT: fdpll/M2 */
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		   AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-		   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-		   NULL);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
-			&dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
-			&dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
-			&dpll_core_m4_ck, 0x0, 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-			1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
-			8);
-
-/*
- * Below clock nodes describes clockdomains derived out
- * of core clock.
- */
-static const struct clk_ops clk_ops_null = {
-};
-
-static const char *l3_gclk_parents[] = {
-	"dpll_core_m4_ck"
-};
-
-static struct clk l3_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
-DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
-
-static struct clk l4hs_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
-DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
-
-static const char *l3s_gclk_parents[] = {
-	"dpll_core_m4_div2_ck"
-};
-
-static struct clk l3s_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
-DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4fw_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
-DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4ls_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
-DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk sysclk_div_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
-DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
-
-/*
- * In order to match the clock domain with hwmod clockdomain entry,
- * separate clock nodes is required for the modules which are
- * directly getting their funtioncal clock from sys_clkin.
- */
-static struct clk adc_tsc_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
-DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
-DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
-DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk sha0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
-DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk aes0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
-DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
-
-/*
- * Modules clock nodes
- *
- * The following clock leaf nodes are added for the moment because:
- *
- *  - hwmod data is not present for these modules, either hwmod
- *    control is not required or its not populated.
- *  - Driver code is not yet migrated to use hwmod/runtime pm
- *  - Modules outside kernel access (to disable them by default)
- *
- *     - mmu (gfx domain)
- *     - cefuse
- *     - usbotg_fck (its additional clock and not really a modulemode)
- *     - ieee5000
- */
-
-DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-		AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-		AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-/*
- * clkdiv32 is generated from fixed division of 732.4219
- */
-DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
-
-static struct clk clkdiv32k_ick;
-
-static const char *clkdiv32k_ick_parent_names[] = {
-	"clkdiv32k_ck",
-};
-
-static const struct clk_ops clkdiv32k_ick_ops = {
-	.enable         = &omap2_dflt_clk_enable,
-	.disable        = &omap2_dflt_clk_disable,
-	.is_enabled     = &omap2_dflt_clk_is_enabled,
-	.init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap clkdiv32k_ick_hw = {
-	.hw	= {
-		.clk	= &clkdiv32k_ick,
-	},
-	.enable_reg	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
-	.enable_bit	= AM33XX_MODULEMODE_SWCTRL_SHIFT,
-	.clkdm_name	= "clk_24mhz_clkdm",
-};
-
-DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
-
-/* "usbotg_fck" is an additional clock and not really a modulemode */
-DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
-		0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
-		AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-/* Timers */
-static const struct clksel timer1_clkmux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-	{ .parent = &tclkin_ck, .rates = div_1_2_rates },
-	{ .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
-	{ .parent = &clk_32768_ck, .rates = div_1_4_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer1_ck_parents[] = {
-	"sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
-	"clk_32768_ck",
-};
-
-static struct clk timer1_fck;
-
-static const struct clk_ops timer1_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap timer1_fck_hw = {
-	.hw	= {
-		.clk	= &timer1_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer1_clkmux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER1MS_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_2_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
-
-static const struct clksel timer2_to_7_clk_sel[] = {
-	{ .parent = &tclkin_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_clkin_ck, .rates = div_1_1_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer2_to_7_ck_parents[] = {
-	"tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
-};
-
-static struct clk timer2_fck;
-
-static struct clk_hw_omap timer2_fck_hw = {
-	.hw	= {
-		.clk	= &timer2_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER2_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer3_fck;
-
-static struct clk_hw_omap timer3_fck_hw = {
-	.hw	= {
-		.clk	= &timer3_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER3_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer4_fck;
-
-static struct clk_hw_omap timer4_fck_hw = {
-	.hw	= {
-		.clk	= &timer4_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER4_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer5_fck;
-
-static struct clk_hw_omap timer5_fck_hw = {
-	.hw	= {
-		.clk	= &timer5_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER5_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer6_fck;
-
-static struct clk_hw_omap timer6_fck_hw = {
-	.hw	= {
-		.clk	= &timer6_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER6_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer7_fck;
-
-static struct clk_hw_omap timer7_fck_hw = {
-	.hw	= {
-		.clk	= &timer7_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER7_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
-			"dpll_core_m5_ck",
-			&dpll_core_m5_ck,
-			0x0,
-			1, 2);
-
-static const struct clk_ops cpsw_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-};
-
-static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
-	{ .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *cpsw_cpts_rft_ck_parents[] = {
-	"dpll_core_m5_ck", "dpll_core_m4_ck",
-};
-
-static struct clk cpsw_cpts_rft_clk;
-
-static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
-	.hw	= {
-		.clk	= &cpsw_cpts_rft_clk,
-	},
-	.clkdm_name	= "cpsw_125mhz_clkdm",
-	.clksel		= cpsw_cpts_rft_clkmux_sel,
-	.clksel_reg	= AM33XX_CM_CPTS_RFT_CLKSEL,
-	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
-
-
-/* gpio */
-static const char *gpio0_ck_parents[] = {
-	"clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel gpio0_dbclk_mux_sel[] = {
-	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-	{ .parent = &clk_32768_ck, .rates = div_1_1_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const struct clk_ops gpio_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk gpio0_dbclk_mux_ck;
-
-static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
-	.hw	= {
-		.clk	= &gpio0_dbclk_mux_ck,
-	},
-	.clkdm_name	= "l4_wkup_clkdm",
-	.clksel		= gpio0_dbclk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_GPIO0_DBCLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
-
-DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
-		AM33XX_CM_WKUP_GPIO0_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO1_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO2_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO3_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
-
-
-static const char *pruss_ck_parents[] = {
-	"l3_gclk", "dpll_disp_m2_ck",
-};
-
-static const struct clksel pruss_ocp_clk_mux_sel[] = {
-	{ .parent = &l3_gclk, .rates = div_1_0_rates },
-	{ .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk pruss_ocp_gclk;
-
-static struct clk_hw_omap pruss_ocp_gclk_hw = {
-	.hw	= {
-		.clk	= &pruss_ocp_gclk,
-	},
-	.clkdm_name	= "pruss_ocp_clkdm",
-	.clksel		= pruss_ocp_clk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_PRUSS_OCP_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
-
-static const char *lcd_ck_parents[] = {
-	"dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel lcd_clk_mux_sel[] = {
-	{ .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static struct clk lcd_gclk;
-
-static struct clk_hw_omap lcd_gclk_hw = {
-	.hw	= {
-		.clk	= &lcd_gclk,
-	},
-	.clkdm_name	= "lcdc_clkdm",
-	.clksel		= lcd_clk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_LCDC_PIXEL_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
-			gpio_fck_ops, CLK_SET_RATE_PARENT);
-
-DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
-
-static const char *gfx_ck_parents[] = {
-	"dpll_core_m4_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel gfx_clksel_sel[] = {
-	{ .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk gfx_fclk_clksel_ck;
-
-static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
-	.hw	= {
-		.clk	= &gfx_fclk_clksel_ck,
-	},
-	.clksel		= gfx_clksel_sel,
-	.clksel_reg	= AM33XX_CLKSEL_GFX_FCLK,
-	.clksel_mask	= AM33XX_CLKSEL_GFX_FCLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
-
-static const struct clk_div_table div_1_0_2_1_rates[] = {
-	{ .div = 1, .val = 0, },
-	{ .div = 2, .val = 1, },
-	{ .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
-			 &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
-			 AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
-			 0x0, div_1_0_2_1_rates, NULL);
-
-static const char *sysclkout_ck_parents[] = {
-	"clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
-	"lcd_gclk",
-};
-
-static const struct clksel sysclkout_pre_sel[] = {
-	{ .parent = &clk_32768_ck, .rates = div_1_0_rates },
-	{ .parent = &l3_gclk, .rates = div_1_1_rates },
-	{ .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
-	{ .parent = &lcd_gclk, .rates = div_1_4_rates },
-	{ .parent = NULL },
-};
-
-static struct clk sysclkout_pre_ck;
-
-static struct clk_hw_omap sysclkout_pre_ck_hw = {
-	.hw	= {
-		.clk	= &sysclkout_pre_ck,
-	},
-	.clksel		= sysclkout_pre_sel,
-	.clksel_reg	= AM33XX_CM_CLKOUT_CTRL,
-	.clksel_mask	= AM33XX_CLKOUT2SOURCE_MASK,
-};
-
-DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
-
-/* Divide by 8 clock rates with default clock is 1/1*/
-static const struct clk_div_table div8_rates[] = {
-	{ .div = 1, .val = 0, },
-	{ .div = 2, .val = 1, },
-	{ .div = 3, .val = 2, },
-	{ .div = 4, .val = 3, },
-	{ .div = 5, .val = 4, },
-	{ .div = 6, .val = 5, },
-	{ .div = 7, .val = 6, },
-	{ .div = 8, .val = 7, },
-	{ .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
-			 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
-			 AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
-
-DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
-		AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
-
-static const char *wdt_ck_parents[] = {
-	"clk_rc32k_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel wdt_clkmux_sel[] = {
-	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk wdt1_fck;
-
-static struct clk_hw_omap wdt1_fck_hw = {
-	.hw	= {
-		.clk	= &wdt1_fck,
-	},
-	.clkdm_name	= "l4_wkup_clkdm",
-	.clksel		= wdt_clkmux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_WDT1_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
-
-static const char *pwmss_clk_parents[] = {
-	"dpll_per_m2_ck",
-};
-
-static const struct clk_ops ehrpwm_tbclk_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS0_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS1_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS2_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-/*
- * debugss optional clocks
- */
-DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
-		0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
-		0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
-
-static const char *stm_pmd_clock_mux_ck_parents[] = {
-	"dbg_sysclk_ck", "dbg_clka_ck",
-};
-
-DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-	       AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
-	       AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-	       AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-	       AM33XX_TRC_PMD_CLKSEL_SHIFT,
-	       AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
-		   &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		   AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
-		   AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
-		   &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		   AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
-		   AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-/*
- * clkdev
- */
-static struct omap_clk am33xx_clks[] = {
-	CLK(NULL,	"clk_32768_ck",		&clk_32768_ck),
-	CLK(NULL,	"clk_rc32k_ck",		&clk_rc32k_ck),
-	CLK(NULL,	"virt_19200000_ck",	&virt_19200000_ck),
-	CLK(NULL,	"virt_24000000_ck",	&virt_24000000_ck),
-	CLK(NULL,	"virt_25000000_ck",	&virt_25000000_ck),
-	CLK(NULL,	"virt_26000000_ck",	&virt_26000000_ck),
-	CLK(NULL,	"sys_clkin_ck",		&sys_clkin_ck),
-	CLK(NULL,	"tclkin_ck",		&tclkin_ck),
-	CLK(NULL,	"dpll_core_ck",		&dpll_core_ck),
-	CLK(NULL,	"dpll_core_x2_ck",	&dpll_core_x2_ck),
-	CLK(NULL,	"dpll_core_m4_ck",	&dpll_core_m4_ck),
-	CLK(NULL,	"dpll_core_m5_ck",	&dpll_core_m5_ck),
-	CLK(NULL,	"dpll_core_m6_ck",	&dpll_core_m6_ck),
-	CLK(NULL,	"dpll_mpu_ck",		&dpll_mpu_ck),
-	CLK("cpu0",	NULL,			&dpll_mpu_ck),
-	CLK(NULL,	"dpll_mpu_m2_ck",	&dpll_mpu_m2_ck),
-	CLK(NULL,	"dpll_ddr_ck",		&dpll_ddr_ck),
-	CLK(NULL,	"dpll_ddr_m2_ck",	&dpll_ddr_m2_ck),
-	CLK(NULL,	"dpll_ddr_m2_div2_ck",	&dpll_ddr_m2_div2_ck),
-	CLK(NULL,	"dpll_disp_ck",		&dpll_disp_ck),
-	CLK(NULL,	"dpll_disp_m2_ck",	&dpll_disp_m2_ck),
-	CLK(NULL,	"dpll_per_ck",		&dpll_per_ck),
-	CLK(NULL,	"dpll_per_m2_ck",	&dpll_per_m2_ck),
-	CLK(NULL,	"dpll_per_m2_div4_wkupdm_ck",	&dpll_per_m2_div4_wkupdm_ck),
-	CLK(NULL,	"dpll_per_m2_div4_ck",	&dpll_per_m2_div4_ck),
-	CLK(NULL,	"adc_tsc_fck",		&adc_tsc_fck),
-	CLK(NULL,	"cefuse_fck",		&cefuse_fck),
-	CLK(NULL,	"clkdiv32k_ck",		&clkdiv32k_ck),
-	CLK(NULL,	"clkdiv32k_ick",	&clkdiv32k_ick),
-	CLK(NULL,	"dcan0_fck",		&dcan0_fck),
-	CLK("481cc000.d_can",	NULL,		&dcan0_fck),
-	CLK(NULL,	"dcan1_fck",		&dcan1_fck),
-	CLK("481d0000.d_can",	NULL,		&dcan1_fck),
-	CLK(NULL,	"pruss_ocp_gclk",	&pruss_ocp_gclk),
-	CLK(NULL,	"mcasp0_fck",		&mcasp0_fck),
-	CLK(NULL,	"mcasp1_fck",		&mcasp1_fck),
-	CLK(NULL,	"mmu_fck",		&mmu_fck),
-	CLK(NULL,	"smartreflex0_fck",	&smartreflex0_fck),
-	CLK(NULL,	"smartreflex1_fck",	&smartreflex1_fck),
-	CLK(NULL,	"sha0_fck",		&sha0_fck),
-	CLK(NULL,	"aes0_fck",		&aes0_fck),
-	CLK(NULL,	"timer1_fck",		&timer1_fck),
-	CLK(NULL,	"timer2_fck",		&timer2_fck),
-	CLK(NULL,	"timer3_fck",		&timer3_fck),
-	CLK(NULL,	"timer4_fck",		&timer4_fck),
-	CLK(NULL,	"timer5_fck",		&timer5_fck),
-	CLK(NULL,	"timer6_fck",		&timer6_fck),
-	CLK(NULL,	"timer7_fck",		&timer7_fck),
-	CLK(NULL,	"usbotg_fck",		&usbotg_fck),
-	CLK(NULL,	"ieee5000_fck",		&ieee5000_fck),
-	CLK(NULL,	"wdt1_fck",		&wdt1_fck),
-	CLK(NULL,	"l4_rtc_gclk",		&l4_rtc_gclk),
-	CLK(NULL,	"l3_gclk",		&l3_gclk),
-	CLK(NULL,	"dpll_core_m4_div2_ck",	&dpll_core_m4_div2_ck),
-	CLK(NULL,	"l4hs_gclk",		&l4hs_gclk),
-	CLK(NULL,	"l3s_gclk",		&l3s_gclk),
-	CLK(NULL,	"l4fw_gclk",		&l4fw_gclk),
-	CLK(NULL,	"l4ls_gclk",		&l4ls_gclk),
-	CLK(NULL,	"clk_24mhz",		&clk_24mhz),
-	CLK(NULL,	"sysclk_div_ck",	&sysclk_div_ck),
-	CLK(NULL,	"cpsw_125mhz_gclk",	&cpsw_125mhz_gclk),
-	CLK(NULL,	"cpsw_cpts_rft_clk",	&cpsw_cpts_rft_clk),
-	CLK(NULL,	"gpio0_dbclk_mux_ck",	&gpio0_dbclk_mux_ck),
-	CLK(NULL,	"gpio0_dbclk",		&gpio0_dbclk),
-	CLK(NULL,	"gpio1_dbclk",		&gpio1_dbclk),
-	CLK(NULL,	"gpio2_dbclk",		&gpio2_dbclk),
-	CLK(NULL,	"gpio3_dbclk",		&gpio3_dbclk),
-	CLK(NULL,	"lcd_gclk",		&lcd_gclk),
-	CLK(NULL,	"mmc_clk",		&mmc_clk),
-	CLK(NULL,	"gfx_fclk_clksel_ck",	&gfx_fclk_clksel_ck),
-	CLK(NULL,	"gfx_fck_div_ck",	&gfx_fck_div_ck),
-	CLK(NULL,	"sysclkout_pre_ck",	&sysclkout_pre_ck),
-	CLK(NULL,	"clkout2_div_ck",	&clkout2_div_ck),
-	CLK(NULL,	"timer_32k_ck",		&clkdiv32k_ick),
-	CLK(NULL,	"timer_sys_ck",		&sys_clkin_ck),
-	CLK(NULL,	"dbg_sysclk_ck",	&dbg_sysclk_ck),
-	CLK(NULL,	"dbg_clka_ck",		&dbg_clka_ck),
-	CLK(NULL,	"stm_pmd_clock_mux_ck",	&stm_pmd_clock_mux_ck),
-	CLK(NULL,	"trace_pmd_clk_mux_ck",	&trace_pmd_clk_mux_ck),
-	CLK(NULL,	"stm_clk_div_ck",	&stm_clk_div_ck),
-	CLK(NULL,	"trace_clk_div_ck",	&trace_clk_div_ck),
-	CLK(NULL,	"clkout2_ck",		&clkout2_ck),
-	CLK("48300200.ehrpwm",	"tbclk",	&ehrpwm0_tbclk),
-	CLK("48302200.ehrpwm",	"tbclk",	&ehrpwm1_tbclk),
-	CLK("48304200.ehrpwm",	"tbclk",	&ehrpwm2_tbclk),
-};
-
-
-static const char *enable_init_clks[] = {
-	"dpll_ddr_m2_ck",
-	"dpll_mpu_m2_ck",
-	"l3_gclk",
-	"l4hs_gclk",
-	"l4fw_gclk",
-	"l4ls_gclk",
-	"clkout2_ck",	/* Required for external peripherals like, Audio codecs */
-};
-
-int __init am33xx_clk_init(void)
-{
-	if (soc_is_am33xx())
-		cpu_mask = RATE_IN_AM33XX;
-
-	omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
-
-	omap2_clk_disable_autoidle_all();
-
-	omap2_clk_enable_init_clocks(enable_init_clks,
-				     ARRAY_SIZE(enable_init_clks));
-
-	/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
-	 *    physically present, in such a case HWMOD enabling of
-	 *    clock would be failure with default parent. And timer
-	 *    probe thinks clock is already enabled, this leads to
-	 *    crash upon accessing timer 3 & 6 registers in probe.
-	 *    Fix by setting parent of both these timers to master
-	 *    oscillator clock.
-	 */
-
-	clk_set_parent(&timer3_fck, &sys_clkin_ck);
-	clk_set_parent(&timer6_fck, &sys_clkin_ck);
-	/*
-	 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
-	 * the design/spec, so as a result, for example, timer which supposed
-	 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
-	 * not expected by any use-case, so change WDT1 clock source to PRCM
-	 * 32KHz clock.
-	 */
-	clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
-
-	return 0;
-}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 54969b9..bcc0717 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,5 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
 					   apll.o clk-44xx.o clk-54xx.o \
-					   clk-7xx.o
+					   clk-7xx.o clk-33xx.o
 endif
-- 
1.7.9.5

[PATCHv5 22/31] CLK: TI: add interface clock support for OMAP3

[Tero Kristo]

OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti/interface.txt     |   45 +++++++++
 arch/arm/mach-omap2/clock.h                        |    6 --
 drivers/clk/ti/Makefile                            |    2 +-
 drivers/clk/ti/interface.c                         |  105 ++++++++++++++++++++
 include/linux/clk/ti.h                             |    7 ++
 5 files changed, 158 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt
 create mode 100644 drivers/clk/ti/interface.c

diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt
new file mode 100644
index 0000000..8b09ae7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/interface.txt
@@ -0,0 +1,45 @@
+Binding for Texas Instruments interface clock.
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features, including
+companion clock finding (match corresponding functional gate
+clock) and hardware autoidle enable / disable.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+
+Required properties:
+- compatible : shall be "ti,interface-clock"
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : base address for the control register
+
+Optional properties:
+- ti,enable-bit : bit shift for the bit enabling/disabling the clock
+		  (default 0)
+- ti,iclk-no-wait : flag for selecting non-waiting hw-ops
+- ti,iclk-hsotgusb : flag for selecting hsotgusb hw-ops
+- ti,iclk-dss : flag for selecting DSS interface clock hw-ops
+- ti,iclk-ssi : flag for selecting SSI interface clock hw-ops
+- ti,am35xx-clk : flag for selecting AM35xx interface clock hw-ops
+- ti,clkdm-name : parent clockdomain name
+
+Examples:
+	aes1_ick: aes1_ick at 48004a14 {
+		#clock-cells = <0>;
+		compatible = "ti,interface-clock";
+		clocks = <&security_l4_ick2>;
+		reg = <0x48004a14 0x4>;
+		ti,enable-bit = <3>;
+	};
+
+	cam_ick: cam_ick at 48004f10 {
+		#clock-cells = <0>;
+		compatible = "ti,interface-clock";
+		clocks = <&l4_ick>;
+		reg = <0x48004f10 0x4>;
+		ti,clkdm-name = "cam_clkdm";
+		ti,enable-bit = <0>;
+		ti,iclk-no-wait;
+	};
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 08c9aa6..685da9a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -285,14 +285,8 @@ extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 extern struct clk dummy_ck;
 
-extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
-extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
 extern const struct clk_hw_omap_ops clkhwops_apll54;
 extern const struct clk_hw_omap_ops clkhwops_apll96;
 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index bcc0717..01925fd 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,5 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
 					   apll.o clk-44xx.o clk-54xx.o \
-					   clk-7xx.o clk-33xx.o
+					   clk-7xx.o clk-33xx.o interface.o
 endif
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
new file mode 100644
index 0000000..a2e37da
--- /dev/null
+++ b/drivers/clk/ti/interface.c
@@ -0,0 +1,105 @@
+/*
+ * OMAP interface clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+
+static const struct clk_ops omap_interface_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+void __init of_omap_interface_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_init_data init = { 0 };
+	struct clk_hw_omap *clk_hw;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names = NULL;
+	int i;
+	u32 val;
+
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return;
+	}
+
+	clk_hw->hw.init = &init;
+	clk_hw->ops = &clkhwops_iclk_wait;
+	clk_hw->enable_reg = of_iomap(node, 0);
+
+	if (!of_property_read_u32(node, "ti,enable-bit", &val))
+		clk_hw->enable_bit = val;
+
+	if (of_property_read_bool(node, "ti,iclk-no-wait"))
+		clk_hw->ops = &clkhwops_iclk;
+
+	if (of_property_read_bool(node, "ti,iclk-hsotgusb"))
+		clk_hw->ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
+
+	if (of_property_read_bool(node, "ti,iclk-dss"))
+		clk_hw->ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+
+	if (of_property_read_bool(node, "ti,iclk-ssi"))
+		clk_hw->ops = &clkhwops_omap3430es2_iclk_ssi_wait;
+
+	if (of_property_read_bool(node, "ti,am35xx-clk"))
+		clk_hw->ops = &clkhwops_am35xx_ipss_wait;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
+
+	init.name = clk_name;
+	init.ops = &omap_interface_clk_ops;
+	init.flags = 0;
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap interface_clk %s must have parent(s)\n",
+		       __func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	init.num_parents = num_parents;
+	init.parent_names = parent_names;
+
+	clk = clk_register(NULL, &clk_hw->hw);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		omap2_init_clk_hw_omap_clocks(clk);
+		return;
+	}
+
+cleanup:
+	kfree(parent_names);
+	kfree(clk_hw);
+}
+CLK_OF_DECLARE(omap_interface_clk, "ti,interface-clock",
+	       of_omap_interface_clk_setup);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 8ff2c29..8076394 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -204,5 +204,12 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 extern const struct clk_hw_omap_ops clkhwops_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
+
+extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 
 #endif
-- 
1.7.9.5

[PATCHv5 22/31] CLK: TI: add interface clock support for OMAP3

[Mark Rutland]

On Fri, Aug 02, 2013 at 05:25:41PM +0100, Tero Kristo wrote:
> OMAP3 has interface clocks in addition to functional clocks, which
> require special handling for the autoidle and idle status register
> offsets mainly.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  .../devicetree/bindings/clock/ti/interface.txt     |   45 +++++++++
>  arch/arm/mach-omap2/clock.h                        |    6 --
>  drivers/clk/ti/Makefile                            |    2 +-
>  drivers/clk/ti/interface.c                         |  105 ++++++++++++++++++++
>  include/linux/clk/ti.h                             |    7 ++
>  5 files changed, 158 insertions(+), 7 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt
>  create mode 100644 drivers/clk/ti/interface.c
> 
> diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt
> new file mode 100644
> index 0000000..8b09ae7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ti/interface.txt
> @@ -0,0 +1,45 @@
> +Binding for Texas Instruments interface clock.
> +
> +This binding uses the common clock binding[1]. This clock is
> +quite much similar to the basic gate-clock [2], however,
> +it supports a number of additional features, including
> +companion clock finding (match corresponding functional gate
> +clock) and hardware autoidle enable / disable.
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +[2] Documentation/devicetree/bindings/clock/gate-clock.txt
> +
> +Required properties:
> +- compatible : shall be "ti,interface-clock"

It might make sense to be more specific: "ti,omap3-interface-clock".

> +- #clock-cells : from common clock binding; shall be set to 0
> +- clocks : link to phandle of parent clock
> +- reg : base address for the control register
> +
> +Optional properties:
> +- ti,enable-bit : bit shift for the bit enabling/disabling the clock
> +		  (default 0)
> +- ti,iclk-no-wait : flag for selecting non-waiting hw-ops
> +- ti,iclk-hsotgusb : flag for selecting hsotgusb hw-ops
> +- ti,iclk-dss : flag for selecting DSS interface clock hw-ops
> +- ti,iclk-ssi : flag for selecting SSI interface clock hw-ops
> +- ti,am35xx-clk : flag for selecting AM35xx interface clock hw-ops

I think these should be selected based on the compatible string. They're
mutually exclusive, and incompatible.

Thanks,
Mark.

[PATCHv5 22/31] CLK: TI: add interface clock support for OMAP3

[Tero Kristo]

On 08/13/2013 02:30 PM, Mark Rutland wrote:
> On Fri, Aug 02, 2013 at 05:25:41PM +0100, Tero Kristo wrote:
>> OMAP3 has interface clocks in addition to functional clocks, which
>> require special handling for the autoidle and idle status register
>> offsets mainly.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   .../devicetree/bindings/clock/ti/interface.txt     |   45 +++++++++
>>   arch/arm/mach-omap2/clock.h                        |    6 --
>>   drivers/clk/ti/Makefile                            |    2 +-
>>   drivers/clk/ti/interface.c                         |  105 ++++++++++++++++++++
>>   include/linux/clk/ti.h                             |    7 ++
>>   5 files changed, 158 insertions(+), 7 deletions(-)
>>   create mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt
>>   create mode 100644 drivers/clk/ti/interface.c
>>
>> diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt
>> new file mode 100644
>> index 0000000..8b09ae7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/ti/interface.txt
>> @@ -0,0 +1,45 @@
>> +Binding for Texas Instruments interface clock.
>> +
>> +This binding uses the common clock binding[1]. This clock is
>> +quite much similar to the basic gate-clock [2], however,
>> +it supports a number of additional features, including
>> +companion clock finding (match corresponding functional gate
>> +clock) and hardware autoidle enable / disable.
>> +
>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +[2] Documentation/devicetree/bindings/clock/gate-clock.txt
>> +
>> +Required properties:
>> +- compatible : shall be "ti,interface-clock"
>
> It might make sense to be more specific: "ti,omap3-interface-clock".

Ok.

>
>> +- #clock-cells : from common clock binding; shall be set to 0
>> +- clocks : link to phandle of parent clock
>> +- reg : base address for the control register
>> +
>> +Optional properties:
>> +- ti,enable-bit : bit shift for the bit enabling/disabling the clock
>> +		  (default 0)
>> +- ti,iclk-no-wait : flag for selecting non-waiting hw-ops
>> +- ti,iclk-hsotgusb : flag for selecting hsotgusb hw-ops
>> +- ti,iclk-dss : flag for selecting DSS interface clock hw-ops
>> +- ti,iclk-ssi : flag for selecting SSI interface clock hw-ops
>> +- ti,am35xx-clk : flag for selecting AM35xx interface clock hw-ops
>
> I think these should be selected based on the compatible string. They're
> mutually exclusive, and incompatible.

Ok, I'll change this for next rev so that each has its own compatible 
string.

Thanks for your comments Mark.

-Tero

[PATCHv5 23/31] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm

[Tero Kristo]

If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5cc5123..a6a59bd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -656,6 +656,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
 	if (oh->clkdm) {
 		return oh->clkdm;
 	} else if (oh->_clk) {
+		if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
+			return NULL;
 		clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
 		return  clk->clkdm;
 	}
-- 
1.7.9.5

[PATCHv5 24/31] CLK: TI: gate: add support for OMAP36xx dpllx_mx_ck:s

[Tero Kristo]

OMAP3630 dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
value after their respective PWRDN bits are set.  Any dummy write
(Any other value different from the Read value) to the
corresponding CM_CLKSEL register will refresh the dividers.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti/gate.txt          |    1 +
 drivers/clk/ti/gate.c                              |   58 +++++++++++++++++++-
 2 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
index 620a73d..9cebccb 100644
--- a/Documentation/devicetree/bindings/clock/ti/gate.txt
+++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
@@ -21,6 +21,7 @@ Optional properties:
 - ti,dss-clk : use DSS hardware OPS for the clock
 - ti,am35xx-clk : use AM35xx hardware OPS for the clock
 - ti,clkdm-name : clockdomain to control this gate
+- ti,hsdiv-restore : restore parent clock HSDIV value with enable
 
 Examples:
 	trace_clk_div_ck: trace_clk_div_ck {
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index 2c68310..f15fbec 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -17,10 +17,15 @@
 
 #include <linux/clk-provider.h>
 #include <linux/slab.h>
+#include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/clk/ti.h>
 
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
+
 static const struct clk_ops omap_gate_clkdm_clk_ops = {
 	.init		= &omap2_init_clk_clkdm,
 	.enable		= &omap2_clkops_enable_clkdm,
@@ -34,6 +39,54 @@ static const struct clk_ops omap_gate_clk_ops = {
 	.is_enabled	= &omap2_dflt_clk_is_enabled,
 };
 
+static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap36xx_gate_clk_enable_with_hsdiv_restore,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+/**
+ * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
+ *         from HSDivider PWRDN problem Implements Errata ID: i556.
+ * @clk: DPLL output struct clk
+ *
+ * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
+ * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
+ * valueafter their respective PWRDN bits are set.  Any dummy write
+ * (Any other value different from the Read value) to the
+ * corresponding CM_CLKSEL register will refresh the dividers.
+ */
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
+{
+	struct clk_divider *parent;
+	struct clk_hw *parent_hw;
+	u32 dummy_v, orig_v;
+	int ret;
+
+	/* Clear PWRDN bit of HSDIVIDER */
+	ret = omap2_dflt_clk_enable(clk);
+
+	/* Parent is the x2 node, get parent of parent for the m2 div */
+	parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
+	parent = to_clk_divider(parent_hw);
+
+	/* Restore the dividers */
+	if (!ret) {
+		orig_v = __raw_readl(parent->reg);
+		dummy_v = orig_v;
+
+		/* Write any other value different from the Read value */
+		dummy_v ^= (1 << parent->shift);
+		__raw_writel(dummy_v, parent->reg);
+
+		/* Write the original divider */
+		__raw_writel(orig_v, parent->reg);
+	}
+
+	return ret;
+}
+
 void __init of_omap_gate_clk_setup(struct device_node *node)
 {
 	struct clk *clk;
@@ -63,7 +116,10 @@ void __init of_omap_gate_clk_setup(struct device_node *node)
 		/* No register, clkdm control only */
 		init.ops = &omap_gate_clkdm_clk_ops;
 	} else {
-		init.ops = &omap_gate_clk_ops;
+		if (of_property_read_bool(node, "ti,hsdiv-restore"))
+			init.ops = &omap_gate_clk_hsdiv_restore_ops;
+		else
+			init.ops = &omap_gate_clk_ops;
 		clk_hw->enable_reg = of_iomap(node, 0);
 		of_property_read_u32(node, "ti,enable-bit", &val);
 		clk_hw->enable_bit = val;
-- 
1.7.9.5

[PATCHv5 25/31] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name

[Tero Kristo]

DT clocks are mostly missing clkdm info now, and this causes an issue with
counter32k which makes its slave idlemode wrong and prevents core idle.

Fixed by initializing the hwmod clkdm pointers for omap3 also which makes
sure the clkdm flag matching logic works properly.

This patch also changes the return value for _init_clkdm to 0 for
incorrect clkdm_name, as this a warning, not a fatal error.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index a6a59bd..da26659 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1544,7 +1544,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
 	if (!oh->clkdm) {
 		pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
 			oh->name, oh->clkdm_name);
-		return -EINVAL;
+		return 0;
 	}
 
 	pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
@@ -4115,6 +4115,7 @@ void __init omap_hwmod_init(void)
 		soc_ops.assert_hardreset = _omap2_assert_hardreset;
 		soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
 		soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+		soc_ops.init_clkdm = _init_clkdm;
 	} else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
 		soc_ops.enable_module = _omap4_enable_module;
 		soc_ops.disable_module = _omap4_disable_module;
-- 
1.7.9.5

[PATCHv5 26/31] ARM: dts: omap3 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP3 power,
reset and clock manager (PRCM).

TODO: add still missing am35xx only clock nodes

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap3.dtsi                       |    7 +
 arch/arm/boot/dts/omap3430es1-clocks.dtsi          |  170 +++
 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi    |  240 +++
 arch/arm/boot/dts/omap34xx.dtsi                    |    9 +
 .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi    |  214 +++
 arch/arm/boot/dts/omap36xx-clocks.dtsi             |   91 ++
 .../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi  |  185 +++
 arch/arm/boot/dts/omap36xx.dtsi                    |   10 +
 arch/arm/boot/dts/omap3xxx-clocks.dtsi             | 1589 ++++++++++++++++++++
 9 files changed, 2515 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3430es1-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap3xxx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 7d95cda..939cc20 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -533,4 +533,11 @@
 			ram-bits = <12>;
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap3xxx-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
new file mode 100644
index 0000000..b78f316
--- /dev/null
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -0,0 +1,170 @@
+/*
+ * Device Tree Source for OMAP3430 ES1 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+gfx_l3_ck: gfx_l3_ck at 48004b10 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004b10 0x4>;
+	ti,clkdm-name = "gfx_3430es1_clkdm";
+	ti,enable-bit = <0>;
+};
+
+gfx_l3_fck: gfx_l3_fck at 48004b40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004b40 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+gfx_l3_ick: gfx_l3_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&gfx_l3_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gfx_cg1_ck: gfx_cg1_ck at 48004b00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&gfx_l3_fck>;
+	reg = <0x48004b00 0x4>;
+	ti,clkdm-name = "gfx_3430es1_clkdm";
+	ti,enable-bit = <1>;
+};
+
+gfx_cg2_ck: gfx_cg2_ck at 48004b00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&gfx_l3_fck>;
+	reg = <0x48004b00 0x4>;
+	ti,clkdm-name = "gfx_3430es1_clkdm";
+	ti,enable-bit = <2>;
+};
+
+d2d_26m_fck: d2d_26m_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <3>;
+};
+
+fshostusb_fck: fshostusb_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <5>;
+};
+
+ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&corex2_fck>;
+	bit-shift = <8>;
+	reg = <0x48004a40 0x4>;
+	table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >;
+	bit-mask = <0xf>;
+};
+
+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&ssi_ssr_div_fck_3430es1>;
+	bit-shift = <0>;
+	reg = <0x48004a00 0x4>;
+};
+
+ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&ssi_ssr_fck_3430es1>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <4>;
+	ti,iclk-no-wait;
+};
+
+fac_ick: fac_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <8>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+ssi_ick_3430es1: ssi_ick_3430es1 at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&ssi_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-no-wait;
+};
+
+usb_l4_div_ick: usb_l4_div_ick at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l4_ick>;
+	bit-shift = <4>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+usb_l4_ick: usb_l4_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&usb_l4_div_ick>;
+	bit-shift = <5>;
+	reg = <0x48004a10 0x4>;
+};
+
+dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 at 48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m4x2_ck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <0>;
+};
+
+dss_ick_3430es1: dss_ick_3430es1 at 48004e10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48004e10 0x4>;
+	ti,clkdm-name = "dss_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-no-wait;
+};
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 0000000..8da7ba1
--- /dev/null
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -0,0 +1,240 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+security_l4_ick2: security_l4_ick2 {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+aes1_ick: aes1_ick at 48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <3>;
+};
+
+rng_ick: rng_ick at 48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <2>;
+};
+
+sha11_ick: sha11_ick at 48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <1>;
+};
+
+des1_ick: des1_ick at 48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <0>;
+};
+
+cam_mclk: cam_mclk at 48004f00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m5x2_ck>;
+	bit-shift = <0>;
+	reg = <0x48004f00 0x4>;
+	set-rate-parent;
+};
+
+cam_ick: cam_ick at 48004f10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48004f10 0x4>;
+	ti,clkdm-name = "cam_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-no-wait;
+};
+
+csi2_96m_fck: csi2_96m_fck at 48004f00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004f00 0x4>;
+	bit-shift = <1>;
+};
+
+security_l3_ick: security_l3_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+pka_ick: pka_ick at 48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l3_ick>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <4>;
+};
+
+icr_ick: icr_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <29>;
+};
+
+des2_ick: des2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <26>;
+};
+
+mspro_ick: mspro_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <23>;
+};
+
+mailboxes_ick: mailboxes_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <7>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sr1_fck: sr1_fck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004c00 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <6>;
+};
+
+sr2_fck: sr2_fck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004c00 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <7>;
+};
+
+sr_l4_ick: sr_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll2_fck: dpll2_fck at 48004040 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&core_ck>;
+	bit-shift = <19>;
+	reg = <0x48004040 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+dpll2_ck: dpll2_ck at 48004004 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,modes = <0xa2>;
+	ti,clk-bypass = <&dpll2_fck>;
+	reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>, <0x48004040 0x4>;
+	ti,clkdm-name = "dpll2_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x8>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x8>;
+};
+
+dpll2_m2_ck: dpll2_m2_ck at 48004044 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll2_ck>;
+	reg = <0x48004044 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+iva2_ck: iva2_ck at 48004000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll2_m2_ck>;
+	reg = <0x48004000 0x4>;
+	ti,clkdm-name = "iva2_clkdm";
+	ti,enable-bit = <0>;
+};
+
+modem_fck: modem_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <31>;
+};
+
+sad2d_ick: sad2d_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <3>;
+};
+
+mad2d_ick: mad2d_ick at 48004a18 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004a18 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <3>;
+};
+
+mspro_fck: mspro_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <23>;
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 5355d61..5f3c2ca 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -25,4 +25,13 @@
 			clock-latency = <300000>; /* From legacy driver */
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap34xx-omap36xx-clocks.dtsi"
+		/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+		/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..e0bdfb3
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,214 @@
+/*
+ * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll5_ck: dpll5_ck at 48004d04 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,modes = <0x82>;
+	ti,clk-bypass = <&sys_ck>;
+	reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+	ti,clkdm-name = "dpll5_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x19>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x19>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck at 48004d50 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll5_ck>;
+	reg = <0x48004d50 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+core_d3_ck: core_d3_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+core_d4_ck: core_d4_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+core_d6_ck: core_d6_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <6>;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+core_d2_ck: core_d2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+corex2_d3_fck: corex2_d3_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&corex2_fck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+corex2_d5_fck: corex2_d5_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&corex2_fck>;
+	clock-mult = <1>;
+	clock-div = <5>;
+};
+
+sgx_mux_fck: sgx_mux_fck at 48004b40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+	reg = <0x48004b40 0x4>;
+	table = <&core_d3_ck 0>, <&core_d4_ck 1>, <&core_d6_ck 2>, <&cm_96m_fck 3>, <&omap_192m_alwon_fck 4>, <&core_d2_ck 5>, <&corex2_d3_fck 6>, <&corex2_d5_fck 7>;
+	bit-mask = <0x7>;
+};
+
+sgx_fck: sgx_fck at 48004b00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sgx_mux_fck>;
+	bit-shift = <1>;
+	reg = <0x48004b00 0x4>;
+};
+
+sgx_ick: sgx_ick at 48004b10 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004b10 0x4>;
+	ti,clkdm-name = "sgx_clkdm";
+	ti,enable-bit = <0>;
+};
+
+cpefuse_fck: cpefuse_fck at 48004a08 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004a08 0x4>;
+	bit-shift = <0>;
+};
+
+ts_fck: ts_fck at 48004a08 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&omap_32k_fck>;
+	reg = <0x48004a08 0x4>;
+	bit-shift = <1>;
+};
+
+usbtll_fck: usbtll_fck at 48004a08 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll5_m2_ck>;
+	reg = <0x48004a08 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <2>;
+};
+
+usbtll_ick: usbtll_ick at 48004a18 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a18 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <2>;
+};
+
+mmchs3_ick: mmchs3_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <30>;
+};
+
+mmchs3_fck: mmchs3_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <30>;
+};
+
+dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 at 48004e00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m4x2_ck>;
+	reg = <0x48004e00 0x4>;
+	ti,clkdm-name = "dss_clkdm";
+	ti,enable-bit = <0>;
+	ti,dss-clk;
+};
+
+dss_ick_3430es2: dss_ick_3430es2 at 48004e10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48004e10 0x4>;
+	ti,clkdm-name = "dss_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-dss;
+};
+
+usbhost_120m_fck: usbhost_120m_fck at 48005400 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll5_m2_ck>;
+	reg = <0x48005400 0x4>;
+	bit-shift = <1>;
+};
+
+usbhost_48m_fck: usbhost_48m_fck at 48005400 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&omap_48m_fck>;
+	reg = <0x48005400 0x4>;
+	ti,clkdm-name = "usbhost_clkdm";
+	ti,enable-bit = <0>;
+	ti,dss-clk;
+};
+
+usbhost_ick: usbhost_ick at 48005410 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48005410 0x4>;
+	ti,clkdm-name = "usbhost_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-dss;
+};
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
new file mode 100644
index 0000000..300dcbf
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -0,0 +1,91 @@
+/*
+ * Device Tree Source for OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll4_ck: dpll4_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-per-j-type-clock";
+	clocks = <&sys_ck>;
+	ti,modes = <0x82>;
+	ti,clk-bypass = <&sys_ck>;
+	reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+	ti,clkdm-name = "dpll4_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x6>;
+	ti,auto-recal-bit = <0x13>;
+	ti,recal-st-bit = <0x6>;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m2x2_mul_ck>;
+	bit-shift = <0x1b>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll3_m3x2_mul_ck>;
+	bit-shift = <0xc>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m3x2_mul_ck>;
+	bit-shift = <0x1c>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m5x2_mul_ck>;
+	bit-shift = <0x1e>;
+	reg = <0x48004d00 0x4>;
+	ti,hsdiv-restore;
+	set-rate-parent;
+	set-bit-to-disable;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m6x2_mul_ck>;
+	bit-shift = <0x1f>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+uart4_fck: uart4_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&per_48m_fck>;
+	reg = <0x48005000 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <18>;
+};
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..0b93647
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,185 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&corex2_fck>;
+	bit-shift = <8>;
+	reg = <0x48004a40 0x4>;
+	table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >;
+	bit-mask = <0xf>;
+};
+
+ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&ssi_ssr_div_fck_3430es2>;
+	bit-shift = <0>;
+	reg = <0x48004a00 0x4>;
+};
+
+ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&ssi_ssr_fck_3430es2>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <4>;
+	ti,iclk-hsotgusb;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+ssi_ick_3430es2: ssi_ick_3430es2 at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&ssi_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-ssi;
+};
+
+dpll5_ck: dpll5_ck at 48004d04 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,modes = <0x82>;
+	ti,clk-bypass = <&sys_ck>;
+	reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+	ti,clkdm-name = "dpll5_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x19>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x19>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck at 48004d50 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll5_ck>;
+	reg = <0x48004d50 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <20>;
+};
+
+sys_d2_ck: sys_d2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+omap_96m_d2_fck: omap_96m_d2_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+omap_96m_d4_fck: omap_96m_d4_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+omap_96m_d8_fck: omap_96m_d8_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+omap_96m_d10_fck: omap_96m_d10_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <10>;
+};
+
+dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+usim_mux_fck: usim_mux_fck at 48004c40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_ck>, <&dpll5_m2_d20_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>;
+	bit-shift = <3>;
+	reg = <0x48004c40 0x4>;
+	table = <&sys_ck 1>, <&dpll5_m2_d20_ck 10>, <&sys_d2_ck 2>, <&omap_96m_d2_fck 3>, <&omap_96m_d4_fck 4>, <&omap_96m_d8_fck 5>, <&omap_96m_d10_fck 6>, <&dpll5_m2_d4_ck 7>, <&dpll5_m2_d8_ck 8>, <&dpll5_m2_d16_ck 9>;
+	bit-mask = <0xf>;
+};
+
+usim_fck: usim_fck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&usim_mux_fck>;
+	bit-shift = <9>;
+	reg = <0x48004c00 0x4>;
+};
+
+usim_ick: usim_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <9>;
+};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f8b3765..583c212 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -35,4 +35,14 @@
 			clock-frequency = <48000000>;
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap36xx-clocks.dtsi"
+		/include/ "omap34xx-omap36xx-clocks.dtsi"
+		/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+		/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
new file mode 100644
index 0000000..47ba8b4
--- /dev/null
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -0,0 +1,1589 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dummy_apb_pclk: dummy_apb_pclk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0x0>;
+};
+
+omap_32k_fck: omap_32k_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12m_ck: virt_12m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13m_ck: virt_13m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_38_4m_ck: virt_38_4m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+virt_16_8m_ck: virt_16_8m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+osc_sys_ck: osc_sys_ck at 48306d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+	reg = <0x48306d40 0x4>;
+	bit-mask = <0x7>;
+};
+
+sys_ck: sys_ck at 48307270 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&osc_sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48307270 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+dpll4_ck: dpll4_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-per-clock";
+	clocks = <&sys_ck>;
+	ti,modes = <0x82>;
+	ti,clk-bypass = <&sys_ck>;
+	reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+	ti,clkdm-name = "dpll4_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x6>;
+	ti,auto-recal-bit = <0x13>;
+	ti,recal-st-bit = <0x6>;
+};
+
+dpll4_m2_ck: dpll4_m2_ck at 48004d48 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	reg = <0x48004d48 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m2x2_mul_ck>;
+	bit-shift = <0x1b>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+omap_96m_alwon_fck: omap_96m_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll3_ck: dpll3_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-core-clock";
+	clocks = <&sys_ck>;
+	ti,clk-bypass = <&sys_ck>;
+	reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d40 0x4>;
+	ti,clk-ref = <&sys_ck>;
+	ti,clkdm-name = "dpll3_clkdm";
+	ti,recal-en-bit = <0x5>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x5>;
+};
+
+dpll3_m3_ck: dpll3_m3_ck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll3_ck>;
+	bit-shift = <16>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m3_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll3_m3x2_mul_ck>;
+	bit-shift = <0xc>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+emu_core_alwon_ck: emu_core_alwon_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sys_altclk: sys_altclk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0x0>;
+};
+
+mcbsp_clks: mcbsp_clks {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0x0>;
+};
+
+sys_clkout1: sys_clkout1 at 48306d70 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&osc_sys_ck>;
+	reg = <0x48306d70 0x4>;
+	bit-shift = <7>;
+};
+
+dpll3_m2_ck: dpll3_m2_ck at 48004d40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll3_ck>;
+	bit-shift = <27>;
+	reg = <0x48004d40 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+core_ck: core_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll1_fck: dpll1_fck at 48004940 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&core_ck>;
+	bit-shift = <19>;
+	reg = <0x48004940 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+dpll1_ck: dpll1_ck at 48004904 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>, <&dpll1_fck>;
+	ti,clk-bypass = <&dpll1_fck>;
+	reg = <0x48004904 0x4>, <0x48004924 0x4>, <0x48004934 0x4>, <0x48004940 0x4>;
+	ti,clk-ref = <&sys_ck>;
+	ti,clkdm-name = "dpll1_clkdm";
+	ti,recal-en-bit = <0x7>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x7>;
+};
+
+dpll1_x2_ck: dpll1_x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll1_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll1_x2m2_ck: dpll1_x2m2_ck at 48004944 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll1_x2_ck>;
+	reg = <0x48004944 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll3_x2_ck: dpll3_x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll3_m2x2_ck: dpll3_m2x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m2_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_x2_ck: dpll4_x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+cm_96m_fck: cm_96m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_alwon_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+omap_96m_fck: omap_96m_fck at 48004d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&cm_96m_fck>, <&sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48004d40 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll4_m3_ck: dpll4_m3_ck at 48004e40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	bit-shift = <8>;
+	reg = <0x48004e40 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m3_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m3x2_mul_ck>;
+	bit-shift = <0x1c>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+omap_54m_fck: omap_54m_fck at 48004d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+	bit-shift = <5>;
+	reg = <0x48004d40 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm_96m_d2_fck: cm_96m_d2_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&cm_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+omap_48m_fck: omap_48m_fck at 48004d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+	bit-shift = <3>;
+	reg = <0x48004d40 0x4>;
+	table = <&cm_96m_d2_fck 0>, <&sys_altclk 1>;
+	bit-mask = <0x1>;
+};
+
+omap_12m_fck: omap_12m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_48m_fck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+dpll4_m4_ck: dpll4_m4_ck at 48004e40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	reg = <0x48004e40 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m4_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m4x2_ck: dpll4_m4x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m4x2_mul_ck>;
+	bit-shift = <0x1d>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+dpll4_m5_ck: dpll4_m5_ck at 48004f40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	reg = <0x48004f40 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m5_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m5x2_mul_ck>;
+	bit-shift = <0x1e>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+dpll4_m6_ck: dpll4_m6_ck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	bit-shift = <24>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m6_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m6x2_mul_ck>;
+	bit-shift = <0x1f>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+emu_per_alwon_ck: emu_per_alwon_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m6x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+clkout2_src_mux_ck: clkout2_src_mux_ck at 48004d70 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+	reg = <0x48004d70 0x4>;
+	bit-mask = <0x3>;
+};
+
+clkout2_src_ck: clkout2_src_ck at 48004d70 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkout2_src_mux_ck>;
+	bit-shift = <7>;
+	reg = <0x48004d70 0x4>;
+};
+
+sys_clkout2: sys_clkout2 at 48004d70 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&clkout2_src_ck>;
+	bit-shift = <3>;
+	reg = <0x48004d70 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+corex2_fck: corex2_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mpu_ck: mpu_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll1_x2m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+arm_fck: arm_fck at 48004924 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mpu_ck>;
+	reg = <0x48004924 0x4>;
+	bit-mask = <0x1>;
+};
+
+emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&mpu_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3_ick: l3_ick at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&core_ck>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+l4_ick: l4_ick at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l3_ick>;
+	bit-shift = <2>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+rm_ick: rm_ick at 48004c40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l4_ick>;
+	bit-shift = <1>;
+	reg = <0x48004c40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+gpt10_mux_fck: gpt10_mux_fck at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt10_fck: gpt10_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt10_mux_fck>;
+	bit-shift = <11>;
+	reg = <0x48004a00 0x4>;
+};
+
+gpt11_mux_fck: gpt11_mux_fck at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <7>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt11_fck: gpt11_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt11_mux_fck>;
+	bit-shift = <12>;
+	reg = <0x48004a00 0x4>;
+};
+
+core_96m_fck: core_96m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mmchs2_fck: mmchs2_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <25>;
+};
+
+mmchs1_fck: mmchs1_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <24>;
+};
+
+i2c3_fck: i2c3_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <17>;
+};
+
+i2c2_fck: i2c2_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <16>;
+};
+
+i2c1_fck: i2c1_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <15>;
+};
+
+mcbsp5_mux_fck: mcbsp5_mux_fck at 480022d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <4>;
+	reg = <0x480022d8 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp5_fck: mcbsp5_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp5_mux_fck>;
+	bit-shift = <10>;
+	reg = <0x48004a00 0x4>;
+};
+
+mcbsp1_mux_fck: mcbsp1_mux_fck at 48002274 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <2>;
+	reg = <0x48002274 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp1_fck: mcbsp1_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp1_mux_fck>;
+	bit-shift = <9>;
+	reg = <0x48004a00 0x4>;
+};
+
+core_48m_fck: core_48m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_48m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mcspi4_fck: mcspi4_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <21>;
+};
+
+mcspi3_fck: mcspi3_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <20>;
+};
+
+mcspi2_fck: mcspi2_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <19>;
+};
+
+mcspi1_fck: mcspi1_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <18>;
+};
+
+uart2_fck: uart2_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <14>;
+};
+
+uart1_fck: uart1_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <13>;
+};
+
+core_12m_fck: core_12m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_12m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdq_fck: hdq_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_12m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <22>;
+};
+
+core_l3_ick: core_l3_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sdrc_ick: sdrc_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <1>;
+};
+
+gpmc_fck: gpmc_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_l3_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+core_l4_ick: core_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mmchs2_ick: mmchs2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <25>;
+};
+
+mmchs1_ick: mmchs1_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <24>;
+};
+
+hdq_ick: hdq_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <22>;
+};
+
+mcspi4_ick: mcspi4_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <21>;
+};
+
+mcspi3_ick: mcspi3_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <20>;
+};
+
+mcspi2_ick: mcspi2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <19>;
+};
+
+mcspi1_ick: mcspi1_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <18>;
+};
+
+i2c3_ick: i2c3_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <17>;
+};
+
+i2c2_ick: i2c2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <16>;
+};
+
+i2c1_ick: i2c1_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <15>;
+};
+
+uart2_ick: uart2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <14>;
+};
+
+uart1_ick: uart1_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <13>;
+};
+
+gpt11_ick: gpt11_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <12>;
+};
+
+gpt10_ick: gpt10_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <11>;
+};
+
+mcbsp5_ick: mcbsp5_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <10>;
+};
+
+mcbsp1_ick: mcbsp1_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <9>;
+};
+
+omapctrl_ick: omapctrl_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <6>;
+};
+
+dss_tv_fck: dss_tv_fck at 48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&omap_54m_fck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <2>;
+};
+
+dss_96m_fck: dss_96m_fck at 48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&omap_96m_fck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <2>;
+};
+
+dss2_alwon_fck: dss2_alwon_fck at 48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <1>;
+};
+
+gpt1_mux_fck: gpt1_mux_fck at 48004c40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	reg = <0x48004c40 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt1_fck: gpt1_fck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt1_mux_fck>;
+	bit-shift = <0>;
+	reg = <0x48004c00 0x4>;
+};
+
+aes2_ick: aes2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <28>;
+};
+
+wkup_32k_fck: wkup_32k_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpio1_dbck: gpio1_dbck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&wkup_32k_fck>;
+	reg = <0x48004c00 0x4>;
+	bit-shift = <3>;
+};
+
+sha12_ick: sha12_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <27>;
+};
+
+wdt2_fck: wdt2_fck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&wkup_32k_fck>;
+	reg = <0x48004c00 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <5>;
+};
+
+wkup_l4_ick: wkup_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+wdt2_ick: wdt2_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <5>;
+};
+
+wdt1_ick: wdt1_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <4>;
+};
+
+gpio1_ick: gpio1_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <3>;
+};
+
+omap_32ksync_ick: omap_32ksync_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <2>;
+};
+
+gpt12_ick: gpt12_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <1>;
+};
+
+gpt1_ick: gpt1_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <0>;
+};
+
+per_96m_fck: per_96m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_alwon_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+per_48m_fck: per_48m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_48m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+uart3_fck: uart3_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&per_48m_fck>;
+	reg = <0x48005000 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <11>;
+};
+
+gpt2_mux_fck: gpt2_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt2_fck: gpt2_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt2_mux_fck>;
+	bit-shift = <3>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt3_mux_fck: gpt3_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <1>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt3_fck: gpt3_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt3_mux_fck>;
+	bit-shift = <4>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt4_mux_fck: gpt4_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <2>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt4_fck: gpt4_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt4_mux_fck>;
+	bit-shift = <5>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt5_mux_fck: gpt5_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <3>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt5_fck: gpt5_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt5_mux_fck>;
+	bit-shift = <6>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt6_mux_fck: gpt6_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <4>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt6_fck: gpt6_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt6_mux_fck>;
+	bit-shift = <7>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt7_mux_fck: gpt7_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <5>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt7_fck: gpt7_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt7_mux_fck>;
+	bit-shift = <8>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt8_mux_fck: gpt8_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt8_fck: gpt8_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt8_mux_fck>;
+	bit-shift = <9>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt9_mux_fck: gpt9_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <7>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt9_fck: gpt9_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt9_mux_fck>;
+	bit-shift = <10>;
+	reg = <0x48005000 0x4>;
+};
+
+per_32k_alwon_fck: per_32k_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpio6_dbck: gpio6_dbck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <17>;
+};
+
+gpio5_dbck: gpio5_dbck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <16>;
+};
+
+gpio4_dbck: gpio4_dbck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <15>;
+};
+
+gpio3_dbck: gpio3_dbck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <14>;
+};
+
+gpio2_dbck: gpio2_dbck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <13>;
+};
+
+wdt3_fck: wdt3_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <12>;
+};
+
+per_l4_ick: per_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpio6_ick: gpio6_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <17>;
+};
+
+gpio5_ick: gpio5_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <16>;
+};
+
+gpio4_ick: gpio4_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <15>;
+};
+
+gpio3_ick: gpio3_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <14>;
+};
+
+gpio2_ick: gpio2_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <13>;
+};
+
+wdt3_ick: wdt3_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <12>;
+};
+
+uart3_ick: uart3_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <11>;
+};
+
+uart4_ick: uart4_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <18>;
+};
+
+gpt9_ick: gpt9_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <10>;
+};
+
+gpt8_ick: gpt8_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <9>;
+};
+
+gpt7_ick: gpt7_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <8>;
+};
+
+gpt6_ick: gpt6_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <7>;
+};
+
+gpt5_ick: gpt5_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <6>;
+};
+
+gpt4_ick: gpt4_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <5>;
+};
+
+gpt3_ick: gpt3_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <4>;
+};
+
+gpt2_ick: gpt2_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <3>;
+};
+
+mcbsp2_ick: mcbsp2_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <0>;
+};
+
+mcbsp3_ick: mcbsp3_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <1>;
+};
+
+mcbsp4_ick: mcbsp4_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <2>;
+};
+
+mcbsp2_mux_fck: mcbsp2_mux_fck at 48002274 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <6>;
+	reg = <0x48002274 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp2_fck: mcbsp2_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp2_mux_fck>;
+	bit-shift = <0>;
+	reg = <0x48005000 0x4>;
+};
+
+mcbsp3_mux_fck: mcbsp3_mux_fck at 480022d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_96m_fck>, <&mcbsp_clks>;
+	reg = <0x480022d8 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp3_fck: mcbsp3_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp3_mux_fck>;
+	bit-shift = <1>;
+	reg = <0x48005000 0x4>;
+};
+
+mcbsp4_mux_fck: mcbsp4_mux_fck at 480022d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <2>;
+	reg = <0x480022d8 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp4_fck: mcbsp4_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp4_mux_fck>;
+	bit-shift = <2>;
+	reg = <0x48005000 0x4>;
+};
+
+emu_src_mux_ck: emu_src_mux_ck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+};
+
+emu_src_ck: emu_src_ck {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&emu_src_mux_ck>;
+	ti,clkdm-name = "emu_clkdm";
+};
+
+pclk_fck: pclk_fck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&emu_src_ck>;
+	bit-shift = <8>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+pclkx2_fck: pclkx2_fck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&emu_src_ck>;
+	bit-shift = <6>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+atclk_fck: atclk_fck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&emu_src_ck>;
+	bit-shift = <4>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+traceclk_src_fck: traceclk_src_fck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+	bit-shift = <2>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+};
+
+traceclk_fck: traceclk_fck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&traceclk_src_fck>;
+	bit-shift = <11>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+secure_32k_fck: secure_32k_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+gpt12_fck: gpt12_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&secure_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+wdt1_fck: wdt1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&secure_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
-- 
1.7.9.5

[PATCHv5 27/31] CLK: TI: add omap3 clock init file

[Tero Kristo]

clk-3xxx.c now contains the clock init functionality for omap3, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock3xxx.h |    1 -
 drivers/clk/ti/Makefile         |    3 +-
 drivers/clk/ti/clk-3xxx.c       |  171 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h          |    1 +
 4 files changed, 174 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/ti/clk-3xxx.c

diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index dab90e2..78d9f56 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -11,7 +11,6 @@
 int omap3xxx_clk_init(void);
 int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
 					unsigned long parent_rate);
-void omap3_clk_lock_dpll5(void);
 
 extern struct clk *sdrc_ick_p;
 extern struct clk *arm_fck_p;
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 01925fd..119679b 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,5 +1,6 @@
 ifneq ($(CONFIG_OF),)
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
 					   apll.o clk-44xx.o clk-54xx.o \
-					   clk-7xx.o clk-33xx.o interface.o
+					   clk-7xx.o clk-33xx.o interface.o \
+					   clk-3xxx.o
 endif
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
new file mode 100644
index 0000000..727044b
--- /dev/null
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -0,0 +1,171 @@
+/*
+ * OMAP3 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ *     Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
+
+
+static struct omap_dt_clk omap3xxx_clks[] = {
+	DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
+	DT_CLK("twl", "fck", "osc_sys_ck"),
+	DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
+	DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
+	DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
+	DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
+	DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
+	DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
+	DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
+	DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
+	DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
+	DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
+	DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
+	DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
+	DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
+	DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
+	DT_CLK("omap_wdt", "ick", "wdt2_ick"),
+	DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"),
+	DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"),
+	DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
+	DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
+	DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
+	DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
+	{ NULL },
+};
+
+static struct omap_dt_clk omap34xx_omap36xx_clks[] = {
+	DT_CLK("omap_rng", "ick", "rng_ick"),
+	{ NULL },
+};
+
+static struct omap_dt_clk omap36xx_omap3430es2plus_clks[] = {
+	DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
+	DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
+	DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
+	DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
+	{ NULL },
+};
+
+static struct omap_dt_clk omap3430es1_clks[] = {
+	DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
+	DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
+	DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
+	DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
+	DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
+	DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
+	DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
+	{ NULL },
+};
+
+static struct omap_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
+	DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
+	DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
+	DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
+	DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
+	{ NULL },
+};
+
+static struct omap_dt_clk am35xx_clks[] = {
+	DT_CLK("davinci_emac.0", NULL, "emac_ick"),
+	DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
+	DT_CLK("vpfe-capture", "master", "vpfe_ick"),
+	DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
+	DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
+	DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
+	DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
+	DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
+	{ NULL },
+};
+
+static const char *enable_init_clks[] = {
+	"sdrc_ick",
+	"gpmc_fck",
+	"omapctrl_ick",
+};
+
+enum {
+	OMAP3_SOC_AM35XX,
+	OMAP3_SOC_OMAP3430_ES1,
+	OMAP3_SOC_OMAP3430_ES2_PLUS,
+	OMAP3_SOC_OMAP3630,
+	OMAP3_SOC_TI81XX,
+};
+
+static int __init omap3xxx_clk_init(int soc_type)
+{
+	of_clk_init(NULL);
+
+	if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
+	    soc_type == OMAP3_SOC_OMAP3430_ES1 ||
+	    soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
+		omap_dt_clocks_register(omap3xxx_clks);
+
+	if (soc_type == OMAP3_SOC_AM35XX)
+		omap_dt_clocks_register(am35xx_clks);
+
+	if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
+	    soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
+		omap_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
+
+	if (soc_type == OMAP3_SOC_OMAP3430_ES1)
+		omap_dt_clocks_register(omap3430es1_clks);
+
+	if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
+	    soc_type == OMAP3_SOC_OMAP3630)
+		omap_dt_clocks_register(omap36xx_omap3430es2plus_clks);
+
+	if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
+	    soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
+	    soc_type == OMAP3_SOC_OMAP3630)
+		omap_dt_clocks_register(omap34xx_omap36xx_clks);
+
+	omap2_clk_disable_autoidle_all();
+
+	omap2_clk_enable_init_clocks(enable_init_clks,
+				     ARRAY_SIZE(enable_init_clks));
+
+	pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+		(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
+		(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
+		(clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
+		(clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
+
+	if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1)
+		omap3_clk_lock_dpll5();
+
+	return 0;
+}
+
+int __init omap3430_clk_init(void)
+{
+	return omap3xxx_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
+}
+
+int __init omap3630_clk_init(void)
+{
+	return omap3xxx_clk_init(OMAP3_SOC_OMAP3630);
+}
+
+int __init am35xx_clk_init(void)
+{
+	return omap3xxx_clk_init(OMAP3_SOC_AM35XX);
+}
+
+int __init ti81xx_clk_init(void)
+{
+	return omap3xxx_clk_init(OMAP3_SOC_TI81XX);
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 8076394..adeddb4 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -187,6 +187,7 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 int omap2_dflt_clk_enable(struct clk_hw *hw);
 void omap2_dflt_clk_disable(struct clk_hw *hw);
 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
+void omap3_clk_lock_dpll5(void);
 
 void omap_dt_clocks_register(struct omap_dt_clk *oclks);
 #ifdef CONFIG_OF
-- 
1.7.9.5

[PATCHv5 28/31] ARM: dts: AM35xx clock data

[Tero Kristo]

This patch creates a unique node for each AM35xx specific clock in the
AM35xx power, reset and clock manager (PRCM). Most of the AM35xx clock
data is shared with OMAP3xxx, this patch only creates the delta.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/am35xx-clocks.dtsi |  113 ++++++++++++++++++++++++++++++++++
 1 file changed, 113 insertions(+)
 create mode 100644 arch/arm/boot/dts/am35xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
new file mode 100644
index 0000000..d28aa5c
--- /dev/null
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -0,0 +1,113 @@
+/*
+ * Device Tree Source for AM35xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+ipss_ick: ipss_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <4>;
+	ti,am35xx-clk;
+};
+
+rmii_ck: rmii_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <50000000>;
+};
+
+pclk_ck: pclk_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+emac_ick: emac_ick at 4800259c {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&ipss_ick>;
+	reg = <0x4800259c 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <1>;
+	ti,am35xx-clk;
+};
+
+emac_fck: emac_fck at 4800259c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&rmii_ck>;
+	reg = <0x4800259c 0x4>;
+	bit-shift = <9>;
+};
+
+vpfe_ick: vpfe_ick at 4800259c {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&ipss_ick>;
+	reg = <0x4800259c 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <2>;
+	ti,am35xx-clk;
+};
+
+vpfe_fck: vpfe_fck at 4800259c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pclk_ck>;
+	reg = <0x4800259c 0x4>;
+	bit-shift = <10>;
+};
+
+hsotgusb_ick_am35xx: hsotgusb_ick_am35xx at 4800259c {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&ipss_ick>;
+	reg = <0x4800259c 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <0>;
+	ti,am35xx-clk;
+};
+
+hsotgusb_fck_am35xx: hsotgusb_fck_am35xx at 4800259c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x4800259c 0x4>;
+	bit-shift = <8>;
+};
+
+hecc_ck: hecc_ck at 4800259c {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x4800259c 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <3>;
+	ti,am35xx-clk;
+};
+
+uart4_ick_am35xx: uart4_ick_am35xx at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <23>;
+};
+
+uart4_fck_am35xx: uart4_fck_am35xx at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <23>;
+};
-- 
1.7.9.5

[PATCHv5 29/31] ARM: dts: AM35xx: use DT clock data

[Tero Kristo]

AM35xx now uses the clock data from device tree. Most of the data is
shared with OMAP3xxx, but as there is some delta, a new base .dtsi
file is also created for the SoC.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/am3517-evm.dts        |    2 +-
 arch/arm/boot/dts/am3517.dtsi           |   36 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/am3517_mt_ventoux.dts |    2 +-
 3 files changed, 38 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/boot/dts/am3517.dtsi

diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index e99dfaf..9ff51d7 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-#include "omap34xx.dtsi"
+#include "am3517.dtsi"
 
 / {
 	model = "TI AM3517 EVM (AM3517/05)";
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
new file mode 100644
index 0000000..cb7a58d
--- /dev/null
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -0,0 +1,36 @@
+/*
+ * Device Tree Source for AM3517 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "omap3.dtsi"
+
+/ {
+	cpus {
+		cpu at 0 {
+			/* OMAP343x/OMAP35xx variants OPP1-5 */
+			operating-points = <
+				/* kHz    uV */
+				125000   975000
+				250000  1075000
+				500000  1200000
+				550000  1270000
+				600000  1350000
+			>;
+			clock-latency = <300000>; /* From legacy driver */
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "am35xx-clocks.dtsi"
+		/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+	};
+};
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index fdf5ce6..d00e934 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-#include "omap34xx.dtsi"
+#include "am3517.dtsi"
 
 / {
 	model = "TeeJet Mt.Ventoux";
-- 
1.7.9.5

[PATCHv5 30/31] ARM: OMAP3: use DT clock init if DT data is available

[Tero Kristo]

OMAP3 platforms support both DT and non-DT boot at the moment, make
the clock init work according to the used setup.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock3xxx.h |    4 ++++
 arch/arm/mach-omap2/io.c        |   13 ++++++++++++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 78d9f56..a5e2308 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,6 +9,10 @@
 #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
 
 int omap3xxx_clk_init(void);
+int omap3430_clk_init(void);
+int omap3630_clk_init(void);
+int ti81xx_clk_init(void);
+int am35xx_clk_init(void);
 int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
 					unsigned long parent_rate);
 
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index e8d5d75..e15d43b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -488,21 +488,29 @@ void __init omap3_init_early(void)
 void __init omap3430_init_early(void)
 {
 	omap3_init_early();
+	if (of_have_populated_dt())
+		omap_clk_init = omap3430_clk_init;
 }
 
 void __init omap35xx_init_early(void)
 {
 	omap3_init_early();
+	if (of_have_populated_dt())
+		omap_clk_init = omap3430_clk_init;
 }
 
 void __init omap3630_init_early(void)
 {
 	omap3_init_early();
+	if (of_have_populated_dt())
+		omap_clk_init = omap3630_clk_init;
 }
 
 void __init am35xx_init_early(void)
 {
 	omap3_init_early();
+	if (of_have_populated_dt())
+		omap_clk_init = am35xx_clk_init;
 }
 
 void __init ti81xx_init_early(void)
@@ -520,7 +528,10 @@ void __init ti81xx_init_early(void)
 	omap3xxx_clockdomains_init();
 	omap3xxx_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap_clk_init = omap3xxx_clk_init;
+	if (of_have_populated_dt())
+		omap_clk_init = ti81xx_clk_init;
+	else
+		omap_clk_init = omap3xxx_clk_init;
 }
 
 void __init omap3_init_late(void)
-- 
1.7.9.5

[PATCHv5 31/31] ARM: dts: am43xx clock data

[Tero Kristo]

This patch creates a unique node for each clock in the AM43xx power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/am43xx-clocks.dtsi |  671 ++++++++++++++++++++++++++++++++++
 1 file changed, 671 insertions(+)
 create mode 100644 arch/arm/boot/dts/am43xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
new file mode 100644
index 0000000..16dc0ea
--- /dev/null
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -0,0 +1,671 @@
+/*
+ * Device Tree Source for AM43xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clk_32768_ck: clk_32768_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+clk_rc32k_ck: clk_rc32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_24000000_ck: virt_24000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <24000000>;
+};
+
+virt_25000000_ck: virt_25000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <25000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+sys_clkin_ck: sys_clkin_ck at 44e10040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+	bit-shift = <22>;
+	reg = <0x44e10040 0x4>;
+	bit-mask = <0x3>;
+};
+
+tclkin_ck: tclkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+dpll_core_ck: dpll_core_ck at 44df2d20 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-core-lock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44df2d20 0x4>, <0x44df2d24 0x4>, <0x0 0x4>, <0x44df2d2c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_core_ck>;
+};
+
+dpll_core_m4_ck: dpll_core_m4_ck at 44df2d38 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x44df2d38 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_m5_ck: dpll_core_m5_ck at 44df2d3c {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x44df2d3c 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_m6_ck: dpll_core_m6_ck at 44df2d40 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x44df2d40 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 44df2d60 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44df2d60 0x4>, <0x44df2d64 0x4>, <0x0 0x4>, <0x44df2d6c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 44df2d70 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x44df2d70 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_ddr_ck: dpll_ddr_ck at 44df2da0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44df2da0 0x4>, <0x44df2da4 0x4>, <0x0 0x4>, <0x44df2dac 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck at 44df2db0 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_ddr_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x44df2db0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_disp_ck: dpll_disp_ck at 44df2e20 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44df2e20 0x4>, <0x44df2e24 0x4>, <0x0 0x4>, <0x44df2e2c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_disp_m2_ck: dpll_disp_m2_ck at 44df2e30 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_disp_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x44df2e30 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_ck: dpll_per_ck at 44df2de0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-j-type-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44df2de0 0x4>, <0x44df2de4 0x4>, <0x0 0x4>, <0x44df2dec 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 44df2df0 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_per_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x44df2df0 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+adc_tsc_fck: adc_tsc_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+clk_24mhz: clk_24mhz {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+clkdiv32k_ck: clkdiv32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&clk_24mhz>;
+	clock-mult = <1>;
+	clock-div = <732>;
+};
+
+clkdiv32k_ick: clkdiv32k_ick at 44df2a38 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ck>;
+	bit-shift = <8>;
+	reg = <0x44df2a38 0x4>;
+};
+
+dcan0_fck: dcan0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dcan1_fck: dcan1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sysclk_div: sysclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+pruss_ocp_gclk: pruss_ocp_gclk at 44df4248 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
+	reg = <0x44df4248 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcasp0_fck: mcasp0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mcasp1_fck: mcasp1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+smartreflex0_fck: smartreflex0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+smartreflex1_fck: smartreflex1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sha0_fck: sha0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+aes0_fck: aes0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+clk_32k_tpm_ck: clk_32k_tpm_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+timer1_fck: timer1_fck at 44df4200 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+	reg = <0x44df4200 0x4>;
+	bit-mask = <0x7>;
+};
+
+timer2_fck: timer2_fck at 44df4204 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44df4204 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer3_fck: timer3_fck at 44df4208 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44df4208 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer4_fck: timer4_fck at 44df420c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44df420c 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer5_fck: timer5_fck at 44df4210 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44df4210 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer6_fck: timer6_fck at 44df4214 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44df4214 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer7_fck: timer7_fck at 44df4218 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44df4218 0x4>;
+	bit-mask = <0x3>;
+};
+
+wdt1_fck: wdt1_fck at 44df422c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+	reg = <0x44df422c 0x4>;
+	bit-mask = <0x1>;
+};
+
+l3_gclk: l3_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sysclk_div>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+l4hs_gclk: l4hs_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3s_gclk: l3s_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l4ls_gclk: l4ls_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m5_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk at 44df4238 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
+	reg = <0x44df4238 0x4>;
+	bit-mask = <0x3>;
+};
+
+clk_32k_mosc_ck: clk_32k_mosc_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck at 44df4240 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
+	reg = <0x44df4240 0x4>;
+	bit-mask = <0x7>;
+};
+
+gpio0_dbclk: gpio0_dbclk at 44df2b68 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpio0_dbclk_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x44df2b68 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk at 44df8c78 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <8>;
+	reg = <0x44df8c78 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 44df8c80 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <8>;
+	reg = <0x44df8c80 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 44df8c88 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <8>;
+	reg = <0x44df8c88 0x4>;
+};
+
+mmc_clk: mmc_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck at 44df423c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
+	bit-shift = <1>;
+	reg = <0x44df423c 0x4>;
+	bit-mask = <0x1>;
+};
+
+gfx_fck_div_ck: gfx_fck_div_ck at 44df423c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&gfx_fclk_clksel_ck>;
+	reg = <0x44df423c 0x4>;
+	bit-mask = <0x1>;
+};
+
+disp_clk: disp_clk at 44df4244 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+	reg = <0x44df4244 0x4>;
+	bit-mask = <0x3>;
+};
+
+dpll_extdev_ck: dpll_extdev_ck at 44df2e60 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44df2e60 0x4>, <0x44df2e64 0x4>, <0x0 0x4>, <0x44df2e6c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_extdev_m2_ck: dpll_extdev_m2_ck at 44df2e70 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_extdev_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x44df2e70 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+mux_synctimer32k_ck: mux_synctimer32k_ck at 44df4230 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
+	reg = <0x44df4230 0x4>;
+	bit-mask = <0x3>;
+};
+
+synctimer_32kclk: synctimer_32kclk at 44df2a30 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mux_synctimer32k_ck>;
+	bit-shift = <8>;
+	reg = <0x44df2a30 0x4>;
+};
+
+timer8_fck: timer8_fck at 44df421c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+	reg = <0x44df421c 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer9_fck: timer9_fck at 44df4220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+	reg = <0x44df4220 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer10_fck: timer10_fck at 44df4224 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+	reg = <0x44df4224 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer11_fck: timer11_fck at 44df4228 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+	reg = <0x44df4228 0x4>;
+	bit-mask = <0x3>;
+};
+
+cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m5_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&cpsw_50m_clkdiv>;
+	clock-mult = <1>;
+	clock-div = <10>;
+};
+
+dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-x2-clock";
+	clocks = <&dpll_ddr_ck>;
+};
+
+dpll_ddr_m4_ck: dpll_ddr_m4_ck at 44df2db8 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_ddr_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x44df2db8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_clkdcoldo: dpll_per_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dll_aging_clk_div: dll_aging_clk_div at 44df4250 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44df4250 0x4>;
+	table = < 8 0 >, < 16 1 >, < 32 2 >;
+	bit-mask = <0x3>;
+};
+
+div_core_25m_ck: div_core_25m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sysclk_div>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+func_12m_clk: func_12m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+vtp_clk_div: vtp_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+usbphy_32khz_clkmux: usbphy_32khz_clkmux at 44df4260 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+	reg = <0x44df4260 0x4>;
+	bit-mask = <0x1>;
+};
-- 
1.7.9.5