[PATCH v4 0/5] clk/exynos5420: add clocks for hdmi subsystem

[PATCH v4 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Rahul Sharma]

Add clock changes for hdmi subsystem for exynos5250 SoC. These
include addition of new clocks like mout_hdmi and smmu_tv, associating
ID to clk_hdmiphy and some essential corrections.

V4:
1) Optimised gaps between Gate, Muxes and Dividers.

V3:
1) Assign new ID to divider clock keeping sclk_pixel gate same.

V2:
1) Rebase to Mike's Tree.
2) Change smmu_tv to smmu_mixer.

This set is based on Mike's clk-next branch at
https://git.linaro.org/gitweb?p=people/mturquette/linux.git

Rahul Sharma (5):
  clk/exynos5420: add sclk_hdmiphy to the list of special clocks
  clk/exynos5420: add gate clock for mixer sysmmu
  clk/exynos5420: fix the order of parents of hdmi mux
  clk/exynos5420: add hdmi mux to change parents in hdmi driver
  clk/exynos5420: assign dout_pixel id to pixel clock divider

 .../devicetree/bindings/clock/exynos5420-clock.txt  |   12 ++++++++++++
 drivers/clk/samsung/clk-exynos5420.c                |   19 +++++++++++++------
 2 files changed, 25 insertions(+), 6 deletions(-)

-- 
1.7.10.4

[PATCH v4 1/5] clk/exynos5420: add sclk_hdmiphy to the list of special clocks

[Rahul Sharma]

Add sclk_hdmiphy to the list of exposed clocks. This is required
by hdmi driver to change the parent of hdmi clock.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 Documentation/devicetree/bindings/clock/exynos5420-clock.txt |    1 +
 drivers/clk/samsung/clk-exynos5420.c                         |    4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 9bcc4b1..596a368 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -59,6 +59,7 @@ clock which they consume.
   sclk_pwm		155
   sclk_gscl_wa		156
   sclk_gscl_wb		157
+  sclk_hdmiphy		158
 
    [Peripheral Clock Gates]
 
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index e035fd0..a86cadc 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -120,7 +120,7 @@ enum exynos5420_clks {
 	sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
 	sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
 	sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
-	sclk_pwm, sclk_gscl_wa, sclk_gscl_wb,
+	sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,
 
 	/* gate clocks */
 	aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
@@ -297,7 +297,7 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initda
 
 /* fixed rate clocks generated inside the soc */
 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
-	FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
+	FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
 	FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
 	FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
 	FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
-- 
1.7.10.4

[PATCH v4 2/5] clk/exynos5420: add gate clock for mixer sysmmu

[Rahul Sharma]

Adding sysmmu clock for mixer for exynos5420.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 Documentation/devicetree/bindings/clock/exynos5420-clock.txt |    1 +
 drivers/clk/samsung/clk-exynos5420.c                         |    3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 596a368..5758a69 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -180,6 +180,7 @@ clock which they consume.
   fimc_lite3		495
   aclk_g3d		500
   g3d			501
+  smmu_mixer		502
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index a86cadc..4e0c13e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -138,7 +138,7 @@ enum exynos5420_clks {
 	aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
 	gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
 	aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
-	smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d,
+	smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,
 
 	nr_clks,
 };
@@ -725,6 +725,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 	GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),
 	GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),
 	GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
+	GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0),
 };
 
 static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
-- 
1.7.10.4

[PATCH v4 3/5] clk/exynos5420: fix the order of parents of hdmi mux

[Rahul Sharma]

Listing sclk_hdmiphy at 0th position in the list of parents is
causing wrong configuration in reg SRC_DISP10.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 4e0c13e..522c033 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -286,7 +286,7 @@ PNAME(audio2_p)	= { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
 		  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
 PNAME(spdif_p)	= { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
 		  "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(hdmi_p)	= { "sclk_hdmiphy", "dout_hdmi_pixel" };
+PNAME(hdmi_p)	= { "dout_hdmi_pixel", "sclk_hdmiphy" };
 PNAME(maudio0_p)	= { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
 			  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
 
-- 
1.7.10.4

[PATCH v4 4/5] clk/exynos5420: add hdmi mux to change parents in hdmi driver

[Rahul Sharma]

hdmi driver needs to change the parent of hdmi clock
to pixel clock or hdmiphy clock, based on the stability
of hdmiphy. This patch is exposing the mux for changing
the parent.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 Documentation/devicetree/bindings/clock/exynos5420-clock.txt |    5 +++++
 drivers/clk/samsung/clk-exynos5420.c                         |    5 ++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 5758a69..343430b 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -182,6 +182,11 @@ clock which they consume.
   g3d			501
   smmu_mixer		502
 
+  Mux			ID
+  ----------------------------
+
+  mout_hdmi		640
+
 Example 1: An example of a clock controller node is listed below.
 
 	clock: clock-controller at 0x10010000 {
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 522c033..78465a5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -140,6 +140,9 @@ enum exynos5420_clks {
 	aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
 	smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,
 
+	/* mux clocks */
+	mout_hdmi = 640,
+
 	nr_clks,
 };
 
@@ -400,7 +403,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 	MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
 	MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
 	MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
-	MUX(none, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
+	MUX(mout_hdmi, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
 
 	/* MAU Block */
 	MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
-- 
1.7.10.4

[PATCH v4 5/5] clk/exynos5420: assign dout_pixel id to pixel clock divider

[Rahul Sharma]

dout_pixel is a new ID allocated for pixel clock divider. It is
queried in the driver to pass as the parent to hdmi clock while
switching between parents.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 Documentation/devicetree/bindings/clock/exynos5420-clock.txt |    5 +++++
 drivers/clk/samsung/clk-exynos5420.c                         |    5 ++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 343430b..32aa34e 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -187,6 +187,11 @@ clock which they consume.
 
   mout_hdmi		640
 
+  Divider		ID
+  ----------------------------
+
+  dout_pixel		768
+
 Example 1: An example of a clock controller node is listed below.
 
 	clock: clock-controller at 0x10010000 {
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 78465a5..48c4a93 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -143,6 +143,9 @@ enum exynos5420_clks {
 	/* mux clocks */
 	mout_hdmi = 640,
 
+	/* divider clocks */
+	dout_pixel = 768,
+
 	nr_clks,
 };
 
@@ -463,7 +466,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 	DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
 	DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
 	DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
-	DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
+	DIV(dout_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
 
 	/* Audio Block */
 	DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
-- 
1.7.10.4

[PATCH v4 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Tomasz Figa]

Hi Rahul,

On Thursday 29 of August 2013 11:07:04 Rahul Sharma wrote:
> Add clock changes for hdmi subsystem for exynos5250 SoC. These
> include addition of new clocks like mout_hdmi and smmu_tv, associating
> ID to clk_hdmiphy and some essential corrections.
> 
> V4:
> 1) Optimised gaps between Gate, Muxes and Dividers.
> 
> V3:
> 1) Assign new ID to divider clock keeping sclk_pixel gate same.
> 
> V2:
> 1) Rebase to Mike's Tree.
> 2) Change smmu_tv to smmu_mixer.
> 
> This set is based on Mike's clk-next branch at
> https://git.linaro.org/gitweb?p=people/mturquette/linux.git
> 
> Rahul Sharma (5):
>   clk/exynos5420: add sclk_hdmiphy to the list of special clocks
>   clk/exynos5420: add gate clock for mixer sysmmu
>   clk/exynos5420: fix the order of parents of hdmi mux
>   clk/exynos5420: add hdmi mux to change parents in hdmi driver
>   clk/exynos5420: assign dout_pixel id to pixel clock divider
> 
>  .../devicetree/bindings/clock/exynos5420-clock.txt  |   12 ++++++++++++
>  drivers/clk/samsung/clk-exynos5420.c                |   19
> +++++++++++++------ 2 files changed, 25 insertions(+), 6 deletions(-)

For the whole series:

Acked-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

[PATCH v4 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Rahul Sharma]

On 29 August 2013 18:00, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Rahul,
>
> On Thursday 29 of August 2013 11:07:04 Rahul Sharma wrote:
>> Add clock changes for hdmi subsystem for exynos5250 SoC. These
>> include addition of new clocks like mout_hdmi and smmu_tv, associating
>> ID to clk_hdmiphy and some essential corrections.
>>
>> V4:
>> 1) Optimised gaps between Gate, Muxes and Dividers.
>>
>> V3:
>> 1) Assign new ID to divider clock keeping sclk_pixel gate same.
>>
>> V2:
>> 1) Rebase to Mike's Tree.
>> 2) Change smmu_tv to smmu_mixer.
>>
>> This set is based on Mike's clk-next branch at
>> https://git.linaro.org/gitweb?p=people/mturquette/linux.git
>>
>> Rahul Sharma (5):
>>   clk/exynos5420: add sclk_hdmiphy to the list of special clocks
>>   clk/exynos5420: add gate clock for mixer sysmmu
>>   clk/exynos5420: fix the order of parents of hdmi mux
>>   clk/exynos5420: add hdmi mux to change parents in hdmi driver
>>   clk/exynos5420: assign dout_pixel id to pixel clock divider
>>
>>  .../devicetree/bindings/clock/exynos5420-clock.txt  |   12 ++++++++++++
>>  drivers/clk/samsung/clk-exynos5420.c                |   19
>> +++++++++++++------ 2 files changed, 25 insertions(+), 6 deletions(-)
>
> For the whole series:
>
> Acked-by: Tomasz Figa <t.figa@samsung.com>
>

Thanks Tomasz,

Mike ! please consider it for clk-next branch.

regards,
Rahul Sharma.

> Best regards,
> Tomasz
>

[PATCH v4 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Mike Turquette]

Quoting Rahul Sharma (2013-08-29 06:36:51)
> On 29 August 2013 18:00, Tomasz Figa <t.figa@samsung.com> wrote:
> > Hi Rahul,
> >
> > On Thursday 29 of August 2013 11:07:04 Rahul Sharma wrote:
> >> Add clock changes for hdmi subsystem for exynos5250 SoC. These
> >> include addition of new clocks like mout_hdmi and smmu_tv, associating
> >> ID to clk_hdmiphy and some essential corrections.
> >>
> >> V4:
> >> 1) Optimised gaps between Gate, Muxes and Dividers.
> >>
> >> V3:
> >> 1) Assign new ID to divider clock keeping sclk_pixel gate same.
> >>
> >> V2:
> >> 1) Rebase to Mike's Tree.
> >> 2) Change smmu_tv to smmu_mixer.
> >>
> >> This set is based on Mike's clk-next branch at
> >> https://git.linaro.org/gitweb?p=people/mturquette/linux.git
> >>
> >> Rahul Sharma (5):
> >>   clk/exynos5420: add sclk_hdmiphy to the list of special clocks
> >>   clk/exynos5420: add gate clock for mixer sysmmu
> >>   clk/exynos5420: fix the order of parents of hdmi mux
> >>   clk/exynos5420: add hdmi mux to change parents in hdmi driver
> >>   clk/exynos5420: assign dout_pixel id to pixel clock divider
> >>
> >>  .../devicetree/bindings/clock/exynos5420-clock.txt  |   12 ++++++++++++
> >>  drivers/clk/samsung/clk-exynos5420.c                |   19
> >> +++++++++++++------ 2 files changed, 25 insertions(+), 6 deletions(-)
> >
> > For the whole series:
> >
> > Acked-by: Tomasz Figa <t.figa@samsung.com>
> >
> 
> Thanks Tomasz,
> 
> Mike ! please consider it for clk-next branch.

Taken into clk-next.

Regards,
Mike

> 
> regards,
> Rahul Sharma.
> 
> > Best regards,
> > Tomasz
> >