From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Fri, 30 Aug 2013 15:30:52 +0100 Subject: [PATCH] ARM64: KVM: Fix coherent_icache_guest_page() for host with external L3-cache. In-Reply-To: References: <20130816171912.GB20246@cbox> <20130816175034.GE20246@cbox> <20130830095215.GC62188@MacBook-Pro.local> <20130830140446.GA14125@darko.cambridge.arm.com> Message-ID: <20130830143052.GH12160@mudshark.cambridge.arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Aug 30, 2013 at 03:22:11PM +0100, Marc Zyngier wrote: > On 2013-08-30 15:04, Catalin Marinas wrote: > > On Fri, Aug 30, 2013 at 02:21:57PM +0100, Marc Zyngier wrote: > >> On 2013-08-30 11:44, Anup Patel wrote: > >> > For KVM, we can avoid flushing d-cache to PoC every time in > >> > coherent_icache_guest_page() by only doing it when Guest MMU is > >> > turned-off. This may reduce the performance penalty. > >> > >> What about the I and C bits in SCTLR_EL1? Does L3 also honour these > >> bits? > > > > I would think so, it probably cares about how the transactions are > > presented at the bus level by the CPU. > > That'd make sense indeed. So we need to track both SCTLR_EL1.{I,C,M} in > order to find out whether or not we need to clean the cache. Could you use a dummy ATS_* operation, then read the cacheability attributes out of the PAR? Will