* [PATCH v2 0/4] Add Core Divider clock support for Armada 370/XP @ 2013-09-26 19:35 Ezequiel Garcia 2013-09-26 19:35 ` [PATCH v2 1/4] clk: mvebu: Add Core Divider clock Ezequiel Garcia ` (3 more replies) 0 siblings, 4 replies; 16+ messages in thread From: Ezequiel Garcia @ 2013-09-26 19:35 UTC (permalink / raw) To: linux-arm-kernel This patchset adds support for a set of clocks available in Armada 370/XP known as "Core Divider" clocks. These are a set of gatable clocks, derived from a fixed PLL at a configurable ratio. Although this patchset adds support for the more general case, we only support one of the clocks, namely the NAND clock. With this infrastructure in place, the addition of the rest of the clocks would be fairly easy. A pictorical representation of the clock tree would be: PLL | | --------------------- | | | | NAND clock ... This patchset is based on v3.12-rc2. Any opinions are highly appreciated. Thanks! Changes from v1: * The most significative change is the simplification of the NAND clock tree. Instead of exposing two clocks: NAND ECC and NAND, we choose a simpler approach and view both clocks as one. The only impact these simplification has is that the NAND controller driver will have to divide the rate by two when using it to calculate the timings. * A spinlock protecting the enable, disable and set_rate operations is added as noted by Andrew Lunn. * The round_rate algorithm was also simplified, as the previous one was rather silly; also noted by Andrew. * The size of the 'reg' property was fixed; also noted by Andrew. * The exceedingly long macros names have been simplified and some other minor coding style issues have been solved. Ezequiel Garcia (4): clk: mvebu: Add Core Divider clock ARM: mvebu: Add Core Divider clock device-tree binding ARM: mvebu: Add a 2 GHz fixed-clock Armada 370/XP ARM: mvebu: Add the core-divider clock to Armada 370/XP .../bindings/clock/mvebu-corediv-clock.txt | 19 ++ arch/arm/boot/dts/armada-370-xp.dtsi | 17 ++ drivers/clk/mvebu/Kconfig | 5 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/clk-corediv.c | 223 +++++++++++++++++++++ 5 files changed, 265 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt create mode 100644 drivers/clk/mvebu/clk-corediv.c -- 1.8.1.5 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock 2013-09-26 19:35 [PATCH v2 0/4] Add Core Divider clock support for Armada 370/XP Ezequiel Garcia @ 2013-09-26 19:35 ` Ezequiel Garcia 2013-10-02 17:43 ` Jason Cooper 2013-09-26 19:35 ` [PATCH v2 2/4] ARM: mvebu: Add Core Divider clock device-tree binding Ezequiel Garcia ` (2 subsequent siblings) 3 siblings, 1 reply; 16+ messages in thread From: Ezequiel Garcia @ 2013-09-26 19:35 UTC (permalink / raw) To: linux-arm-kernel This commit introduces a new group of clocks present in Armada 370/XP SoCs (called "Core Divider" clocks) and add a provider for them. The only clock supported for now is the NAND clock (ndclk), but the infrastructure to add the rest is already set. Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> --- drivers/clk/mvebu/Kconfig | 5 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 229 insertions(+) create mode 100644 drivers/clk/mvebu/clk-corediv.c diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig index 0b0f3e7..c339b82 100644 --- a/drivers/clk/mvebu/Kconfig +++ b/drivers/clk/mvebu/Kconfig @@ -4,15 +4,20 @@ config MVEBU_CLK_COMMON config MVEBU_CLK_CPU bool +config MVEBU_CLK_COREDIV + bool + config ARMADA_370_CLK bool select MVEBU_CLK_COMMON select MVEBU_CLK_CPU + select MVEBU_CLK_COREDIV config ARMADA_XP_CLK bool select MVEBU_CLK_COMMON select MVEBU_CLK_CPU + select MVEBU_CLK_COREDIV config DOVE_CLK bool diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile index 1c7e70c..21bbfb4 100644 --- a/drivers/clk/mvebu/Makefile +++ b/drivers/clk/mvebu/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o +obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c new file mode 100644 index 0000000..7162615 --- /dev/null +++ b/drivers/clk/mvebu/clk-corediv.c @@ -0,0 +1,223 @@ +/* + * MVEBU Core divider clock + * + * Copyright (C) 2013 Marvell + * + * Ezequiel Garcia <ezequiel.garcia@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include "common.h" + +#define CORE_CLK_DIV_RATIO_MASK 0xff +#define CORE_CLK_DIV_RATIO_RELOAD BIT(8) +#define CORE_CLK_DIV_ENABLE_OFFSET 24 +#define CORE_CLK_DIV_RATIO_OFFSET 0x8 + +struct clk_corediv_desc { + unsigned int mask; + unsigned int offset; + unsigned int fieldbit; +}; + +struct clk_corediv { + struct clk_hw hw; + void __iomem *reg; + struct clk_corediv_desc desc; + spinlock_t lock; +}; + +static struct clk_onecell_data clk_data; + +static const struct clk_corediv_desc mvebu_corediv_desc[] __initconst = { + { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */ +}; + +#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw) + +static int clk_corediv_is_enabled(struct clk_hw *hwclk) +{ + struct clk_corediv *corediv = to_corediv_clk(hwclk); + struct clk_corediv_desc *desc = &corediv->desc; + u32 enable_mask = BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET; + + return !!(readl(corediv->reg) & enable_mask); +} + +static int clk_corediv_enable(struct clk_hw *hwclk) +{ + struct clk_corediv *corediv = to_corediv_clk(hwclk); + struct clk_corediv_desc *desc = &corediv->desc; + unsigned long flags = 0; + u32 reg; + + spin_lock_irqsave(&corediv->lock, flags); + + reg = readl(corediv->reg); + reg |= (BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET); + writel(reg, corediv->reg); + + spin_unlock_irqrestore(&corediv->lock, flags); + + return 0; +} + +static void clk_corediv_disable(struct clk_hw *hwclk) +{ + struct clk_corediv *corediv = to_corediv_clk(hwclk); + struct clk_corediv_desc *desc = &corediv->desc; + unsigned long flags = 0; + u32 reg; + + spin_lock_irqsave(&corediv->lock, flags); + + reg = readl(corediv->reg); + reg &= ~(BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET); + writel(reg, corediv->reg); + + spin_unlock_irqrestore(&corediv->lock, flags); +} + +static unsigned long clk_corediv_recalc_rate(struct clk_hw *hwclk, + unsigned long parent_rate) +{ + struct clk_corediv *corediv = to_corediv_clk(hwclk); + struct clk_corediv_desc *desc = &corediv->desc; + u32 reg, div; + + reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET); + div = (reg >> desc->offset) & desc->mask; + return parent_rate / div; +} + +static long clk_corediv_round_rate(struct clk_hw *hwclk, unsigned long rate, + unsigned long *parent_rate) +{ + /* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */ + u32 div; + + div = *parent_rate / rate; + if (div < 4) + div = 4; + else if (div > 6) + div = 8; + + return *parent_rate / div; +} + +static int clk_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_corediv *corediv = to_corediv_clk(hwclk); + struct clk_corediv_desc *desc = &corediv->desc; + unsigned long flags = 0; + u32 reg, div; + + div = parent_rate / rate; + + spin_lock_irqsave(&corediv->lock, flags); + + /* Write new divider to the divider ratio register */ + reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET); + reg &= ~(desc->mask << desc->offset); + reg |= (div & desc->mask) << desc->offset; + writel(reg, corediv->reg + CORE_CLK_DIV_RATIO_OFFSET); + + /* Set reload-force for this clock */ + reg = readl(corediv->reg) | BIT(desc->fieldbit); + writel(reg, corediv->reg); + + /* Now trigger the clock update */ + reg = readl(corediv->reg) | CORE_CLK_DIV_RATIO_RELOAD; + writel(reg, corediv->reg); + + /* + * Wait for clocks to settle down, and then clear all the + * ratios request and the reload request. + */ + udelay(1000); + reg &= ~(CORE_CLK_DIV_RATIO_MASK | CORE_CLK_DIV_RATIO_RELOAD); + writel(reg, corediv->reg); + udelay(1000); + + spin_unlock_irqrestore(&corediv->lock, flags); + + return 0; +} + +static const struct clk_ops corediv_ops = { + .enable = clk_corediv_enable, + .disable = clk_corediv_disable, + .is_enabled = clk_corediv_is_enabled, + .recalc_rate = clk_corediv_recalc_rate, + .round_rate = clk_corediv_round_rate, + .set_rate = clk_corediv_set_rate, +}; + +static void __init mvebu_corediv_clk_init(struct device_node *node) +{ + struct clk_init_data init; + struct clk_corediv *corediv; + struct clk **clks; + void __iomem *base; + const char *parent_name; + const char *clk_name; + int i; + + base = of_iomap(node, 0); + if (WARN_ON(!base)) + return; + + parent_name = of_clk_get_parent_name(node, 0); + + clk_data.clk_num = ARRAY_SIZE(mvebu_corediv_desc); + + /* clks holds the clock array */ + clks = kcalloc(clk_data.clk_num, sizeof(struct clk *), + GFP_KERNEL); + if (WARN_ON(!clks)) + goto err_unmap; + /* corediv holds the clock specific array */ + corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv), + GFP_KERNEL); + if (WARN_ON(!corediv)) + goto err_free_clks; + + spin_lock_init(&corediv->lock); + + for (i = 0; i < clk_data.clk_num; i++) { + of_property_read_string_index(node, "clock-output-names", + i, &clk_name); + init.num_parents = 1; + init.parent_names = &parent_name; + init.name = clk_name; + init.ops = &corediv_ops; + init.flags = 0; + + corediv[i].desc = mvebu_corediv_desc[i]; + corediv[i].reg = base; + corediv[i].hw.init = &init; + + clks[i] = clk_register(NULL, &corediv[i].hw); + WARN_ON(IS_ERR(clks[i])); + } + + clk_data.clks = clks; + of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data); + return; + +err_free_clks: + kfree(clks); +err_unmap: + iounmap(base); +} +CLK_OF_DECLARE(mvebu_corediv_clk, "marvell,armada-370-corediv-clock", + mvebu_corediv_clk_init); -- 1.8.1.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock 2013-09-26 19:35 ` [PATCH v2 1/4] clk: mvebu: Add Core Divider clock Ezequiel Garcia @ 2013-10-02 17:43 ` Jason Cooper 2013-10-02 18:09 ` Ezequiel Garcia 0 siblings, 1 reply; 16+ messages in thread From: Jason Cooper @ 2013-10-02 17:43 UTC (permalink / raw) To: linux-arm-kernel On Thu, Sep 26, 2013 at 04:35:27PM -0300, Ezequiel Garcia wrote: > This commit introduces a new group of clocks present in Armada 370/XP > SoCs (called "Core Divider" clocks) and add a provider for them. > The only clock supported for now is the NAND clock (ndclk), but the > infrastructure to add the rest is already set. > > Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> > --- > drivers/clk/mvebu/Kconfig | 5 + > drivers/clk/mvebu/Makefile | 1 + > drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 229 insertions(+) > create mode 100644 drivers/clk/mvebu/clk-corediv.c Acked-by: Jason Cooper <jason@lakedaemon.net> Please let me know once this gets pulled into the clock tree, and I'll pull in the remaining patches. thx, Jason. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock 2013-10-02 17:43 ` Jason Cooper @ 2013-10-02 18:09 ` Ezequiel Garcia 2013-10-08 19:59 ` Ezequiel Garcia 0 siblings, 1 reply; 16+ messages in thread From: Ezequiel Garcia @ 2013-10-02 18:09 UTC (permalink / raw) To: linux-arm-kernel On Wed, Oct 02, 2013 at 01:43:32PM -0400, Jason Cooper wrote: > On Thu, Sep 26, 2013 at 04:35:27PM -0300, Ezequiel Garcia wrote: > > This commit introduces a new group of clocks present in Armada 370/XP > > SoCs (called "Core Divider" clocks) and add a provider for them. > > The only clock supported for now is the NAND clock (ndclk), but the > > infrastructure to add the rest is already set. > > > > Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> > > --- > > drivers/clk/mvebu/Kconfig | 5 + > > drivers/clk/mvebu/Makefile | 1 + > > drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 229 insertions(+) > > create mode 100644 drivers/clk/mvebu/clk-corediv.c > > Acked-by: Jason Cooper <jason@lakedaemon.net> > Mike: any comments on this? -- Ezequiel Garc?a, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock 2013-10-02 18:09 ` Ezequiel Garcia @ 2013-10-08 19:59 ` Ezequiel Garcia 2013-10-16 11:08 ` Ezequiel Garcia 0 siblings, 1 reply; 16+ messages in thread From: Ezequiel Garcia @ 2013-10-08 19:59 UTC (permalink / raw) To: linux-arm-kernel On Wed, Oct 02, 2013 at 03:09:44PM -0300, Ezequiel Garcia wrote: > On Wed, Oct 02, 2013 at 01:43:32PM -0400, Jason Cooper wrote: > > On Thu, Sep 26, 2013 at 04:35:27PM -0300, Ezequiel Garcia wrote: > > > This commit introduces a new group of clocks present in Armada 370/XP > > > SoCs (called "Core Divider" clocks) and add a provider for them. > > > The only clock supported for now is the NAND clock (ndclk), but the > > > infrastructure to add the rest is already set. > > > > > > Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > > > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> > > > --- > > > drivers/clk/mvebu/Kconfig | 5 + > > > drivers/clk/mvebu/Makefile | 1 + > > > drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ > > > 3 files changed, 229 insertions(+) > > > create mode 100644 drivers/clk/mvebu/clk-corediv.c > > > > Acked-by: Jason Cooper <jason@lakedaemon.net> > > > > Mike: any comments on this? ping? I'd like to move along with the NAND driver for this controller and -although these are not a hard requirement- it would be nice to have them merged. Thanks! -- Ezequiel Garc?a, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock 2013-10-08 19:59 ` Ezequiel Garcia @ 2013-10-16 11:08 ` Ezequiel Garcia 2013-10-17 19:18 ` Ezequiel Garcia 0 siblings, 1 reply; 16+ messages in thread From: Ezequiel Garcia @ 2013-10-16 11:08 UTC (permalink / raw) To: linux-arm-kernel On Tue, Oct 08, 2013 at 04:59:33PM -0300, Ezequiel Garcia wrote: > On Wed, Oct 02, 2013 at 03:09:44PM -0300, Ezequiel Garcia wrote: > > On Wed, Oct 02, 2013 at 01:43:32PM -0400, Jason Cooper wrote: > > > On Thu, Sep 26, 2013 at 04:35:27PM -0300, Ezequiel Garcia wrote: > > > > This commit introduces a new group of clocks present in Armada 370/XP > > > > SoCs (called "Core Divider" clocks) and add a provider for them. > > > > The only clock supported for now is the NAND clock (ndclk), but the > > > > infrastructure to add the rest is already set. > > > > > > > > Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > > > > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> > > > > --- > > > > drivers/clk/mvebu/Kconfig | 5 + > > > > drivers/clk/mvebu/Makefile | 1 + > > > > drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ > > > > 3 files changed, 229 insertions(+) > > > > create mode 100644 drivers/clk/mvebu/clk-corediv.c > > > > > > Acked-by: Jason Cooper <jason@lakedaemon.net> > > > > > > > Mike: any comments on this? > > ping? > > I'd like to move along with the NAND driver for this controller and > -although these are not a hard requirement- it would be nice > to have them merged. > Mike? Any chance you pick these soon? It's been almost three-weeks since these patchset has been sent and I'm starting to forget the details of it ;) -- Ezequiel Garc?a, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock 2013-10-16 11:08 ` Ezequiel Garcia @ 2013-10-17 19:18 ` Ezequiel Garcia 2013-10-17 19:25 ` Jason Cooper 0 siblings, 1 reply; 16+ messages in thread From: Ezequiel Garcia @ 2013-10-17 19:18 UTC (permalink / raw) To: linux-arm-kernel On Wed, Oct 16, 2013 at 08:08:19AM -0300, Ezequiel Garcia wrote: > On Tue, Oct 08, 2013 at 04:59:33PM -0300, Ezequiel Garcia wrote: > > On Wed, Oct 02, 2013 at 03:09:44PM -0300, Ezequiel Garcia wrote: > > > On Wed, Oct 02, 2013 at 01:43:32PM -0400, Jason Cooper wrote: > > > > On Thu, Sep 26, 2013 at 04:35:27PM -0300, Ezequiel Garcia wrote: > > > > > This commit introduces a new group of clocks present in Armada 370/XP > > > > > SoCs (called "Core Divider" clocks) and add a provider for them. > > > > > The only clock supported for now is the NAND clock (ndclk), but the > > > > > infrastructure to add the rest is already set. > > > > > > > > > > Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > > > > > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> > > > > > --- > > > > > drivers/clk/mvebu/Kconfig | 5 + > > > > > drivers/clk/mvebu/Makefile | 1 + > > > > > drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ > > > > > 3 files changed, 229 insertions(+) > > > > > create mode 100644 drivers/clk/mvebu/clk-corediv.c > > > > > > > > Acked-by: Jason Cooper <jason@lakedaemon.net> > > > > > > > > > > Mike: any comments on this? > > > > ping? > > > > I'd like to move along with the NAND driver for this controller and > > -although these are not a hard requirement- it would be nice > > to have them merged. > > > > Mike? Any chance you pick these soon? It's been almost three-weeks since > these patchset has been sent and I'm starting to forget the details of it ;) Jason: It seems Mike went on 'stealth mode' so I'm wondering if you would consider taking this patchset through you (given it's for our SoCs). The patches have been reviewed by Gregory and have your Ack, but unfortunately I don't know if Mike took a look on them. On the other side, this adds a new clock to be used with NAND, so it's completely isolated and innocuous. I hate to re-route patches this way -so feel free to refuse- but other I don't see any way this can be in v3.13. Thanks! -- Ezequiel Garc?a, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock 2013-10-17 19:18 ` Ezequiel Garcia @ 2013-10-17 19:25 ` Jason Cooper 2013-10-22 9:53 ` Mike Turquette 0 siblings, 1 reply; 16+ messages in thread From: Jason Cooper @ 2013-10-17 19:25 UTC (permalink / raw) To: linux-arm-kernel On Thu, Oct 17, 2013 at 04:18:53PM -0300, Ezequiel Garcia wrote: > On Wed, Oct 16, 2013 at 08:08:19AM -0300, Ezequiel Garcia wrote: > > On Tue, Oct 08, 2013 at 04:59:33PM -0300, Ezequiel Garcia wrote: > > > On Wed, Oct 02, 2013 at 03:09:44PM -0300, Ezequiel Garcia wrote: > > > > On Wed, Oct 02, 2013 at 01:43:32PM -0400, Jason Cooper wrote: > > > > > On Thu, Sep 26, 2013 at 04:35:27PM -0300, Ezequiel Garcia wrote: > > > > > > This commit introduces a new group of clocks present in Armada 370/XP > > > > > > SoCs (called "Core Divider" clocks) and add a provider for them. > > > > > > The only clock supported for now is the NAND clock (ndclk), but the > > > > > > infrastructure to add the rest is already set. > > > > > > > > > > > > Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > > > > > > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> > > > > > > --- > > > > > > drivers/clk/mvebu/Kconfig | 5 + > > > > > > drivers/clk/mvebu/Makefile | 1 + > > > > > > drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ > > > > > > 3 files changed, 229 insertions(+) > > > > > > create mode 100644 drivers/clk/mvebu/clk-corediv.c > > > > > > > > > > Acked-by: Jason Cooper <jason@lakedaemon.net> > > > > > > > > > > > > > Mike: any comments on this? > > > > > > ping? > > > > > > I'd like to move along with the NAND driver for this controller and > > > -although these are not a hard requirement- it would be nice > > > to have them merged. > > > > > > > Mike? Any chance you pick these soon? It's been almost three-weeks since > > these patchset has been sent and I'm starting to forget the details of it ;) > > Jason: It seems Mike went on 'stealth mode' so I'm wondering if you would > consider taking this patchset through you (given it's for our SoCs). I considered it, and it didn't sit well with me. I don't mind taking a bugfix, everyone wants to see those moved along. However, this is an entirely new driver. Yes, it's scope of use is limited, but I'd prefer to let the maintainer review the driver before agreeing to maintain it. Otherwise, I'd be forcing him to maintain something he hasn't even looked at. :( I know it sucks, but we're going to wait for Mike. thx, Jason. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock 2013-10-17 19:25 ` Jason Cooper @ 2013-10-22 9:53 ` Mike Turquette 2013-10-23 13:07 ` Ezequiel Garcia 2013-11-17 4:52 ` Ezequiel Garcia 0 siblings, 2 replies; 16+ messages in thread From: Mike Turquette @ 2013-10-22 9:53 UTC (permalink / raw) To: linux-arm-kernel Quoting Jason Cooper (2013-10-17 12:25:45) > On Thu, Oct 17, 2013 at 04:18:53PM -0300, Ezequiel Garcia wrote: > > On Wed, Oct 16, 2013 at 08:08:19AM -0300, Ezequiel Garcia wrote: > > > On Tue, Oct 08, 2013 at 04:59:33PM -0300, Ezequiel Garcia wrote: > > > > On Wed, Oct 02, 2013 at 03:09:44PM -0300, Ezequiel Garcia wrote: > > > > > On Wed, Oct 02, 2013 at 01:43:32PM -0400, Jason Cooper wrote: > > > > > > On Thu, Sep 26, 2013 at 04:35:27PM -0300, Ezequiel Garcia wrote: > > > > > > > This commit introduces a new group of clocks present in Armada 370/XP > > > > > > > SoCs (called "Core Divider" clocks) and add a provider for them. > > > > > > > The only clock supported for now is the NAND clock (ndclk), but the > > > > > > > infrastructure to add the rest is already set. > > > > > > > > > > > > > > Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > > > > > > > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> > > > > > > > --- > > > > > > > drivers/clk/mvebu/Kconfig | 5 + > > > > > > > drivers/clk/mvebu/Makefile | 1 + > > > > > > > drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ > > > > > > > 3 files changed, 229 insertions(+) > > > > > > > create mode 100644 drivers/clk/mvebu/clk-corediv.c > > > > > > > > > > > > Acked-by: Jason Cooper <jason@lakedaemon.net> > > > > > > > > > > > > > > > > Mike: any comments on this? > > > > > > > > ping? > > > > > > > > I'd like to move along with the NAND driver for this controller and > > > > -although these are not a hard requirement- it would be nice > > > > to have them merged. > > > > > > > > > > Mike? Any chance you pick these soon? It's been almost three-weeks since > > > these patchset has been sent and I'm starting to forget the details of it ;) > > > > Jason: It seems Mike went on 'stealth mode' so I'm wondering if you would > > consider taking this patchset through you (given it's for our SoCs). > > I considered it, and it didn't sit well with me. I don't mind taking a > bugfix, everyone wants to see those moved along. However, this is an > entirely new driver. Yes, it's scope of use is limited, but I'd prefer > to let the maintainer review the driver before agreeing to maintain it. > Otherwise, I'd be forcing him to maintain something he hasn't even > looked at. :( > > I know it sucks, but we're going to wait for Mike. Sorry for the delay. This driver looks fine and I've taken it into clk-next. Thanks! Mike > > thx, > > Jason. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock 2013-10-22 9:53 ` Mike Turquette @ 2013-10-23 13:07 ` Ezequiel Garcia 2013-11-17 4:52 ` Ezequiel Garcia 1 sibling, 0 replies; 16+ messages in thread From: Ezequiel Garcia @ 2013-10-23 13:07 UTC (permalink / raw) To: linux-arm-kernel On Tue, Oct 22, 2013 at 02:53:17AM -0700, Mike Turquette wrote: > Quoting Jason Cooper (2013-10-17 12:25:45) > > On Thu, Oct 17, 2013 at 04:18:53PM -0300, Ezequiel Garcia wrote: > > > On Wed, Oct 16, 2013 at 08:08:19AM -0300, Ezequiel Garcia wrote: > > > > On Tue, Oct 08, 2013 at 04:59:33PM -0300, Ezequiel Garcia wrote: > > > > > On Wed, Oct 02, 2013 at 03:09:44PM -0300, Ezequiel Garcia wrote: > > > > > > On Wed, Oct 02, 2013 at 01:43:32PM -0400, Jason Cooper wrote: > > > > > > > On Thu, Sep 26, 2013 at 04:35:27PM -0300, Ezequiel Garcia wrote: > > > > > > > > This commit introduces a new group of clocks present in Armada 370/XP > > > > > > > > SoCs (called "Core Divider" clocks) and add a provider for them. > > > > > > > > The only clock supported for now is the NAND clock (ndclk), but the > > > > > > > > infrastructure to add the rest is already set. > > > > > > > > > > > > > > > > Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > > > > > > > > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> > > > > > > > > --- > > > > > > > > drivers/clk/mvebu/Kconfig | 5 + > > > > > > > > drivers/clk/mvebu/Makefile | 1 + > > > > > > > > drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ > > > > > > > > 3 files changed, 229 insertions(+) > > > > > > > > create mode 100644 drivers/clk/mvebu/clk-corediv.c > > > > > > > > > > > > > > Acked-by: Jason Cooper <jason@lakedaemon.net> > > > > > > > > > > > > > > > > > > > Mike: any comments on this? > > > > > > > > > > ping? > > > > > > > > > > I'd like to move along with the NAND driver for this controller and > > > > > -although these are not a hard requirement- it would be nice > > > > > to have them merged. > > > > > > > > > > > > > Mike? Any chance you pick these soon? It's been almost three-weeks since > > > > these patchset has been sent and I'm starting to forget the details of it ;) > > > > > > Jason: It seems Mike went on 'stealth mode' so I'm wondering if you would > > > consider taking this patchset through you (given it's for our SoCs). > > > > I considered it, and it didn't sit well with me. I don't mind taking a > > bugfix, everyone wants to see those moved along. However, this is an > > entirely new driver. Yes, it's scope of use is limited, but I'd prefer > > to let the maintainer review the driver before agreeing to maintain it. > > Otherwise, I'd be forcing him to maintain something he hasn't even > > looked at. :( > > > > I know it sucks, but we're going to wait for Mike. > > Sorry for the delay. This driver looks fine and I've taken it into > clk-next. > No problem, thanks Mike! -- Ezequiel Garc?a, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock 2013-10-22 9:53 ` Mike Turquette 2013-10-23 13:07 ` Ezequiel Garcia @ 2013-11-17 4:52 ` Ezequiel Garcia 2013-11-19 18:31 ` Ezequiel Garcia 1 sibling, 1 reply; 16+ messages in thread From: Ezequiel Garcia @ 2013-11-17 4:52 UTC (permalink / raw) To: linux-arm-kernel Hi Mike, On Tue, Oct 22, 2013 at 02:53:17AM -0700, Mike Turquette wrote: > Quoting Jason Cooper (2013-10-17 12:25:45) > > On Thu, Oct 17, 2013 at 04:18:53PM -0300, Ezequiel Garcia wrote: > > > On Wed, Oct 16, 2013 at 08:08:19AM -0300, Ezequiel Garcia wrote: > > > > On Tue, Oct 08, 2013 at 04:59:33PM -0300, Ezequiel Garcia wrote: > > > > > On Wed, Oct 02, 2013 at 03:09:44PM -0300, Ezequiel Garcia wrote: > > > > > > On Wed, Oct 02, 2013 at 01:43:32PM -0400, Jason Cooper wrote: > > > > > > > On Thu, Sep 26, 2013 at 04:35:27PM -0300, Ezequiel Garcia wrote: > > > > > > > > This commit introduces a new group of clocks present in Armada 370/XP > > > > > > > > SoCs (called "Core Divider" clocks) and add a provider for them. > > > > > > > > The only clock supported for now is the NAND clock (ndclk), but the > > > > > > > > infrastructure to add the rest is already set. > > > > > > > > > > > > > > > > Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > > > > > > > > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> > > > > > > > > --- > > > > > > > > drivers/clk/mvebu/Kconfig | 5 + > > > > > > > > drivers/clk/mvebu/Makefile | 1 + > > > > > > > > drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ > > > > > > > > 3 files changed, 229 insertions(+) > > > > > > > > create mode 100644 drivers/clk/mvebu/clk-corediv.c > > > > > > > > > > > > > > Acked-by: Jason Cooper <jason@lakedaemon.net> > > > > > > > > > > > > > > > > > > > Mike: any comments on this? > > > > > > > > > > ping? > > > > > > > > > > I'd like to move along with the NAND driver for this controller and > > > > > -although these are not a hard requirement- it would be nice > > > > > to have them merged. > > > > > > > > > > > > > Mike? Any chance you pick these soon? It's been almost three-weeks since > > > > these patchset has been sent and I'm starting to forget the details of it ;) > > > > > > Jason: It seems Mike went on 'stealth mode' so I'm wondering if you would > > > consider taking this patchset through you (given it's for our SoCs). > > > > I considered it, and it didn't sit well with me. I don't mind taking a > > bugfix, everyone wants to see those moved along. However, this is an > > entirely new driver. Yes, it's scope of use is limited, but I'd prefer > > to let the maintainer review the driver before agreeing to maintain it. > > Otherwise, I'd be forcing him to maintain something he hasn't even > > looked at. :( > > > > I know it sucks, but we're going to wait for Mike. > > Sorry for the delay. This driver looks fine and I've taken it into > clk-next. > This commit doesn't seem to be in clk-next (or in any other place), nearly two months after I submitted it, and after a month I was told it was accepted. What's going on? I really hope I'm missing something or I'm looking at the wrong tree. -- Ezequiel Garc?a, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock 2013-11-17 4:52 ` Ezequiel Garcia @ 2013-11-19 18:31 ` Ezequiel Garcia 0 siblings, 0 replies; 16+ messages in thread From: Ezequiel Garcia @ 2013-11-19 18:31 UTC (permalink / raw) To: linux-arm-kernel On Sun, Nov 17, 2013 at 01:52:52AM -0300, Ezequiel Garcia wrote: > Hi Mike, > > On Tue, Oct 22, 2013 at 02:53:17AM -0700, Mike Turquette wrote: > > Quoting Jason Cooper (2013-10-17 12:25:45) > > > On Thu, Oct 17, 2013 at 04:18:53PM -0300, Ezequiel Garcia wrote: > > > > On Wed, Oct 16, 2013 at 08:08:19AM -0300, Ezequiel Garcia wrote: > > > > > On Tue, Oct 08, 2013 at 04:59:33PM -0300, Ezequiel Garcia wrote: > > > > > > On Wed, Oct 02, 2013 at 03:09:44PM -0300, Ezequiel Garcia wrote: > > > > > > > On Wed, Oct 02, 2013 at 01:43:32PM -0400, Jason Cooper wrote: > > > > > > > > On Thu, Sep 26, 2013 at 04:35:27PM -0300, Ezequiel Garcia wrote: > > > > > > > > > This commit introduces a new group of clocks present in Armada 370/XP > > > > > > > > > SoCs (called "Core Divider" clocks) and add a provider for them. > > > > > > > > > The only clock supported for now is the NAND clock (ndclk), but the > > > > > > > > > infrastructure to add the rest is already set. > > > > > > > > > > > > > > > > > > Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > > > > > > > > > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> > > > > > > > > > --- > > > > > > > > > drivers/clk/mvebu/Kconfig | 5 + > > > > > > > > > drivers/clk/mvebu/Makefile | 1 + > > > > > > > > > drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > 3 files changed, 229 insertions(+) > > > > > > > > > create mode 100644 drivers/clk/mvebu/clk-corediv.c > > > > > > > > > > > > > > > > Acked-by: Jason Cooper <jason@lakedaemon.net> > > > > > > > > > > > > > > > > > > > > > > Mike: any comments on this? > > > > > > > > > > > > ping? > > > > > > > > > > > > I'd like to move along with the NAND driver for this controller and > > > > > > -although these are not a hard requirement- it would be nice > > > > > > to have them merged. > > > > > > > > > > > > > > > > Mike? Any chance you pick these soon? It's been almost three-weeks since > > > > > these patchset has been sent and I'm starting to forget the details of it ;) > > > > > > > > Jason: It seems Mike went on 'stealth mode' so I'm wondering if you would > > > > consider taking this patchset through you (given it's for our SoCs). > > > > > > I considered it, and it didn't sit well with me. I don't mind taking a > > > bugfix, everyone wants to see those moved along. However, this is an > > > entirely new driver. Yes, it's scope of use is limited, but I'd prefer > > > to let the maintainer review the driver before agreeing to maintain it. > > > Otherwise, I'd be forcing him to maintain something he hasn't even > > > looked at. :( > > > > > > I know it sucks, but we're going to wait for Mike. > > > > Sorry for the delay. This driver looks fine and I've taken it into > > clk-next. > > > > This commit doesn't seem to be in clk-next (or in any other place), > nearly two months after I submitted it, and after a month I was told > it was accepted. > > What's going on? > > I really hope I'm missing something or I'm looking at the wrong tree. Hi Mike, This commit seems to be in your clk-next-3.13-fail branch: http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=shortlog;h=refs/heads/clk-next-3.13-fail What's the purpose of this branch? Why is the commit there and not in clk-next? If there's anything to review on this driver, just let me know so we can have this merged and move forward with the NAND support. -- Ezequiel Garc?a, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 2/4] ARM: mvebu: Add Core Divider clock device-tree binding 2013-09-26 19:35 [PATCH v2 0/4] Add Core Divider clock support for Armada 370/XP Ezequiel Garcia 2013-09-26 19:35 ` [PATCH v2 1/4] clk: mvebu: Add Core Divider clock Ezequiel Garcia @ 2013-09-26 19:35 ` Ezequiel Garcia 2013-09-26 19:35 ` [PATCH v2 3/4] ARM: mvebu: Add a 2 GHz fixed-clock Armada 370/XP Ezequiel Garcia 2013-09-26 19:35 ` [PATCH v2 4/4] ARM: mvebu: Add the core-divider clock to " Ezequiel Garcia 3 siblings, 0 replies; 16+ messages in thread From: Ezequiel Garcia @ 2013-09-26 19:35 UTC (permalink / raw) To: linux-arm-kernel The Armada 370/XP SoCs have a Core Divider clock providing several clocks. For now, only the NAND clock is supported. Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> --- .../devicetree/bindings/clock/mvebu-corediv-clock.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt new file mode 100644 index 0000000..c62391f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt @@ -0,0 +1,19 @@ +* Core Divider Clock bindings for Marvell MVEBU SoCs + +The following is a list of provided IDs and clock names on Armada 370/XP: + 0 = nand (NAND clock) + +Required properties: +- compatible : must be "marvell,armada-370-corediv-clock" +- reg : must be the register address of Core Divider control register +- #clock-cells : from common clock binding; shall be set to 1 +- clocks : must be set to the parent's phandle + +Example: + +corediv_clk: corediv-clocks at 18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; + #clock-cells = <1>; + clocks = <&pll>; +}; -- 1.8.1.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 3/4] ARM: mvebu: Add a 2 GHz fixed-clock Armada 370/XP 2013-09-26 19:35 [PATCH v2 0/4] Add Core Divider clock support for Armada 370/XP Ezequiel Garcia 2013-09-26 19:35 ` [PATCH v2 1/4] clk: mvebu: Add Core Divider clock Ezequiel Garcia 2013-09-26 19:35 ` [PATCH v2 2/4] ARM: mvebu: Add Core Divider clock device-tree binding Ezequiel Garcia @ 2013-09-26 19:35 ` Ezequiel Garcia 2013-09-26 19:35 ` [PATCH v2 4/4] ARM: mvebu: Add the core-divider clock to " Ezequiel Garcia 3 siblings, 0 replies; 16+ messages in thread From: Ezequiel Garcia @ 2013-09-26 19:35 UTC (permalink / raw) To: linux-arm-kernel Armada 370/XP SoCs have a 2 GHz fixed PLL that is used to feed other clocks. This commit adds a DT representation of this clock through a fixed-clock compatible node. Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> --- arch/arm/boot/dts/armada-370-xp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 1de2dae..924c721 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -252,4 +252,13 @@ }; }; + + clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + }; }; -- 1.8.1.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 4/4] ARM: mvebu: Add the core-divider clock to Armada 370/XP 2013-09-26 19:35 [PATCH v2 0/4] Add Core Divider clock support for Armada 370/XP Ezequiel Garcia ` (2 preceding siblings ...) 2013-09-26 19:35 ` [PATCH v2 3/4] ARM: mvebu: Add a 2 GHz fixed-clock Armada 370/XP Ezequiel Garcia @ 2013-09-26 19:35 ` Ezequiel Garcia 3 siblings, 0 replies; 16+ messages in thread From: Ezequiel Garcia @ 2013-09-26 19:35 UTC (permalink / raw) To: linux-arm-kernel The Armada 370/XP SoC has a clock provider called "Core Divider", that is derived from a fixed 2 GHz PLL clock. Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> --- arch/arm/boot/dts/armada-370-xp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 924c721..01e69fc 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -137,6 +137,14 @@ status = "disabled"; }; + coredivclk: corediv-clock at 18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + timer at 20300 { reg = <0x20300 0x30>, <0x21040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>; -- 1.8.1.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
[parent not found: <CAFJTrDtxt7M77W_DMMUhWAMUFDL7-N3oktKvd0mixaS9yOvaBg@mail.gmail.com>]
* [PATCH v2 1/4] clk: mvebu: Add Core Divider clock [not found] <CAFJTrDtxt7M77W_DMMUhWAMUFDL7-N3oktKvd0mixaS9yOvaBg@mail.gmail.com> @ 2013-10-10 14:44 ` Ezequiel Garcia 0 siblings, 0 replies; 16+ messages in thread From: Ezequiel Garcia @ 2013-10-10 14:44 UTC (permalink / raw) To: linux-arm-kernel Hi Mattew: On Thu, Oct 10, 2013 at 03:04:29PM +0100, Matthew Minter wrote: > > I noticed this patch set and mention to developing a nand driver for > this chip. I am involved in the work with a board based around it and > lack of current nand support with its controller is a problem. Is > there any way I could help with the nand driver development if any has > started? > Sure. You can start by taking a look at the first series I sent to linux-mtd mailing list: http://lwn.net/Articles/567884/ And test them or provide some feedback and comments. We can certainly use some more eyes looking at the code! > (I do have some experience in kernel driver development so if there > are any known issues or known incomplete drivers I would be happy to > take a look, else I would like to know any other way I could support > here) > I'm currently working on this, so you can expect a v2 patchset soon. If you can comment and/or test the patches as they arrive, that would be great help. Of course, keep in mind this work-in-progress so be extra-careful where you use this driver. Thanks! -- Ezequiel Garc?a, Free Electrons Embedded Linux, Kernel and Android Engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2013-11-19 18:31 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-09-26 19:35 [PATCH v2 0/4] Add Core Divider clock support for Armada 370/XP Ezequiel Garcia 2013-09-26 19:35 ` [PATCH v2 1/4] clk: mvebu: Add Core Divider clock Ezequiel Garcia 2013-10-02 17:43 ` Jason Cooper 2013-10-02 18:09 ` Ezequiel Garcia 2013-10-08 19:59 ` Ezequiel Garcia 2013-10-16 11:08 ` Ezequiel Garcia 2013-10-17 19:18 ` Ezequiel Garcia 2013-10-17 19:25 ` Jason Cooper 2013-10-22 9:53 ` Mike Turquette 2013-10-23 13:07 ` Ezequiel Garcia 2013-11-17 4:52 ` Ezequiel Garcia 2013-11-19 18:31 ` Ezequiel Garcia 2013-09-26 19:35 ` [PATCH v2 2/4] ARM: mvebu: Add Core Divider clock device-tree binding Ezequiel Garcia 2013-09-26 19:35 ` [PATCH v2 3/4] ARM: mvebu: Add a 2 GHz fixed-clock Armada 370/XP Ezequiel Garcia 2013-09-26 19:35 ` [PATCH v2 4/4] ARM: mvebu: Add the core-divider clock to " Ezequiel Garcia [not found] <CAFJTrDtxt7M77W_DMMUhWAMUFDL7-N3oktKvd0mixaS9yOvaBg@mail.gmail.com> 2013-10-10 14:44 ` [PATCH v2 1/4] clk: mvebu: Add Core Divider clock Ezequiel Garcia
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