[PATCH V5] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[PATCH V5] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Sricharan R]

From: R Sricharan <r.sricharan@ti.com>

The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is passed from the
DT file, but this is not scalable when we have other non-DT guest
OS. This register must be set to the right value by the
secure rom code. Setting this register helps in propagating the right
frequency value across OSes.

More discussions and the reason for adding this in a non-DT
way can be seen from below.
http://www.mail-archive.com/linux-omap at vger.kernel.org/msg93832.html

So configuring this secure register for all the cpus here.

Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tony Lindgren <tony@atomide.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
---
 [V5] Removed the use of extern variable in omap-smp.c
      as per suggestion from Santosh Shilimkar <santosh.shilimkar@ti.com>

 arch/arm/mach-omap2/omap-secure.h |    4 ++++
 arch/arm/mach-omap2/omap-smp.c    |    7 +++++++
 arch/arm/mach-omap2/timer.c       |   10 ++++++++++
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index 0e72917..a5ee09d 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -42,6 +42,8 @@
 #define OMAP4_MON_L2X0_AUXCTRL_INDEX	0x109
 #define OMAP4_MON_L2X0_PREFETCH_INDEX	0x113
 
+#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX	0x109
+
 /* Secure PPA(Primary Protected Application) APIs */
 #define OMAP4_PPA_L2_POR_INDEX		0x23
 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX	0x25
@@ -60,5 +62,7 @@ extern int omap_barrier_reserve_memblock(void);
 static inline void omap_barrier_reserve_memblock(void)
 { }
 #endif
+
+void set_cntfreq(void);
 #endif /* __ASSEMBLER__ */
 #endif /* OMAP_ARCH_OMAP_SECURE_H */
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 22c3129..b1c6e5d 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -78,6 +78,13 @@ static void omap4_secondary_init(unsigned int cpu)
 							4, 0, 0, 0, 0, 0);
 
 	/*
+	 * Configure the CNTFRQ register for the secondary cpu's which
+	 * indicates the frequency of the cpu local timers.
+	 */
+	if (soc_is_omap54xx() || soc_is_dra7xx())
+		set_cntfreq();
+
+	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index fa74a06..60df58a 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -55,6 +55,7 @@
 #include "soc.h"
 #include "common.h"
 #include "powerdomain.h"
+#include "omap-secure.h"
 
 #define REALTIME_COUNTER_BASE				0x48243200
 #define INCREMENTER_NUMERATOR_OFFSET			0x10
@@ -65,6 +66,12 @@
 
 static struct omap_dm_timer clkev;
 static struct clock_event_device clockevent_gpt;
+static unsigned long arch_timer_freq;
+
+void set_cntfreq(void)
+{
+	omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
+}
 
 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 {
@@ -542,6 +549,9 @@ static void __init realtime_counter_init(void)
 	reg |= den;
 	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 
+	arch_timer_freq = (rate / den) * num;
+	set_cntfreq();
+
 	iounmap(base);
 }
 #else
-- 
1.7.9.5

[PATCH V5] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Santosh Shilimkar]

On Thursday 10 October 2013 03:43 AM, Sricharan R wrote:
> From: R Sricharan <r.sricharan@ti.com>
> 
> The realtime counter called master counter, produces the count
> used by the private timer peripherals in the MPU_CLUSTER. The
> CNTFRQ per cpu register is used to denote the frequency of the counter.
> Currently the frequency value is passed from the
> DT file, but this is not scalable when we have other non-DT guest
> OS. This register must be set to the right value by the
> secure rom code. Setting this register helps in propagating the right
> frequency value across OSes.
> 
> More discussions and the reason for adding this in a non-DT
> way can be seen from below.
> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg93832.html
> 
> So configuring this secure register for all the cpus here.
> 
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Tested-by: Nishanth Menon <nm@ti.com>
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: Sricharan R <r.sricharan@ti.com>
> ---
>  [V5] Removed the use of extern variable in omap-smp.c
>       as per suggestion from Santosh Shilimkar <santosh.shilimkar@ti.com>
> 
Thanks for the updates Sricharan. Looks fine now.

Tony, Can you apply this version if you are fine with it.

Regards,
Santosh

[PATCH V5] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [131010 06:20]:
> On Thursday 10 October 2013 03:43 AM, Sricharan R wrote:
> > From: R Sricharan <r.sricharan@ti.com>
> > 
> > The realtime counter called master counter, produces the count
> > used by the private timer peripherals in the MPU_CLUSTER. The
> > CNTFRQ per cpu register is used to denote the frequency of the counter.
> > Currently the frequency value is passed from the
> > DT file, but this is not scalable when we have other non-DT guest
> > OS. This register must be set to the right value by the
> > secure rom code. Setting this register helps in propagating the right
> > frequency value across OSes.
> > 
> > More discussions and the reason for adding this in a non-DT
> > way can be seen from below.
> > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg93832.html
> > 
> > So configuring this secure register for all the cpus here.
> > 
> > Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > Cc: Nishanth Menon <nm@ti.com>
> > Cc: Rajendra Nayak <rnayak@ti.com>
> > Cc: Marc Zyngier <marc.zyngier@arm.com>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Tony Lindgren <tony@atomide.com>
> > Tested-by: Nishanth Menon <nm@ti.com>
> > Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > Signed-off-by: Sricharan R <r.sricharan@ti.com>
> > ---
> >  [V5] Removed the use of extern variable in omap-smp.c
> >       as per suggestion from Santosh Shilimkar <santosh.shilimkar@ti.com>
> > 
> Thanks for the updates Sricharan. Looks fine now.
> 
> Tony, Can you apply this version if you are fine with it.

Yes thanks looks good to me now. Applying into omap-for-v3.13/soc.

Tony

[PATCH V5] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [131010 10:23]:
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [131010 06:20]:
> > On Thursday 10 October 2013 03:43 AM, Sricharan R wrote:
> > > From: R Sricharan <r.sricharan@ti.com>
> > > 
> > > The realtime counter called master counter, produces the count
> > > used by the private timer peripherals in the MPU_CLUSTER. The
> > > CNTFRQ per cpu register is used to denote the frequency of the counter.
> > > Currently the frequency value is passed from the
> > > DT file, but this is not scalable when we have other non-DT guest
> > > OS. This register must be set to the right value by the
> > > secure rom code. Setting this register helps in propagating the right
> > > frequency value across OSes.
> > > 
> > > More discussions and the reason for adding this in a non-DT
> > > way can be seen from below.
> > > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg93832.html
> > > 
> > > So configuring this secure register for all the cpus here.
> > > 
> > > Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > > Cc: Nishanth Menon <nm@ti.com>
> > > Cc: Rajendra Nayak <rnayak@ti.com>
> > > Cc: Marc Zyngier <marc.zyngier@arm.com>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > Cc: Tony Lindgren <tony@atomide.com>
> > > Tested-by: Nishanth Menon <nm@ti.com>
> > > Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > > Signed-off-by: Sricharan R <r.sricharan@ti.com>
> > > ---
> > >  [V5] Removed the use of extern variable in omap-smp.c
> > >       as per suggestion from Santosh Shilimkar <santosh.shilimkar@ti.com>
> > > 
> > Thanks for the updates Sricharan. Looks fine now.
> > 
> > Tony, Can you apply this version if you are fine with it.
> 
> Yes thanks looks good to me now. Applying into omap-for-v3.13/soc.

Grr, had to apply the following fix on top of this for some configs.

Tony

8< ---------------------------

From: Tony Lindgren <tony@atomide.com>
Date: Fri, 11 Oct 2013 17:28:04 -0700
Subject: [PATCH] ARM: OMAP2+: Fix build error for realtime counter init if not enabled

Otherwise we can get an error with some configs:

arch/arm/mach-omap2/timer.c:73: undefined reference to `omap_smc1'

Signed-off-by: Tony Lindgren <tony@atomide.com>

--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -66,12 +66,15 @@
 
 static struct omap_dm_timer clkev;
 static struct clock_event_device clockevent_gpt;
+
+#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 static unsigned long arch_timer_freq;
 
 void set_cntfreq(void)
 {
 	omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
 }
+#endif
 
 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 {

[PATCH V5] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register

[Santosh Shilimkar]

On Friday 11 October 2013 08:34 PM, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [131010 10:23]:
>> * Santosh Shilimkar <santosh.shilimkar@ti.com> [131010 06:20]:
>>> On Thursday 10 October 2013 03:43 AM, Sricharan R wrote:
>>>> From: R Sricharan <r.sricharan@ti.com>
>>>>
>>>> The realtime counter called master counter, produces the count
>>>> used by the private timer peripherals in the MPU_CLUSTER. The
>>>> CNTFRQ per cpu register is used to denote the frequency of the counter.
>>>> Currently the frequency value is passed from the
>>>> DT file, but this is not scalable when we have other non-DT guest
>>>> OS. This register must be set to the right value by the
>>>> secure rom code. Setting this register helps in propagating the right
>>>> frequency value across OSes.
>>>>
>>>> More discussions and the reason for adding this in a non-DT
>>>> way can be seen from below.
>>>> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg93832.html
>>>>
>>>> So configuring this secure register for all the cpus here.
>>>>
>>>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> Cc: Nishanth Menon <nm@ti.com>
>>>> Cc: Rajendra Nayak <rnayak@ti.com>
>>>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>>> Cc: Tony Lindgren <tony@atomide.com>
>>>> Tested-by: Nishanth Menon <nm@ti.com>
>>>> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>>>> ---
>>>>  [V5] Removed the use of extern variable in omap-smp.c
>>>>       as per suggestion from Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>>
>>> Thanks for the updates Sricharan. Looks fine now.
>>>
>>> Tony, Can you apply this version if you are fine with it.
>>
>> Yes thanks looks good to me now. Applying into omap-for-v3.13/soc.
> 
> Grr, had to apply the following fix on top of this for some configs.
> 
Looks like Sricharan missed some builds. Sorry for the trouble Tony.

> 
> 8< ---------------------------
> 
> From: Tony Lindgren <tony@atomide.com>
> Date: Fri, 11 Oct 2013 17:28:04 -0700
> Subject: [PATCH] ARM: OMAP2+: Fix build error for realtime counter init if not enabled
> 
> Otherwise we can get an error with some configs:
> 
> arch/arm/mach-omap2/timer.c:73: undefined reference to `omap_smc1'
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
Looks fine to me. Thanks 

Regards,
Santosh