[PATCH 0/4] Socfpga: clk: trivial fixes and cleanup

[PATCH 0/4] Socfpga: clk: trivial fixes and cleanup

[Steffen Trumtrar]

Hi!

This series includes two trivial fixes to the code (1,2),
then goes on to split the single clk.c file up into clock-type
specific files (3) and finally adds a divider to the peripheral
clock path.

The patches are rebased to the for-next branch of

        git://git.rocketboards.org/linux-socfpga-next.git

Regards,
Steffen

Steffen Trumtrar (4):
  ARM: socfpga: clk: remove unused field
  ARM: socfpga: clk: fix define typo
  ARM: socfpga: clk: split clk code
  ARM: socfpga: clk: add clk_divider to periph

 drivers/clk/socfpga/Makefile     |   3 +
 drivers/clk/socfpga/clk-gate.c   | 197 ++++++++++++++++++++++++
 drivers/clk/socfpga/clk-periph.c |  87 +++++++++++
 drivers/clk/socfpga/clk-pll.c    | 114 ++++++++++++++
 drivers/clk/socfpga/clk.c        | 313 +--------------------------------------
 drivers/clk/socfpga/clk.h        |  56 +++++++
 6 files changed, 458 insertions(+), 312 deletions(-)
 create mode 100644 drivers/clk/socfpga/clk-gate.c
 create mode 100644 drivers/clk/socfpga/clk-periph.c
 create mode 100644 drivers/clk/socfpga/clk-pll.c
 create mode 100644 drivers/clk/socfpga/clk.h

-- 
1.8.4.rc3

[PATCH 1/4] ARM: socfpga: clk: remove unused field

[Steffen Trumtrar]

The clk_name field from the socfpga_clk struct is unused.
Remove it.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 drivers/clk/socfpga/clk.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index 81dd31a..9bcf84e 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -60,7 +60,6 @@ extern void __iomem *clk_mgr_base_addr;
 struct socfpga_clk {
 	struct clk_gate hw;
 	char *parent_name;
-	char *clk_name;
 	u32 fixed_div;
 	void __iomem *div_reg;
 	u32 width;	/* only valid if div_reg != 0 */
-- 
1.8.4.rc3

[PATCH 2/4] ARM: socfpga: clk: fix define typo

[Steffen Trumtrar]

It should be SOCFPGA instead of SOCFGPA.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 drivers/clk/socfpga/clk.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index 9bcf84e..c6fd6e6 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -43,7 +43,7 @@
 #define SOCFPGA_PLL_DIVF_SHIFT	3
 #define SOCFPGA_PLL_DIVQ_MASK		0x003F0000
 #define SOCFPGA_PLL_DIVQ_SHIFT	16
-#define SOCFGPA_MAX_PARENTS	3
+#define SOCFPGA_MAX_PARENTS	3
 
 #define SOCFPGA_L4_MP_CLK		"l4_mp_clk"
 #define SOCFPGA_L4_SP_CLK		"l4_sp_clk"
@@ -258,7 +258,7 @@ static void __init socfpga_gate_clk_init(struct device_node *node,
 	struct clk *clk;
 	struct socfpga_clk *socfpga_clk;
 	const char *clk_name = node->name;
-	const char *parent_name[SOCFGPA_MAX_PARENTS];
+	const char *parent_name[SOCFPGA_MAX_PARENTS];
 	struct clk_init_data init;
 	int rc;
 	int i = 0;
@@ -299,7 +299,7 @@ static void __init socfpga_gate_clk_init(struct device_node *node,
 	init.name = clk_name;
 	init.ops = ops;
 	init.flags = 0;
-	while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
+	while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
 			of_clk_get_parent_name(node, i)) != NULL)
 		i++;
 
-- 
1.8.4.rc3

[PATCH 3/4] ARM: socfpga: clk: split clk code

[Steffen Trumtrar]

Move the different kinds of clocks into their own files. The reason is to aid
readability of the code. This also goes along with the other SoC-specific
clock drivers.

The split introduces new structs for the three types of clocks and uses them.
Other changes are not done to the code.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 drivers/clk/socfpga/Makefile     |   3 +
 drivers/clk/socfpga/clk-gate.c   | 197 ++++++++++++++++++++++++
 drivers/clk/socfpga/clk-periph.c |  97 ++++++++++++
 drivers/clk/socfpga/clk-pll.c    | 114 ++++++++++++++
 drivers/clk/socfpga/clk.c        | 312 +--------------------------------------
 drivers/clk/socfpga/clk.h        |  54 +++++++
 6 files changed, 466 insertions(+), 311 deletions(-)
 create mode 100644 drivers/clk/socfpga/clk-gate.c
 create mode 100644 drivers/clk/socfpga/clk-periph.c
 create mode 100644 drivers/clk/socfpga/clk-pll.c
 create mode 100644 drivers/clk/socfpga/clk.h

diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index 0303c0b..7e2d15a 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -1 +1,4 @@
 obj-y += clk.o
+obj-y += clk-gate.o
+obj-y += clk-pll.o
+obj-y += clk-periph.o
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
new file mode 100644
index 0000000..8bd6023
--- /dev/null
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -0,0 +1,197 @@
+/*
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Based from clk-highbank.c
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include "clk.h"
+
+#define SOCFPGA_L4_MP_CLK		"l4_mp_clk"
+#define SOCFPGA_L4_SP_CLK		"l4_sp_clk"
+#define SOCFPGA_NAND_CLK		"nand_clk"
+#define SOCFPGA_NAND_X_CLK		"nand_x_clk"
+#define SOCFPGA_MMC_CLK			"sdmmc_clk"
+#define SOCFPGA_DB_CLK			"gpio_db_clk"
+
+#define div_mask(width)	((1 << (width)) - 1)
+#define streq(a, b) (strcmp((a), (b)) == 0)
+
+#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
+
+static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
+{
+	u32 l4_src;
+	u32 perpll_src;
+
+	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		return l4_src &= 0x1;
+	}
+	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		return !!(l4_src & 2);
+	}
+
+	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
+		return perpll_src &= 0x3;
+	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
+			return (perpll_src >> 2) & 3;
+
+	/* QSPI clock */
+	return (perpll_src >> 4) & 3;
+
+}
+
+static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
+{
+	u32 src_reg;
+
+	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		src_reg &= ~0x1;
+		src_reg |= parent;
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+		src_reg &= ~0x2;
+		src_reg |= (parent << 1);
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+	} else {
+		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
+			src_reg &= ~0x3;
+			src_reg |= parent;
+		} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
+			src_reg &= ~0xC;
+			src_reg |= (parent << 2);
+		} else {/* QSPI clock */
+			src_reg &= ~0x30;
+			src_reg |= (parent << 4);
+		}
+		writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+	}
+
+	return 0;
+}
+
+static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
+	u32 div = 1, val;
+
+	if (socfpgaclk->fixed_div)
+		div = socfpgaclk->fixed_div;
+	else if (socfpgaclk->div_reg) {
+		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+		val &= div_mask(socfpgaclk->width);
+		if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
+			div = val + 1;
+		else
+			div = (1 << val);
+	}
+
+	return parent_rate / div;
+}
+
+static struct clk_ops gateclk_ops = {
+	.recalc_rate = socfpga_clk_recalc_rate,
+	.get_parent = socfpga_clk_get_parent,
+	.set_parent = socfpga_clk_set_parent,
+};
+
+static void __init __socfpga_gate_init(struct device_node *node,
+	const struct clk_ops *ops)
+{
+	u32 clk_gate[2];
+	u32 div_reg[3];
+	u32 fixed_div;
+	struct clk *clk;
+	struct socfpga_gate_clk *socfpga_clk;
+	const char *clk_name = node->name;
+	const char *parent_name[SOCFPGA_MAX_PARENTS];
+	struct clk_init_data init;
+	int rc;
+	int i = 0;
+
+	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
+	if (WARN_ON(!socfpga_clk))
+		return;
+
+	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
+	if (rc)
+		clk_gate[0] = 0;
+
+	if (clk_gate[0]) {
+		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
+		socfpga_clk->hw.bit_idx = clk_gate[1];
+
+		gateclk_ops.enable = clk_gate_ops.enable;
+		gateclk_ops.disable = clk_gate_ops.disable;
+	}
+
+	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+	if (rc)
+		socfpga_clk->fixed_div = 0;
+	else
+		socfpga_clk->fixed_div = fixed_div;
+
+	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+	if (!rc) {
+		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
+		socfpga_clk->shift = div_reg[1];
+		socfpga_clk->width = div_reg[2];
+	} else {
+		socfpga_clk->div_reg = 0;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
+	while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
+			of_clk_get_parent_name(node, i)) != NULL)
+		i++;
+
+	init.parent_names = parent_name;
+	init.num_parents = i;
+	socfpga_clk->hw.hw.init = &init;
+
+	clk = clk_register(NULL, &socfpga_clk->hw.hw);
+	if (WARN_ON(IS_ERR(clk))) {
+		kfree(socfpga_clk);
+		return;
+	}
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	if (WARN_ON(rc))
+		return;
+}
+
+static void __init socfpga_gate_init(struct device_node *node)
+{
+	__socfpga_gate_init(node, &gateclk_ops);
+}
+CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
new file mode 100644
index 0000000..7ff8f80
--- /dev/null
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -0,0 +1,97 @@
+/*
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Based from clk-highbank.c
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include "clk.h"
+
+#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
+
+static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
+					     unsigned long parent_rate)
+{
+	struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
+	u32 div;
+
+	if (socfpgaclk->fixed_div)
+		div = socfpgaclk->fixed_div;
+	else
+		div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
+
+	return parent_rate / div;
+}
+
+static const struct clk_ops periclk_ops = {
+	.recalc_rate = clk_periclk_recalc_rate,
+};
+
+static __init void __socfpga_periph_init(struct device_node *node,
+	const struct clk_ops *ops)
+{
+	u32 reg;
+	struct clk *clk;
+	struct socfpga_periph_clk *periph_clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct clk_init_data init;
+	int rc;
+	u32 fixed_div;
+
+	of_property_read_u32(node, "reg", &reg);
+
+	periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
+	if (WARN_ON(!periph_clk))
+		return;
+
+	periph_clk->hw.reg = clk_mgr_base_addr + reg;
+
+	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+	if (rc)
+		periph_clk->fixed_div = 0;
+	else
+		periph_clk->fixed_div = fixed_div;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
+	parent_name = of_clk_get_parent_name(node, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	periph_clk->hw.hw.init = &init;
+
+	clk = clk_register(NULL, &periph_clk->hw.hw);
+	if (WARN_ON(IS_ERR(clk))) {
+		kfree(periph_clk);
+		return;
+	}
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+
+static void __init socfpga_periph_init(struct device_node *node)
+{
+	__socfpga_periph_init(node, &periclk_ops);
+}
+CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
new file mode 100644
index 0000000..6dde9d3
--- /dev/null
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -0,0 +1,114 @@
+/*
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Based from clk-highbank.c
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include "clk.h"
+
+/* Clock bypass bits */
+#define MAINPLL_BYPASS		(1<<0)
+#define SDRAMPLL_BYPASS		(1<<1)
+#define SDRAMPLL_SRC_BYPASS	(1<<2)
+#define PERPLL_BYPASS		(1<<3)
+#define PERPLL_SRC_BYPASS	(1<<4)
+
+#define SOCFPGA_PLL_BG_PWRDWN		0
+#define SOCFPGA_PLL_EXT_ENA		1
+#define SOCFPGA_PLL_PWR_DOWN		2
+#define SOCFPGA_PLL_DIVF_MASK		0x0000FFF8
+#define SOCFPGA_PLL_DIVF_SHIFT		3
+#define SOCFPGA_PLL_DIVQ_MASK		0x003F0000
+#define SOCFPGA_PLL_DIVQ_SHIFT		16
+
+#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
+					 unsigned long parent_rate)
+{
+	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
+	unsigned long divf, divq, vco_freq, reg;
+	unsigned long bypass;
+
+	reg = readl(socfpgaclk->hw.reg);
+	bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
+	if (bypass & MAINPLL_BYPASS)
+		return parent_rate;
+
+	divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
+	divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
+	vco_freq = parent_rate * (divf + 1);
+	return vco_freq / (1 + divq);
+}
+
+static struct clk_ops clk_pll_ops = {
+	.recalc_rate = clk_pll_recalc_rate,
+};
+
+static __init struct clk *__socfpga_pll_init(struct device_node *node,
+	const struct clk_ops *ops)
+{
+	u32 reg;
+	struct clk *clk;
+	struct socfpga_pll *pll_clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct clk_init_data init;
+	int rc;
+
+	of_property_read_u32(node, "reg", &reg);
+
+	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
+	if (WARN_ON(!pll_clk))
+		return NULL;
+
+	pll_clk->hw.reg = clk_mgr_base_addr + reg;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
+	parent_name = of_clk_get_parent_name(node, 0);
+	init.parent_names = parent_name ? &parent_name : NULL;
+	init.num_parents = parent_name ? 1 : 0;
+
+	pll_clk->hw.hw.init = &init;
+
+	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
+	clk_pll_ops.enable = clk_gate_ops.enable;
+	clk_pll_ops.disable = clk_gate_ops.disable;
+
+	clk = clk_register(NULL, &pll_clk->hw.hw);
+	if (WARN_ON(IS_ERR(clk))) {
+		kfree(pll_clk);
+		return NULL;
+	}
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	return clk;
+}
+
+static void __init socfpga_pll_init(struct device_node *node)
+{
+	__socfpga_pll_init(node, &clk_pll_ops);
+}
+CLK_OF_DECLARE(socfpga_pll, "altr,socfpga-pll-clock", socfpga_pll_init);
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index c6fd6e6..34bb557 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -23,317 +23,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 
-/* Clock Manager offsets */
-#define CLKMGR_CTRL	0x0
-#define CLKMGR_BYPASS	0x4
-#define CLKMGR_L4SRC	0x70
-#define CLKMGR_PERPLL_SRC	0xAC
-
-/* Clock bypass bits */
-#define MAINPLL_BYPASS		(1<<0)
-#define SDRAMPLL_BYPASS		(1<<1)
-#define SDRAMPLL_SRC_BYPASS	(1<<2)
-#define PERPLL_BYPASS		(1<<3)
-#define PERPLL_SRC_BYPASS	(1<<4)
-
-#define SOCFPGA_PLL_BG_PWRDWN		0
-#define SOCFPGA_PLL_EXT_ENA		1
-#define SOCFPGA_PLL_PWR_DOWN		2
-#define SOCFPGA_PLL_DIVF_MASK		0x0000FFF8
-#define SOCFPGA_PLL_DIVF_SHIFT	3
-#define SOCFPGA_PLL_DIVQ_MASK		0x003F0000
-#define SOCFPGA_PLL_DIVQ_SHIFT	16
-#define SOCFPGA_MAX_PARENTS	3
-
-#define SOCFPGA_L4_MP_CLK		"l4_mp_clk"
-#define SOCFPGA_L4_SP_CLK		"l4_sp_clk"
-#define SOCFPGA_NAND_CLK		"nand_clk"
-#define SOCFPGA_NAND_X_CLK		"nand_x_clk"
-#define SOCFPGA_MMC_CLK			"sdmmc_clk"
-#define SOCFPGA_DB_CLK			"gpio_db_clk"
-
-#define div_mask(width)	((1 << (width)) - 1)
-#define streq(a, b) (strcmp((a), (b)) == 0)
-
-extern void __iomem *clk_mgr_base_addr;
-
-struct socfpga_clk {
-	struct clk_gate hw;
-	char *parent_name;
-	u32 fixed_div;
-	void __iomem *div_reg;
-	u32 width;	/* only valid if div_reg != 0 */
-	u32 shift;	/* only valid if div_reg != 0 */
-};
-#define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
-
-static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
-					 unsigned long parent_rate)
-{
-	struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
-	unsigned long divf, divq, vco_freq, reg;
-	unsigned long bypass;
-
-	reg = readl(socfpgaclk->hw.reg);
-	bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
-	if (bypass & MAINPLL_BYPASS)
-		return parent_rate;
-
-	divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
-	divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
-	vco_freq = parent_rate * (divf + 1);
-	return vco_freq / (1 + divq);
-}
-
-
-static struct clk_ops clk_pll_ops = {
-	.recalc_rate = clk_pll_recalc_rate,
-};
-
-static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
-					     unsigned long parent_rate)
-{
-	struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
-	u32 div;
-
-	if (socfpgaclk->fixed_div)
-		div = socfpgaclk->fixed_div;
-	else
-		div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
-
-	return parent_rate / div;
-}
-
-static const struct clk_ops periclk_ops = {
-	.recalc_rate = clk_periclk_recalc_rate,
-};
-
-static __init struct clk *socfpga_clk_init(struct device_node *node,
-	const struct clk_ops *ops)
-{
-	u32 reg;
-	struct clk *clk;
-	struct socfpga_clk *socfpga_clk;
-	const char *clk_name = node->name;
-	const char *parent_name;
-	struct clk_init_data init;
-	int rc;
-	u32 fixed_div;
-
-	rc = of_property_read_u32(node, "reg", &reg);
-	if (WARN_ON(rc))
-		return NULL;
-
-	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
-	if (WARN_ON(!socfpga_clk))
-		return NULL;
-
-	socfpga_clk->hw.reg = clk_mgr_base_addr + reg;
-
-	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
-	if (rc)
-		socfpga_clk->fixed_div = 0;
-	else
-		socfpga_clk->fixed_div = fixed_div;
-
-	of_property_read_string(node, "clock-output-names", &clk_name);
-
-	init.name = clk_name;
-	init.ops = ops;
-	init.flags = 0;
-	parent_name = of_clk_get_parent_name(node, 0);
-	init.parent_names = &parent_name;
-	init.num_parents = 1;
-
-	socfpga_clk->hw.hw.init = &init;
-
-	if (streq(clk_name, "main_pll") ||
-		streq(clk_name, "periph_pll") ||
-		streq(clk_name, "sdram_pll")) {
-		socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
-		clk_pll_ops.enable = clk_gate_ops.enable;
-		clk_pll_ops.disable = clk_gate_ops.disable;
-	}
-
-	clk = clk_register(NULL, &socfpga_clk->hw.hw);
-	if (WARN_ON(IS_ERR(clk))) {
-		kfree(socfpga_clk);
-		return NULL;
-	}
-	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
-	return clk;
-}
-
-static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
-{
-	u32 l4_src;
-	u32 perpll_src;
-
-	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
-		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
-		return l4_src &= 0x1;
-	}
-	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
-		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
-		return !!(l4_src & 2);
-	}
-
-	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
-	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
-		return perpll_src &= 0x3;
-	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
-			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
-			return (perpll_src >> 2) & 3;
-
-	/* QSPI clock */
-	return (perpll_src >> 4) & 3;
-
-}
-
-static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
-{
-	u32 src_reg;
-
-	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
-		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
-		src_reg &= ~0x1;
-		src_reg |= parent;
-		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
-	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
-		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
-		src_reg &= ~0x2;
-		src_reg |= (parent << 1);
-		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
-	} else {
-		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
-		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
-			src_reg &= ~0x3;
-			src_reg |= parent;
-		} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
-			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
-			src_reg &= ~0xC;
-			src_reg |= (parent << 2);
-		} else {/* QSPI clock */
-			src_reg &= ~0x30;
-			src_reg |= (parent << 4);
-		}
-		writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
-	}
-
-	return 0;
-}
-
-static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
-	unsigned long parent_rate)
-{
-	struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
-	u32 div = 1, val;
-
-	if (socfpgaclk->fixed_div)
-		div = socfpgaclk->fixed_div;
-	else if (socfpgaclk->div_reg) {
-		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-		val &= div_mask(socfpgaclk->width);
-		if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
-			div = val + 1;
-		else
-			div = (1 << val);
-	}
-
-	return parent_rate / div;
-}
-
-static struct clk_ops gateclk_ops = {
-	.recalc_rate = socfpga_clk_recalc_rate,
-	.get_parent = socfpga_clk_get_parent,
-	.set_parent = socfpga_clk_set_parent,
-};
-
-static void __init socfpga_gate_clk_init(struct device_node *node,
-	const struct clk_ops *ops)
-{
-	u32 clk_gate[2];
-	u32 div_reg[3];
-	u32 fixed_div;
-	struct clk *clk;
-	struct socfpga_clk *socfpga_clk;
-	const char *clk_name = node->name;
-	const char *parent_name[SOCFPGA_MAX_PARENTS];
-	struct clk_init_data init;
-	int rc;
-	int i = 0;
-
-	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
-	if (WARN_ON(!socfpga_clk))
-		return;
-
-	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
-	if (rc)
-		clk_gate[0] = 0;
-
-	if (clk_gate[0]) {
-		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
-		socfpga_clk->hw.bit_idx = clk_gate[1];
-
-		gateclk_ops.enable = clk_gate_ops.enable;
-		gateclk_ops.disable = clk_gate_ops.disable;
-	}
-
-	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
-	if (rc)
-		socfpga_clk->fixed_div = 0;
-	else
-		socfpga_clk->fixed_div = fixed_div;
-
-	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
-	if (!rc) {
-		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
-		socfpga_clk->shift = div_reg[1];
-		socfpga_clk->width = div_reg[2];
-	} else {
-		socfpga_clk->div_reg = 0;
-	}
-
-	of_property_read_string(node, "clock-output-names", &clk_name);
-
-	init.name = clk_name;
-	init.ops = ops;
-	init.flags = 0;
-	while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-			of_clk_get_parent_name(node, i)) != NULL)
-		i++;
-
-	init.parent_names = parent_name;
-	init.num_parents = i;
-	socfpga_clk->hw.hw.init = &init;
-
-	clk = clk_register(NULL, &socfpga_clk->hw.hw);
-	if (WARN_ON(IS_ERR(clk))) {
-		kfree(socfpga_clk);
-		return;
-	}
-	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
-	if (WARN_ON(rc))
-		return;
-}
-
-static void __init socfpga_pll_init(struct device_node *node)
-{
-	socfpga_clk_init(node, &clk_pll_ops);
-}
-CLK_OF_DECLARE(socfpga_pll, "altr,socfpga-pll-clock", socfpga_pll_init);
-
-static void __init socfpga_periph_init(struct device_node *node)
-{
-	socfpga_clk_init(node, &periclk_ops);
-}
-CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
-
-static void __init socfpga_gate_init(struct device_node *node)
-{
-	socfpga_gate_clk_init(node, &gateclk_ops);
-}
-CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
+#include "clk.h"
 
 void __init socfpga_init_clocks(void)
 {
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
new file mode 100644
index 0000000..d272048
--- /dev/null
+++ b/drivers/clk/socfpga/clk.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * based on drivers/clk/tegra/clk.h
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SOCFPGA_CLK_H
+#define __SOCFPGA_CLK_H
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
+/* Clock Manager offsets */
+#define CLKMGR_CTRL		0x0
+#define CLKMGR_BYPASS		0x4
+#define CLKMGR_L4SRC		0x70
+#define CLKMGR_PERPLL_SRC	0xAC
+
+#define SOCFPGA_MAX_PARENTS		3
+
+extern void __iomem *clk_mgr_base_addr;
+
+struct socfpga_pll {
+	struct clk_gate	hw;
+};
+
+struct socfpga_gate_clk {
+	struct clk_gate hw;
+	char *parent_name;
+	u32 fixed_div;
+	void __iomem *div_reg;
+	u32 width;	/* only valid if div_reg != 0 */
+	u32 shift;	/* only valid if div_reg != 0 */
+};
+
+struct socfpga_periph_clk {
+	struct clk_gate hw;
+	char *parent_name;
+	u32 fixed_div;
+};
+
+#endif /* SOCFPGA_CLK_H */
-- 
1.8.4.rc3

[PATCH 4/4] ARM: socfpga: clk: add clk_divider to periph

[Steffen Trumtrar]

The socfpga-perip-clks all have a variable clk_divider in their path.
Add it to the tree and also use clk_register_fixed_factor for the
fixed-dividers instead of a custom implementation.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 drivers/clk/socfpga/clk-periph.c | 78 ++++++++++++++++++----------------------
 drivers/clk/socfpga/clk.h        |  6 ++--
 2 files changed, 38 insertions(+), 46 deletions(-)

diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
index 7ff8f80..28f2c2d 100644
--- a/drivers/clk/socfpga/clk-periph.c
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -1,6 +1,7 @@
 /*
  *  Copyright 2011-2012 Calxeda, Inc.
  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,37 +26,17 @@
 
 #include "clk.h"
 
-#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
-
-static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
-					     unsigned long parent_rate)
-{
-	struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
-	u32 div;
-
-	if (socfpgaclk->fixed_div)
-		div = socfpgaclk->fixed_div;
-	else
-		div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
-
-	return parent_rate / div;
-}
-
-static const struct clk_ops periclk_ops = {
-	.recalc_rate = clk_periclk_recalc_rate,
-};
-
-static __init void __socfpga_periph_init(struct device_node *node,
-	const struct clk_ops *ops)
+static __init void __socfpga_periph_init(struct device_node *node)
 {
 	u32 reg;
-	struct clk *clk;
 	struct socfpga_periph_clk *periph_clk;
 	const char *clk_name = node->name;
 	const char *parent_name;
-	struct clk_init_data init;
-	int rc;
+	const char *div_name;
 	u32 fixed_div;
+	int ret;
+	int i;
+	unsigned int clk_idx = 0;
 
 	of_property_read_u32(node, "reg", &reg);
 
@@ -63,35 +44,44 @@ static __init void __socfpga_periph_init(struct device_node *node,
 	if (WARN_ON(!periph_clk))
 		return;
 
-	periph_clk->hw.reg = clk_mgr_base_addr + reg;
-
-	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
-	if (rc)
-		periph_clk->fixed_div = 0;
-	else
-		periph_clk->fixed_div = fixed_div;
+	periph_clk->reg = clk_mgr_base_addr + reg;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
-	init.name = clk_name;
-	init.ops = ops;
-	init.flags = 0;
 	parent_name = of_clk_get_parent_name(node, 0);
-	init.parent_names = &parent_name;
-	init.num_parents = 1;
 
-	periph_clk->hw.hw.init = &init;
+	spin_lock_init(&periph_clk->lock);
 
-	clk = clk_register(NULL, &periph_clk->hw.hw);
-	if (WARN_ON(IS_ERR(clk))) {
-		kfree(periph_clk);
-		return;
+	ret = of_property_read_u32(node, "fixed-divider", &fixed_div);
+	if (!ret) {
+		div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name);
+		periph_clk->clks[clk_idx++] = clk_register_fixed_factor(NULL,
+							div_name, parent_name,
+							0, 1, fixed_div);
+	} else {
+		div_name = kasprintf(GFP_KERNEL, "%s", parent_name);
 	}
-	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+	periph_clk->clks[clk_idx++] = clk_register_divider(NULL, clk_name,
+					div_name, 0, periph_clk->reg, 0, 9,
+					CLK_DIVIDER_ONE_BASED |
+					CLK_DIVIDER_ALLOW_ZERO,
+					&periph_clk->lock);
+
+	for (i = 0; i < ARRAY_SIZE(periph_clk->clks); i++)
+		if (IS_ERR(periph_clk->clks[i]))
+			pr_err("%s: clk %d: register failed with %ld\n",
+				node->name, i, PTR_ERR(periph_clk->clks[i]));
+
+	kfree(div_name);
+
+	periph_clk->clk_data.clks = periph_clk->clks;
+	periph_clk->clk_data.clk_num = clk_idx;
+	of_clk_add_provider(node, of_clk_src_simple_get, &periph_clk->clk_data);
 }
 
 static void __init socfpga_periph_init(struct device_node *node)
 {
-	__socfpga_periph_init(node, &periclk_ops);
+	__socfpga_periph_init(node);
 }
 CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index d272048..8b60c6b 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -46,9 +46,11 @@ struct socfpga_gate_clk {
 };
 
 struct socfpga_periph_clk {
-	struct clk_gate hw;
+	void __iomem *reg;
+	struct clk_onecell_data clk_data;
+	struct clk *clks[2];
 	char *parent_name;
-	u32 fixed_div;
+	spinlock_t lock;
 };
 
 #endif /* SOCFPGA_CLK_H */
-- 
1.8.4.rc3

[PATCH 0/4] Socfpga: clk: trivial fixes and cleanup

[Dinh Nguyen]

Hi Steffen,

On Thu, 2013-11-07 at 16:07 +0100, Steffen Trumtrar wrote:
> Hi!
> 
> This series includes two trivial fixes to the code (1,2),
> then goes on to split the single clk.c file up into clock-type
> specific files (3) and finally adds a divider to the peripheral
> clock path.
> 
> The patches are rebased to the for-next branch of
> 
>         git://git.rocketboards.org/linux-socfpga-next.git
> 
> Regards,
> Steffen
> 
> Steffen Trumtrar (4):
>   ARM: socfpga: clk: remove unused field
>   ARM: socfpga: clk: fix define typo

The first two patches are fine.

>   ARM: socfpga: clk: split clk code
>   ARM: socfpga: clk: add clk_divider to periph

These two patches are causing the ethernet driver to not be able to grab
the correct clock during probe.

Lets wait for 3.13-rc1 and I will push a new for-next that will be more
up-to-date.

Thanks,

Dinh
> 
>  drivers/clk/socfpga/Makefile     |   3 +
>  drivers/clk/socfpga/clk-gate.c   | 197 ++++++++++++++++++++++++
>  drivers/clk/socfpga/clk-periph.c |  87 +++++++++++
>  drivers/clk/socfpga/clk-pll.c    | 114 ++++++++++++++
>  drivers/clk/socfpga/clk.c        | 313 +--------------------------------------
>  drivers/clk/socfpga/clk.h        |  56 +++++++
>  6 files changed, 458 insertions(+), 312 deletions(-)
>  create mode 100644 drivers/clk/socfpga/clk-gate.c
>  create mode 100644 drivers/clk/socfpga/clk-periph.c
>  create mode 100644 drivers/clk/socfpga/clk-pll.c
>  create mode 100644 drivers/clk/socfpga/clk.h
> 

[PATCH 0/4] Socfpga: clk: trivial fixes and cleanup

[Dinh Nguyen]

On 11/11/13 6:12 PM, Dinh Nguyen wrote:
> Hi Steffen,
>
> On Thu, 2013-11-07 at 16:07 +0100, Steffen Trumtrar wrote:
>> Hi!
>>
>> This series includes two trivial fixes to the code (1,2),
>> then goes on to split the single clk.c file up into clock-type
>> specific files (3) and finally adds a divider to the peripheral
>> clock path.
>>
>> The patches are rebased to the for-next branch of
>>
>>         git://git.rocketboards.org/linux-socfpga-next.git
>>
>> Regards,
>> Steffen
>>
>> Steffen Trumtrar (4):
>>   ARM: socfpga: clk: remove unused field
>>   ARM: socfpga: clk: fix define typo
> The first two patches are fine.
>
>>   ARM: socfpga: clk: split clk code
>>   ARM: socfpga: clk: add clk_divider to periph
> These two patches are causing the ethernet driver to not be able to grab
> the correct clock during probe.
>
> Lets wait for 3.13-rc1 and I will push a new for-next that will be more
> up-to-date.

Also the values do not look correct with your patch:

per_nand_mmc_clk         1           1            52631578
          nand_clk              0           0            13157894
          nand_x_clk            0           0            52631578
          sdmmc_clk             1           1            52631578

Without your patch:

 per_nand_mmc_clk         1           1            50000000
          nand_clk              0           0            12500000
          nand_x_clk            0           0            50000000
          sdmmc_clk             1           1            50000000

Dinh
>
> Thanks,
>
> Dinh
>>  drivers/clk/socfpga/Makefile     |   3 +
>>  drivers/clk/socfpga/clk-gate.c   | 197 ++++++++++++++++++++++++
>>  drivers/clk/socfpga/clk-periph.c |  87 +++++++++++
>>  drivers/clk/socfpga/clk-pll.c    | 114 ++++++++++++++
>>  drivers/clk/socfpga/clk.c        | 313 +--------------------------------------
>>  drivers/clk/socfpga/clk.h        |  56 +++++++
>>  6 files changed, 458 insertions(+), 312 deletions(-)
>>  create mode 100644 drivers/clk/socfpga/clk-gate.c
>>  create mode 100644 drivers/clk/socfpga/clk-periph.c
>>  create mode 100644 drivers/clk/socfpga/clk-pll.c
>>  create mode 100644 drivers/clk/socfpga/clk.h
>>
>
>
>
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[PATCH 0/4] Socfpga: clk: trivial fixes and cleanup

[Steffen Trumtrar]

Hi Dinh,

On Mon, Nov 11, 2013 at 09:40:34PM -0600, Dinh Nguyen wrote:
> 
> On 11/11/13 6:12 PM, Dinh Nguyen wrote:
> > Hi Steffen,
> >
> > On Thu, 2013-11-07 at 16:07 +0100, Steffen Trumtrar wrote:
> >> Hi!
> >>
> >> This series includes two trivial fixes to the code (1,2),
> >> then goes on to split the single clk.c file up into clock-type
> >> specific files (3) and finally adds a divider to the peripheral
> >> clock path.
> >>
> >> The patches are rebased to the for-next branch of
> >>
> >>         git://git.rocketboards.org/linux-socfpga-next.git
> >>
> >> Regards,
> >> Steffen
> >>
> >> Steffen Trumtrar (4):
> >>   ARM: socfpga: clk: remove unused field
> >>   ARM: socfpga: clk: fix define typo
> > The first two patches are fine.
> >
> >>   ARM: socfpga: clk: split clk code
> >>   ARM: socfpga: clk: add clk_divider to periph
> > These two patches are causing the ethernet driver to not be able to grab
> > the correct clock during probe.
> >
> > Lets wait for 3.13-rc1 and I will push a new for-next that will be more
> > up-to-date.
> 

Hm, okay. It works fine on my SoCKit. But maybe I missed something in the
split up.

> Also the values do not look correct with your patch:
> 
> per_nand_mmc_clk         1           1            52631578
>           nand_clk              0           0            13157894
>           nand_x_clk            0           0            52631578
>           sdmmc_clk             1           1            52631578
> 
> Without your patch:
> 
>  per_nand_mmc_clk         1           1            50000000
>           nand_clk              0           0            12500000
>           nand_x_clk            0           0            50000000
>           sdmmc_clk             1           1            50000000
> 

Yes. I can confirm that on my board, too. I actually seem to have read over
those three values and missed them.

Let's wait for 3.13-rc1, then.

I actually also wanted to change the l3_sp_clk, as it seems to be neglect
the "1 or 2" divider from l3_mp_clk IIRC, but I couldn't come up with a good
way without changing the binding or something. What do you thing about that?
Is that wrong at the moment or do I miss something?


Thanks,
Steffen

-- 
Pengutronix e.K.                           |                             |
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[PATCH 0/4] Socfpga: clk: trivial fixes and cleanup

[Steffen Trumtrar]

Hi Dinh!

On Mon, Nov 18, 2013 at 11:11:52AM -0600, Dinh Nguyen wrote:
> Hi Steffen,
> 
> 
> On Tue, Nov 12, 2013 at 1:40 AM, Steffen Trumtrar <s.trumtrar@pengutronix.de
> > wrote:
> > I actually also wanted to change the l3_sp_clk, as it seems to be neglect
> > the "1 or 2" divider from l3_mp_clk IIRC, but I couldn't come up with a
> > good
> > way without changing the binding or something. What do you thing about
> > that?
> > Is that wrong at the moment or do I miss something?
> >
> 
> Ah yes, the l3_sp_clk's parent should be l3_mp_clk and not mainclk.
> 
> Thanks for spotting that...
> 
> Dinh
> 

Hm, that doesn't sound right. Don't we currently have Gate+Divider combo in
the l3_mp_clk? If you turn off the clock gate from the l3_mp_clk, then l3_sp_clk
would also be turned off.
But according to Figure 2-3 in cv_5v4.pdf

	DIV1 --------> GATE -----> L3_MP_CLK
                 |
		 |---- DIV2 -----> L3_SP_CLK

So, l3_sp_clk's parent is the divider of l3_mp_clk but NOT the gate.

Regards,
Steffen

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 0/4] Socfpga: clk: trivial fixes and cleanup

[Dinh Nguyen]

On Tue, 2013-11-19 at 09:14 +0100, Steffen Trumtrar wrote:
> Hi Dinh!
> 
> On Mon, Nov 18, 2013 at 11:11:52AM -0600, Dinh Nguyen wrote:
> > Hi Steffen,
> > 
> > 
> > On Tue, Nov 12, 2013 at 1:40 AM, Steffen Trumtrar <s.trumtrar@pengutronix.de
> > > wrote:
> > > I actually also wanted to change the l3_sp_clk, as it seems to be neglect
> > > the "1 or 2" divider from l3_mp_clk IIRC, but I couldn't come up with a
> > > good
> > > way without changing the binding or something. What do you thing about
> > > that?
> > > Is that wrong at the moment or do I miss something?
> > >
> > 
> > Ah yes, the l3_sp_clk's parent should be l3_mp_clk and not mainclk.
> > 
> > Thanks for spotting that...
> > 
> > Dinh
> > 
> 
> Hm, that doesn't sound right. Don't we currently have Gate+Divider combo in
> the l3_mp_clk? If you turn off the clock gate from the l3_mp_clk, then l3_sp_clk
> would also be turned off.
> But according to Figure 2-3 in cv_5v4.pdf
> 
> 	DIV1 --------> GATE -----> L3_MP_CLK
>                  |
> 		 |---- DIV2 -----> L3_SP_CLK
> 
> So, l3_sp_clk's parent is the divider of l3_mp_clk but NOT the gate.

ah, yes. I'll have to dig into this issue a bit more.

Dinh
> 
> Regards,
> Steffen
> 

[PATCH 0/4] Socfpga: clk: trivial fixes and cleanup

[Dinh Nguyen]

Hi Steffen,

On Tue, 2013-11-19 at 09:14 +0100, Steffen Trumtrar wrote:
> Hi Dinh!
> 
> On Mon, Nov 18, 2013 at 11:11:52AM -0600, Dinh Nguyen wrote:
> > Hi Steffen,
> > 
> > 
> > On Tue, Nov 12, 2013 at 1:40 AM, Steffen Trumtrar <s.trumtrar@pengutronix.de
> > > wrote:
> > > I actually also wanted to change the l3_sp_clk, as it seems to be neglect
> > > the "1 or 2" divider from l3_mp_clk IIRC, but I couldn't come up with a
> > > good
> > > way without changing the binding or something. What do you thing about
> > > that?
> > > Is that wrong at the moment or do I miss something?
> > >
> > 
> > Ah yes, the l3_sp_clk's parent should be l3_mp_clk and not mainclk.
> > 
> > Thanks for spotting that...
> > 
> > Dinh
> > 
> 
> Hm, that doesn't sound right. Don't we currently have Gate+Divider combo in
> the l3_mp_clk? If you turn off the clock gate from the l3_mp_clk, then l3_sp_clk
> would also be turned off.
> But according to Figure 2-3 in cv_5v4.pdf
> 
> 	DIV1 --------> GATE -----> L3_MP_CLK
>                  |
> 		 |---- DIV2 -----> L3_SP_CLK
> 
> So, l3_sp_clk's parent is the divider of l3_mp_clk but NOT the gate.

I just doubled checked. The L3_SP_CLK is taken before the gate of the
L3_MP_CLK, so turning off the L3_MP_CLK does not turn off the L3_SP_CLK.
So with this information, I think the parent for the L3_SP_CLK can be
the L3_MP_CLK, so that the extra divider is accounted for.

Dinh
> 
> Regards,
> Steffen
> 

[PATCH 0/4] Socfpga: clk: trivial fixes and cleanup

[Steffen Trumtrar]

On Tue, Nov 19, 2013 at 03:34:28PM -0600, Dinh Nguyen wrote:
> Hi Steffen,
> 
> On Tue, 2013-11-19 at 09:14 +0100, Steffen Trumtrar wrote:
> > Hi Dinh!
> > 
> > On Mon, Nov 18, 2013 at 11:11:52AM -0600, Dinh Nguyen wrote:
> > > Hi Steffen,
> > > 
> > > 
> > > On Tue, Nov 12, 2013 at 1:40 AM, Steffen Trumtrar <s.trumtrar@pengutronix.de
> > > > wrote:
> > > > I actually also wanted to change the l3_sp_clk, as it seems to be neglect
> > > > the "1 or 2" divider from l3_mp_clk IIRC, but I couldn't come up with a
> > > > good
> > > > way without changing the binding or something. What do you thing about
> > > > that?
> > > > Is that wrong at the moment or do I miss something?
> > > >
> > > 
> > > Ah yes, the l3_sp_clk's parent should be l3_mp_clk and not mainclk.
> > > 
> > > Thanks for spotting that...
> > > 
> > > Dinh
> > > 
> > 
> > Hm, that doesn't sound right. Don't we currently have Gate+Divider combo in
> > the l3_mp_clk? If you turn off the clock gate from the l3_mp_clk, then l3_sp_clk
> > would also be turned off.
> > But according to Figure 2-3 in cv_5v4.pdf
> > 
> > 	DIV1 --------> GATE -----> L3_MP_CLK
> >                  |
> > 		 |---- DIV2 -----> L3_SP_CLK
> > 
> > So, l3_sp_clk's parent is the divider of l3_mp_clk but NOT the gate.
> 
> I just doubled checked. The L3_SP_CLK is taken before the gate of the
> L3_MP_CLK, so turning off the L3_MP_CLK does not turn off the L3_SP_CLK.
> So with this information, I think the parent for the L3_SP_CLK can be
> the L3_MP_CLK, so that the extra divider is accounted for.

Yes. Giving it another thought, you are right. That should be okay.

Thanks,
Steffen

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |