From: s.hauer@pengutronix.de (Sascha Hauer)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 RESEND] ARM: imx: pllv1: Fix PLL calculation for i.MX27
Date: Tue, 3 Dec 2013 10:33:12 +0100 [thread overview]
Message-ID: <20131203093311.GI24559@pengutronix.de> (raw)
In-Reply-To: <1384076089-30536-1-git-send-email-shc_work@mail.ru>
On Sun, Nov 10, 2013 at 01:34:49PM +0400, Alexander Shiyan wrote:
> MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
> is a just sign bit. This patch makes different calculation for i.MX27.
>
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha
> ---
> arch/arm/mach-imx/clk-pllv1.c | 23 +++++++++++++++++++----
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
> index c1eaee3..d21d14c 100644
> --- a/arch/arm/mach-imx/clk-pllv1.c
> +++ b/arch/arm/mach-imx/clk-pllv1.c
> @@ -18,6 +18,11 @@
> *
> * PLL clock version 1, found on i.MX1/21/25/27/31/35
> */
> +
> +#define MFN_BITS (10)
> +#define MFN_SIGN (BIT(MFN_BITS - 1))
> +#define MFN_MASK (MFN_SIGN - 1)
> +
> struct clk_pllv1 {
> struct clk_hw hw;
> void __iomem *base;
> @@ -25,6 +30,11 @@ struct clk_pllv1 {
>
> #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
>
> +static inline bool mfn_is_negative(unsigned int mfn)
> +{
> + return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
> +}
> +
> static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> @@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
>
> /*
> * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
> - * 2's complements number
> + * 2's complements number.
> + * On i.MX27 the bit 9 is the sign bit.
> */
> - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
> - mfn_abs = 0x400 - mfn;
> + if (mfn_is_negative(mfn)) {
> + if (cpu_is_mx27())
> + mfn_abs = mfn & MFN_MASK;
> + else
> + mfn_abs = BIT(MFN_BITS) - mfn;
> + }
>
> rate = parent_rate * 2;
> rate /= pd + 1;
> @@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
>
> do_div(ll, mfd + 1);
>
> - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
> + if (mfn_is_negative(mfn))
> ll = -ll;
>
> ll = (rate * mfi) + ll;
> --
> 1.8.1.5
>
>
--
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next prev parent reply other threads:[~2013-12-03 9:33 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-10 9:34 [PATCH v3 RESEND] ARM: imx: pllv1: Fix PLL calculation for i.MX27 Alexander Shiyan
2013-12-03 9:33 ` Sascha Hauer [this message]
2013-12-03 10:50 ` Shawn Guo
-- strict thread matches above, loose matches on Subject: below --
2013-11-30 5:08 Alexander Shiyan
2013-12-03 7:28 ` Shawn Guo
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