[PATCH 0/4] clk: sunxi: add A20 external output clock support

[PATCH 0/4] clk: sunxi: add A20 external output clock support

[Chen-Yu Tsai]

Hi everyone,

This patch series adds support for the Allwinner A20's 2 external clock
outputs. The CubieTruck uses one such output to supply a stable 32.768
KHz low power clock to its AP6210 WiFi module. Support for the module
is being added to brcmfmac (brcm80211) by Broadcom people.

The patches should be applied after Emilio's sunxi clock series, as it
uses the new factors clocks setup code.

Comments?


Cheers,
ChenYu


Chen-Yu Tsai (4):
  clk: sunxi: Allwinner A20 output clock support
  ARM: dts: sun7i: external clock outputs
  pinctrl: sunxi: Add Allwinner A20 clock output pin functions
  ARM: dts: sun7i: Add pin muxing options for clock outputs

 arch/arm/boot/dts/sun7i-a20.dtsi     | 39 ++++++++++++++++++++++++
 drivers/clk/sunxi/clk-sunxi.c        | 57 ++++++++++++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-sunxi-pins.h |  2 ++
 3 files changed, 98 insertions(+)

-- 
1.8.5.2

[PATCH 1/4] clk: sunxi: Allwinner A20 output clock support

[Chen-Yu Tsai]

This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 25d99b6..19d9e9e 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -330,6 +330,47 @@ static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
 
 
 /**
+ * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
+ * CLK_OUT rate is calculated as follows
+ * rate = (parent_rate >> p) / (m + 1);
+ */
+
+static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
+				      u8 *n, u8 *k, u8 *m, u8 *p)
+{
+	u8 div, calcm, calcp;
+
+	/* These clocks can only divide, so we will never be able to achieve
+	 * frequencies higher than the parent frequency */
+	if (*freq > parent_rate)
+		*freq = parent_rate;
+
+	div = parent_rate / *freq;
+
+	if (div < 32)
+		calcp = 0;
+	else if (div / 2 < 32)
+		calcp = 1;
+	else if (div / 4 < 32)
+		calcp = 2;
+	else
+		calcp = 3;
+
+	calcm = DIV_ROUND_UP(div, 1 << calcp);
+
+	*freq = (parent_rate >> calcp) / calcm;
+
+	/* we were called to round the frequency, we can now return */
+	if (n == NULL)
+		return;
+
+	*m = calcm - 1;
+	*p = calcp;
+}
+
+
+
+/**
  * sunxi_factors_clk_setup() - Setup function for factor clocks
  */
 
@@ -384,6 +425,14 @@ static struct clk_factors_config sun4i_mod0_config = {
 	.pwidth = 2,
 };
 
+/* user manual says "n" but it's really "p" */
+static struct clk_factors_config sun7i_a20_out_config = {
+	.mshift = 8,
+	.mwidth = 5,
+	.pshift = 20,
+	.pwidth = 2,
+};
+
 static const struct factors_data sun4i_pll1_data __initconst = {
 	.enable = 31,
 	.table = &sun4i_pll1_config,
@@ -414,6 +463,13 @@ static const struct factors_data sun4i_mod0_data __initconst = {
 	.getter = sun4i_get_mod0_factors,
 };
 
+static const struct factors_data sun7i_a20_out_data __initconst = {
+	.enable = 31,
+	.mux = 24,
+	.table = &sun7i_a20_out_config,
+	.getter = sun7i_a20_get_out_factors,
+};
+
 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
 						const struct factors_data *data)
 {
@@ -912,6 +968,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
 	{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
 	{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
 	{.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
+	{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
 	{}
 };
 
-- 
1.8.5.2

[PATCH 2/4] ARM: dts: sun7i: external clock outputs

[Chen-Yu Tsai]

This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also added to serve as
the first input of the clock outputs, which according to AW's A20 user
manual, is the 24MHz oscillator divided by 750.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 4c25f81..6ad5507 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -302,6 +302,31 @@
 			clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 			clock-output-names = "mbus";
 		};
+
+		/*
+		 * Dummy clock used by output clocks
+		 */
+		osc24M_32k: osc24M_32k {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <750>;
+			clock-mult = <1>;
+			clocks = <&osc24M>;
+		};
+
+		clk_out_a: clk_out_a at 01c201f0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-out-clk";
+			reg = <0x01c201f0 0x4>;
+			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+		};
+
+		clk_out_b: clk_out_b at 01c201f4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-out-clk";
+			reg = <0x01c201f4 0x4>;
+			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+		};
 	};
 
 	soc at 01c00000 {
-- 
1.8.5.2

[PATCH 3/4] pinctrl: sunxi: Add Allwinner A20 clock output pin functions

[Chen-Yu Tsai]

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/pinctrl/pinctrl-sunxi-pins.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
index 2c7446a..567bc44 100644
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -3774,12 +3774,14 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi0"),		/* MOSI */
 		  SUNXI_FUNCTION(0x3, "uart6"),		/* TX */
+		  SUNXI_FUNCTION(0x4, "clk_out_a"),
 		  SUNXI_FUNCTION_IRQ(0x5, 24)),		/* EINT24 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi0"),		/* MISO */
 		  SUNXI_FUNCTION(0x3, "uart6"),		/* RX */
+		  SUNXI_FUNCTION(0x4, "clk_out_b"),
 		  SUNXI_FUNCTION_IRQ(0x5, 25)),		/* EINT25 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
-- 
1.8.5.2

[PATCH 4/4] ARM: dts: sun7i: Add pin muxing options for clock outputs

[Chen-Yu Tsai]

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 6ad5507..d6e7251 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -414,6 +414,20 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			clk_out_a_pins: clk_out_a {
+				allwinner,pins = "PI12";
+				allwinner,function = "clk_out_a";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			clk_out_b_pins: clk_out_b {
+				allwinner,pins = "PI13";
+				allwinner,function = "clk_out_b";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.5.2

[PATCH 0/4] clk: sunxi: add A20 external output clock support

[Chen-Yu Tsai]

Hi everyone,

This patch series adds support for the Allwinner A20's 2 external clock
outputs. The CubieTruck uses one such output to supply a stable 32.768
KHz low power clock to its AP6210 WiFi module. Support for the module
is being added to brcmfmac (brcm80211) by Broadcom people.

The patches should be applied after Emilio's sunxi clock series, as it
reuses the new "module 0" type clock support.

Comments?


Cheers,
ChenYu


Chen-Yu Tsai (4):
  clk: sunxi: Allwinner A20 output clock support
  ARM: dts: sun7i: external clock outputs
  pinctrl: sunxi: Add Allwinner A20 clock output pin functions
  ARM: dts: sun7i: Add pin muxing options for clock outputs

 arch/arm/boot/dts/sun7i-a20.dtsi     | 39 ++++++++++++++++++++++++++++++++++++
 drivers/clk/sunxi/clk-sunxi.c        | 15 ++++++++++++++
 drivers/pinctrl/pinctrl-sunxi-pins.h |  2 ++
 3 files changed, 56 insertions(+)

-- 
1.8.5.2

[PATCH 1/4] clk: sunxi: Allwinner A20 output clock support

[Emilio López]

Hi,

El 23/12/13 05:37, Chen-Yu Tsai escribi?:
> This patch adds support for the external clock outputs on the
> Allwinner A20 SoC. The clock outputs are similar to "module 0"
> type clocks, with different offsets and widths for clock factors.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

This patch looks good to me,

Acked-by: Emilio L?pez <emilio@elopez.com.ar>

> ---
>   drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 57 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 25d99b6..19d9e9e 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -330,6 +330,47 @@ static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
>
>
>   /**
> + * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
> + * CLK_OUT rate is calculated as follows
> + * rate = (parent_rate >> p) / (m + 1);
> + */
> +
> +static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
> +				      u8 *n, u8 *k, u8 *m, u8 *p)
> +{
> +	u8 div, calcm, calcp;
> +
> +	/* These clocks can only divide, so we will never be able to achieve
> +	 * frequencies higher than the parent frequency */
> +	if (*freq > parent_rate)
> +		*freq = parent_rate;
> +
> +	div = parent_rate / *freq;
> +
> +	if (div < 32)
> +		calcp = 0;
> +	else if (div / 2 < 32)
> +		calcp = 1;
> +	else if (div / 4 < 32)
> +		calcp = 2;
> +	else
> +		calcp = 3;
> +
> +	calcm = DIV_ROUND_UP(div, 1 << calcp);
> +
> +	*freq = (parent_rate >> calcp) / calcm;
> +
> +	/* we were called to round the frequency, we can now return */
> +	if (n == NULL)
> +		return;
> +
> +	*m = calcm - 1;
> +	*p = calcp;
> +}
> +
> +
> +
> +/**
>    * sunxi_factors_clk_setup() - Setup function for factor clocks
>    */
>
> @@ -384,6 +425,14 @@ static struct clk_factors_config sun4i_mod0_config = {
>   	.pwidth = 2,
>   };
>
> +/* user manual says "n" but it's really "p" */
> +static struct clk_factors_config sun7i_a20_out_config = {
> +	.mshift = 8,
> +	.mwidth = 5,
> +	.pshift = 20,
> +	.pwidth = 2,
> +};
> +
>   static const struct factors_data sun4i_pll1_data __initconst = {
>   	.enable = 31,
>   	.table = &sun4i_pll1_config,
> @@ -414,6 +463,13 @@ static const struct factors_data sun4i_mod0_data __initconst = {
>   	.getter = sun4i_get_mod0_factors,
>   };
>
> +static const struct factors_data sun7i_a20_out_data __initconst = {
> +	.enable = 31,
> +	.mux = 24,
> +	.table = &sun7i_a20_out_config,
> +	.getter = sun7i_a20_get_out_factors,
> +};
> +
>   static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
>   						const struct factors_data *data)
>   {
> @@ -912,6 +968,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
>   	{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
>   	{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
>   	{.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
> +	{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
>   	{}
>   };

[PATCH 2/4] ARM: dts: sun7i: external clock outputs

[Emilio López]

Hi,

El 23/12/13 05:37, Chen-Yu Tsai escribi?:
> This commit adds the two external clock outputs available on A20 to
> its device tree. A dummy fixed factor clock is also added to serve as
> the first input of the clock outputs, which according to AW's A20 user
> manual, is the 24MHz oscillator divided by 750.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
(,,,)
> +		clk_out_a: clk_out_a at 01c201f0 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun7i-a20-out-clk";
> +			reg = <0x01c201f0 0x4>;
> +			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
> +		};

These nodes should, as per Maxime's recommendation, look more like

	clk_out_a: clk at 01c201f0 {
		#clock-cells = <0>;
		compatible = "allwinner,sun7i-a20-out-clk";
		reg = <0x01c201f0 0x4>;
		clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
		clk-output-names = "clk_out_a";
	};

Cheers,

Emilio

[PATCH 1/4] clk: sunxi: Allwinner A20 output clock support

[Emilio López]

Hi again,

El 23/12/13 13:13, Emilio L?pez escribi?:
> Hi,
>
> El 23/12/13 05:37, Chen-Yu Tsai escribi?:
>> This patch adds support for the external clock outputs on the
>> Allwinner A20 SoC. The clock outputs are similar to "module 0"
>> type clocks, with different offsets and widths for clock factors.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> This patch looks good to me,
>
> Acked-by: Emilio L?pez <emilio@elopez.com.ar>
>
>> ---
>>   drivers/clk/sunxi/clk-sunxi.c | 57
>> +++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 57 insertions(+)

Please add the new binding to the binding document; I just noticed it 
was missing. You can keep the Ack once you do so.

Cheers,

Emilio

[PATCH 3/4] pinctrl: sunxi: Add Allwinner A20 clock output pin functions

[Emilio López]

Hi,

El 23/12/13 05:37, Chen-Yu Tsai escribi?:
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---

A commit description would be nice :) What are these outputs used for?

>   drivers/pinctrl/pinctrl-sunxi-pins.h | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
> index 2c7446a..567bc44 100644
> --- a/drivers/pinctrl/pinctrl-sunxi-pins.h
> +++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
> @@ -3774,12 +3774,14 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
>   		  SUNXI_FUNCTION(0x1, "gpio_out"),
>   		  SUNXI_FUNCTION(0x2, "spi0"),		/* MOSI */
>   		  SUNXI_FUNCTION(0x3, "uart6"),		/* TX */
> +		  SUNXI_FUNCTION(0x4, "clk_out_a"),

I would add a /* comment */ here and below too, to keep in line with the 
rest of the file, but this is just me nitpicking :)

>   		  SUNXI_FUNCTION_IRQ(0x5, 24)),		/* EINT24 */
>   	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
>   		  SUNXI_FUNCTION(0x0, "gpio_in"),
>   		  SUNXI_FUNCTION(0x1, "gpio_out"),
>   		  SUNXI_FUNCTION(0x2, "spi0"),		/* MISO */
>   		  SUNXI_FUNCTION(0x3, "uart6"),		/* RX */
> +		  SUNXI_FUNCTION(0x4, "clk_out_b"),
>   		  SUNXI_FUNCTION_IRQ(0x5, 25)),		/* EINT25 */
>   	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
>   		  SUNXI_FUNCTION(0x0, "gpio_in"),
>

Cheers!

Emilio

[PATCH 2/4] ARM: dts: sun7i: external clock outputs

[Chen-Yu Tsai]

Hi,

On Tue, Dec 24, 2013 at 12:21 AM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> Hi,
>
> El 23/12/13 05:37, Chen-Yu Tsai escribi?:
>
>> This commit adds the two external clock outputs available on A20 to
>> its device tree. A dummy fixed factor clock is also added to serve as
>> the first input of the clock outputs, which according to AW's A20 user
>> manual, is the 24MHz oscillator divided by 750.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>
> (,,,)
>
>> +               clk_out_a: clk_out_a at 01c201f0 {
>> +                       #clock-cells = <0>;
>> +                       compatible = "allwinner,sun7i-a20-out-clk";
>> +                       reg = <0x01c201f0 0x4>;
>> +                       clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
>> +               };
>
>
> These nodes should, as per Maxime's recommendation, look more like
>
>         clk_out_a: clk at 01c201f0 {
>                 #clock-cells = <0>;
>                 compatible = "allwinner,sun7i-a20-out-clk";
>                 reg = <0x01c201f0 0x4>;
>
>                 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
>                 clk-output-names = "clk_out_a";
>         };

I see. I was following the structure for the main clocks,
such as pll* or axi/ahb/apb, as the output clocks do not
have a specific device tied to them, and no worries that
a node name collision might happen. Do you plan to convert
the other clocks to this scheme as well? Or are they
considered reserved or special names?

>
> Cheers,
>
> Emilio

[PATCH 4/4] ARM: dts: sun7i: Add pin muxing options for clock outputs

[Emilio López]

Hi,

El 23/12/13 05:37, Chen-Yu Tsai escribi?:
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---

Other than the lack of a commit description, the patch looks ok to me.

>   arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 6ad5507..d6e7251 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -414,6 +414,20 @@
>   				allwinner,drive = <0>;
>   				allwinner,pull = <0>;
>   			};
> +
> +			clk_out_a_pins: clk_out_a {

I see the other nodes all start like

	foo_pins_a: foo0 at 0 {

Maybe yours should too? Maxime, thoughts?

> +				allwinner,pins = "PI12";
> +				allwinner,function = "clk_out_a";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
> +
> +			clk_out_b_pins: clk_out_b {
> +				allwinner,pins = "PI13";
> +				allwinner,function = "clk_out_b";
> +				allwinner,drive = <0>;
> +				allwinner,pull = <0>;
> +			};
>   		};
>
>   		timer at 01c20c00 {
>

Thanks for working on this!

Emilio

[PATCH 4/4] ARM: dts: sun7i: Add pin muxing options for clock outputs

[Chen-Yu Tsai]

On Tue, Dec 24, 2013 at 12:44 AM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> Hi,
>
> El 23/12/13 05:37, Chen-Yu Tsai escribi?:
>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>
>
> Other than the lack of a commit description, the patch looks ok to me.

I'll try to add something meaningful. Might be the same as patch 3 for pinctrl
though.

>
>
>>   arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi
>> b/arch/arm/boot/dts/sun7i-a20.dtsi
>> index 6ad5507..d6e7251 100644
>> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
>> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
>> @@ -414,6 +414,20 @@
>>                                 allwinner,drive = <0>;
>>                                 allwinner,pull = <0>;
>>                         };
>> +
>> +                       clk_out_a_pins: clk_out_a {
>
>
> I see the other nodes all start like
>
>         foo_pins_a: foo0 at 0 {
>
> Maybe yours should too? Maxime, thoughts?

I suppose this makes sense if we wanted multiple pinctrl states
for the same device?

>
>
>> +                               allwinner,pins = "PI12";
>> +                               allwinner,function = "clk_out_a";
>> +                               allwinner,drive = <0>;
>> +                               allwinner,pull = <0>;
>> +                       };
>> +
>> +                       clk_out_b_pins: clk_out_b {
>> +                               allwinner,pins = "PI13";
>> +                               allwinner,function = "clk_out_b";
>> +                               allwinner,drive = <0>;
>> +                               allwinner,pull = <0>;
>> +                       };
>>                 };
>>
>>                 timer at 01c20c00 {
>>
>
> Thanks for working on this!
>
> Emilio

[PATCH 2/4] ARM: dts: sun7i: external clock outputs

[Emilio López]

El 23/12/13 13:43, Chen-Yu Tsai escribi?:
> Hi,
>
> On Tue, Dec 24, 2013 at 12:21 AM, Emilio L?pez <emilio@elopez.com.ar> wrote:
>> Hi,
>>
>> El 23/12/13 05:37, Chen-Yu Tsai escribi?:
>>
>>> This commit adds the two external clock outputs available on A20 to
>>> its device tree. A dummy fixed factor clock is also added to serve as
>>> the first input of the clock outputs, which according to AW's A20 user
>>> manual, is the 24MHz oscillator divided by 750.
>>>
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>> ---
>>
>> (,,,)
>>
>>> +               clk_out_a: clk_out_a at 01c201f0 {
>>> +                       #clock-cells = <0>;
>>> +                       compatible = "allwinner,sun7i-a20-out-clk";
>>> +                       reg = <0x01c201f0 0x4>;
>>> +                       clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
>>> +               };
>>
>>
>> These nodes should, as per Maxime's recommendation, look more like
>>
>>          clk_out_a: clk at 01c201f0 {
>>                  #clock-cells = <0>;
>>                  compatible = "allwinner,sun7i-a20-out-clk";
>>                  reg = <0x01c201f0 0x4>;
>>
>>                  clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
>>                  clk-output-names = "clk_out_a";
>>          };
>
> I see. I was following the structure for the main clocks,
> such as pll* or axi/ahb/apb, as the output clocks do not
> have a specific device tied to them, and no worries that
> a node name collision might happen. Do you plan to convert
> the other clocks to this scheme as well? Or are they
> considered reserved or special names?

Yes, with time they should be renamed. A quote from 
http://devicetree.org/Device_Tree_Usage to give a bit of background

"""
It is worth taking a moment to talk about naming conventions. Every node 
must have a name in the form <name>[@<unit-address>].
<name> is a simple ascii string and can be up to 31 characters in 
length. In general, nodes are named according to what kind of device it 
represents. ie. A node for a 3com Ethernet adapter would be use the name 
ethernet, not 3com509. [...]
Sibling nodes must be uniquely named, but it is normal for more than one 
node to use the same generic name so long as the address is different 
(ie, serial at 101f1000 & serial at 101f2000).
"""

Have a look at the last iteration of my patches, where I remade all the 
mod0 nodes to fit with this.

Cheers,

Emilio

[PATCH 1/4] clk: sunxi: Allwinner A20 output clock support

[Mike Turquette]

Quoting Emilio L?pez (2013-12-23 08:23:47)
> Hi again,
> 
> El 23/12/13 13:13, Emilio L?pez escribi?:
> > Hi,
> >
> > El 23/12/13 05:37, Chen-Yu Tsai escribi?:
> >> This patch adds support for the external clock outputs on the
> >> Allwinner A20 SoC. The clock outputs are similar to "module 0"
> >> type clocks, with different offsets and widths for clock factors.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >
> > This patch looks good to me,
> >
> > Acked-by: Emilio L?pez <emilio@elopez.com.ar>
> >
> >> ---
> >>   drivers/clk/sunxi/clk-sunxi.c | 57
> >> +++++++++++++++++++++++++++++++++++++++++++
> >>   1 file changed, 57 insertions(+)
> 
> Please add the new binding to the binding document; I just noticed it 
> was missing. You can keep the Ack once you do so.

Feel free to add this to your "[PATCH v3 00/13] clk: sunxi: add PLL5 and
PLL6 support" pull request.

Regards,
Mike

> 
> Cheers,
> 
> Emilio

[PATCH 0/4] clk: sunxi: add A20 external output clock support

[Chen-Yu Tsai]

Hi everyone,

This is v2 of A20 external output clock support patch series.

The patch series builds upon Emilio's clock series, and adds
support for external output clocks on the Allwinner A20 SoC.
The outputs can be used to supply a stable clock to external
modules, such as WiFi or Bluetooth.


Changes since v1:

  - Add clock binding to sunxi clock DT binding documentation
  - Rename clock nodes to match device tree conventions
  - Add commit message for pin function/mux commits
  - Add comments to pin functions


Cheers,
ChenYu


Chen-Yu Tsai (4):
  clk: sunxi: Allwinner A20 output clock support
  ARM: dts: sun7i: external clock outputs
  pinctrl: sunxi: Add Allwinner A20 clock output pin functions
  ARM: dts: sun7i: Add pin muxing options for clock outputs

 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 arch/arm/boot/dts/sun7i-a20.dtsi                  | 41 ++++++++++++++++
 drivers/clk/sunxi/clk-sunxi.c                     | 57 +++++++++++++++++++++++
 drivers/pinctrl/pinctrl-sunxi-pins.h              |  2 +
 4 files changed, 101 insertions(+)

-- 
1.8.5.2

[PATCH 1/4] clk: sunxi: Allwinner A20 output clock support

[Chen-Yu Tsai]

This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c                     | 57 +++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 46d8433..c2cb762 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -36,6 +36,7 @@ Required properties:
 	"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
 	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
 	"allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
+	"allwinner,sun7i-a20-out-clk" - for the external output clocks
 
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 25d99b6..19d9e9e 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -330,6 +330,47 @@ static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
 
 
 /**
+ * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
+ * CLK_OUT rate is calculated as follows
+ * rate = (parent_rate >> p) / (m + 1);
+ */
+
+static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
+				      u8 *n, u8 *k, u8 *m, u8 *p)
+{
+	u8 div, calcm, calcp;
+
+	/* These clocks can only divide, so we will never be able to achieve
+	 * frequencies higher than the parent frequency */
+	if (*freq > parent_rate)
+		*freq = parent_rate;
+
+	div = parent_rate / *freq;
+
+	if (div < 32)
+		calcp = 0;
+	else if (div / 2 < 32)
+		calcp = 1;
+	else if (div / 4 < 32)
+		calcp = 2;
+	else
+		calcp = 3;
+
+	calcm = DIV_ROUND_UP(div, 1 << calcp);
+
+	*freq = (parent_rate >> calcp) / calcm;
+
+	/* we were called to round the frequency, we can now return */
+	if (n == NULL)
+		return;
+
+	*m = calcm - 1;
+	*p = calcp;
+}
+
+
+
+/**
  * sunxi_factors_clk_setup() - Setup function for factor clocks
  */
 
@@ -384,6 +425,14 @@ static struct clk_factors_config sun4i_mod0_config = {
 	.pwidth = 2,
 };
 
+/* user manual says "n" but it's really "p" */
+static struct clk_factors_config sun7i_a20_out_config = {
+	.mshift = 8,
+	.mwidth = 5,
+	.pshift = 20,
+	.pwidth = 2,
+};
+
 static const struct factors_data sun4i_pll1_data __initconst = {
 	.enable = 31,
 	.table = &sun4i_pll1_config,
@@ -414,6 +463,13 @@ static const struct factors_data sun4i_mod0_data __initconst = {
 	.getter = sun4i_get_mod0_factors,
 };
 
+static const struct factors_data sun7i_a20_out_data __initconst = {
+	.enable = 31,
+	.mux = 24,
+	.table = &sun7i_a20_out_config,
+	.getter = sun7i_a20_get_out_factors,
+};
+
 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
 						const struct factors_data *data)
 {
@@ -912,6 +968,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
 	{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
 	{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
 	{.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
+	{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
 	{}
 };
 
-- 
1.8.5.2

[PATCH 2/4] ARM: dts: sun7i: external clock outputs

[Chen-Yu Tsai]

This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also added to serve as
the first input of the clock outputs, which according to AW's A20 user
manual, is the 24MHz oscillator divided by 750.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 4c25f81..f255a49 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -302,6 +302,33 @@
 			clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 			clock-output-names = "mbus";
 		};
+
+		/*
+		 * Dummy clock used by output clocks
+		 */
+		osc24M_32k: osc24M_32k {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <750>;
+			clock-mult = <1>;
+			clocks = <&osc24M>;
+		};
+
+		clk_out_a: clk at 01c201f0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-out-clk";
+			reg = <0x01c201f0 0x4>;
+			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+			clock-output-names = "clk_out_a";
+		};
+
+		clk_out_b: clk at 01c201f4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-out-clk";
+			reg = <0x01c201f4 0x4>;
+			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+			clock-output-names = "clk_out_b";
+		};
 	};
 
 	soc at 01c00000 {
-- 
1.8.5.2

[PATCH 3/4] pinctrl: sunxi: Add Allwinner A20 clock output pin functions

[Chen-Yu Tsai]

This patch adds the clock output pin functions on the A20.
The 2 pins can output a configurable clock to be used by
external modules. This is used on the CubieTruck, to supply
a 32768 Hz low power clock to the onboard Wifi+BT module.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/pinctrl/pinctrl-sunxi-pins.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
index 2c7446a..6fd8d4d 100644
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -3774,12 +3774,14 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi0"),		/* MOSI */
 		  SUNXI_FUNCTION(0x3, "uart6"),		/* TX */
+		  SUNXI_FUNCTION(0x4, "clk_out_a"),	/* CLK_OUT_A */
 		  SUNXI_FUNCTION_IRQ(0x5, 24)),		/* EINT24 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi0"),		/* MISO */
 		  SUNXI_FUNCTION(0x3, "uart6"),		/* RX */
+		  SUNXI_FUNCTION(0x4, "clk_out_b"),	/* CLK_OUT_B */
 		  SUNXI_FUNCTION_IRQ(0x5, 25)),		/* EINT25 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
-- 
1.8.5.2

[PATCH 4/4] ARM: dts: sun7i: Add pin muxing options for clock outputs

[Chen-Yu Tsai]

This patch adds the clock output pin options on the A20.
The 2 pins can output a configurable clock to be used by
external modules. This is used on the CubieTruck, to supply
a 32768 Hz low power clock to the onboard Wifi+BT module.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index f255a49..7b46ce5 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -416,6 +416,20 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			clk_out_a_pins: clk_out_a at 0 {
+				allwinner,pins = "PI12";
+				allwinner,function = "clk_out_a";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			clk_out_b_pins: clk_out_b at 0 {
+				allwinner,pins = "PI13";
+				allwinner,function = "clk_out_b";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
1.8.5.2

[PATCH 0/4] clk: sunxi: add A20 external output clock support

[Maxime Ripard]

Hi Chen-Yu,

On Mon, Dec 23, 2013 at 04:37:02PM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
> 
> This patch series adds support for the Allwinner A20's 2 external clock
> outputs. The CubieTruck uses one such output to supply a stable 32.768
> KHz low power clock to its AP6210 WiFi module. Support for the module
> is being added to brcmfmac (brcm80211) by Broadcom people.
> 
> The patches should be applied after Emilio's sunxi clock series, as it
> uses the new factors clocks setup code.

Overall, it looks nice, but could you resend it as a separate thread,
with [PATCHv2] as a prefix (git format-patch's --reroll-count can help
you there) and CC'ing Linus Walleij for the pinctrl patch?

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 1/4] clk: sunxi: Allwinner A20 output clock support

[Mike Turquette]

Quoting Chen-Yu Tsai (2013-12-24 05:26:17)
> This patch adds support for the external clock outputs on the
> Allwinner A20 SoC. The clock outputs are similar to "module 0"
> type clocks, with different offsets and widths for clock factors.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Looks good to me.

Regards,
Mike

> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
>  drivers/clk/sunxi/clk-sunxi.c                     | 57 +++++++++++++++++++++++
>  2 files changed, 58 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 46d8433..c2cb762 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -36,6 +36,7 @@ Required properties:
>         "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
>         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
>         "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
> +       "allwinner,sun7i-a20-out-clk" - for the external output clocks
>  
>  Required properties for all clocks:
>  - reg : shall be the control register address for the clock.
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 25d99b6..19d9e9e 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -330,6 +330,47 @@ static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
>  
>  
>  /**
> + * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
> + * CLK_OUT rate is calculated as follows
> + * rate = (parent_rate >> p) / (m + 1);
> + */
> +
> +static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
> +                                     u8 *n, u8 *k, u8 *m, u8 *p)
> +{
> +       u8 div, calcm, calcp;
> +
> +       /* These clocks can only divide, so we will never be able to achieve
> +        * frequencies higher than the parent frequency */
> +       if (*freq > parent_rate)
> +               *freq = parent_rate;
> +
> +       div = parent_rate / *freq;
> +
> +       if (div < 32)
> +               calcp = 0;
> +       else if (div / 2 < 32)
> +               calcp = 1;
> +       else if (div / 4 < 32)
> +               calcp = 2;
> +       else
> +               calcp = 3;
> +
> +       calcm = DIV_ROUND_UP(div, 1 << calcp);
> +
> +       *freq = (parent_rate >> calcp) / calcm;
> +
> +       /* we were called to round the frequency, we can now return */
> +       if (n == NULL)
> +               return;
> +
> +       *m = calcm - 1;
> +       *p = calcp;
> +}
> +
> +
> +
> +/**
>   * sunxi_factors_clk_setup() - Setup function for factor clocks
>   */
>  
> @@ -384,6 +425,14 @@ static struct clk_factors_config sun4i_mod0_config = {
>         .pwidth = 2,
>  };
>  
> +/* user manual says "n" but it's really "p" */
> +static struct clk_factors_config sun7i_a20_out_config = {
> +       .mshift = 8,
> +       .mwidth = 5,
> +       .pshift = 20,
> +       .pwidth = 2,
> +};
> +
>  static const struct factors_data sun4i_pll1_data __initconst = {
>         .enable = 31,
>         .table = &sun4i_pll1_config,
> @@ -414,6 +463,13 @@ static const struct factors_data sun4i_mod0_data __initconst = {
>         .getter = sun4i_get_mod0_factors,
>  };
>  
> +static const struct factors_data sun7i_a20_out_data __initconst = {
> +       .enable = 31,
> +       .mux = 24,
> +       .table = &sun7i_a20_out_config,
> +       .getter = sun7i_a20_get_out_factors,
> +};
> +
>  static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
>                                                 const struct factors_data *data)
>  {
> @@ -912,6 +968,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
>         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
>         {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
>         {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
> +       {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
>         {}
>  };
>  
> -- 
> 1.8.5.2
> 

[PATCH 1/4] clk: sunxi: Allwinner A20 output clock support

[Emilio López]

Hi,

El 29/12/13 18:30, Mike Turquette escribi?:
> Quoting Chen-Yu Tsai (2013-12-24 05:26:17)
>> This patch adds support for the external clock outputs on the
>> Allwinner A20 SoC. The clock outputs are similar to "module 0"
>> type clocks, with different offsets and widths for clock factors.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> Looks good to me.

I have included this patch on my pull request to Mike.

Cheers,

Emilio

[PATCH 0/4] clk: sunxi: add A20 external output clock support

[Mike Turquette]

Quoting Maxime Ripard (2013-12-29 12:59:27)
> Hi Chen-Yu,
> 
> On Mon, Dec 23, 2013 at 04:37:02PM +0800, Chen-Yu Tsai wrote:
> > Hi everyone,
> > 
> > This patch series adds support for the Allwinner A20's 2 external clock
> > outputs. The CubieTruck uses one such output to supply a stable 32.768
> > KHz low power clock to its AP6210 WiFi module. Support for the module
> > is being added to brcmfmac (brcm80211) by Broadcom people.
> > 
> > The patches should be applied after Emilio's sunxi clock series, as it
> > uses the new factors clocks setup code.
> 
> Overall, it looks nice, but could you resend it as a separate thread,
> with [PATCHv2] as a prefix (git format-patch's --reroll-count can help
> you there) and CC'ing Linus Walleij for the pinctrl patch?

Hi Maxime,

Just FYI I have taken patch #1 of this series via Emilio's pull request.

Regards,
Mike

> 
> Thanks!
> Maxime
> 
> -- 
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

[PATCH 0/4] clk: sunxi: add A20 external output clock support

[Maxime Ripard]

Hi Mike,

On Sun, Dec 29, 2013 at 01:56:33PM -0800, Mike Turquette wrote:
> Quoting Maxime Ripard (2013-12-29 12:59:27)
> > Hi Chen-Yu,
> > 
> > On Mon, Dec 23, 2013 at 04:37:02PM +0800, Chen-Yu Tsai wrote:
> > > Hi everyone,
> > > 
> > > This patch series adds support for the Allwinner A20's 2 external clock
> > > outputs. The CubieTruck uses one such output to supply a stable 32.768
> > > KHz low power clock to its AP6210 WiFi module. Support for the module
> > > is being added to brcmfmac (brcm80211) by Broadcom people.
> > > 
> > > The patches should be applied after Emilio's sunxi clock series, as it
> > > uses the new factors clocks setup code.
> > 
> > Overall, it looks nice, but could you resend it as a separate thread,
> > with [PATCHv2] as a prefix (git format-patch's --reroll-count can help
> > you there) and CC'ing Linus Walleij for the pinctrl patch?
> 
> Hi Maxime,
> 
> Just FYI I have taken patch #1 of this series via Emilio's pull request.

Yeah, Emilio told me. Thanks for the heads up!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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